A single particle transient pulse detection circuit in a nano-integrated circuit

Abstract

The present invention provides a single-particle transient pulse detection circuit in a nano-integrated circuit, which relates to the field of single-particle transient effect detection technology. The circuit includes: a chain-type circuit to be tested, a single-particle transient pulse capture circuit and a single-particle transient pulse number counting circuit; wherein the single-particle transient pulse capture circuit and the chain-type circuit to be tested are tightly coupled circuits, and the single-particle transient pulse capture circuit includes a plurality of D-type latches with reset. When the single-particle transient pulse width is greater than the propagation delay time of the buffer, it will be captured and stored by the D-type latch, thereby realizing the detection of the single-particle transient pulse width; the single-particle transient pulse number counting circuit includes a plurality of D-type trigger groups with reset and a counter group; when the D-type trigger group detects a single-particle transient pulse signal entering its input end, a counting signal will be input to the counter group, and the counter group will complete the counting. The present invention can realize the specific quantitative detection of single-particle transient effects.

Description

Technical Field

[0001] The invention relates to the technical field of single particle transient effect detection, and in particular to a single particle transient pulse detection circuit in a nano integrated circuit. Background Art

[0002] Single Event Transient (SET) refers to the instantaneous change of the device output signal due to the energy transfer of a single particle in a microelectronic device. In a space irradiation environment, when high-energy particles bombard the device material, they will ionize the extranuclear electrons of the material atoms, generating a large number of carriers (electron-hole pairs). After these carriers are collected by sensitive electrodes, they will cause changes in the circuit state, thereby generating single-particle transient effects. The generation of single-particle transient effects is related to the energy transfer when high-energy particles hit the device. The energy of the particles will be transferred to the electrons in the device, resulting in an increase in the energy of the electrons, or the electrons will be excited to a high-energy state. These phenomena will cause the output signal of the device to change instantaneously, or even cause failures.

[0003] Single-particle transient effects are transient, that is, the effects are generated and disappear very quickly, usually at the microsecond or nanosecond level. In addition, the effect is random and unpredictable, because the impact of high-energy particles is random, and the time and location of its occurrence cannot be accurately predicted. In high-frequency digital integrated circuits, single-particle transient effects may cause changes in circuit states, thereby affecting the normal operation of the circuit and posing a threat to the stability and reliability of the system.

[0004] With the continuous development of semiconductor technology, the integration of devices is getting higher and higher, and the frequency is getting higher and higher. The probability of single-particle transient effects in digital integrated circuits used in space radiation environments is also gradually increasing. In nanoscale integrated circuits, it is difficult to quantify and study them specifically because of problems such as narrow pulse width and difficulty in capturing transient effects. Summary of the invention

[0005] In order to solve the problems existing in the detection of single particle transient effect pulses in nano-scale integrated circuits, the present invention provides a single particle transient pulse detection circuit in a nano-integrated circuit, which can realize the measurement of the pulse width of the single particle transient pulse on the one hand, and the measurement of the number of single particle transients on the other hand.

[0006] Specifically, the present invention provides a single-particle transient pulse detection circuit in a nano-integrated circuit, comprising: a chain-type circuit to be tested, a single-particle transient pulse capture circuit and a single-particle transient pulse number counting circuit; wherein,

[0007] The chain-type circuit to be tested is a test circuit comprising a basic logic unit circuit and a plurality of buffers, and when a single-particle transient pulse signal is input into the test circuit, it will be delayed and propagated through the buffers;

[0008] The single-particle transient pulse capture circuit and the chain-type circuit to be tested are tightly coupled circuits. The single-particle transient pulse capture circuit includes a plurality of D-type latches with reset. When the single-particle transient pulse width is greater than the propagation delay time of the buffer, it will be captured and stored by the D-type latch, thereby realizing the detection of the single-particle transient pulse width;

[0009] The single-particle transient pulse number counting circuit is connected to the reset end of the single-particle transient pulse capture circuit, and the single-particle transient pulse number counting circuit includes multiple D-type trigger groups with reset and counter groups; when the D-type trigger group with reset detects a single-particle transient pulse signal entering its input end, a counting signal is input to the counter group, and the counter group completes the counting.

[0010] As a further explanation of the present invention, a signal filter composed of two stages of latches is connected to the end of the buffer, wherein the first stage latch is used to capture the data transmitted from the previous stage and ensure its signal integrity, and the second stage latch is used to form a reset signal input through a single-particle transient pulse signal, thereby filtering out the single-particle transient pulse signal generated therein at the end of the test chain.

[0011] As a further illustration of the present invention, the data input interface of the first-level latch is connected to the input end of the first buffer, and the data output interface is connected to the data input interface of the second-level latch; the reset input interface of the second-level latch is connected to the output end of the first buffer, and the data output interface of the second-level latch is connected to the output end of the second buffer; the enable input interfaces of the first-level latch and the second-level latch are both connected to the enable input interface of the D-type latch in the single-particle transient pulse capture circuit.

[0012] As a further illustration of the present invention, the single-particle transient pulse capture circuit includes multiple groups of triple-module redundant D-type latch groups with reset, the data input interface of each group of triple-module redundant D-type latch groups with reset is connected to the output end of each buffer in turn, the data output interface is connected to the host computer for pulse width statistics, the enable input interface is connected to the enable input interface of the signal filter, and the asynchronous low-effective reset input interface is connected to the output end of the first buffer in the test circuit.

[0013] As a further illustration of the present invention, each group of triple-module redundant D-type latches with reset includes three D-type latches and a multiplexer. In a single group of triple-module redundant D-type latches with reset: the data input interface of each of the D-type latches is connected to the output end of the corresponding buffer, the data output interface is connected to the input end of the multiplexer of the group, the enable input interface is connected to the enable input interface of the signal filter, the asynchronous low-effective reset input interface is connected to the output end of the first buffer in the test circuit, and the output end of the multiplexer is connected to the host computer;

[0014] The captured single-particle transient pulse signal is stored in the D-type latch and judged in the subsequent multiplexer. Only if two or more single-particle transient pulse signals appear in the three latches can they be captured and processed by the subsequent multiplexer; when a fault occurs in a single latch among the three latches, the error will be shielded by its subsequent multiplexer.

[0015] As a further explanation of the present invention, the D-type flip-flop group with reset and the counter group are both triple-module redundant structures, and each group of the D-type flip-flop group with reset is respectively connected to a counter.

[0016] As a further explanation of the present invention, each group of the D-type flip-flop group with reset includes three D-type flip-flops and a multiplexer. In a single group of the D-type flip-flop group with reset: the input interface of each of the D-type flip-flops is connected to a high level, the output interface is connected to the input end of the multiplexer of the group, the falling edge trigger clock interface CKN is connected to the reset end of the single particle transient pulse capture circuit, and the low reset interface RDN is connected to the count indication output end of the counter group; the output ends of the multiplexer of the group are respectively connected to the corresponding counter input ends;

[0017] The single-particle transient pulse signal detected by the D-type trigger is judged in its subsequent multiplexer. Only if two or more single-particle transient pulse signals appear in the three triggers can they be captured and processed by the subsequent multiplexer; when a fault occurs in a single trigger among the three triggers, the error will be shielded by its subsequent multiplexer.

[0018] As a further explanation of the present invention, the counter group includes three counters and two multiplexers, and the output ends of the three counters are respectively connected to the input ends of the two multiplexers; one of the multiplexers is used for judging and outputting the counting indication signal, and its output end is connected to the reset end of the D-type flip-flop group with reset, and the other multiplexer is used for judging and outputting the counting result signal, and its output end is connected to the host computer;

[0019] The counting indication signal and counting result signal output by the counter are judged in the two subsequent multiplexers respectively. If the three counters output more than two counting indication signals or more than two counting result signals, they can be captured and processed by the corresponding multiplexers of the subsequent stage. When a fault occurs in a single counter among the three counters, the error will be shielded by the multiplexers of the subsequent stage.

[0020] Compared with the prior art, the present invention has the following beneficial technical effects:

[0021] The present invention stores possible erroneous transient pulse signals and realizes accurate detection of pulse width by designing a tightly coupled chain-type circuit to be tested and a single-particle transient pulse capture circuit; through the designed pulse number counting circuit, it is possible to measure the number of pulses while measuring the single-particle transient pulse width, thereby realizing specific quantitative detection of single-particle transient effects in nanoscale integrated circuits.

[0022] Other features and advantages of the technical solution will be described in the subsequent description, and partly become apparent from the description, or understood by implementing the technical solution. The purpose and other advantages of the technical solution can be achieved and obtained through the structures specifically pointed out in the written description and the drawings.

[0023] The technical solution of the present technical solution is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the technical solution and constitute a part of the specification. Together with the embodiments of the technical solution, they are used to explain the technical solution and do not constitute a limitation of the technical solution. In the accompanying drawings:

[0025] Figure 1 The present invention provides an overall architecture of a single-particle transient pulse detection circuit in a nano-integrated circuit.

[0026] Figure 2 It is a connection circuit diagram of the single-particle transient pulse capture circuit and the chain-type circuit to be tested in the present invention.

[0027] Figure 3 This is a circuit diagram for counting the number of single-particle transient pulses in the present invention.

[0028] Figure 4 This is a simulation example diagram of a single-particle transient pulse detection circuit in a nano-integrated circuit provided by the present invention. DETAILED DESCRIPTION

[0029] The preferred embodiments of the present technical solution are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present technical solution, and are not used to limit the present technical solution.

[0030] The basic unit of elapsed time in digital ICs is the propagation delay associated with the inverter, called one inverter delay. The test circuit described in this invention characterizes the SET pulse width in units of one buffer delay (two inverter delays). The pulse width is defined as the pulse width measured at the buffer threshold (Vdd / 2). If a SET pulse of sufficient duration is input to the buffer chain, it will propagate through each buffer after a specific time delay, as Figure 2 As shown, it will reach the third buffer after two buffer delays, and reach the fifth buffer after four buffer delays, and so on, so that the pulse width of the single-particle transient effect can be estimated by adjusting the test chain length. Based on this, the present invention designs the following single-particle transient pulse detection circuit.

[0031] like Figure 1 As shown, the present invention provides a single-particle transient pulse detection circuit in a nano integrated circuit, comprising: a chain-type circuit to be tested, a single-particle transient pulse capture circuit and a single-particle transient pulse number counting circuit; wherein the chain-type circuit to be tested is a test circuit comprising a basic logic unit circuit and a plurality of buffers, and when a single-particle transient pulse signal is input to the test circuit, it will be delayed and propagated through the buffer; the single-particle transient pulse capture circuit and the chain-type circuit to be tested are tightly coupled circuits, and the single-particle transient pulse capture circuit comprises a plurality of D-type latches with reset, and when the single-particle transient pulse width is greater than the propagation delay time of the buffer, it will be captured and stored by the D-type latch, thereby realizing the detection of the single-particle transient pulse width; the single-particle transient pulse number counting circuit is connected to the reset end of the single-particle transient pulse capture circuit, and the single-particle transient pulse number counting circuit comprises a plurality of D-type trigger groups with reset and a counter group; when the D-type trigger group with reset detects the single-particle transient pulse signal entering its input end, it will input a counting signal to the counter group, and the counter group completes the counting.

[0032] In one achievable manner, the basic logic unit circuit in the circuit to be tested can be composed of basic unit circuits such as NAND gates and NOR gates, and the specific circuit structure can correspond to the main function of the circuit to be tested. The circuit to be tested in the present invention is an adjustable test circuit with buffer logic, and the pulse width of a single particle transient can be effectively inferred through the delay of a single digital unit circuit. Specifically, Figure 2The buffer chain in the test chain can form a new test chain by changing the basic logic unit circuit structure. For example, it can be changed into a NAND gate structure in which the N tube is fixedly pulled to a high level and the P tube passes the signal. The pulse width and number of single-particle transients of the PMOS can be tested; by fixing the P tube to a low level and the N tube passing the signal through a NOR gate structure, the pulse width and number of single-particle transients of the NMOS can be tested. Both of the above circuits show the logical characteristics of the buffer, so the principle is the same as the above buffer test circuit.

[0033] In one achievable manner, the end of the buffer in the present invention is also connected to a signal filter consisting of two stages of latches, wherein the first stage latch is used to capture the data transmitted from the previous stage and ensure its signal integrity, and the second stage latch is used to form a reset signal input through a single-particle transient pulse signal, thereby filtering out the single-particle transient pulse signal generated therein at the end of the test chain.

[0034] Specifically, the data input interface of the first-stage latch is connected to the input end of the first buffer, and the data output interface is connected to the data input interface of the second-stage latch; the reset input interface of the second-stage latch is connected to the output end of the first buffer, and the data output interface of the second-stage latch is connected to the output end of the second buffer; the enable input interfaces of the first-stage latch and the second-stage latch are both connected to the enable input interface of the D-type latch in the single-particle transient pulse capture circuit.

[0035] The present invention connects two-stage latches at the end of the buffer to form a signal filter. If there is no SET in the test circuit, the low-level signal will return to the input end of the test chain to form a loop; if there is a SET in the test chain, the first-stage latch is responsible for capturing the data transmitted by the previous stage and ensuring its signal integrity. The rear-stage latch forms a reset signal input through the SET to ensure that the single-particle transient error generated in the signal will not be transmitted back along the path to the original input end of the test chain. Therefore, the signal filter can filter out the SET generated at the end of the test chain, avoid the problem of multiple capture of a single error caused by repeated transmission of the SET signal in the entire chain, and ensure that the signal integrity of the SET in the buffer in the test circuit is not destroyed.

[0036] The single-particle transient pulse capture circuit in the present invention is mainly composed of a D-type latch with reset, which saves possible erroneous transient pulse signals through signal control, and further performs data processing through counting logic, pulse width detection and other methods to achieve the purpose of observing the number and pulse width of single-particle transient pulses.

[0037] Specifically, the single-particle transient pulse capture circuit includes multiple groups of triple-module redundant D-type latch groups with reset, the data input interface of each group of triple-module redundant D-type latch groups with reset is connected to the output end of each buffer in turn, the data output interface is connected to the host computer for pulse width statistics, the enable input interface is connected to the enable input interface of the signal filter, and the asynchronous low-effective reset input interface is connected to the output end of the first buffer in the test circuit.

[0038] More specifically, each set of triple-module redundant D-type latch groups with reset includes three D-type latches and a multiplexer. In a single set of triple-module redundant D-type latch groups with reset: the data input interface of each D-type latch is connected to the output end of the corresponding buffer, the data output interface is connected to the input end of the multiplexer of the group, the enable input interface is connected to the enable input interface of the signal filter, the asynchronous low-effective reset input interface is connected to the output end of the first buffer in the test circuit, and the output end of the multiplexer is connected to the host computer; the captured single-particle transient pulse signal is stored in the D-type latch and judged in the subsequent multiplexer. If more than two single-particle transient pulse signals appear in the three latches, they can be captured and processed by the subsequent multiplexer; when a fault occurs in a single latch among the three latches, the error will be shielded by its subsequent multiplexer.

[0039] like Figure 2 As shown, the above-mentioned D-type latch in the present invention is a high-level triggered D latch with asynchronous low-position reset, wherein D in the latch is a data input interface, Q is a data output interface, E is an enable input interface, and RDN is an asynchronous low-effective reset input interface. The three identical latches form a triple-module redundant structure, which can ensure that the single-particle transient effect will not have an erroneous impact on the latch circuit. The captured single-particle transient signal is stored in the latch and further judged in the post-stage multiplexer (MUX in the figure). If more than two single-particle transient signals appear in the three latches, they can be captured and processed by the post-stage circuit; when a fault occurs in a single latch among the three latches, the error in the triple-module redundant latch group will be shielded by the multiplexer.

[0040] like Figure 2As shown, when the single-particle transient pulse width is greater than the propagation delay time of the buffer, it will be captured by the first group of three-module redundant latches in the single-particle transient pulse capture circuit, and the single-particle transient continues to propagate backward in the buffer chain and is captured by the second group of three-module redundant latches. Similarly, this single-particle transient pulse will be captured and output by multiple latches, where signals E1, E1 / 2, E1 / 2 / 3, and E1 / 2 / 3 / 4 are respectively the signals of the transient pulse being captured for the first time, the second time after the buffer delay, the third time after the buffer delay, and the fourth time after the buffer delay. The RDN interfaces of the four D-type latches are connected to the output of the first buffer in the buffer chain, and the SET signal passes through a buffer and multiple buffers completely. The SET pulse width is calculated by the number of SET latches captured, and the SET number is mainly obtained by edge-triggered measurement through a counting circuit, and finally a relatively accurate single-particle transient pulse width value and single-particle transient number are obtained. Figure 2 Only the test circuit structure for the first buffer is given. If you want to continue testing the error signal in the subsequent buffer chain, you need to continue connecting the latch chain at the output of the next buffer and connect the output of the second latch to the latch chain.

[0041] In one achievable manner, both the D-type flip-flop group with reset and the counter group are triple-module redundant structures, and each group of the D-type flip-flop group with reset is connected to a counter.

[0042] Specifically, each group of D-type flip-flops with reset includes three D-type flip-flops and a multiplexer. In a single group of D-type flip-flops with reset: the input interface of each D-type flip-flop is connected to a high level, the output interface is connected to the input end of the multiplexer of the group, the falling edge trigger clock interface CKN is connected to the reset end of the single-particle transient pulse capture circuit, and the low-level reset interface RDN is connected to the count indication output end of the counter group; the output end of the multiplexer of the group is respectively connected to the corresponding counter input end; the single-particle transient pulse signal detected by the D-type flip-flop is judged in its subsequent multiplexer, and only if more than two single-particle transient pulse signals appear in the three flip-flops can they be captured and processed by the subsequent multiplexer; when a fault occurs in a single flip-flop among the three flip-flops, the error will be shielded by its subsequent multiplexer.

[0043] Specifically, the counter group includes three counters and two multiplexers, and the output ends of the three counters are respectively connected to the input ends of the two multiplexers; one of the multiplexers is used for judging and outputting the counting indication signal, and its output end is connected to the reset end of the D-type flip-flop group with reset; the other multiplexer is used for judging and outputting the counting result signal, and its output end is connected to the host computer; the counting indication signal and the counting result signal output by the counter are respectively judged in the two subsequent multiplexers, and only if more than two counting indication signals or more than two counting result signals are output by the three counters can they be captured and processed by the corresponding multiplexers of the subsequent stage; when a fault occurs in a single counter among the three counters, the error will be shielded by the multiplexer of the subsequent stage.

[0044] like Figure 3 As shown, the captured single-particle pulse enters the single-particle transient pulse number counting circuit. The single-particle transient pulse number counting circuit contains a negative edge D-type flip-flop with low reset and forms a three-module redundant structure, in which the D port is the input signal of the flip-flop and is configured as a high level for a long time ( Figure 3 The data interface D in the interface is connected to a high level, represented by logic "1" in the figure); Q is the output port of its trigger; CKN is its falling edge touch interface; RDN is a low reset signal; when the SET capture circuit completes the pulse width detection, RDN is forcibly pulled down to a low level by the input signal of the chain to be tested, and the falling edge is detected in the D-type trigger. The D-type trigger inputs a counting signal to the three-module redundant counter. After the counting signal completes the counting, a low-bit counting indication signal is issued to reset all D-type triggers and wait for the next trigger signal. At the same time, the counting result after the counting is completed is output to the upper computer statistical data through the counter; the counting result signal is the number of single-particle transient pulses captured by the actual counter, and is output backward through the multiplexer MUX. It should be noted that in the present invention, the single-particle transient pulse number counting circuit is related to the number of buffers in the circuit to be tested. A buffer needs to be accompanied by a single-particle transient pulse number counting circuit to ensure the reliability of the reset signal and the counting result.

[0045] Figure 4 This is a simulation example diagram of the entire detection circuit. It mainly calculates the execution process of the latch in the capture circuit recording the SET pulse width through the control design of the reset signal. Figure 2 and Figure 4 Explain the SET pulse width detection. Figure 4 E is the enable signal, corresponding to Figure 2 The enable signal E of the D-type latch in the middle is set to on by default; Figure 4 Error is an error signal, corresponding to Figure 2The input of the first buffer is a square wave signal with a pulse width of 250ps, which is used as the error injection in this example; Figure 4 D1, D2, D3, and D4 correspond to Figure 2 Four buffered output signals and four latch input signals D are connected to the latch low reset interface RDN at the same time. Figure 4 It can be seen that the signal transmission has a buffer delay during the transmission process between the two buffers. In this example, the buffer delay is 83ps; Figure 4 Q1, Q2, Q3, Q4 correspond to Figure 2 The output terminal Q of the four latches is the output terminal of this pulse width detection calculation; it can be seen that transient pulse widths are captured in Q1, Q2, and Q3, but single-particle transient errors cannot be captured in Q4. The error signal has completed the measurement of the entire error signal through three buffers, so when it reaches the Q4 end, SET has passed the first buffer, so the reset signal RDN of the four latches is triggered, so that the subsequent latches can no longer capture the error signal. At the same time, the error signal is measured as 3 buffer delays, that is, 249ps, which is close to the actual error signal injection of 250ps, that is, the error pulse width measurement is completed.

[0046] The above test circuit is formed only for the first buffer, wherein the latch chain and the buffer chain can be expanded according to the above structure, and the measurable SET pulse width is adjusted based on the buffer delay, and the adjustment range is 1 buffer delay to n buffer delays.

[0047] Obviously, those skilled in the art can make various changes and modifications to the technical solution without departing from the spirit and scope of the technical solution. Thus, if these modifications and variations of the technical solution fall within the scope of the claims of the technical solution and their equivalents, the technical solution is also intended to include these modifications and variations.

Claims

1. A single particle transient pulse detection circuit in a nano-integrated circuit, characterized in that: include: Chain test circuit, single particle transient pulse capture circuit and single particle transient pulse number counting circuit; wherein, The chain-type circuit to be tested is a test circuit comprising a basic logic unit circuit and a plurality of buffers, and when a single-particle transient pulse signal is input into the test circuit, it will be delayed and propagated through the buffers; The single-particle transient pulse capture circuit and the chain-type circuit to be tested are tightly coupled circuits. The single-particle transient pulse capture circuit includes a plurality of D-type latches with reset. When the single-particle transient pulse width is greater than the propagation delay time of the buffer, it will be captured and stored by the D-type latch, thereby realizing the detection of the single-particle transient pulse width; The single-particle transient pulse number counting circuit is connected to the reset terminal of the single-particle transient pulse capture circuit, and the single-particle transient pulse number counting circuit includes a plurality of D-type flip-flop groups with reset and a counter group; when the D-type flip-flop group with reset detects a single-particle transient pulse signal entering its input terminal, a counting signal is input to the counter group, and the counter group completes the counting; The D-type flip-flop group with reset and the counter group are both triple-module redundant structures, and each group of the D-type flip-flop group with reset is respectively connected to a counter; Each group of the D-type flip-flop groups with reset includes three D-type flip-flops and a multiplexer. In a single group of the D-type flip-flop groups with reset: the input interface of each of the D-type flip-flops is connected to a high level, the output interface is connected to the input end of the multiplexer of the group, the falling edge trigger clock interface CKN is connected to the reset end of the single particle transient pulse capture circuit, and the low reset interface RDN is connected to the count indication output end of the counter group; the output ends of the multiplexer of the group are respectively connected to the corresponding counter input ends; The single-particle transient pulse signal detected by the D-type flip-flop is judged in its subsequent multiplexer. If more than two single-particle transient pulse signals appear in the three flip-flops, they can be captured and processed by the subsequent multiplexer. When a fault occurs in a single flip-flop among the three flip-flops, the error will be masked by its subsequent multiplexer; The counter group includes three counters and two multiplexers, and the output ends of the three counters are respectively connected to the input ends of the two multiplexers; one of the multiplexers is used for judging and outputting the counting indication signal, and its output end is connected to the reset end of the D-type flip-flop group with reset, and the other multiplexer is used for judging and outputting the counting result signal, and its output end is connected to the host computer; The counting indication signal and counting result signal output by the counter are judged in the two subsequent multiplexers respectively. If the three counters output more than two counting indication signals or more than two counting result signals, they can be captured and processed by the corresponding multiplexers of the subsequent stage. When a fault occurs in a single counter among the three counters, the error will be shielded by the multiplexers of the subsequent stage.

2. The single particle transient pulse detection circuit in a nano-integrated circuit as claimed in claim 1, characterized in that: The end of the buffer is connected to a signal filter consisting of two-stage latches, wherein the first-stage latch is used to capture the data transmitted from the previous stage and ensure its signal integrity, and the second-stage latch is used to form a reset signal input through a single-particle transient pulse signal, thereby filtering out the single-particle transient pulse signal generated therein at the end of the test chain.

3. The single particle transient pulse detection circuit in a nano-integrated circuit as claimed in claim 2, characterized in that: The data input interface of the first-level latch is connected to the input end of the first buffer, and the data output interface is connected to the data input interface of the second-level latch; the reset input interface of the second-level latch is connected to the output end of the first buffer, and the data output interface of the second-level latch is connected to the output end of the second buffer; the enable input interfaces of the first-level latch and the second-level latch are both connected to the enable input interface of the D-type latch in the single-particle transient pulse capture circuit.

4. The single particle transient pulse detection circuit in a nano-integrated circuit as claimed in claim 2, characterized in that: The single-particle transient pulse capture circuit includes multiple groups of triple-module redundant D-type latch groups with reset, the data input interface of each group of triple-module redundant D-type latch groups with reset is connected to the output end of each buffer in sequence, the data output interfaces are connected to the host computer for pulse width statistics, the enable input interfaces are connected to the enable input interface of the signal filter, and the asynchronous low-effective reset input interfaces are connected to the output end of the first buffer in the test circuit.

5. The single particle transient pulse detection circuit in a nano-integrated circuit as claimed in claim 4, characterized in that: Each group of triple-module redundant D-type latches with reset includes three D-type latches and a multiplexer. In a single group of triple-module redundant D-type latches with reset: the data input interface of each of the D-type latches is connected to the output end of the corresponding buffer, the data output interface is connected to the input end of the multiplexer of the group, the enable input interface is connected to the enable input interface of the signal filter, the asynchronous low-effective reset input interface is connected to the output end of the first buffer in the test circuit, and the output end of the multiplexer is connected to the host computer; The captured single-particle transient pulse signal is stored in the D-type latch and judged in the subsequent multiplexer. Only if two or more single-particle transient pulse signals appear in the three latches can they be captured and processed by the subsequent multiplexer; when a fault occurs in a single latch among the three latches, the error will be shielded by its subsequent multiplexer.

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