Photonic component with beveled sidewalls

Abstract

The invention relates to a photonic component with beveled sidewalls. A structure for a photonic chip including a photonic component and a method of forming such a structure. A structure may include a light detector and a waveguide core on a substrate. The light detector includes a light absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoining the first sidewall at an inner angle. The first sidewall is inclined relative to the longitudinal axis and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered portion adjacent a first sidewall and a second sidewall of the light absorbing layer.

Description

Technical Field

[0001] The present disclosure relates to photonic chips, and more particularly, to structures for photonic chips including photonic components and methods of forming such structures. Background Art

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. Photonic chips include photonic integrated circuits, which are composed of photonic components for manipulating light received from a light source such as an optical fiber or a laser, such as modulators, polarizers, and optical couplers. The light source can be coupled to the photonic integrated circuit on the photonic chip through an edge coupler (also called a spot size converter). The edge coupler is configured to transmit a given mode of light from the light source to the photonic integrated circuit. Photodetectors can be used in the photonic integrated circuit to convert light that can be modulated into an optical signal into an electrical signal.

[0003] There is a need for improved structures for photonic chips including photonic components and methods of forming such structures. Summary of the invention

[0004] In an embodiment of the present invention, a structure for a photonic chip is provided. The structure includes a photodetector and a waveguide core on a substrate. The photodetector includes a light absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjacent to the first sidewall at an internal angle. The first sidewall is inclined relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered portion of the first sidewall and the second sidewall adjacent to the light absorbing layer.

[0005] In an embodiment of the present invention, a structure for a photonic chip is provided. The structure includes an edge coupler on a substrate. The edge coupler includes a longitudinal axis and a facet, the facet having a first sidewall and a second sidewall adjacent to the first sidewall at an internal angle, the first sidewall is inclined relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis.

[0006] In an embodiment of the present invention, a method of forming a structure for a photonic chip is provided. The method includes forming a light absorbing layer of a photodetector on a substrate. The light absorbing layer has a longitudinal axis, a first sidewall, and a second sidewall adjacent to the first sidewall at an internal angle. The first sidewall is inclined relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The method further includes forming a waveguide core, the waveguide core including a tapered section adjacent to the first sidewall and the second sidewall of the light absorbing layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain embodiments of the present invention. In the accompanying drawings, the same reference numerals represent the same features in each view.

[0008] Figure 1 is a top view of a structure at an initial manufacturing stage of a processing method according to an embodiment of the present invention.

[0009] Figure 2 It is roughly along Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0010] Figure 2A It is roughly along Figure 1 A cross-sectional view taken along line 2A-2A in FIG.

[0011] Figure 3 is Figure 1 , Figure 2 , Figure 2A A top view of the structure at a manufacturing stage following a processing method.

[0012] Figure 4 It is roughly along Figure 3 A cross-sectional view taken along line 4-4 in FIG.

[0013] Figure 4A It is roughly along Figure 3 A cross-sectional view taken along the center line 4A-4A.

[0014] Figure 5 , 5A is Figure 3 , 4 , a cross-sectional view of the structure in the manufacturing stage of the processing method after 4A.

[0015] Figure 6 is a cross-sectional view of a structure according to an alternative embodiment of the present invention.

[0016] Figure 7 is a top view of a structure according to an alternative embodiment of the present invention.

[0017] Fig. 7A is a top view of a structure according to an alternative embodiment of the present invention.

[0018] Figure 8 is a top view of a structure according to an alternative embodiment of the present invention.

[0019] Fig. 9 is a top view of a structure at an initial manufacturing stage of a processing method according to an embodiment of the present invention.

[0020] Fig. 9Ayes Fig. 9 A magnified view of a portion of .

[0021] Fig.10 It is roughly along Fig. 9 A cross-sectional view taken along line 10-10 in FIG.

[0022] Fig.11 is Fig. 9 , 9A , a cross-sectional view of the structure in the manufacturing stage of the processing method after 10.

[0023] Fig.12 is a top view of a structure according to an alternative embodiment of the present invention.

[0024] Fig.13 is a top view of a structure according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0025] refer to Figure 1 , 2 , 2A, and according to an embodiment of the present invention, structure 10 includes a waveguide core 12 and a photodetector 14 representing a photonic component located on and above a dielectric layer 16 and a semiconductor substrate 18. In an embodiment, dielectric layer 16 may be composed of a dielectric material such as silicon dioxide, and semiconductor substrate 18 may be composed of a semiconductor material such as single crystal silicon. In an embodiment, dielectric layer 16 may be a buried oxide layer in a silicon-on-insulator substrate, and dielectric layer 16 may separate waveguide core 12 and photodetector 14 from semiconductor substrate 18.

[0026] The waveguide core 12 includes a tapered section 20, which is located adjacent to the photodetector. The tapered section 20, which extends longitudinally along a longitudinal axis 21, has a side wall 17 and a side wall 19 opposite the side wall 17. The photodetector 14 includes a pad 24 having side edges 23, 25, 27, 29 and a semiconductor layer 26 disposed on the pad 24 and inside the side edges 23, 25, 27, 29. The tapered section 20 can be connected to the side edge 23 of the pad 24 so that the side walls 17, 19 intersect the side edge 23.

[0027] The tapered section 20 may have a width dimension that increases as the distance from the side edge 23 of the pad 24 along the longitudinal axis 21 decreases. In an embodiment, the width dimension of the tapered section 20 may increase linearly as the distance from the side edge 23 decreases. In an alternative embodiment, the width dimension of the tapered section 20 may vary based on a non-linear function, such as a quadratic function, a cubic function, a parabolic function, a sine function, a cosine function, a Bessel function, or an exponential function. In an embodiment, the tapered section 20 may include a taper in a single step characterized by a taper angle. In an alternative embodiment, the tapered section 20 may taper in multiple steps, each step characterized by a different taper angle.

[0028] In alternative embodiments, the tapered section 20 of the waveguide core 12 may taper in both the height dimension and the width dimension. For example, the height dimension of the tapered section 20 may increase as the distance from the side edge 23 of the pad 24 decreases. In alternative embodiments, the semiconductor substrate 18 may include a cavity or undercut below the entirety or a portion of the tapered section 20 of the semiconductor core 12.

[0029] In an embodiment, the waveguide core 12 and the pad 24 of the photodetector 14 may include a refractive index greater than that of silicon dioxide. In an embodiment, the waveguide core 12 and the pad 24 of the photodetector 14 may include a semiconductor material. In an embodiment, the waveguide core 12 and the pad 24 of the photodetector 14 may include single crystal silicon. The waveguide core 12 and the pad 24 of the photodetector 14 may be formed by patterning a layer including their constituent materials using a photolithography and etching process. In an embodiment, the waveguide core 12 and the pad 24 of the photodetector 14 may be formed by patterning a semiconductor material (e.g., single crystal silicon) of a device layer in a silicon-on-insulator substrate. In an embodiment, the tapered section of the semiconductor core 12 may be a stacked waveguide including, for example, a tapered section of another waveguide core composed of a different material (e.g., polysilicon or silicon nitride) disposed in a layer above the tapered section 20.

[0030] The semiconductor layer 26 of the photodetector 14 may include a light absorbing material that generates charge carriers from photons of absorbed light by the photoelectric effect. In an embodiment, the semiconductor layer 26 may be composed of a material whose composition includes germanium. In an embodiment, the semiconductor layer 26 may include intrinsic germanium. In alternative embodiments, the semiconductor layer 26 may include a different light absorbing material, such as a III-V compound semiconductor material or silicon. The semiconductor layer 26 may be formed by an epitaxial growth process. In an embodiment, the semiconductor layer 26 may be epitaxially grown inside the trench 22 patterned in the pad so that the semiconductor layer 26 includes a lower portion disposed below the top surface 28 of the pad 24 and an upper portion disposed above the top surface 28 of the pad 24.

[0031] The semiconductor layer 26 has a non-rectangular shape when viewed in a vertical direction orthogonal to the top surface 39 of the semiconductor layer 26. In an embodiment, the shape of the semiconductor layer 26 may be consistent with the shape of the trench 22 patterned in the liner 24. In an embodiment, the semiconductor layer 26 may have four (4) or more sidewalls. In an embodiment, the semiconductor layer 26 may have a sidewall 30 and a sidewall 32 positioned adjacent to the side edge 23 of the liner 24, a sidewall 34 positioned adjacent to the side edge 25 of the liner 24, a sidewall 36 positioned adjacent to the side edge 27 of the liner 24, and a sidewall 38 positioned adjacent to the side edge 29 of the liner 24. In a representative embodiment, the sidewalls 30, 32, 34, 36, 38 surrounding the semiconductor layer 26 may have a pentagonal or pentagonal shape. Each of the sidewalls 30, 32, 34, 36, 38 includes an upper portion disposed above the top surface 28 of the liner 24 and a lower portion disposed below the top surface 28 of the liner 24.

[0032] Sidewalls 30, 32, 34, 36, 38 may intersect at respective corners. In an embodiment, sidewall 30 may intersect sidewall 32 at a sharp angle, sidewall 30 may intersect sidewall 36 at a sharp angle, and sidewall 32 may intersect sidewall 38 at a sharp angle. In alternative embodiments, the corners where sidewalls 30, 32 intersect, the corners where sidewalls 30, 36 intersect, and the corners where sidewalls 32, 38 intersect may be rounded or radiused. Sidewall 30 and sidewall 36 may abut at a right angle corner, sidewall 34 and sidewall 36 may abut at a right angle corner, and sidewall 36 and sidewall 38 may abut at a right angle corner.

[0033] The sidewall 32 defines a chamfer connecting the sidewall 30 to the sidewall 38. The sidewall 30 may abut the sidewall 32 at an internal angle α, and the sidewall 32 may abut the sidewall 38 at an internal angle β. In an embodiment, the internal angle α may be an obtuse angle. In an embodiment, the internal angle β may be an obtuse angle. In an embodiment, the internal angle α and the internal angle β may be obtuse angles. The tapered section 20 of the waveguide core 12 is positioned adjacent to both the sidewalls 30, 32 of the semiconductor layer 26. In an embodiment, the side edge 23 of the liner 24 may be positioned between the tapered section 20 of the waveguide core 12 and the sidewalls 30, 32 of the semiconductor layer 26.

[0034] The semiconductor layer 26 has a longitudinal axis 31 that is aligned parallel to the longitudinal axis 21 of the tapered subsection 20. The sidewalls 30 are oriented transverse to the longitudinal axis 31 such that the longitudinal axis 31 is perpendicular to the sidewalls 30. The sidewalls 32 may be aligned at an angle relative to the longitudinal axis 31 such that the internal angle α is an obtuse angle. The sidewalls 30, 32 may be viewed as facets of the semiconductor layer 26 that define the photodetector 14, which are configured to receive light from the tapered subsection 20 of the waveguide core 12.

[0035] In an alternative embodiment, semiconductor layer 26 may be formed on top surface 28 of liner 24, rather than being formed inside trench 22, such that semiconductor layer 26 is disposed entirely above top surface 28. In this regard, semiconductor layer 26 may be grown from top surface 28 of liner 24 and then patterned by photolithography and etching processes to define non-rectangular shaped sidewalls 30, 32, 34, 36, 38. In an alternative embodiment, semiconductor layer 26 may include additional sidewalls defining a chamfer connecting sidewall 30 to sidewall 36.

[0036] refer to Figure 3 , 4 , 4A, wherein like reference numerals refer to Figure 1 , 2 2A and at a subsequent manufacturing stage, structure 10 may include doped regions 40 and 42 formed in respective portions of liner 24. Doped regions 40, 42 of different conductivity types may extend through the entire thickness of liner 24 to underlying dielectric layer 16. Semiconductor layer 26 is laterally positioned between doped regions 40 and 42. Doped regions 40 and 42 may define an anode and a cathode of photodetector 14, respectively.

[0037] For example, doped regions 40 may be formed by ion implantation using an implantation mask having openings defining implantation regions of pads 24. The implantation mask may include a photoresist layer applied by a spin coating process, pre-baking, exposure to light projected through a photomask, post-exposure baking, and development with a chemical developer to define an opening above the region of pads 24 to be implanted. Implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of doped regions 40. The implantation mask may be stripped after forming doped regions 40. In an embodiment, the semiconductor material of doped regions 40 may include a p-type dopant (e.g., boron) that provides p-type conductivity. In an alternative embodiment, portions of semiconductor layer 26 adjacent to doped regions 40 and underlying portions of pads 24 may be implanted with p-type dopants due to the overlap of the openings in the implantation mask.

[0038] For example, doped regions 42 may be formed by ion implantation using an implantation mask having openings defining implantation regions of pads 24. The implantation mask may include a photoresist layer applied by a spin coating process, pre-baking, exposure to light projected through a photomask, post-exposure baking, and development with a chemical developer to define an opening above the region of pads 24 to be implanted. Implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of doped regions 42. The implantation mask may be stripped after forming doped regions 42. In an embodiment, the semiconductor material of doped regions 42 may include an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. In an alternative embodiment, portions of semiconductor layer 26 adjacent to doped regions 42 and underlying portions of pads 24 may be implanted with n-type dopants due to the overlap of the openings in the implantation mask.

[0039] The portion of the liner 24 below the semiconductor layer 26 may include an intrinsic semiconductor material, such as intrinsic silicon, that has not been doped by ion implantation to form the doped regions 40, 42. The longitudinal axis 21 of the tapered segment 20 is aligned with the intrinsic portion of the liner 24. In an embodiment, the intrinsic portion of the liner 24 may extend from a side edge 23 of the liner 24 to a side edge 25 of the liner 24. The doped region 40, the intrinsic semiconductor material of the semiconductor layer 26 and the portion of the liner 24 below the semiconductor layer 26, and the doped region 42 may define a pin diode structure that provides the functionality of the photodetector 14.

[0040] A heavily doped region 41 may be formed in a portion of the doped region 40 adjacent to the side edge 27 by masked ion implantation, and a heavily doped region 43 may be formed in a portion of the doped region 42 adjacent to the side edge 29 by masked ion implantation. The heavily doped region 41 may be doped with the same conductivity type as the doped region 40, but at a higher dopant concentration. The heavily doped region 43 may be doped with the same conductivity type as the doped region 42, but at a higher dopant concentration.

[0041] refer to Figure 5 , 5A , where like reference numerals refer to Figure 3 , 4 4A and in a subsequent manufacturing stage, a conformal dielectric layer 45 may be formed that follows the topography created by semiconductor layer 26 and extends across liner 24 and semiconductor layer 26. Conformal dielectric layer 45 may include a dielectric material, such as silicon nitride. An additional conformal dielectric layer (not shown) may be disposed between semiconductor layer 26 and conformal dielectric layer 45, including a dielectric material, such as silicon dioxide.

[0042] Dielectric layers 46, 47 are formed over the waveguide core 12 and the photodetector 14. In an embodiment, the dielectric layers 46, 47 may include a dielectric material, such as silicon dioxide, having a lower refractive index than the material of the waveguide core 12. The dielectric layer 46 may be deposited and planarized, and the dielectric layer 47 may be deposited over the planarized dielectric layer 46.

[0043] A contact 48 may be formed that completely penetrates the conformal dielectric layer 45 and the dielectric layers 46, 47 to land on the heavily doped region 41, and a contact 49 may be formed that completely penetrates the conformal dielectric layer 45 and the dielectric layers 46, 47 to land on the heavily doped region 43. The heavily doped region 41 electrically couples the contact 48 to the doped region 40 with reduced contact resistance. The heavily doped region 43 couples the contact 49 to the doped region 42 with reduced contact resistance. The contacts 48, 49 may include a metal, such as tungsten. The doped regions 40, 42 may be biased by the contacts 48, 49.

[0044] In use, light (e.g., laser light) propagates in the waveguide core 12 toward the photodetector 14 and is coupled from the tapered section 20 of the waveguide core 12 to the semiconductor layer 26 of the photodetector 14. The waveguide core 12 can support the propagation of light having transverse electric polarization, transverse magnetic polarization, or a combination of the two. In an embodiment, the light received by the photodetector 14 can be modulated into an optical signal. The semiconductor layer 26 absorbs photons of light and converts the absorbed photons into charge carriers by the photoelectric effect. The biasing of the doped regions 40, 42 causes the charge carriers to be collected and output to provide a measurable photocurrent as a function of time.

[0045] The sidewalls 30, 32 of the semiconductor layer 26 positioned adjacent to the tapered section 20 of the waveguide core 12 can significantly reduce light reflection losses while maintaining high coupling efficiency and without causing a loss in responsivity of the photodetector 14. The sidewalls 30, 32 of the semiconductor layer 26 can help maintain modal overlap between the modes in the waveguide core 12 and the modes in the semiconductor layer 26.

[0046] refer to Figure 6 According to an alternative embodiment, the structure 10 can be modified so that the photodetector 14 has a vertical arrangement instead of a lateral arrangement. Specifically, in the vertical arrangement, the doped region 40 and the heavily doped region 41 can be arranged in the pad 24 on both sides of the semiconductor layer, and the doped region 42 and the heavily doped region 43 can be arranged in the semiconductor layer 26.

[0047] In an alternative embodiment, structure 10 may be configured with doped regions 40 in pad 24 adjacent only one side of semiconductor layer 26. In an alternative embodiment, photodetector 14 may be configured as an avalanche photodetector including an intrinsic semiconductor region in pad 24 defining a multiplication region and an additional doped region in pad 24 defining a charge control region.

[0048] refer to Figure 7 , 7A According to an alternative embodiment, the longitudinal axis 21 of the tapered subdivision 20 can be angled to further reduce light return losses from the side edges 23 of the liner 24 and the sidewalls 30, 32 of the semiconductor layer 26. Specifically, the longitudinal axis 31 of the semiconductor layer 26 can be aligned at an acute angle relative to the longitudinal axis 21 of the tapered subdivision 20. In an embodiment and as shown Figure 7 As shown, the tapered section 20 can be oriented to increase the angular difference between the longitudinal axis 21 and the plane of the side wall 32 so that the incident angle of light relative to the side wall 32 increases. Fig. 7A As shown, the tapered section 20 may be oriented to reduce the angular difference between the side wall 32 and the longitudinal axis 21 .

[0049] refer to Figure 8 And according to an alternative embodiment, semiconductor layer 26 can include sidewall 35, sidewall 35 defining a chamfer connecting sidewall 34 with sidewall 38. Sidewall 35 can abut sidewall 34 at an internal angle similar to internal angle α, and sidewall 35 can abut sidewall 38 at an internal angle similar to internal angle β. In an embodiment, one or both internal angles can be obtuse. Sidewall 34 can be oriented transverse to longitudinal axis 31 so that longitudinal axis 31 is perpendicular to sidewall 34. Sidewall 35 can be aligned at an angle relative to longitudinal axis 31.

[0050] The structure 10 may include a waveguide core 52 having a tapered subdivision 54, the tapered subdivision 54 being positioned adjacent to a side edge 25 of the liner 24 opposite to the side edge 23. The tapered subdivision 54 of the waveguide core 52 is positioned adjacent to both sidewalls 34, 35 of the semiconductor layer 26. In an embodiment, the side edge 25 of the liner 24 may be positioned between the tapered subdivision 54 of the waveguide core 52 and the sidewalls 34, 35 of the semiconductor layer 26. The tapered subdivision 54 of the waveguide core 52 may be similar or identical to the tapered subdivision 20 of the waveguide core 12. In an embodiment, the waveguide core 52 may include the same material as the waveguide core 12. The sidewalls 34 and 35 define a facet of the semiconductor layer 26 of the photodetector 14, the facet being configured to receive light from the tapered subdivision 54 of the waveguide core 52.

[0051] In addition to the input provided by the tapered section 20 of the waveguide core 12, the tapered section 54 of the waveguide core 52 can provide another input to the photodetector 14. For example, the total power delivered to the photodetector 14 can be split between the input provided by the tapered section 20 and the input provided by the tapered section 54. The sidewalls 35 of the semiconductor layer 26 can significantly reduce light reflection losses while maintaining high coupling efficiency and without causing a loss in responsivity of the photodetector 14. The sidewalls 34, 35 of the semiconductor layer 26 can help maintain modal overlap between the modes in the waveguide core 52 and the modes in the semiconductor layer 26.

[0052] In alternative embodiments, sidewall 35 may be formed between sidewall 34 and sidewall 36. In alternative embodiments, longitudinal axis 21 of tapered section 20 of waveguide core 12 and / or longitudinal axis 53 of tapered section 54 of waveguide core 52 may be as shown. Figure 7 or Fig. 7A Angled as shown.

[0053] refer to Fig. 9 , 9A , 10 and according to an embodiment of the present invention, a structure 50 for a photonic chip includes a waveguide core 56 positioned on or above a dielectric layer 16 and a semiconductor substrate 18. The waveguide core 56 is separated from the semiconductor substrate 18 by an intermediate dielectric layer 16. In alternative embodiments, one or more additional dielectric layers composed of, for example, silicon dioxide, may be positioned between the waveguide core 56 and the upper surface of the dielectric layer 16.

[0054] In an embodiment, the waveguide core 56 may be composed of a material having a refractive index greater than that of silicon dioxide. In an embodiment, the waveguide core 56 may be composed of a semiconductor material such as single crystal silicon, amorphous silicon, or polycrystalline silicon. In an alternative embodiment, the waveguide core 56 may be composed of a dielectric material such as silicon nitride, silicon oxynitride, or aluminum nitride. In an alternative embodiment, other materials such as III-V compound semiconductors may be used to form the waveguide core 56.

[0055] In an embodiment, the waveguide core 56 may be formed by patterning a layer using a photolithography and etching process. In an embodiment, an etching mask may be formed on the layer by a photolithography process, and an unmasked portion of the layer may be etched and removed by an etching process. The masked portion of the layer may determine the patterned shape of the waveguide core 56. In an embodiment, the waveguide core 56 may be formed by patterning a semiconductor material (e.g., single crystal silicon) of a device layer in a silicon-on-insulator substrate. In an embodiment, the waveguide core 56 may be formed by patterning a deposited layer composed of its constituent materials (e.g., silicon nitride).

[0056] The waveguide core 56 may include a segment 57, a plurality of segments 58, a plurality of segments 60, a rib 61 overlapping some of the segments 60, and a segment 62 positioned adjacent to a segment including the segment 60 and the rib 61. The segments 57, 58, 60, the rib 61, and the segment 62 of the waveguide core 56 may define an edge coupler 55 representing a photonic component. The segments 57, 58, 60, the ridge 61, and the segment 62 may be aligned along a longitudinal axis 75 of the edge coupler 55. The edge coupler 55 may be coupled to a photonic integrated circuit of a photonic chip by the segment 62 of the waveguide core 56. In an alternative embodiment, the ridge 61 may be missing so that all segments 60 are disconnected from each other. In an embodiment, the edge coupler 55 may be configured to receive light from a light source, which is routed to the photonic integrated circuit through the waveguide core 56 as described subsequently.

[0057] The segments 57, 58, 60 may be separated by gaps G. In an embodiment, the pitch and duty cycle of the segments 57, 58, 60 may be uniform to define a periodic arrangement. In an alternative embodiment, the pitch and / or duty cycle of the segments 57, 58, 60 may be apodized (i.e., non-uniform) to define a non-periodic arrangement. The segments 57, 58, 60 may be sized and positioned with a sufficiently small pitch to form a sub-wavelength grating that does not radiate or reflect light at an operating wavelength.

[0058] Segments 57 at the ends of edge couplers 55 have a non-rectangular shape when viewed in a vertical direction orthogonal to top surfaces 63 of segments 57. The shape of segments 57 may be established when edge couplers 55 are patterned. In embodiments, segments 57 may have four (4) or more sidewalls. In embodiments, and as shown in FIG. Fig. 9A As best shown in , segment 57 can have sidewalls 64 and 65 disposed adjacent to each other and together defining facets of edge coupler 55, sidewall 66 disposed adjacent to one of segments 58, and sidewalls 67, 68 connecting sidewalls 64, 65 with sidewall 66. In a representative example, sidewalls 64, 65, 66, 67, 68 surrounding segment 57 have a pentagonal or pentagonal shape. Sidewalls 64, 65, 66, 67, 68 can extend in a vertical direction from dielectric layer 16 to top surface 63. Sidewalls 64, 65, 66, 67, 68 can intersect at respective corners. In an embodiment, the facets of edge coupler 55 can include exclusively sidewalls 64, 65. In an embodiment, the facets of edge coupler 55 can be asymmetric in a lateral direction relative to longitudinal axis 75.

[0059] Side wall 65 defines a chamfer connecting side wall 64 and side wall 68. Side wall 65 may be formed at an angle similar to interior angle α ( Figure 1 ) is adjacent to the side wall 64, and the side wall 65 may be adjacent to the side wall 64 at an interior angle similar to the interior angle β ( Figure 1 ) is adjacent to the side wall 68. In an embodiment, the inner angle between the side wall 64 and the side wall 65 can be an obtuse angle. In an embodiment, the inner angle between the side wall 65 and the side wall 68 can be an obtuse angle. In an embodiment, both inner angles can be obtuse angles.

[0060] refer to Fig.11 , where like reference numerals refer to Fig. 9 , 9A , 10 and in a subsequent manufacturing stage, a dielectric layer 69 may be formed over the waveguide core 56. The dielectric layer 69 may include a dielectric material such as silicon dioxide. The edge coupler 55 may be embedded in the dielectric layer 69.

[0061] The dielectric material of the dielectric layer 69 is located in the gaps G between adjacent pairs of the segments 57, 58, 60 of the edge coupler 55 so that a metamaterial structure can be defined in which the material constituting the segments 57, 58, 60 has a higher refractive index than the dielectric material of the dielectric layer 69. The metamaterial structure can be treated as a homogeneous material having an effective refractive index intermediate the refractive index of the material constituting the segments 57, 58, 60 and the refractive index of the dielectric material constituting the dielectric layer 69.

[0062] A back end of line stack 70 may be formed on the structure 10. A dielectric layer 72 may be formed that replaces the removed portion of the back end of line stack 70 above the edge coupler 55. A cavity 74 may be formed in the semiconductor substrate 18 adjacent to the edge coupler 55. The back end of line stack 70 may include stacked dielectric layers, wherein each dielectric layer is composed of a dielectric material such as silicon dioxide, silicon nitride, tetraethyl orthosilicate silicon dioxide, or fluorinated tetraethyl orthosilicate silicon dioxide. The dielectric layer 72 may be composed of a homogenous dielectric material such as silicon dioxide. The cavity 74 may include a portion extending below the dielectric layer 16 as an undercut region so that all or a portion of the edge coupler 55 is suspended on the dielectric layer 16 above the undercut region. The undercut region of the cavity 74 may be used to reduce light loss to the semiconductor substrate 18.

[0063] A light source 80 can be placed within the cavity 74. The light source 80 can include a light output 78 that is aligned with the facets of the edge coupler 55 and is configured to provide light in a mode propagation direction toward the facets of the edge coupler 55. In an embodiment, the light output 78 of the light source 80 can be aligned parallel to the longitudinal axis 75 of the edge coupler 55. In an embodiment, the sidewalls 64, 65 ( Fig. 9 , 9A) can face the light output 78 of the light source 80. In an embodiment, light from the light output 78 of the light source 80 can be incident on the side walls 64, 65 of the segment 57. In an embodiment, light from the light source 80 can be incident exclusively on the side walls 64, 65 of the segment 57 of the edge coupler 55 and not on the other side walls 66, 67, 68 of the segment 57. In an embodiment, the light output 78 of the light source 80 can be aligned orthogonal to the side wall 64 and at an angle relative to the side wall 65.

[0064] In an embodiment, the light source 80 may be an optical fiber including a tip inserted into a cavity 74 adjacent to the edge coupler 55. In an embodiment, the optical fiber defining the light source 80 may output light in the infrared wavelength range. In an alternative embodiment, the light source 80 may be a laser chip including a semiconductor laser configured to output light in the infrared wavelength range from the light output 78. In an embodiment, the laser chip may include a laser comprised of a III-V compound semiconductor material. In an embodiment, the laser chip may include an InP / InGaAsP laser configured to generate and emit continuous laser light in the infrared wavelength range. In an alternative embodiment, the light source 80 may include a photon bump having an internal turning mirror and a lensed mirror that collimates and focuses light received from the optical fiber and provides the collimated and focused light to the edge coupler 55.

[0065] refer to Fig.12 And in accordance with embodiments of the present invention, one or more segments 58 of edge coupler 55 adjacent to segment 57 can be configured with sidewalls 88 that provide a chamfer similar to sidewall 65 of segment 57. Sidewalls 89 of each modified segment 58 and the added sidewalls 88 can face toward light output 78 of light source 80. The chamfers of these segments 58 adjacent to the facets defined by sidewalls 64, 65 of segment 57 can enhance the performance improvements provided by segment 57.

[0066] refer to Fig.13 And according to an embodiment of the present invention, the edge coupler 55 of the structure 50 can be configured as an inverted cone 82, and when the light source 80 is added, the inverted cone 82 has a width dimension that increases as the distance from the facet at the top of the inverted cone 82 increases. The facets of the inverted cone 82 include sidewalls 64, 65 that are adjacent at an internal angle, as described above, the internal angle can be an obtuse angle. The inverted cone 82 can have sidewalls 84, 86 adjacent to the sidewall 64, and the sidewall 65 can be adjacent to the sidewall 86 at an internal angle. In an embodiment, the internal angle between the sidewall 65 and the sidewall 86 can be an obtuse angle.

[0067] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0068] References herein to terms modified by approximate language such as "about," "approximately," and "substantially" are not limited to the precise value specified. Approximate language may correspond to the precision of an instrument used to measure the value, and, unless instrument precision is relied upon, may indicate a range of + / - 10% of the stated value.

[0069] References herein to terms such as "vertical," "horizontal," and the like are by way of example and not limitation to establish a reference frame. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to directions in a reference frame that are perpendicular to the horizontal direction just defined. The term "lateral" refers to a direction in a reference frame that is within a horizontal plane.

[0070] A feature that is "connected" or "coupled" to or "connected to" or "coupled to" another feature may be directly connected or coupled to or to the other features, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to or "directly connected to" or "directly coupled to" another feature if there are no intermediate features. A feature may be "indirectly connected" or "indirectly coupled" to or "indirectly connected to" or "indirectly coupled to" another feature if there is at least one intermediate feature. A feature that is "on" or "contacting" another feature may be directly on or in direct contact with the other features, or one or more intermediate features may be present. A feature may be "directly on" or "directly in contact with" another feature if there are no intermediate features. A feature may be "indirectly on" or "indirectly in contact with" another feature if there is at least one intermediate feature. Different features may "overlap" if one feature extends over another feature and covers a portion of another feature.

[0071] The description of various embodiments of the present invention is given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are intended to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a photonic chip, the structure comprising: substrate; a photodetector on the substrate, the photodetector comprising a light absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjacent to the first sidewall at a first interior angle, the first sidewall being inclined relative to the longitudinal axis, and the second sidewall being oriented transverse to the longitudinal axis; as well as A first waveguide core includes tapered portions of the first sidewall and the second sidewall adjacent to the light absorbing layer.

2. The structure according to claim 1, wherein: The tapered section of the first waveguide core has a longitudinal axis aligned with the longitudinal axis of the light absorbing layer.

3. The structure according to claim 2, wherein: The longitudinal axis of the tapered section of the first waveguide core is aligned parallel to the longitudinal axis of the light absorbing layer.

4. The structure according to claim 1, wherein: The tapered section of the first waveguide core has a longitudinal axis aligned at an acute angle relative to the longitudinal axis of the light absorbing layer.

5. The structure according to claim 1, wherein: The first interior angle is an obtuse angle.

6. The structure according to claim 5, wherein: The light absorbing layer has a third side wall, the first side wall adjoins the third side wall at a second inner angle, and the second inner angle is an obtuse angle.

7. The structure according to claim 5, wherein: The light absorbing layer has a third side wall, the second side wall is adjacent to the third side wall at a second inner angle, and the second inner angle is a right angle.

8. The structure according to claim 1, wherein: The light absorbing layer has a third sidewall and a fourth sidewall adjacent to the third sidewall at a second interior angle, the third sidewall is inclined relative to the longitudinal axis, and the fourth sidewall is oriented transverse to the longitudinal axis.

9. The structure according to claim 8, wherein: The first interior angle and the second interior angle are obtuse angles.

10. The structure according to claim 8, wherein: The light absorbing layer has a fifth sidewall, the fifth sidewall adjoins the first sidewall at a third inner angle, the fifth sidewall adjoins the third sidewall at a fourth inner angle, and the third inner angle and the fourth inner angle are obtuse angles.

11. The structure according to claim 8, further comprising: A second waveguide core includes tapered portions of the third sidewall and the fourth sidewall adjacent to the light absorbing layer.

12. The structure according to claim 1, wherein: The light absorbing layer includes germanium.

13. The structure of claim 1, further comprising: a spacer connected to the tapered section of the first waveguide core; a first doped region in the pad, the first doped region having a first conductivity type; as well as a second doped region in the pad, the second doped region having a second conductivity type opposite to the first conductivity type, The light absorbing layer is disposed on a portion of the pad located between the first doping region and the second doping region, and the portion of the pad includes an intrinsic semiconductor material.

14. A structure for a photonic chip, the structure comprising: substrate; as well as An edge coupler on the substrate, the edge coupler comprising a longitudinal axis and a facet, the facet having a first sidewall and a second sidewall adjacent to the first sidewall at a first interior angle, the first sidewall being inclined relative to the longitudinal axis, and the second sidewall being oriented transverse to the longitudinal axis.

15. The structure according to claim 14, further comprising: A light source is positioned adjacent to the facet of the edge coupler, the light source having a light output configured to provide light in a mode propagation direction toward the edge coupler.

16. The structure according to claim 15, wherein: The light output is aligned parallel to the longitudinal axis of the edge coupler.

17. The structure of claim 15, wherein: The edge coupler includes an inverted cone adjacent to the light source, and the first side wall and the second side wall are disposed at a top end of the inverted cone.

18. The structure of claim 15, wherein: The edge coupler includes a first segment adjacent to the light source, and the first sidewall and the second sidewall are disposed on the first segment.

19. The structure of claim 18, wherein: The first interior angle is an obtuse angle, the edge coupler includes a second segment adjacent to the first segment, the second segment has a third side wall and a fourth side wall adjacent to the third side wall at a second interior angle, the third side wall is inclined relative to the longitudinal axis, the fourth side wall is oriented transverse to the longitudinal axis, and the second interior angle is an obtuse angle.

20. A method for forming a photonic chip, the method comprising: forming a light absorbing layer of a light detector on a substrate, wherein the light absorbing layer has a longitudinal axis, a first sidewall, and a second sidewall adjacent to the first sidewall at an inner angle, the first sidewall is inclined relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis; as well as A waveguide core is formed, the waveguide core including tapered sections of the first sidewall and the second sidewall adjacent to the light absorbing layer.

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