Semiconductor processing method, electronic device, and computer-readable storage medium

Abstract

The application belongs to the technical field of semiconductor, and discloses a semiconductor processing method, an electronic device and a computer readable storage medium. After the front layer photolithography of a wafer is completed, the wafer warping information is obtained, and the position offset of the target overlay alignment mark is calculated based on the wafer warping information, so that the position information of the target overlay alignment mark is accurately positioned. In the subsequent process, the position offset can be used, specifically, the position offset can be used to compensate the position of the overlay alignment mark of the wafer layer during the photolithography of the wafer layer, so as to reduce the overlay error. Moreover, the original photolithography process flow does not need to be changed, and there is no increase or change of materials.

Description

[0001] This application is a divisional application filed on November 29, 2023, with application number 2023116270419 and invention title "Method for detecting position offset of overlay alignment marks and semiconductor processing method". Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a method, apparatus, electronic device, storage medium, and semiconductor processing method for detecting the position offset of an overlay alignment mark. Background Technology

[0003] In semiconductor R&D and mass production, OVL (Overlay error) has always been an important indicator for monitoring in lithography.

[0004] OVL (Order Value Lift) refers to the positional offset between two adjacent patterns on a wafer. Wafer manufacturing involves stacking multiple circuit layers. Alignment marks are placed on each layer of the wafer. The photolithography process uses these alignment marks to locate and expose the wafer, thus aligning the patterns between adjacent layers. However, the degree of wafer warpage varies at each stage of the wafer manufacturing process. This causes the position of the alignment marks to change with the wafer's warpage. Because the exposure machine cannot accurately identify the actual alignment mark information in real time, the exposure accuracy is affected, ultimately leading to a deterioration in OVL. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a method, apparatus, electronic device, storage medium, and semiconductor processing method for detecting the position offset of an overlay alignment mark.

[0006] According to one aspect of the embodiments of this application, a method for detecting the position offset of an overlay alignment mark is disclosed, the method comprising:

[0007] After the front layer photolithography of the wafer is completed, the warpage information of the wafer is obtained;

[0008] Based on the warpage information of the wafer, the position offset of the target overlay alignment mark is calculated, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer or an overlay alignment mark expected to be formed on the current layer of the wafer;

[0009] Output the position offset.

[0010] In some embodiments, calculating the positional offset of the target overlay alignment mark based on the warp information of the wafer includes:

[0011] Obtain the baseline position of the target overlay alignment mark;

[0012] Based on the warpage information of the wafer and the baseline position of the target overlay alignment mark, the position offset of the target overlay alignment mark is calculated.

[0013] In some embodiments, the wafer warpage information includes a critical position located between a warped position and a non-warped position of the wafer and multiple sampling point positions, wherein the multiple sampling points are distributed along the radial spacing of the wafer and located between the critical position and the edge position of the wafer;

[0014] The step of calculating the position offset of the target overlay alignment mark based on the warp information of the wafer and the baseline position of the target overlay alignment mark includes:

[0015] Based on the critical position and the positions of the multiple sampling points, curve fitting is performed to obtain the corresponding curve function;

[0016] Construct an arc length expression based on the curve function;

[0017] Based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression, the position offset of the target overlay alignment mark is obtained, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer.

[0018] In some embodiments, constructing the arc length expression based on the curve function includes:

[0019] The distance between the critical position and the center position of the wafer is used as the lower limit of integration, and the actual distance between the target overlay alignment mark and the center position of the wafer after warping is used as the upper limit of integration. An arc length integral formula is constructed based on the curve function.

[0020] The step of obtaining the position offset of the target overlay alignment mark based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression includes:

[0021] The distance between the critical position and the baseline position of the target overlay alignment mark is set as the arc length integral value;

[0022] Based on the arc length integral value and the arc length integral formula, the position offset of the target overlay alignment mark is obtained.

[0023] In some embodiments, obtaining the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula includes:

[0024] Based on the arc length integral value and the arc length integral formula, the actual distance between the target overlay alignment mark and the center position of the wafer under the warping information is obtained;

[0025] Substituting the actual distance into the curve function, the actual position of the target overlay alignment mark under the warping information is obtained;

[0026] The displacement vector is obtained based on the actual position and the baseline position, and is used as the position offset of the target overlay alignment mark.

[0027] In some embodiments, the number of sampling points is at least three, and the distance between adjacent sampling points is equal.

[0028] In some embodiments, calculating the positional offset of the target overlay alignment mark based on the warp information of the wafer and the baseline position of the target overlay alignment mark includes:

[0029] Based on the baseline position and the deformation angle of the wafer, the position offset of the target overlay alignment mark is obtained; wherein, the target overlay alignment mark is the overlay alignment mark expected to be formed on the current layer of the wafer.

[0030] In some embodiments, the wafer warpage information includes the wafer deformation height; obtaining the position offset of the target overlay alignment mark based on the baseline position and the wafer deformation angle includes:

[0031] Obtain the horizontal distance between the baseline position and the center position of the wafer;

[0032] Based on the baseline position, the deformation height, and the horizontal distance, the position offset of the target overlay alignment mark is obtained.

[0033] In some embodiments, obtaining the positional offset of the target overlay alignment mark based on the baseline position, the deformation height, and the horizontal distance includes:

[0034] Based on relational The positional offset of the target overlay alignment mark in a first direction in the horizontal direction is obtained, where X represents the positional offset in the first direction, Tx represents the position coordinate in the first direction, h represents the deformation height, and R represents the horizontal distance;

[0035] Based on relational The positional offset of the target overlay alignment mark in the second direction in the horizontal direction is obtained, where Y represents the positional offset in the second direction, Ty represents the positional coordinate in the second direction, h represents the deformation height, and R represents the horizontal distance.

[0036] According to one aspect of the embodiments of this application, a device for detecting the position offset of an overlay alignment mark is disclosed. The device includes a warpage acquisition module, an offset calculation module, and an offset output module. The warpage acquisition module is used to acquire warpage information of the wafer after the previous layer photolithography is completed. The offset calculation module is used to calculate the position offset of a target overlay alignment mark based on the warpage information of the wafer. The target overlay alignment mark is an overlay alignment mark formed on the previous layer of the wafer or an overlay alignment mark expected to be formed on the current layer of the wafer. The offset output module is used to output the position offset.

[0037] According to one aspect of the embodiments of this application, an electronic device is disclosed, which includes one or more processors and a memory, the memory being used to store one or more computer programs, which, when executed by the one or more processors, cause the processors to implement the position offset detection method for overlay alignment marks as described above.

[0038] According to one aspect of the embodiments of this application, a computer-readable storage medium is disclosed, the computer-readable storage medium storing computer-readable instructions, which, when executed by a computer processor, cause the computer to perform the position offset detection method of the overlay alignment mark as described above.

[0039] The technical solutions provided by the embodiments of this application have at least the following beneficial effects:

[0040] The scheme disclosed in this application, after completing the photolithography of the previous layer of the wafer, obtains the wafer's warpage information and calculates the position offset of the target overlay alignment mark based on the wafer's warpage information, thereby achieving precise positioning of the target overlay alignment mark's position information. This position offset can be used in subsequent processes; specifically, it can be used to compensate for the position of the overlay alignment mark on the current layer of the wafer during photolithography, thereby reducing overlay errors. Furthermore, this application does not require changes to the original photolithography process flow, and there is no addition or alteration of materials.

[0041] According to one aspect of the embodiments of this application, a semiconductor processing method is disclosed, the semiconductor processing method comprising:

[0042] Photolithography is performed on the front layer of the wafer;

[0043] Perform the aforementioned method for detecting the position offset of the overlay alignment marks;

[0044] Based on the position offset output by the position offset detection method, the wafer layer is subjected to photolithography.

[0045] In some embodiments, when performing the position offset detection method, obtaining the warpage information of the wafer includes:

[0046] Warp information of multiple locations in the wafer is obtained, the multiple locations being distributed at circumferential and / or radial spacings in the wafer, and each location being associated with a target overlay alignment mark;

[0047] When executing the position offset detection method, the baseline position of the target overlay alignment mark associated with the plurality of position points is obtained; and based on the warp information of each position point and the baseline position of the target overlay alignment mark associated with the position point, the position offset of the target overlay alignment mark associated with the position point is obtained.

[0048] The scheme disclosed in this application obtains wafer warpage information after the photolithography of the front layer of the wafer is completed and before the photolithography of the current layer of the wafer is performed. Based on the wafer warpage information, the position offset of the target overlay alignment mark is calculated. Then, the photolithography of the current layer of the wafer is performed based on the position offset. Specifically, the position of the overlay alignment mark of the current layer of the wafer can be compensated based on the position offset. This can compensate for the position offset of the overlay alignment mark caused by wafer warpage, so that the overlay alignment mark of the current layer of the wafer is accurately aligned with the overlay alignment mark of the front layer of the wafer, reducing overlay error.

[0049] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0051] Figure 1 The alignment of the overlay alignment marks under ideal conditions and the OVL distribution diagram are shown;

[0052] Figure 2 This diagram illustrates the warpage of a wafer at different stages of the wafer fabrication process.

[0053] Figure 3 The alignment of the overlay alignment marks and the OVL distribution diagram are shown in the case of warping.

[0054] Figure 4A flowchart of a method for detecting the position offset of an overlay alignment mark according to an embodiment of this application is shown;

[0055] Figure 5 A flowchart illustrating the position offset calculation steps of Embodiment 1 of this application is shown;

[0056] Figure 6 A schematic diagram illustrating the position offset calculation steps of Embodiment 1 of this application is shown;

[0057] Figure 7 A flowchart illustrating the position offset calculation steps of Embodiment 2 of this application is shown;

[0058] Figure 8 A schematic diagram illustrating the principle steps for calculating the position offset in Embodiment 2 of this application is shown;

[0059] Figure 9 This invention provides a block diagram illustrating the composition of a device for detecting the position offset of an overlay alignment mark according to an embodiment of this application.

[0060] Figure 10 A block diagram of an electronic device according to an embodiment of this application is shown;

[0061] Figure 11 This diagram illustrates a computer system architecture block diagram for implementing some embodiments of this application;

[0062] Figure 12 A flowchart illustrating a semiconductor processing method according to an embodiment of this application is shown;

[0063] Figure 13 A schematic diagram of a semiconductor processing method according to an embodiment of this application is shown.

[0064] The annotations in the attached figures are explained as follows:

[0065] 101. Wafer; 1011. Fan-shaped area; 102. Previous layer overlay alignment mark; 103. Current layer overlay alignment mark; 104. Target overlay alignment mark; 900. Overlay alignment mark position offset detection device; 901. Warp acquisition module; 902. Offset calculation module; 903. Offset output module; 1000. Electronic device; 1001. Processor; 1002. Memory; 1100. Computer system; 1101. CPU; 1102. ROM; 1103. RAM; 1104. Bus; 1105. I / O interface; 1106. Input section; 1107. Output section; 1108. Storage section; 1109. Communication section; 1110. Driver; 1111. Removable medium. Detailed Implementation

[0066] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this application will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0067] In the description of this application, it should be understood that the terms "center", "front", "rear", "left", "right", "vertical", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0068] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0069] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0070] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0071] Wafer manufacturing involves stacking multiple circuit layers. Alignment marks are set on each layer of the wafer. The photolithography process uses these alignment marks to perform exposure, thus aligning the patterns between adjacent layers. Typically, when wafer 101 has no warpage or minimal warpage, the photolithography equipment processes the wafer's current layer according to a set reference position. Each alignment mark 103 of the current layer corresponds one-to-one with each alignment mark 102 of the preceding layer. Figure 1As shown in (a). In this case, the OVL distribution at various locations on the wafer is as follows. Figure 1 As shown in (b), the length of the arrow indicates the size of the OVL, which is determined by... Figure 1 As shown in (b), the OVL size is almost equal at all locations on the wafer, and the OVL is relatively small.

[0072] However, in actual wafer fabrication processes, the influence of film stack and pattern leads to inconsistent warpage at each stage of the wafer fabrication process. Figure 2 As shown, the wafer's warpage degree changes continuously from FEOL (Front-end-of-line) to MOL (Middle-of-line) and up to BEOL (Back-end-of-line).

[0073] The position of the previous layer overlay alignment mark 102 changes with the warpage of wafer 101. If the warpage of wafer 101 is not considered during photolithography of the current layer, the current layer overlay alignment mark 103 may not be aligned with the previous layer overlay alignment mark 102. Figure 3 As shown in (a). In this case, the OVL distribution at various locations on the wafer is as follows. Figure 3 As shown in (b), the length of the arrow indicates the size of the OVL, which is determined by... Figure 3 As shown in (b), along the radial direction of the wafer, the OVL gradually increases at various locations on the wafer, meaning the OVL gradually deteriorates. This is because the warping near the edge of the wafer is more severe than that near the center. Corresponding to Figure 3 In (b), a more intuitive OVL distribution diagram is shown below. Figure 3 As shown in (c).

[0074] A large OVL (Out-of-Vehicle Least) can affect the lithography process window margin, leading to WAT (Wafer Acceptance Test) parameter drift, such as resistance drift, voltage drift, and current drift. With an even larger OVL, chips made from this wafer may not function properly, resulting in yield loss, which in turn increases costs. Furthermore, as the semiconductor industry increasingly demands miniaturization, functional integration, and large-capacity storage, pattern shrinkage promotes an increase in structural units on the effective area, causing a significant reduction in the OVL process window for critical layers. Therefore, it is necessary to control the overlay error to a minimum.

[0075] However, existing technologies generally only measure overlay error. When the overlay error is too large, the wafer fabrication process is stopped or the manufactured wafer is scrapped. It is impossible to accurately control the overlay error to a minimum during the wafer fabrication process based on the OVL process window. Therefore, this application provides a method for detecting the positional offset of overlay alignment marks that can accurately locate the position information of the overlay alignment marks without changing the original lithography process flow or adding or altering materials. This provides the lithography equipment with precise positional information for the overlay alignment marks, ultimately reducing overlay error.

[0076] The method for detecting the position offset of the overlay alignment mark provided in this application will be described in detail below with reference to specific embodiments.

[0077] Figure 4 A flowchart illustrating a method for detecting the position offset of an overlay alignment mark according to an embodiment of this application is shown. (See attached document.) Figure 4 As shown, the method for detecting the position offset of the alignment mark includes at least a warping information acquisition step, a position offset calculation step, and a position offset output step, which correspond to steps S110 to S130 below, and are described in detail below:

[0078] In step S110, after the front layer photolithography of the wafer is completed, the warpage information of the wafer is obtained.

[0079] The wafer warpage information can be data that directly characterizes the wafer's warpage, such as the wafer's deformation angle and deformation height. The deformation angle refers to the angle between the perpendicular line to the tangent at the position corresponding to the target overlay alignment mark and the normal to the wafer's flat surface. Figure 8 The included angle θ is shown, where L1 represents the tangent line at the position corresponding to the target overlay alignment mark, F1 represents the perpendicular line to the tangent line L1, and F2 represents the normal line of the wafer plane; the included angle θ is also equal to the angle between the tangent line at the position corresponding to the target overlay alignment mark and the horizontal line in the wafer plane, where L2 represents the horizontal line. The deformation height refers to the warpage height of the wafer at the position corresponding to the target overlay alignment mark, such as... Figure 8 The h shown.

[0080] Wafer warpage information can also be data that indirectly characterizes the warpage of a wafer, such as the critical position between the warped and non-warped locations, like... Figure 6 Point Q0, as shown in (a), is a location such as the point between the critical position and the edge of the wafer. Figure 6 As shown in (a), point Q1 to Q n point.

[0081] In step S120, the position offset of the target overlay alignment mark is calculated based on the wafer warpage information.

[0082] The target overlay alignment mark can be an overlay alignment mark formed on the front layer of the wafer, or it can be an overlay alignment mark that is expected to be formed on the current layer of the wafer.

[0083] In one embodiment, in step S120, the positional offset of the target overlay alignment mark is calculated based on the baseline position of the target overlay alignment mark. Understandably, the baseline position is the positional information used by the lithography equipment during lithography processing. In conventional techniques, the positional offset of the target overlay alignment mark is not considered; the lithography equipment directly performs lithography processing based on this baseline position.

[0084] In detail, step S120 includes: first, obtaining the baseline position of the target overlay alignment mark; then, based on the wafer warpage information and the baseline position of the target overlay alignment mark, calculating the position offset of the target overlay alignment mark.

[0085] It should be noted that the wafer warpage information can be the warpage information corresponding to the position point associated with the target overlay alignment mark, or it can include the warpage information corresponding to the position point associated with the target overlay alignment mark and the warpage information corresponding to other position points on the wafer. In this step S120, the position offset of the target overlay alignment mark is calculated based on the warpage information corresponding to the position point associated with the target overlay alignment mark and the baseline position of the target overlay alignment mark.

[0086] In one embodiment, the wafer warpage information includes a critical location between a warped and non-warped position on the wafer and multiple sampling point locations, wherein the multiple sampling points are distributed along the radial spacing of the wafer and located between the critical location and the edge location of the wafer. See also... Figure 5 As shown, in this embodiment, step S120 includes steps S210 to S230, which are described in detail below:

[0087] In step S210, curve fitting is performed based on the critical position and the positions of multiple sampling points to obtain the corresponding curve function.

[0088] Multiple sampling points can be at least two sampling points. In this case, curve fitting is performed using three location points: two sampling points and the critical position. To improve the accuracy of the curve fitting results, more sampling points can be selected, such as six, eight, ten, or more sampling points, while considering both data computation and curve fitting efficiency.

[0089] To improve the accuracy of the fitting results, the multiple sampling points are uniformly distributed along the radial direction of the wafer. In this embodiment, the number of sampling points is three or more, for example, ten, and the distance between adjacent sampling points is equal.

[0090] In detail, curve fitting based on critical positions and multiple sampling point positions can be performed using the least squares method, which fits the curve by minimizing the sum of squares of the errors from the data points to the fitted curve; it can also be performed using spline interpolation, which fits the curve by creating a smooth curve between the data points; or it can be performed using polynomial regression, etc., which will not be described in detail here.

[0091] In one embodiment, such as Figure 6 As shown in (a), multiple sampling points are from point Q1 to Q. n Points, where n is greater than 2, the coordinates of the critical position Q0 are (r, a, z), based on the critical position Q0 and multiple sampling points Q1 to Q n Curve fitting is performed at the point location to obtain the curve function z(x).

[0092] In step S220, an arc length expression is constructed based on the curve function.

[0093] In one embodiment, step S220 specifically involves: using the distance between the critical position and the center position of the wafer as the lower limit of integration, and using the actual distance between the target overlay alignment mark and the center position of the wafer after warping as the upper limit of integration, an arc length integral formula is constructed based on the curve function. The constructed arc length integral formula is shown below:

[0094]

[0095] Where r represents the lower limit of integration, i.e., the distance between the critical position and the center position O of the wafer; R′ represents the upper limit of integration, i.e., the actual distance between the target overlay alignment mark and the center position O of the wafer after warping; and z′ represents the upper limit of integration. 2 (r) represents the square of the derivative of z(r), which is the derivative of the curve function z(x) obtained in step S210, and its square, which is z′. 2 (r), where dr represents the differential of r. As the integrand, s′ represents the integral value of the arc length, which is the curve length from point Q0 (r, a, z) corresponding to r to point P' (R′, a, z′) corresponding to R′.

[0096] In step S230, the position offset of the target alignment mark is obtained based on the distance and arc length expression between the critical position and the baseline position of the target alignment mark.

[0097] Among them, the target overlay alignment mark is the overlay alignment mark formed on the front layer of the wafer.

[0098] In one embodiment, step S230 includes: setting the distance between the critical position and the baseline position of the target overlay alignment mark as an arc length integral value; and obtaining the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula.

[0099] As explained above, the baseline position of the target overlay alignment mark is the positional information used by the photolithography equipment during photolithography. In the absence of wafer warping, this baseline position is the actual position of the target overlay alignment mark. Figure 6 Point P (R, a, z) is shown in (a).

[0100] Before and after wafer warping, the distance from the same point to the critical position is equal. That is, the distance from the critical position Q0 (r, a, z) to the baseline position P (R, a, z) is equal to the distance from the critical position Q0 (r, a, z) to the actual position P' (R′, a, z′). Therefore, the distance s from the critical position Q0 (r, a, z) to the baseline position P (R, a, z) is equal to s′ in the arc length integral formula. That is, it satisfies the expression s′=s=Rr. Combining this expression and the arc length integral formula, R′ can be obtained.

[0101] In this embodiment, by constructing an arc length integral formula and based on the fact that the arc length remains unchanged before and after warping, the distance between the actual position of the target overlay alignment mark and the center position of the wafer after warping can be obtained, thereby further obtaining the actual position of the target overlay alignment mark after warping. The data calculation is simple and efficient.

[0102] In one embodiment, based on the arc length integral value and the arc length integral formula, the actual distance between the target overlay alignment mark and the center position O of the wafer under the warp information is obtained; substituting the actual distance into the curve function, the actual position P' (R′, a, z′) of the target overlay alignment mark under the warp information is obtained; the displacement vector is obtained based on the actual position and the baseline position. This serves as the position offset of the target overlay alignment mark.

[0103] This method allows for the acquisition of three-dimensional positional offsets, enabling accurate positioning of the target alignment mark in three-dimensional space. Regarding the obtained positional offsets... Subsequent data processing can be performed to determine the position offset. Dimensionality reduction is performed, decomposing the material into horizontal and vertical offsets. The horizontal offset is then compensated for during the photolithography process on the wafer layer. During exposure, the focusing system of the photolithography equipment must maintain focus on the area to be exposed on the wafer surface. Once the vertical offset is obtained, the focusing position of the photolithography equipment's light matrix can be adjusted using a lens, thus resolving the defocusing problem caused by z-direction deformation.

[0104] It should be noted that in the aforementioned embodiments, in the coordinates (r, a, z) of point Q0, (R, a, z) of point P, and (R′, a, z′) of point P', 'a' represents the angle of the sector region corresponding to the arc length S, such as... Figure 6 As shown in (b), wafer 101 has 360 degrees. A sector region 1011 corresponding to 0° to 5° is cut off. The positional offset of the target overlay alignment mark 104 in this region is calculated, and a is 5°. Here, z represents the coordinate in the vertical direction.

[0105] In one embodiment, the positional offset of the target overlay alignment mark is obtained based on the baseline position of the target overlay alignment mark and the deformation angle of the wafer. The target overlay alignment mark is the overlay alignment mark expected to be formed on the current layer of the wafer.

[0106] By predicting the baseline position of the overlay alignment mark formed on the wafer layer and combining it with the wafer deformation angle, the position offset of the baseline position of the target overlay alignment mark relative to the correct position under the warping information is obtained. The calculation method of the position offset is simple and easy to implement.

[0107] In one embodiment, the deformation angle is characterized by the deformation height and the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer. This eliminates the need to detect the deformation angle, making the determination of the deformation height and horizontal distance simpler and simplifying the calculation of the position offset. See also... Figure 7 As shown, in this embodiment, step S120 includes steps S310 to S320, which are described in detail below:

[0108] In step S310, the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer is obtained.

[0109] As shown in Figure 8, the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer is, in other words, the distance R between the position coordinate Tx of the baseline position of the target overlay alignment mark in the first direction and the position coordinate Tox of the center position O of the wafer in the first direction. Here, the first direction is also the x-axis direction.

[0110] In step S320, the position offset of the target overlay alignment mark is obtained based on the baseline position, deformation height, and horizontal distance of the target overlay alignment mark.

[0111] In one embodiment, based on relational Obtain the positional offset of the target overlay alignment mark in the first horizontal direction. Here, X represents the positional offset of the target overlay alignment mark in the first horizontal direction, Tx represents the position coordinates of the baseline position of the target overlay alignment mark in the first direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer.

[0112] Based on relational Obtain the positional offset of the target overlay alignment mark in a second direction within the horizontal direction. Here, Y represents the positional offset of the target overlay alignment mark in the second direction, Ty represents the position coordinates of the baseline position of the target overlay alignment mark in the second direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer. This second direction is also the y-axis direction.

[0113] This method obtains the horizontal offset X and Y of the target overlay alignment mark. The calculation of the position offset is simple, and it enables accurate positioning of the horizontal position information of the target overlay alignment mark.

[0114] In step S130, the position offset is output.

[0115] That is, the position offset calculated in step S120 is output to the target object, such as a lithography device or other devices besides the lithography device.

[0116] In summary, the solution disclosed in this application, after completing the photolithography of the previous layer of the wafer, obtains the wafer warpage information and calculates the position offset of the target overlay alignment mark based on the wafer warpage information, thus achieving precise positioning of the target overlay alignment mark. This position offset can be used in subsequent processes, specifically, during photolithography of the current layer of the wafer, to compensate for the position of the overlay alignment mark on that layer, thereby reducing overlay errors. Furthermore, this application does not require changes to the original photolithography process flow, and there is no addition or alteration of materials.

[0117] See next. Figure 9 As shown, this embodiment provides a position offset detection device 900 for overlay alignment marks. The position offset detection device 900 mainly includes a warpage acquisition module 901, an offset calculation module 902, and an offset output module 903.

[0118] The warpage acquisition module 901 is used to acquire the warpage information of the wafer after the front-layer photolithography is completed.

[0119] The offset calculation module 902 is used to calculate the position offset of the target overlay alignment mark based on the wafer warpage information, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer or an overlay alignment mark expected to be formed on the current layer of the wafer.

[0120] In one embodiment, the offset calculation module 902 is configured to: obtain the baseline position of the target overlay alignment mark; and calculate the position offset of the target overlay alignment mark based on the wafer warpage information and the baseline position of the target overlay alignment mark.

[0121] In one embodiment, the wafer warpage information includes a critical position located between the warped and non-warped positions of the wafer and multiple sampling point positions, wherein the multiple sampling points are distributed along the radial spacing of the wafer and located between the critical position and the edge position of the wafer; the offset calculation module 902 is configured to: perform curve fitting based on the critical position and the multiple sampling point positions to obtain a corresponding curve function; construct an arc length expression based on the curve function; and obtain the position offset of the target overlay alignment mark based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer.

[0122] In one embodiment, the offset calculation module 902 is configured to: construct an arc length integral formula based on a curve function, using the distance between the critical position and the center position of the wafer as the lower limit of integration and the actual distance between the target overlay alignment mark and the center position of the wafer after warping as the upper limit of integration; and set the distance between the critical position and the baseline position of the target overlay alignment mark as the arc length integral value; and obtain the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula.

[0123] In one embodiment, the offset calculation module 902 is configured to: obtain the actual distance between the target overlay alignment mark and the center position of the wafer under the warping information based on the arc length integral value and the arc length integral formula; substitute the actual distance into the curve function to obtain the actual position of the target overlay alignment mark under the warping information; and obtain the displacement vector based on the actual position and the baseline position as the position offset of the target overlay alignment mark.

[0124] In one embodiment, the number of sampling points is at least three, and the distance between adjacent sampling points is equal.

[0125] In one embodiment, the offset calculation module 902 is configured to: obtain the position offset of the target overlay alignment mark based on the baseline position and the deformation angle of the wafer; wherein the target overlay alignment mark is an overlay alignment mark expected to be formed on the current layer of the wafer.

[0126] In one embodiment, the wafer warpage information includes the wafer deformation height; the offset calculation module 902 is configured to: obtain the horizontal distance between the baseline position and the center position of the wafer; and obtain the position offset of the target overlay alignment mark based on the baseline position, deformation height and horizontal distance.

[0127] In one embodiment, the offset calculation module 902 is configured to: be based on a relational expression Obtain the position offset of the target overlay alignment mark in the first direction in the horizontal direction, where X represents the position offset of the target overlay alignment mark in the first direction in the horizontal direction, Tx represents the position coordinate of the baseline position of the target overlay alignment mark in the first direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer.

[0128] Based on relational Obtain the positional offset of the target overlay alignment mark in the second direction of the horizontal direction. Here, Y represents the positional offset of the target overlay alignment mark in the second direction of the horizontal direction, Ty represents the position coordinates of the baseline position of the target overlay alignment mark in the second direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer.

[0129] The offset output module 903 is used to output the position offset calculated by the offset calculation module 902.

[0130] The specific implementation process of the functions and roles of each module in the above-mentioned overlay alignment mark position offset detection device 900 is detailed in the implementation process of the corresponding steps in the above-mentioned overlay alignment mark position offset detection method, and will not be repeated here.

[0131] See Figure 10 As shown, this embodiment provides an electronic device 1000, which includes one or more processors 1001 and a memory 1002. The memory 1002 is used to store one or more programs. When one or more programs are executed by one or more processors 1001, the electronic device 1000 implements the position offset detection method of the overlay alignment mark of this application.

[0132] It should be noted that electronic device 1000 can be a lithography device or other devices besides a lithography device.

[0133] Figure 11 The diagram shows a computer system architecture block diagram for implementing some embodiments of this application. It should be noted that... Figure 11 The computer system shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0134] like Figure 11 As shown, the computer system 1100 includes a CPU (Central Processing Unit) 1101, which can perform various appropriate actions and processes according to a program stored in ROM (Read-Only Memory) 1102 or a program loaded from storage portion 1108 into RAM (Random Access Memory) 1103, such as executing the position offset detection method for overlay alignment marks in the above embodiment. Various programs and data required for system operation are also stored in RAM 1103. The CPU 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. An I / O (Input / Output) interface 1105 is also connected to bus 1104.

[0135] The following components are connected to I / O interface 1105: an input section 1106 including a keyboard, mouse, etc.; an output section 1107 including CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), etc., and speakers, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to I / O interface 1105 as needed. Removable media 1111, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1110 as needed so that computer programs read from them can be installed into storage section 1108 as needed.

[0136] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing all or part of the steps shown in the flowchart of the method for detecting the position offset of overlay alignment marks. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1109, and / or installed from removable medium 1111. When the computer program is executed by central processing unit (CPU) 1101, it performs various functions defined in the system of this application.

[0137] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. The transmitted data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0139] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0140] In another aspect, this application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to implement the methods described in the above embodiments.

[0141] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0142] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of this application.

[0143] See next. Figure 12 As shown, this embodiment provides a semiconductor processing method, which includes at least a wafer pre-layer photolithography step, a position offset detection step, and a wafer current-layer photolithography step, corresponding to steps S410 to S430 below, which are described in detail below:

[0144] In step S410, the front layer of the wafer is subjected to photolithography.

[0145] Among them, the wafer front layer refers to the layer that has undergone photolithography before the wafer current layer, and the wafer current layer refers to the layer that will undergo photolithography next.

[0146] In step S420, the aforementioned method for detecting the position offset of the overlay alignment mark is performed to obtain the position offset of the target overlay alignment mark.

[0147] The specific execution process of step S420 can be found in the foregoing description, and will not be repeated here.

[0148] Among them, it can be adopted Figure 5 The embodiment shown calculates the position offset of the target overlay alignment mark, which can also be achieved by using... Figure 7 The illustrated embodiment calculates the positional offset of the target overlay alignment mark. Specifically, in cases where the wafer's layer composition is relatively simple and warpage is slight, the following method is employed. Figure 7 The illustrated embodiment calculates the positional offset of the target overlay alignment mark. Since only a two-dimensional positional offset is obtained, the calculation process is simpler. However, in cases where the wafer's layer composition is complex and warping is severe, [the following method is used]. Figure 5 The embodiment shown calculates the positional offset of the target overlay alignment mark, which can obtain the three-dimensional positional offset, helping to control the overlay error to a smaller value.

[0149] In one embodiment, to minimize overlay errors, the position offset detection method detects the position offsets of multiple target overlay alignment marks, each corresponding to a different position point on the wafer. In this embodiment, when acquiring wafer warpage information, warpage information of multiple position points on the wafer is acquired, each position point being associated with a target overlay alignment mark. These multiple position points can be distributed along the circumferential spacing of the wafer, along the radial spacing of the wafer, or along both the circumferential and radial spacings; that is, the multiple position points include multiple position points distributed along the circumferential spacing of the wafer and multiple position points distributed along the radial spacing of the wafer. In this embodiment, the baseline positions of the target overlay alignment marks associated with the multiple position points are acquired; and based on the warpage information of each position point and the baseline positions of the target overlay alignment marks associated with the position points, the position offset of the target overlay alignment marks associated with the position points is obtained.

[0150] Specifically, when multiple location points are distributed along the circumferential spacing of the wafer, the positional offset of the target overlay alignment mark associated with different location points in the circumferential direction of the wafer can be obtained; when multiple location points are distributed along the radial spacing of the wafer, the positional offset of the target overlay alignment mark associated with different location points in the radial direction of the wafer can be obtained; when multiple location points are distributed along both the circumferential and radial spacing of the wafer, the positional offset of the target overlay alignment mark associated with different location points in the circumferential direction of the wafer can be obtained; and the positional offset of the target overlay alignment mark associated with different location points in the radial direction of the wafer can also be obtained.

[0151] It should be noted that the correlation between the location point and the target overlay alignment mark can be either a direct correspondence in position or a proximity in position. For example, the associated location point could be one or more locations within a specific wafer region corresponding to the target overlay alignment mark that are close to it. The warpage of the wafer often varies in different circumferential and radial regions. By acquiring warpage information from multiple location points distributed at circumferential and / or radial intervals on the wafer, and obtaining the positional offset of the target overlay alignment mark associated with each location point, the positional information of more overlay alignment marks can be accurately located. This allows for accurate photolithography processing in subsequent processes, reducing overlay errors.

[0152] Of course, in other embodiments, warpage information may be obtained only at one location point on the wafer. In this case, only the position offset of the target overlay alignment mark associated with that one location point will be obtained, and subsequent photolithography steps will only compensate for the position of the target overlay alignment mark associated with that one location point.

[0153] In step S430, the wafer layer is photolithographically processed based on the position offset output in step S420.

[0154] In this case, the position offset output in step S420 can be directly output to the photolithography equipment. In this case, the photolithography equipment directly performs photolithography processing on the target overlay alignment mark corresponding to the current layer of the wafer based on the position offset output in step S420. That is, the baseline position of the target overlay alignment mark corresponding to the current layer of the wafer is compensated based on the position offset. For example, when the position of a target overlay alignment mark is shifted to the left by d1 in the first direction, the baseline position of the target overlay alignment mark is adjusted to the right by d1 to obtain the compensated position, and then photolithography processing is performed based on the compensated position. As another example, when the position of a target overlay alignment mark is shifted forward by d2 in the second direction, the baseline position of the target overlay alignment mark is adjusted backward by d2 to obtain the compensated position, and then photolithography processing is performed based on the compensated position.

[0155] The position offset output in step S420 can also be used to compensate the baseline position of the target overlay alignment mark based on the position offset to obtain the compensated position vector map, which is then output to the photolithography equipment. The photolithography equipment can directly use the position vector map for photolithography processing.

[0156] The front layer of a wafer can be the first layer, or it can be the second, third, etc. For example... Figure 13 As shown, in one embodiment, after photolithography of each layer of the wafer, wafer warpage information is acquired. When the wafer warpage exceeds the requirements, subsequent processing steps are terminated to avoid meaningless processing steps and improve the utilization rate of the photolithography equipment. Before photolithography, step S420 is executed using the acquired wafer warpage information to obtain the position offset of the target overlay alignment mark, and position compensation is performed during photolithography.

[0157] The steps S420 can be performed on multiple layers of the wafer and position compensation can be performed during photolithography, or the steps S420 can be performed on only the critical layers of the wafer and position compensation can be performed during photolithography.

[0158] The scheme disclosed in this application, after photolithography of the previous layer of the wafer and before photolithography of the current layer, obtains the wafer warpage information and calculates the position offset of the target overlay alignment mark based on the wafer warpage information. Then, photolithography is performed on the current layer of the wafer based on the position offset. Specifically, it can compensate for the position offset of the overlay alignment mark on the current layer of the wafer based on the position offset. This can compensate for the position offset of the overlay alignment mark caused by wafer warpage, so that the overlay alignment mark on the current layer of the wafer is accurately aligned with the overlay alignment mark on the previous layer of the wafer, reducing overlay errors. It can be applied to the processing of a series of semiconductors such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), 3D NAND (Flash Memory), and Logic IC (Logic Integrated Circuit).

[0159] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.

Claims

1. A semiconductor processing method, characterized in that, include: Photolithography is performed on the front layer of the wafer; After the front layer photolithography of the wafer is completed, the warpage information of the wafer is obtained. The warpage information of the wafer includes the critical position between the warped position and the non-warped position of the wafer and the position of multiple sampling points. The multiple sampling points are distributed along the radial spacing of the wafer and are located between the critical position and the edge position of the wafer. Obtain the baseline position of the target overlay alignment mark, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer; Based on the critical position and the positions of the multiple sampling points, curve fitting is performed to obtain the corresponding curve function; The distance between the critical position and the center position of the wafer is used as the lower limit of integration, and the actual distance between the target overlay alignment mark and the center position of the wafer after warping is used as the upper limit of integration. An arc length integral formula is constructed based on the curve function. The distance between the critical position and the baseline position of the target overlay alignment mark is set as the arc length integral value; Based on the arc length integral value and the arc length integral formula, the actual distance between the target overlay alignment mark and the center position of the wafer under the warping information is obtained; Substituting the actual distance into the curve function, the actual position of the target overlay alignment mark under the warping information is obtained; The displacement vector is obtained based on the actual position and the baseline position, and is used as the position offset of the target overlay alignment mark; Output the position offset; The baseline position of the target overlay alignment mark corresponding to the current layer of the wafer is compensated based on the output position offset to obtain the compensated position; The wafer layer is photolithographically processed based on the compensated position.

2. The semiconductor processing method according to claim 1, characterized in that, The plurality of sampling points shall have at least three sampling points, and the distance between adjacent sampling points shall be equal.

3. An electronic device, characterized in that, include: One or more processors; A memory for storing one or more computer programs that, when executed by one or more processors, cause the processors to implement a semiconductor processing method as described in any one of claims 1 to 2.

4. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions that, when executed by a computer's processor, cause the computer to perform a semiconductor processing method as described in any one of claims 1 to 2.

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