Managing pulse width modulated trip signals from multiple sources

Abstract

Embodiments of the invention relate to managing pulse width modulated trip signals from multiple sources. An integrated communication subsystem (ICSS) (200) includes a pulse width modulator (244) that drives a power stage, such as a motor. The pulse width modulator (244) is configured to switch off the power stage when the pulse width modulator (244) receives a trip signal from a logic circuit (421) of the ICSS (200). The logic circuit (421) may be readily reprogrammed to send a trip signal only when a particular error condition is detected. Furthermore, the ICSS (200) contains one or more filters that can adjust the sensitivity of the logic circuit (421) to error signals, thereby enabling the ICSS (200) to distinguish between true errors that require shutdown and negligible prompt fluctuations during operation of the ICSS (200).

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with the application date of December 27, 2019, the invention name of which is “Managing Pulse Width Modulated Trip Signals from Multiple Sources” and the application number of which is 201911380322.2.

[0003] Related Applications Cross Reference

[0004] This application claims priority to U.S. Provisional Application No. 62 / 677,878, filed on May 30, 2018, and U.S. Provisional Application No. 62 / 786,477, filed on December 30, 2018, both of which are incorporated herein by reference in their entirety. Technical Field

[0005] The present invention generally relates to an industrial communication subsystem (ICSS) that may be formed as part of an integrated circuit, such as a digital signal processor (DSP), a system on a chip (SoC) or an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). More specifically, the present invention relates to systems and methods for managing pulse width modulated trip signals from multiple sources in an industrial control subsystem. Background Art

[0006] Industrial motor control applications such as robotics, servo drives, and computer numerical control require the ability to shut down powered devices when error conditions occur that could cause damage to the motor, machine, and / or person. Summary of the invention

[0007] At least one example of the present invention includes a control system comprising: a power stage; a pulse width modulator coupled to the power stage, the pulse width modulator being configured to cut off the power stage when the pulse width modulator receives a trip signal; a processor coupled to the pulse width modulator; a logic circuit coupled to the pulse width modulator and the processor, the logic circuit comprising: a first interface comprising a plurality of inputs, wherein the plurality of inputs comprises: a first input configured to receive a first trip event indication signal originating from the pulse width modulator; a second input configurable to receive a second trip event indication signal originating from an electronic device releasably coupled to the second input at a connection port; and a third input configured to receive a third trip event indication signal from the processor; and a second interface comprising: a first selection input configured to receive a first selection; and a second selection input configured to receive a second selection, wherein the logic circuit is configured to send the trip signal to the pulse width modulator when the logic circuit receives at least one of the three trip event indication signals.

[0008] At least one other example of the present invention includes a logic circuit coupled to a pulse width modulator, the logic circuit being configured to receive a plurality of inputs, the plurality of inputs comprising: a first input corresponding to a first signal originating from the pulse width modulator; a second input corresponding to a second signal originating from an electronic device; and a third input corresponding to a third signal originating from one or more processors; wherein the logic circuit is configured to controllably select which of the plurality of inputs to output to the pulse width modulator as a trip signal to cause the pulse width modulator to shut down a power stage driven by the pulse width modulator.

[0009] At least one additional example of the present invention is a method for managing a trip signal for a pulse width modulator, the method comprising: using a pulse width modulator to drive a power stage; receiving a first input at a logic circuit, the first input corresponding to a first trip event indication signal originating from the pulse width modulator; receiving a second input at the logic circuit, the second input corresponding to a second trip event indication signal originating from an electronic device, the electronic device being releasably coupled to the logic circuit at a port; receiving a third input, the third input corresponding to a third trip event indication signal from a processor; selecting by the logic circuit which input to output to the pulse width modulator as a trip signal to cause the pulse width modulator to shut down a power stage driven by the pulse width modulator, wherein the selection comprises selecting from a plurality of inputs including the first input, the second input, and the third input; and outputting the selected input from the logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a system having an architecture according to an example of the present invention;

[0012] Figure 2A The present invention is described in detail in the following example. Figure 1 A first communication and control portion of the system of the system illustrated in FIG.

[0013] Figure 2B The present invention is described in detail in the following example. Figure 1 The shared components of the system illustrated in the system;

[0014] Figure 2C The present invention is described in detail in the following example. Figure 1 a second communication and control portion of the system of the system illustrated in FIG.

[0015] Figure 3 illustrates aspects of pulse width generation according to an example of the present invention;

[0016] Figure 4A Illustrate a logical configuration of a pulse width modulation monitor and controller according to an example of the present invention;

[0017] Figure 4B The present invention is an example of Figure 4A A trip signal logic unit interacting with the logic configuration illustrated in the diagram;

[0018] Figure 5 The present invention is described in detail in the following example. Figure 1 and Figures 2A to 2C Aspects of the system of the system illustrated in FIG.

[0019] Figure 6 Examples of the present invention are shown in Figure 1 and Figures 2A to 2C A state diagram illustrating the relationship of possible states of one or more components of the system of the system illustrated in FIG.

[0020] Figure 7 is a block diagram of a state machine 700 according to an example of the present invention. DETAILED DESCRIPTION

[0021] In the following description, numerous specific details are set forth for the purpose of explanation in order to provide a thorough understanding of the examples disclosed herein. In other examples, structures and devices are shown in block diagram form to avoid obscuring the disclosed examples.

[0022] When introducing elements of various examples of the present invention, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The examples discussed below are intended to be illustrative in nature and should not be construed to mean that the examples described herein are necessarily preferred in nature.

[0023] The examples described in this disclosure are neither mutually exclusive nor jointly exhaustive. References to "one example" or "an example" should not be interpreted as excluding the existence of additional examples that also incorporate the recited features.

[0024] As used herein, the term "media" refers to one or more non-transitory physical media that store together the content described as being stored thereon. The term "media" does not include signals, electrical or otherwise. Examples may include non-volatile secondary storage, read-only memory (ROM), and / or random access memory (RAM).

[0025] As used herein, the terms "application" and "function" refer to one or more computing modules, programs, processes, workloads, threads, and / or a set of computing instructions executed by a computing system. Example implementations of applications and functions include software modules, software objects, software instances, and / or other types of executable code.

[0026] One or more examples of the present invention are implemented on a 'system on a chip' (SoC). In at least one example, the SoC includes multiple hardware components. In at least one example, the SoC includes a microcontroller, a microprocessor, a digital signal processor (DSP) core, and / or a multi-processor SoC with more than one processor core. In at least one example, the SoC includes a memory block, the memory block including a selection of ROM, RAM, electrically erasable programmable read-only memory, and flash memory. In at least one example, the SoC includes a timing source, the timing source including an oscillator and a phase-locked loop. In at least one example, the SoC includes peripheral devices, the peripheral devices including a counter-timer, a real-time timer, and a power-on reset generator. In at least one example, the SoC includes an analog interface, the analog interface including an analog / digital converter and a digital / analog converter. In at least one example, the SoC includes a voltage regulator and a power management circuit.

[0027] In at least one example, a SoC includes both the hardware described above as well as software and / or firmware that controls a microcontroller, microprocessor or DSP core, peripherals, and interfaces.

[0028] Within the present invention, pulse width modulation refers to the process of modifying the width of the pulses in a pulse train in proportion to a small control signal; the larger the control voltage, the wider the resulting pulses become. By using a sine wave of the desired frequency as the control voltage for a pulse width modulation control circuit (also called a 'pulse width modulator'), it is possible to produce a high power waveform whose average voltage varies sinusoidally in a manner suitable for driving an alternating current (AC) motor. AC motors are used in many industrial applications, such as robotics, servo drives, and computer numerical control. Pulse width modulation is a way of describing a digital (binary / discrete) signal formed by a modulation technique that involves encoding a message into a pulse signal.

[0029] In an example of the present invention, pulse width modulation is used to control the amount of power supplied to an electrical device including an inertial load (e.g., a motor). The average value of the voltage (and current) fed to this load is controlled by quickly turning on and off the switch between the power supply and the load. The longer the switch is on compared to the period when the switch is off, the higher the total power supplied to the load will be. In an example of the present invention, the pulse width modulation switching frequency is much higher than the switching frequency that will affect the load (device using power). The resulting waveform perceived by the load (e.g., a motor) is made as smooth as possible. Jitter is therefore minimized.

[0030] Sometimes, such as when an error condition exists, it is necessary to quickly shut down one or more motors under the control of a pulse width modulator (PWM). Examples of the present invention are directed to apparatus and methods for quickly shutting down PWM controlled devices while minimizing the possibility of harm to people, motors, and machinery due to the shutdown.

[0031] Within the present invention, the term 'event indication signal' refers to a signal (e.g., within a device or network) that indicates that a pulse width modulator (PWM) may be required to quickly shut down one or more motors (e.g., in a power stage cutoff). In examples of the present invention, one or more event indication signals (EIS) may come from various sources. One or more examples of the present invention are directed to systems and methods for managing EIS from such sources. At least one example of the present invention is directed to a method of reducing the generation of unnecessary EIS by such sources.

[0032] EIS may be caused by an operational error of a device, circuit, component, or the like. EIS may also correspond to a transient fluctuation. A transient fluctuation includes a signal caused by a minor operational error that does not actually necessitate a power stage shutdown. A transient fluctuation includes a short signal error that may be caused by a non-error event (e.g., electromagnetic interference caused by environmental factors). A transient fluctuation corresponds to a 'false positive' detection of an error event. At least one example of the present invention is a method for mitigating the effects of transient fluctuations. In one or more examples, if the filter determines that the EIS is not due to a transient fluctuation, the filter will emit a trip event indication signal (TEIS); in an ideal case, all false positive EIS are filtered out, and all true positive EIS are communicated to a trip signal transmitter (e.g., Figure 4B 4. It is worth noting that the EIS may be of varying lengths, and generally speaking, the longer the EIS persists, the greater the likelihood that the EIS indicates a fault rather than just a momentary fluctuation.

[0033] At least one embodiment of the present invention is a method of combining multiple TEIS into a single TEIS.

[0034] Examples of the present invention include diagnostic mechanisms and methods for identifying EIS sources, determining with greater accuracy when an event that produces a given EIS occurs (accurate to within plus or minus three nanoseconds), and storing this source and timing information for consideration. Unlike conventional solutions, the mechanisms and methods provide the ability to read back EIS source information and timing information for multiple events. The ability to respond immediately to errors is a corollary of the accuracy of error timing determinations. For example, in an implementation of the present invention's technology, a field effect transformer (FET)-based power stage must be shut down within 1 microsecond of an error to avoid damaging the FET-based power stage. In some implementations, damage prevention requires cutting off the FET-based power stage before no more than 500 nanoseconds of the error condition have passed. For an error condition to be handled quickly, the error condition must be quickly communicated to the shutdown mechanism; the delay from detecting the error signal to tripping the PWM should be minimized.

[0035] Depending on the operating environment of a given ICSS, and taking into account propagation delays in the signal chain of one or more devices with which the ICSS interacts (and / or communicates and / or controls), the maximum acceptable delay between transmitting the EIS and issuing the trip signal will be 10 nanoseconds. However, as described above, the longer the EIS persists, the greater the likelihood that the EIS indicates a fault rather than just a momentary fluctuation. The reverse is also true; the shorter the EIS, the greater the probability that the EIS is caused by a momentary fluctuation. Therefore, there is a tradeoff between ensuring that errors are resolved immediately (e.g., by powering down a component) and avoiding acting on false alarms (e.g., momentary fluctuations caused by extraneous signal fluctuations).

[0036] In one or more embodiments of the present invention, the ICSS user can adjust the response time to avoid false detection. In some embodiments, the user can change the setting of the transient fluctuation filter, for example, by lengthening or shortening the time required for the transient fluctuation filter to send the TEIS to the trip signal controller (e.g. Figure 4B 421). Typical transient filter settings are from 10 nanoseconds to 100 nanoseconds. In at least one example, if the transient filter is not set to zero (0), the transient filter will eliminate all noise, but (as explained) will also increase propagation delay. In some examples, the user can also adjust the trip signal controller (e.g. Figure 4B Here, the user can increase or decrease the length of time required for the trip signal controller to read one or more incoming TEIS (for example, from one or more error signal sources) before the trip signal controller will trip the PWM.

[0037] At least one example within the present invention is a system comprising a position feedback interface, a motor current and voltage interface, a pulse width modulator (PWM), a programmable real-time unit, and trip generation hardware configured to generate a trip signal based on a set of static and / or dynamic input events for each motor controlled by a given PWM. In one or more examples, the system can be dynamically configured. In at least one example, the system enables programmable selection of input events to the trip signal generation logic. An example of the present invention is a system configured to enable programming of event-based transient fluctuation mitigation.

[0038] At least one embodiment of the present invention is a programmable state machine having an active state and a reset state. In some embodiments of the present invention, the reset state is used for pulse width modulation cycles. In one or more embodiments, the reset state is controlled by a software reset and / or a timer. In embodiments of the present invention, the system includes a reset function that implements single and / or cycle-by-cycle EIS analysis.

[0039] An example of the present invention is a configurable hardware state machine capable of managing pulse width modulation with minimal latency. An example of the present invention is a configurable hardware state machine capable of managing power stage shutdown regardless of the source of the event requiring such power stage shutdown. In at least one example, all EIS inputs are ingested by a single hardware device with minimal latency and minimal jitter for EIS management.

[0040] As used in this invention, the term jitter refers to the deviation from the true periodicity of an approximately periodic signal (which is usually related to a reference clock signal).

[0041] In examples of the present invention, a communication protocol is a system of rules that allow two or more entities of a communication system to transmit information. A specific communication protocol such as EtherCAT (Ethernet for control automation technology) may have multiple datagrams within one packet, which requires parsing the packet multiple times with a variable start offset. EtherCAT is an Ethernet-based fieldbus system. A fieldbus system is an industrial network system for real-time distributed control. The EtherCAT protocol is standardized in IEC61158 and is suitable for both hard and soft real-time computing requirements in automation technology. A real-time system such as EtherCAT needs to have its data packets parsed during the receiving process and to make processing / forwarding decisions during the receiving process before the end of the packet has been reached - for example where to send the received packet.

[0042] As mentioned, many different communication protocols have been developed across different industries and market segments to address real-time communications for data exchange running on proprietary developed processing devices such as SoCs, DSPs, ASICs, and FPGAs. Examples of the present invention are directed to providing and / or enabling multi-protocol flexibility for communications between such processing devices. At least one example of the present invention is directed to providing and / or enabling real-time Ethernet communications at speeds of 1 Gigabit / second or faster.

[0043] At least one example of the present invention is an architecture for an Industrial Communication Subsystem (ICSS) that addresses the flexibility requirements of multi-protocol and the performance requirements of real-time Gigabit Ethernet. With integration onto a directory processor, industrial communication is made as easy as standard Ethernet. The ICSS has a hybrid architecture. In one example, the ICSS includes four 32-bit Reduced Instruction Set Computer (RISC) cores coupled with a set of tightly integrated hardware accelerators, called Programmable Real-Time Units (PRUs). A Reduced Instruction Set Computer (RISC) is a computer whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a Complex Instruction Set Computer (CISC).

[0044] The combination of 128 / 256 Gbit / s data transfer and 4 nanosecond (ns) deterministic programming resolution provides a highly differentiated method of communication interface. Figures 2A to 2C The diagram in FIG. 5 illustrates a detailed view of a hardware accelerator in conjunction with a 128 / 512 Gbit / s data bus architecture.

[0045] Examples of the present invention are directed to a Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) that includes a dual 32-bit RISC core (PRU), data and instruction memory, internal peripheral modules, and an interrupt controller (INTC). The programmable nature of the PRU-ICSS, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time response, specialized data handling operations, peripheral interface control, and in offloading tasks from other processor cores of a System on a Chip (SoC).

[0046] For Industrial Ethernet use cases, the ICSS may require a tradeoff between programmability (flexibility) and the need to maintain line rate packet load. In one example, the programmable components (PRU) will run at a 250 MHz clock and therefore limit the firmware (f / w) budget to approximately 84 cycles per packet (for minimum size transmit and receive frames). This may be insufficient for full 802.1D compliant packet processing at 1 GHz rates. Therefore, the exemplary ICSS of the present invention includes a hardware (HW) accelerator for time-consuming bridging tasks.

[0047] According to the disclosed example, the PRU microprocessor core has a load / store interface to external memory. Using data I / O instructions (load / store), data can be read from or written to external memory, but at the expense of stalling the core while the access is made. Reading of an N-32-bit word typically takes about 3+N cycles, while writing takes about 2+N cycles.

[0048] In at least one example, the broadside RAM and / or broadside interface are optimized for 32-byte wide transfers. Lower transfer widths can be supported by padding the size to 32 bytes. In at least one example, the read location is first written to the attached RAM using the xout broadside instruction, and then the data is read using the xin broadside instruction. Thus, the read operation will take two cycles. For a write transfer, the address is placed in the register just after the register holds 32 bytes of data, and the data plus address is transferred to the attached RAM with one xout instruction. In at least one example, this method has the additional advantage of also being able to potentially perform operations on the data in parallel with the transfer.

[0049] In addition to speeding up writes and transfers, examples of the present invention also provide advantages, such as glue logic between the RAM and the broadside interface to locally store the last accessed RAM address, which allows an auto-increment mode of operation so that the firmware does not have to constantly update the address (especially useful for batch reads). Examples of the present invention enable useful operations on data using this interface in parallel with write operations. For example, a cut through data can be run through a checksum circuit to calculate a running checksum of the packet while the packet is stored in the RAM. In at least one example, the processor can perform endian flipping on the data within the packet at various data size boundaries. In at least one example, this interface can be used to perform data pivot / swap operations, for example, to swap registers r2 to r5 with r6 to r9. This is useful when moving data between interfaces with different block sizes (e.g., a 32-byte RX FIFO and a 16-byte PSI interface). In an alternative example, an organization is associated with an attached memory or an independent memory 'view' is achieved by different firmware tasks by using different broadside identifiers (IDs) (parameters of broadside instructions). Broadside IDs can be mapped to different read or write memory addresses (maintained by glue logic) so that data structures such as FIFOs (first in first out) and queues can be implemented by attached RAM in a flexible and firmware managed manner. At least one example utilizes embedded processing.

[0050] In at least one embodiment of the invention, ingress filter hardware is combined with an ingress classifier to implement hardware decisions for real-time forwarding and processing. This filter hardware is placed at a variable and context-dependent starting address, reloaded within a packet with a variable and context-dependent starting address, masked to an application address range, and compared using greater than and less than operations.

[0051] In an example of the present invention, multiple hardware filters can be combined with binary logic to form a complex receive decision matrix. In an example, multiple hardware filters can be combined with time windows to make time-aware receive decisions. Multiple hardware filters can also be combined with rate counters to make rate-limited receive decisions.

[0052] In at least one example of the present invention, hardware filters and classifiers enable decisions related to receiving and forwarding packets with relatively small bridge delays. In an example, a combination of content, time window, and data rate provides robust ingress classification for Ethernet bridging while maintaining relatively small bridge delays. As will be explained in more detail below, examples of the present invention achieve bridge delays of less than 1 microsecond.

[0053] Figure 1 1 is a functional block diagram of a system 100 (which may be a component of a SoC 130) based on an ICSS architecture according to an example of the present invention. Figure 1 100, a 16 kilobyte broadside random access memory (BS-RAM) 101 is coupled to (in signal communication with) an AUX_PRU 112. The BS-RAM 101 is coupled to a PRU 116 via the AUX_PRU 112. The BS-RAM 101 can transfer 32 data bytes in one clock cycle of the system 100. The BS-RAM 101 has ultra-high bandwidth and ultra-low latency. Within the present invention, coupled components (e.g., circuits) are able to communicate with each other. Connected components are components that are coupled via direct or indirect connections. Within the present invention, components that are coupled to each other are also connected unless otherwise indicated.

[0054] like Figure 1 , data coming in through interface circuit 104 (which is a real-time interface) is passed to FIFO receive circuit 105. Classifier 108 is applied to this incoming data as it passes through receive circuit 105. The combinational logic of filter 106, rate counter 107, and classification engine 108 is applied to the received data packets.

[0055] Management data input / output (MDIO) circuit 102 is a media interface. MDIO circuit 102 uses PRU 116 to communicate with an external Reduced Gigabit Media Independent Interface (RGMII) physical layer and a Media Independent Interface (MII) physical layer (interface circuit 104, interface circuit 119). MDIO circuit 102 has low latency and is dedicated to PRU 116. Figure 1 , the system 100 also includes a statistics counter circuit 103 that tracks statistics of the Ethernet port of the real-time interface circuit 104, such as packet size, errors, etc. The real-time interface circuit 104 (including RGMII, serial gigabit media independent interface (SGMII), and real-time media independent interface 231, 259 (RTMII)) is a hardware layer connected to the input / output (IO) (such as MDIO circuit 102) of the system 100. The real-time interface circuit 104 is coupled to the FIFO receive circuit 105, which includes a level one first-in-first-out (FIFO) receive layer (RX_L1) and a level two FIFO receive layer (RX_L2). The FIFO receive circuit 105 can receive level one FIFO data and level two FIFO data.

[0056] As described, system 100 includes filter 106, which is a filter for eight filter type 1 data streams and / or sixteen filter type 3 data streams. Filter 106 determines whether a given data packet is a data packet of a particular "type". Filter type 3 data packets have a variable starting address, which depends on whether a virtual LAN is utilized to deliver the packet. System 100 also includes rate tracker 107. In at least one example, system 100 includes eight rate trackers 107. Based on the filter type hit rate, rate tracker 107 calculates the throughput of FIFO receive circuit 105. System 100 also includes filter database (FDB) 109. FDB 109 is used for routing and redundancy. Receive circuit 105 includes a level one receive layer (RX_L1) and a level two receive layer (RX_L2), the receive layers including physical receive ports. The layer one receive layer (RX_L1) and the layer two receive layer (RX_L2) of the receive circuit 105 can access the FDB 109 to manage the receive and forward decisions based on IEEE802.1Q learning bridge mode 1. The FDB 109 contains a lookup table (LUT) that stores results, which can be given to the PRU 116 to help the PRU 116 make data routing decisions. In at least one example, the system 100 also includes a virtual local area network tag (VLAN TAG) circuit 110. A tag (a / k / a 'ID') is a keyword or term assigned to a piece of information (such as an Internet bookmark, a digital image, a database record, a computer file, or a VLAN). Statistics tracker 103, filter 106, rate tracker 107, classifier 108, FDB 109, and (optionally) VLAN TAG 110 are aspects of the receive circuit 105.

[0057] MDIO circuit 102 controls the interaction with the external physical layer (not shown) of the system according to the Open Systems Interconnection (OSI) model. The physical layer connects the link layer devices (such as the media access controller (MAC) (see Figure 2A 206(266) and 220(290) of Figure 2C 266 and 290)) connected to a physical medium of a host (e.g., 246) device / system of which subsystem 200 is a component or to which subsystem 200 is coupled. The physical layer includes both physical coding sublayer (PCS) functionality and physical medium dependent (PMD) layer functionality. There is a transceiver external to SoC 130 in which system 100 is embedded. MDIO circuit 102 configures one or more external physical layers (not shown) and minimizes latency of the ICSS.

[0058] Each central processing unit (CPU), such as the programmable real-time unit 116, includes a task manager circuit, such as the task manager circuit 111. In at least one example, the task manager circuit 111 and the task manager circuit 121 can recognize 200 events or more. The events correspond to hardware status signals, such as from the filter 106, from the rate tracker 107, or from the interrupt controller 123. The AUX_PRU 112 is responsible for control. For example, based on the start frame, the PRU-RTU 112 detects that a new packet is going to the data processor—PRU 116, and in parallel with the data processor collecting data, the PRU-RTU 112 will set up addresses and direct memory access (DMA) per packet as needed to get the packet to the host (130, 246). Although the data is pushed to the BS-RAM 117, the data can also be pushed to a checksum accelerator, such as the CRC 120. Therefore, the CRC 120 can cause the BS-RAM 117 to stop. The transmit circuit 113 communicates with the AUX_PRU 112 and the PRU 116. The transmit circuit 113 can receive (RX) and transmit (TX) information, such as by Figure 1 112 and PRU 116. The transmit circuit 113 is configured with a DMA that enables both the AUX_PRU 112 and PRU 116 to access the main system 100 memory. When either the AUX_PRU 112 or PRU 116 initiates a transaction, the transmit circuit 113 will manage the movement of data to the SoC 130 memory to pull or push data. The transmit circuit 113 is thus a general asset that can be used for data transfer. In at least one example, Figure 1 In the architecture of AUX_PRU 112, AUX_PRU 112 can control the address location while PRU 116 pushes data. Therefore, the architecture is flexible because a single CPU (e.g., 112, 116) is not responsible for both data management and control functions.

[0059] In at least one example subsystem 100, there is a structure with local memory. Figure 1 The structures in the exemplary subsystem 100 of may be 4 bytes wide. However, there are two sets of data memory 114 dedicated to each CPU (e.g., 112, 116), and another set of larger memory 115 is shared across the CPUs (112, 116). The data memory 114 may be used with registers 126 and 127, while the shared memory 115 is used for link lists, which are used for DMA or for storing metadata. Registers 126, 127 are like BS-RAMs 101, 117. However, registers 126 and 127 differ from BS-RAMs 101 and 117 in that registers 126, 127 are sliced ​​(see Figure 2Aslice_0 and Figure 2C 109 , the PRU 116 may be used to store and retrieve the received packet. The PRU 116 may store and retrieve the received packet from the host via the transmit circuit 113 and / or to a different port via the transmit circuit 118. The PRU 116 may store and retrieve the received packet from the host via the transmit circuit 113 and / or to a different port via the transmit circuit 118. The PRU 116 may store and retrieve the received packet from the host via the transmit circuit 113 and / or to a different port via the transmit circuit 118. The PRU 116 may store and retrieve the received packet from the host via the transmit circuit 113 and / or to a different port via the transmit circuit 118. The PRU 116 acts as a switch, while the BS-RAM 117 enables actions to be performed simultaneously. The BS-RAM 117 is thus a dual-purpose component. Hardware can be connected to the BS-RAM 117 while the BS-RAM 117 performs a lookup of the FDB 109 for the PRU 116. Just as a checksum can be performed by the CRC 120 while a RAM (e.g., 114) is loaded, FDB operations can be performed by the BS-RAM 117 for the PRU 116 while the BS-RAM 125 is interacting with the hardware.

[0060] The transmission circuit 118 handles the data transmission from the PRU 116. The transmission circuit 118 performs preemption, tag insertion and padding. The transmission circuit 118 enables the firmware to terminate the packet cleanly. Thereafter, the task manager circuit 121 will perform the necessary steps to generate the final CRC and if the packet in question is small, the transmission circuit 118 will perform padding. The transmission circuit 118 can insert tags so that the PRU 116 does not have to track the packet. The transmission circuit 118 can thus help the hardware of the SoC 130. The transmission circuit 118 is coupled to the interface circuit 119. The interface circuit 119 is the final layer. Outside the transmission circuit 118, there are different media independent interfaces, for example RGMII, SGMII and real-time MII (see 104, 119, 225 (295)). Other types of interfaces on the system 100 are also possible within the present invention. The FIFO transmission circuit 118 is agnostic about such interfaces. The interface circuit 119 is a demultiplexer. The interface circuit 119 provides protocol conversion for the transmission circuit 118, so that the transmission circuit 118 and therefore the PRU 116 can communicate with the hardware in a protocol suitable for the hardware of a given piece. The PRU 116 and the transmission unit 118 are therefore not constrained to operate in a manner corresponding to only one protocol, making the PRU 116 and the transmission circuit 118 more versatile than they would be without the interface circuit 119. In at least one example of the present invention, the system 100 constrains the data flow of the interface circuit 119 to connect to an external physical layer. Referring to the layers of the open system interconnection (OSI) model, the transmission circuit 118 has a layer one FIFO transmission layer (TX_L1) and a layer two FIFO transmission layer (TX_L2). Layer (or 'layer') one corresponds to the physical layer of the OSI model and layer two corresponds to the data link layer of the OSI model. This dual-layer connectivity provides several options. For example, the level two FIFO transport layer (TX_L2) can be bypassed and data can be sent to the level one FIFO transport layer (TX_L1), which reduces latency. In at least one example, the level two FIFO transport layer (TX_L2) has a wider interface than the level one FIFO transport layer (TX_L1). In at least one example, the level two FIFO transport layer (TX_L2) has a 32-byte interface, while the level one FIFO transport layer (TX_L1) has a 4-byte interface. In at least one example, if at the receive circuit 105, a data packet is going from the level one receive layer (RX_L1) to the level two receive layer (RX_L2) 272 (257), and the PRU 116 accesses the packet at the level two receive layer (RX_L2), then the data will first be pushed to the level two FIFO transmit layer (TX_L2) of the FIFO transmit circuit 118, and then the hardware of the FIFO transmit circuit 118 will push the data packet directly to the level one FIFO transmit layer (TX_L1).However, when communicating with a very low latency interface (e.g., EtherCAT), the level two FIFO transport layer (TX_L2) may be bypassed; data output from the PRU 116 may be pushed directly to the level one FIFO transport layer (TX_L1), (which, as described, has a 4-byte width).

[0061] Interface circuit 104 and interface circuit 119 are at level zero of the OSI model. Thus, data enters system 100 at level zero through interface circuit 104, moves from level zero to level one receive layer (RX_L1) of FIFO receive circuit 105 or level two receive layer (RX_L2) 272 (257) of FIFO receive circuit 105 all the way to PRU 116 (which exists at both level one and level two), and from level one or level two of PRU 116 through FIFO transmit circuit 118 and back to level zero at interface circuit 119. In at least one example, cyclic redundancy check (CRC) circuit 120 is an accelerator that helps PRU 116 perform calculations. PRU 116 interfaces with CRC circuit 120 through BS-RAM 117. CRC circuit 120 applies a hash function to the data of PRU 116. CRC circuit 120 is used to verify the integrity of data packets. For example, all Ethernet packets include a CRC value. CRC circuit 120 performs a CRC check on a packet to see if the CRC value of the packet is consistent with the result calculated by CRC circuit 120. That is, the packet contains a CRC signature and after the signature is calculated, the result is compared with the signature appended to the packet to verify the integrity of the packet.

[0062] The system 100 also includes an interrupt controller (INTC) 123. INTC 123 aggregates CPU (e.g., AUX_PRU 112, PRU 116) level events to host (e.g., 130, 146) events. For example, there may be ten host events. INTC 123 determines that a given set of slave level events should be aggregated, mapped, and classified into a single entity. The single entity can be routed to PRU 116 or task manager circuit 121 and used by the PRU or task manager circuit to cause events to the host (130, 146). In that sense, INTC 123 is both an aggregator and a router.

[0063] Enhanced / external capture (eCAP) circuit 124 is a timer that enables PRU 116 to generate output responses based on time matching with industrial Ethernet peripheral (IEP) circuit 122 and capture event times of events external to system 100 .

[0064] The IEP circuit 122 has two sets of independent timers that implement time synchronization, time stamping, and quality of service for data egress from the system 100. There are several independent capture circuits associated with the IEP circuit 122. For example, if there is a receive (RX) start of frame event and it is important that the frame is pushed to the host at a specific time, the IEP circuit 122 can time stamp the event to indicate the specific time. If the event is a time-triggered transmission for the egress circuit 118, and if it is desired to transmit the packet at a precise time (within 2 to 3 nanoseconds), then the transmission of the packet begins when the timer expires, independent of the PRU 116. Therefore, the transmission of the packet is effectively decoupled from the PRU 116.

[0065] In addition to the described timers, the IEP circuit 122 also contains an enhanced digital input / output interface (EDIO). EDIO is similar to a general purpose input / output (GPIO) interface, but is smarter and better calibrated for Ethernet communications. For example, transmitting a start frame or receiving a start frame can cause an event on the EDIO, which in turn can cause an event outside the SoC 130. Synchronizing the output and locking in are part of time synchronization. It is also possible to have the IEP 120 receive a frame and capture an analog voltage. In a conventional system, this would require a read operation. But for EDIO, the capture can be event-triggered and / or time-triggered, thus making the capture more accurate than in a conventional system. EDIO enables the system 100 to accurately determine when an incoming frame arrives, which in turn enables the system 100 to sample one or more specific values ​​(such as temperature, voltage, etc.) and accurately track when the sampling is performed due to the time stamp of the IEP circuit 122. The frame in question can be amplified. When the frame is transmitted by the transmission circuit 118, the frame can contain the time-stamped sampled value without adding overhead or latency. The IEP circuit 122 also includes a watchdog (WD) timer. Certain events should occur under normal operating conditions. When such events occur, the PRU 116 will usually clear the WD timer. If the WD timer fires, then this means that the PRU 116 did not clear the WD timer in time, or did not reset the WD timer in time, which indicates that there is an unexpected pause or some type of waiting time. The WD timer is therefore used to track errors.

[0066] As described, the task manager circuit 111 and the task manager circuit 121 can recognize a large number of events. The PRU 116 is the main data engine of the system 100. When a frame is started, the system 100 begins to prepare and service the receiving circuit 105. Once the frame is in the transmission circuit 118, the input of the next packet can begin. Since the PRU 116 is the main processor, the PRU 116 needs to access all events in real time. Another operation associated with the PRU 116 is watermarking. Watermarks can be formed at the interface circuit 104, the receiving circuit 105, the transmission circuit 118, and the interface circuit 119. It is not desirable to wait until the FIFO is full before loading or unloading a packet, because this will be too late, and it is not desirable to wait until the FIFO is empty, because this will be too early. When a certain amount of emptiness (or fullness) is reached, the task manager circuit 121 can be triggered, and the PRU 116 will determine whether to watermark the packet.

[0067] An aspect of BS-RAM 117 is that it enables PRU 116 to snoop on packets while system 100 can save context and variables at BS-RAM 117, and can perform operations on the context and variables without overhead costs because the data of the packet does not need to be moved twice. In at least one example of the present invention, an incoming data packet can be moved to a storage location and operations performed on the data at the same time. This is different from conventional systems that move incoming packets to processing circuits and then to storage locations. System 100 thus performs a single operation, while conventional systems would perform two operations.

[0068] As described, the AUX_PRU 112 interacts with the BS-RAM 101. The AUX_PRU 112 has a task manager circuit 111 that can preempt the PRU 116 based on the occurrence of a specific event or context switch. The AUX_PRU 112 also interacts with the transmit circuit 113. In at least one example, the system 100 according to the present invention also includes an eight kilobyte data RAM 114 and a 64 kilobyte shared RAM 115. The AUX_PRU 112 and the transmit circuit 113 both interact with the PRU 116. The task manager circuit 121 inputs real-time tasks for receive and transmit processing based on FIFO watermarks. The PRU 116 is also coupled to a 16 kilobyte BS-RAM filter database 117. The output from the PRU 116 goes to the FIFO transmit circuit 118. In turn, the output from the FIFO transmit circuit 118 goes to the real-time interface circuit 119. PRU 116 also interacts with CRC 120, which calculates a checksum inside an Ethernet packet. In at least one example, system 100 includes IEP / timer / EDIO / WD circuit 122. As described, system 100 may also include interrupt controller (INTC) 123 and eCAP circuit 124.

[0069] Figures 2A to 2C An exemplary industrial communication subsystem (ICSS) (hereinafter referred to simply as subsystem 200) is illustrated. Figures 2A to 2C Graphic instructions and Figure 1 Many of the same components are shown in the , but in different details. Figure 1 The description and Figures 2A to 2C201 and PRU_0 219. The subsystem 200 includes a processing hardware element including one or more hardware processors, such as an auxiliary programmable real-time unit (AUX_PRU_0) 205 and PRU_0 219, each of which may have one or more processor cores. In at least one example, a processor (e.g., AUX_PRU_0 205, PRU_0 219) may include at least one shared cache memory that stores data (e.g., computational instructions) utilized by one or more other components of the processor (AUX_PRU_0 205, PRU_0 219). For example, the shared cache memory may be locally cached data stored in memory for access by components of the processing elements that make up the processor (AUX_PRU_0 205, PRU_0 219). In some cases, the shared cache memory may include one or more mid-level cache memories, such as a level 2 cache memory, a level 3 cache memory, a level 4 cache memory, or other levels of cache memory, a last level cache memory, or a combination thereof. Examples of processors include, but are not limited to, CPU microprocessors. Although not explicitly illustrated in FIG. 2, the processing elements that make up the processor AUX_PRU_0 205 and the processor PRU_0 219 may also include one or more other types of hardware processing components, such as graphics processing units, ASICs, FPGAs, and / or DSPs. Another accelerator of PRU_1 is the BSWAP circuit 224 (294). The BSWAP circuit 224 (294) may swap words depending on the size of the packet in question, little endian and / or big endian. BSWAP circuit 224 (294) may reorder the bytes in the packet depending on the word size.

[0070] Subsystem 200 includes Figure 2C Slice_0 201 is mirrored by slice_1 in . Figure 2AAs can be seen in the figure, slice_0 201 has multiple components. The main components are auxiliary PRU (AUX_PRU_0) 205, PRU_0 219 and MII 228. AUX_PRU_0 205 has several accelerators (a / k / a gadgets). AUX_PRU_0 205 serves as a control processor for slice_0 201. Throughout the present invention, the terms 'control processor', 'AUX_PRU' and 'RTU_PRU' are synonymous and interchangeable unless otherwise indicated or specified by the context in which they appear, but their functions and configurations may be different.

[0071] Figure 2A The diagram illustrates that a memory, such as 204 (264), may be operatively and communicatively coupled to AUX_PRU_0 205. Memory 204 (264) may be a non-transitory medium configured to store various types of data. For example, memory 204 (264) may include one or more storage devices, the one or more storage devices including volatile memory. Volatile memory, such as random access memory (RAM), may be any suitable non-permanent storage device. In a specific example, if the allocated RAM is not large enough to hold all working data, a non-volatile storage device (not shown) may be used to store overflow data. This non-volatile storage device may also be used to store programs loaded into RAM when such programs are selected for execution.

[0072] The software program may be developed, coded and compiled in a variety of computing languages ​​for a variety of software platforms and / or operating systems and subsequently loaded and executed by the AUX_PRU_0 205. In at least one example, the compilation process of the software program may transform the program code written in a programming language into another computer language so that the AUX_PRU_0 205 can execute the programming code. For example, the compilation process of the software program may produce an executable program that provides coded instructions (e.g., machine code instructions) to enable the AUX_PRU_0 205 to implement a specific non-generic computing function.

[0073] After the compilation process, the encoded instructions may then be loaded from the storage device 220 (290), from the memory 210 to the AUX_PRU_0 205 as computer-executable instructions or process steps, and / or embedded within the AUX_PRU_0 205 (e.g., via a cache memory or on-board ROM). In at least one example, the AUX_PRU_0 205 is configured to execute the stored instructions or process steps to execute the instructions or process steps to transform the subsystem 200 into a non-generic and specialized programmed machine or device. The stored data (e.g., data stored by the storage device 220 (290)) may be accessed by the AUX_PRU_0 205 during the execution of the computer-executable instructions or process steps to indicate one or more components within the subsystem 200.

[0074] Figure 2B Illustration by Figure 2A slice_0 with Figure 2C Components and resources shared by slice_1. Figure 2C Included with Figure 2A Same hardware. slice_0 201 and slice_1 261 about Figure 2B Symmetrical. The present invention relates to Figure 2A The description applies mutatis mutandis to Figure 2C . Subsystem 200 includes Subsystem 200 also includes corresponding ports 276 at slice_0 201 and on slice_1 261. There is a third port (see Figure 130), host port 245, which connects subsystem 200 to host 246, of which subsystem 200 may be a component. Port 253 and port 276 can both be connected to Ethernet. Subsystem 200 can thus be used as a three-port switch. Host 246 can be a local source / sync or SoC (130). Although subsystem 200 options can themselves be SoC (130), in some embodiments, subsystem 200 will be a subcomponent of a larger SoC (130). In some examples, host 246 will be a CPU from ARM Holdings PLC of Cambridge, England, UK. In at least one example, host 246 includes several CPUs. There are multiple CPUs. An example of a small CPU is an Arm Cortex-R5-CPU. An example of a large CPU is an Arm Cortex-A57-CPU. In at least one example, the subsystem 200 can be controlled by another such CPU.

[0075] As shown, subsystem 200 includes an internal configurable bus array subsystem (CBASS) 248 ( Figure 2B ) interactive XFR2TR circuit 202 ( Figure 2A ). The 'XFR' in the XFR2TR circuit 202 (280) stands for transfer. The XFR2TR circuit 202 (280) has a broadside interface. The XFR2TR circuit 202 (280) is adjacent to the AUX_PRU_0 205 via the broadside interface of the XFR2TR circuit 202 (280). The internal register set of the AUX_PRU_0 205 is exposed to the accelerator MAC 206, CRC 207 (267), SUM32 circuit 208 (268), byte swap (BSWAP) circuit 203 (263) and BS-RAM 204 (264). In at least one exemplary subsystem 200 of the present invention, the internal register set of the AUX_PRU_0 205 is directly exposed to the accelerator, such as mentioned above, which is different from the architecture of conventional systems. In conventional systems, a load-store operation would be required on the structure in order for the AUX_PRU_0 205 to access the accelerator. 2, the accelerator is actually part of the data path of AUX_PRU_0 205. AUX_PRU_0 205 can import and export its register file to a given accelerator (a / k / a 'gadget') based on the broadside ID of a given register. For example, the XFR2TR circuit 202 (280), which is part of the DMA, can perform a transfer request. The transfer request (TR) can start with a starting address to start the data move, specifying the amount of data to be moved (for example, 200 bytes). The XFR2TR circuit 202 (280) can perform a simple DMA memory copy of the SMEM 235 containing a list of predetermined transfer requests (TRs). The software running on AUX_PRU_0 205 knows the list of pre-existing TRs of the SMEM 235. In operation, the AUX_PRU_0 205 sends instructions to the DMA engine to move data. Because transfer instructions can be extremely complex and / or complicated, predefined instructions reside in a 'work order pool' stored in SMEM 235. Based on the type of packet in question, AUX_PRU_0 205 determines which 'work orders' should be used and in what sequence to cause the packet to be sent to the correct destination. The XFR2TR circuit 202 (280) can create a work order list as directed by AUX_PRU_0 205, and once the work order list is created, the XFR2TR circuit 202 (280) will notify the DMA engine (not shown). The DMA engine will then pull the specified work order from SMEM 235 and execute the pulled work order. Therefore, the XFR2TR 202 (280) minimizes the computational overhead and transfers necessary to build a DMA list (like a link list) to perform the data move. TR stands for Transfer Request.

[0076] Another accelerator of AUX_PRU_0 is BSWAP circuit 203 (263). BSWAP circuit 203 (263) can swap words depending on the size of the packet in question, little endian and / or big endian. BSWAP circuit 203 (263) can reorder the bytes in a packet depending on the word size. BSWAP circuit 203 (263) is thus an accelerator that will automatically perform such swapping. BS-RAM 204 (264) corresponds to the BS-RAM 204 (264) with respect to Figure 1 BS-RAM 101 is discussed. BS-RAM 204 (264) is tightly coupled to AUX_PRU_0 205. When AUX_PRU_0 205 pushes a data element to BS-RAM 204 (264), a CRC for the element can be simultaneously calculated by CRC 207 (267) or a checksum for the data element can be simultaneously calculated by checksum circuit 208. Based on the ID of the data packet, AUX_PRU_0 205 will snoop the necessary transactions (for example, checksum, multiplication, accumulation, etc.) at the same time, which means that pushing the data element to BS-RAM 204 (264) and performing the acceleration constitute a single transaction rather than a double transaction. This operation concurrency is achieved by BS-RAM 204 (264) because BS-RAM 204 (264) can be executed while data is being transferred to physical RAM (for example, Figure 1 14 and shared RAM 115) shown in FIG. 1 while enabling and / or disabling the functionality of the gadget.

[0077] Although the peripherals BSWAP 203 (263), XFR2TR circuit 202 (280), MAC 206 (266), CRC 207 (267), and SUM32 208 are illustrated as being external to BS-RAM 204 (264) for purposes of explanation, the peripherals will be embedded within BS-RAM 204 (264) under most operating conditions. Multiplier-accumulator (MAC) 206 (266) is a simple accelerator that includes a 32-bit by 32-bit multiplier and a 64-bit accumulator. Cyclic redundancy check (CRC) circuit 207 (267) performs redundancy checks cyclically. CRC circuit 207 (267) supports different polynomials. Checksum circuit 208 is the same as CRC circuit 207 (267), except that checksum circuit 208 uses a hash operation to determine the integrity of the payload at AUX_PRU_0 205 before performing a checksum on the payload.

[0078] The Task Manager circuit 209 is a key part of the AUX_PRU_0 205. The Task Manager circuit can prompt the AUX_PRU_0 205 to perform a given function based on which of the 196 events is detected.

[0079] There are two ways that data can be moved into and out of the subsystem 200 and into and from the SoC 130 memory and / or to external devices. One way is through the packet streaming interface (PSI) 211 (281), which provides the ability to push data to and pull data from the host (e.g., 246). This action of the PSI 211 (281) is different from a read request. Instead, the master (writer) component of the PSI 211 (281) is attached to the AUX_PRU_0 205. There is a mapping of received packets to the destination. Under normal operating conditions, the destination will be ready to receive the packet. For the reasons stated, the PSI 211 (281) does not read the data, but rather transfers the data to the destination endpoint. The PSI 211 (281) receives data from the navigation subsystem (NAVSS) 210 and sends the data to the NAVSS. The NAVSS 210 implements complex data movement. The NAVSS 210 has a DMA engine and an advanced TR called a re-engine. The NAVSS 210 supports the PSI 211 (281) and can map the PSI 211 (281) to other devices (e.g., via the PCI Express). Using the PSI 211 (281), data can go directly from the ICSS to the PCI Express while bypassing the host and / or the main DMA engine, enabling data to be streamed from one Ethernet interface (e.g., the interface circuit 225 (295)) to another interface, such as a Universal Serial Bus or a PCI Express.

[0080] AUX_PRU_0 205 communicates with an inter-processor communication scratchpad (IPC SPAD) 212 (282), which in turn communicates with PRU_0 219. IPC SPAD 212 (282) is not a temporary SPAD owned by a single CPU. At least for the purpose, IPC SPAD 212 (282) is able to transfer data or complete controller status across AUX_PRU_0 205 and PRU_0 219. Transfer to Virtual Bus Circuit (XFR2VBUS) Circuit 213 (or simply 'transfer circuit 213') corresponds to Figure 1204, 214, and operates in the same manner as the transfer circuit 113 shown in FIG. 204. The transfer circuit 213 (283) is attached to the BS-RAM 214 (284). The transfer circuit 213 (283) has a broadside interface with the external CBASS 247, the internal CBASS 248, and the spin lock circuit 249. The transfer circuit 213 can request reads and writes from the memory (e.g., 204, 214) to the broadside and from the broadside to the memory. This read / write function is different from the read / write operation at, for example, the dedicated memory (DMEM0) 233. Conventional DMA copy operations move information in the SoC (130) memory to the DMEM0 233 or the shared memory SMEM 235. The internal CBASS 248 is the network-on-chip of the subsystem 200.

[0081] The internal CBASS 248 is 4 bytes wide. In at least one example, to access the internal CBASS 248, load and store operations must be performed, which are high latency, low throughput operations. However, using a tightly coupled and more direct transfer circuit 213 (283) reduces latency and overhead while also providing greater bandwidth due to the broadside width of the transfer circuit 213 (283). Thus, the transfer circuit 213 (283) can act as a direct mapping from the register file to the subsystem 200 memory (e.g., 233). The intermediate memory locations are bypassed and the transfer circuit 213 (283) goes directly to the register file, which reduces latency.

[0082] As described, like AUX_PRU_0 205, PRU_0 219 also has an accelerator. PRU_0 219 corresponds to Figure 1 Like PRU 116, PRU_0 219 has task manager circuit 223. The main difference between AUX_PRU_0 205 and PRU_0 219 is that PRU_0 219 is connected to interface circuit 104, receiving circuit 105, transmitting circuit 118 and interface circuit 119 (see Figure 1 )(Its Figures 2A to 2C The interface circuit 225 (295) is shown in the figure as an interface circuit 225 (295)). The interface circuit 225 (295) includes a receiving circuit 270, which includes a level one FIFO transmission layer (TX_L1) 226 (296) and a level two transmission layer (TX_L2) 262 (256) (see Figure 1 , 118). The transmission circuit 271 includes a layer 1 receiving layer (RX_L1) and a layer 2 receiving layer (RX_L2) 272 (257) (see 105, Figure 1 ).

[0083] The BS-RAM 214 (284) of the PRU_0 219 of the AUX_PRU 205 is the same as the BS-RAM 204 (264). The general purpose input / output (GPIO) circuit 215 (285) enables the subsystem 200 to access additional hard lines of the SoC (e.g., 130, 246). The Σ-Δ circuit 216 (286) is an analog / digital converter that interacts with one or more external sensors (not shown). The Σ-Δ circuit 216 (286) converts the analog data stream from the sensor into a digital data stream. The Σ-Δ circuit 216 (286) is a filter. The data stream from the sensor corresponds to the voltage or temperature at the external device (e.g., a motor). The Σ-Δ circuit 216 (286) informs the PRU_0 219 of a specific event (for example, if there is a current spike, a voltage spike, or a temperature spike). The PRU_0 219 determines what action needs to be taken due to the spike (if any).

[0084] The peripheral interface 217 (287) is used to detect the position or orientation of a device under the control of the subsystem 200 (such as a motor or a robot joint). For example, the peripheral interface 217 (287) uses a protocol to determine the precise radial position of the arm. The Σ-Δ circuit 216 (286) and the peripheral interface 217 (287) are therefore used for device control, such as robot control. The Σ-Δ circuit 216 (286) and the peripheral interface 217 (287) are tightly coupled to PRU_0 219, which enables the subsystem 200 to be useful in industrial scenarios.

[0085] The packet streaming interface PSI 218 (288) of 219 is like the PSI 211 (281) of the 205 PSI. 211 (281) and PSI 218 (288) interact with the navigation subsystem (NAVSS) PSI 210. However, while PSI 211 (281) has four receive (RX) inputs and one transmit (TX) output, PSI 218 (288) has a single transmit (TX) output. As described, PRU_0 219 can move the register file of PRU_0 219 directly to the Ethernet line (port) 253. Therefore, the data packet enters through the layer one receive layer (RX_L1) 227 of the receive circuit 271 and the layer two receive layer (RX_L2) 272 (257) of the receive circuit 271; no memory reading or DMA is required. Alternatively, the data packet can be immediately popped (pushed) to PRU_0 219 in a single data cycle. If necessary, the data packet may be pushed to the layer one transport layer (TX_L1) 226 (296) or the layer two transport layer (TX_L2) 262 (256) in the next clock cycle, which may be referred to as a 'bridge-to-layer-cut-through' operation. In at least one example, the cross-layer bridge operation is faster than a store and forward operation. The cross-layer bridge operation may be performed while the data packet is pushed to the host 246 (for example, SoC 130) or slice_1 261 (as the case may be) via PRU_0 219 and port 245.

[0086] PRU_0 219 is a RISC CPU whose register file can access Ethernet buffers without accessing or passing other memories. Interface 228 (298), interface 229 (299), and interface 230 (258) are physical media interfaces and include at least one RGMII. Real-time media independent interface 228 (298) is a 4-bit interface. Interface 229 (299) is gigabit wide. Interface 229 (299) is a reduced gigabit media interface (RGMII). Interface 230 (258) is a serial gigabit media independent interface (SGMII). In one or more instances, these identified interfaces are implemented in real time.

[0087] The Ethernet interface circuit 225 (295) includes a receive (RX) classifier circuit 232 (108) that uses rate data (107) and filter data (106) as well as other data, and based on a predefined mapping function (e.g., a time function), the classifier circuit 232 (108) classifies several packets according to this mapping function. The classification of the packet will determine the priority of the packet, and the priority will specify which queue (high priority queue, low priority queue, etc.) the packet is placed in. Port 253 of 225 (295) is essentially a line dedicated to the Ethernet interface circuit 225 (295). Port 253 is at level zero of the OSI model. Interface 252 (255) is an interface between PRU_0 219 and the Ethernet interface circuit 225 (295). As described, 270 (273) and 271 (274) are FIFO configured circuits. The FIFO transmission circuit 270 (273) corresponds to Figure 1 The transmission circuit 118, and the FIFO receiving circuit 271 (274) corresponds to Figure 1 The circuit 105 in. While pushing the data into the FIFO circuit 270 (273), the classifier circuit 232 operates on the data.

[0088] Slice_0 201 and slice_1 261 share several resources 301, for example Figure 2B 246. The Slice_0 201 and Slice_1 261 are coupled to each other via the internal CBASS 248. The internal CBASS 248 is coupled to the interrupt controller 236. The interrupt controller 236 is an aggregator that aggregates several event instances (recall that there are 196 possible events). Some of the events may come from the host (130) 246, but most of the events are internal to the subsystem 200. Due to the large number of possible events, the events must be aggregated or merged into a smaller number of super packets for sharing with the large amount of data from the host (e.g., 246). Software running on PRU_0 219 determines the mapping of sources to output destinations.

[0089] As described, subsystem 200 includes an internal configurable bus array subsystem (CBASS) 248 as a shared resource. The internal CBASS 248 receives data from the external CBASS 247 via a 32-bit slave port. The internal CBASS 248 communicates with dedicated memory_0 233, dedicated memory_1 234, and shared memory (SMEM) 235 (115). SMEM 235 is a general purpose memory. SMEM 235 can be used for direct memory access (DMA) operations for the DMA instruction set, as well as other functions. The DMA is like the temporary registers (126, 127) and can contain control and status information. The internal CBASS 248 also communicates with an enhanced capture module (eCAP) 237, which also communicates with the external configurable bus array subsystem (CBASS) 247. The enhanced capture module 237 is a timer used for time management of external devices (such as motors).

[0090] In at least one example, subsystem 200 has different modes of operation. AUX_PRU_0 205 and PRU_0 219 each have memory mapped registers. Host 246 writes information to configuration manager circuit 238. For example, if host 246 needs to enable RGMII mode, configuration manager 238 will enable RGMII 229 (299), which is an example of a configuration register.

[0091] Universal Asynchronous Receiver-Transmitter (UART) 239 is a hardware device for asynchronous serial communication in which the data format and transmission speed are configurable. Electrical signaling levels and methods are handled by driver circuits external to UART 239. UART must operate at a specific baud rate, which requires a fixed clock rate. Asynchronous bridge (AVBUSP2P) 240 communicates with internal CBASS 248 and UART 239. UART 239 in turn communicates with external CBASS 247. AVBUSP2P 240 is a bridge that allows independent timing of UART 239. External CBASS 247 is coupled to Industrial Ethernet Peripheral Device_0 (IEP0) 241A and Industrial Ethernet Peripheral Device_1 (IEP1) 241B. IEP0 241 and IEP1 273 each include a timer, EDIO, and WD (122). IEP0 241A and IEP1 241B together enable two time domain managements to run simultaneously. Similar AP 237 timer searches for timers for IEP0 and IIP2 must operate at a given frequency (for example, 200 MHz), but the PRU can be decoupled from these. Likewise, AVBUSP2P 240, AVBUSP2P 242, and AVBUSP2P 243 are couplers that allow UART 239, IEP0 241A, and IEP1 241B to operate at different frequencies if desired.

[0092] like Figure 2B , there is a second AVBUSP2P circuit 242 communicatively interposed between IEP0 241A and an internal configurable bus array subsystem (CBASS) 248. There is also a third AVBUSP2P 243 communicatively interposed between IEP1 241B and the internal CBASS 248. The subsystem 200 also includes a pulse width modulator (PWM) 244 communicatively interposed between the internal CBASS 248 and external components.

[0093] Components 236, 237, 238, 239, 241A, 241B, and 244 are each connected to a specific SoC line. That is, they each communicate with the IO of the host 246.

[0094] Figure 2BIt is also shown that the subsystem 200 may include a spin lock 249, an AUX_SPAD 275, and a PRU_SPAD 250. The spin lock 249 is a hardware mechanism that provides synchronization between the various cores (for example, 205, 219) of the subsystem 200 and the host 246. Conventionally, a spin lock is a lock that causes a thread that attempts to acquire it atomically to simply wait in a loop ("spin") while repeatedly checking whether the lock is available. Since the thread remains active but does not perform useful tasks, using this lock is a busy green wait. Once acquired, the spin lock will usually be held until it is explicitly released, but in some implementations, if the waiting thread (the thread holding the lock) blocks or "goes to sleep", the spin lock can be automatically released. The lock is a synchronization mechanism for enforcing restrictions on access to resources in an environment where there are many threads of execution. The lock enforces a mutually exclusive concurrency control policy. Based on this principle, the spin lock 249 provides automation of the operation of the subsystem 200 components. For example, spin lock 249 enables each of the cores of the subsystem (eg, AUX_PRU_0 205) to access shared data structures (eg, data structures stored in SMEM 235), which ensures that the various cores are updated simultaneously. Access by the various cores is serialized by spin lock 249.

[0095] As shown in the exemplary subsystem 200, the auxiliary temporary registers (PRU SPAD) 250 and the AUX SPAD 275 each hold three sets of thirty 32-bit registers. The subsystem 200 also includes a filter database (FDB) 251 (109) (which includes two 8-kilobyte sets) and filter database control circuitry. The FDB 251 is a wide-edge RAM accessed by the AUX_PRU_0 205 and PRU_0 219. The FDB 251 can also be accessed by the hardware engine Σ-Δ 216 (286) and the peripheral interface 217 (287). The receive circuit 271 (which includes the level one receive layer (RX_L1) 227 (297) and the level two receive layer (RX_L2) 272 (257)) can also access the FDB 251. FDB 251 is a broadside RAM to AUX_PRU_0 205 and PRU_0 219 to read and write entries, but the hardware also uses FDB 251 to provide an accelerated compressed view of packets arriving through port 253. The hardware will use a hashing mechanism to consult the memory of FDB 251 and pass the result along with the packet to PRU_0 219. Determining where the packet will go next is a routing function. AUX_PRU_0 205 and PRU_0 219 access FDB 251 via its broadside interface to add information and delete information. Receive hardware 225 (295) can also access FDB 251.

[0096] The subsystem 200 may also include a communication interface 225 (295) that may be communicatively coupled to the processor 205, such as a network communication circuit that may include wired communication components and / or wireless communication components. The network communication circuit 225 may utilize any of a variety of proprietary or standardized network protocols (e.g., Ethernet, TCP / IP, to name a few of many protocols) to enable communication between devices. The network communication circuit may also include one or more transceivers that utilize Ethernet, power line communication Wi-Fi, cellular, and / or other communication methods.

[0097] As described, in examples of the present invention, data packets are processed in a real-time deterministic manner, which is different from conventional Ethernet or IEEE Ethernet processing, which defines more of a 'best efforts' traffic system, where packet loss occurs depending on the load of a given network. While conventional Ethernet management is acceptable for many applications (such as video streaming), in industrial environments (for example, robotic assembly lines), sent data packets are delivered accurately and according to a predetermined schedule (under ideal conditions). In the industrial world, packets must arrive according to a strict schedule. Of course, packet loss can occur in an industrial environment, but there are different methods to take care of packet loss in the layers (higher than Layer 0, Layer 1, and Layer 2 involved in examples of the present invention).

[0098] When a packet is received from the physical layer (not shown) at the layer one receive layer (RX_L1) 227 and / or the layer two receive layer (RX_L2) 272 (257), the packet classifier 232 (108) analyzes the packet and identifies which portion of the packet is the content (a / k / a 'payload'). The packet classifier (a / k / a 'packet classification engine') 232 then makes an immediate decision about what to do with the packet. The Ethernet bridge 225 (295) makes forwarding and receiving decisions about each packet received (via the receive circuit 271 and / or the ingress 253). In conventional IEEE Ethernet bridges, such forwarding and receiving operations are performed in a 'store and forward manner', where an incoming data packet is received in a first step, and once the data packet has been received, the content is then examined in a second step. In conventional IEEE Ethernet bridges, a third step forwarding and receiving determination is made once the packet is fully received and the content is examined. After forwarding and receiving determinations are made, the data packet is then provided to the mechanical transport layer (e.g., via transport element 226 (296)). In at least one example of the invention, these steps are simplified in a manner that minimizes latency and jitter. In at least one example, the classification engine 232 (260) is configured to perform the procedures of a conventional IEEE Ethernet bridge in an overlapping manner, whereby by the time a packet has been completely received at 271 (272), the classification engine 232 (260) has determined what needs to be done with the packet, to what destination the packet needs to be sent, and through what to route it.

[0099] In the example of the present invention, the bridging delay is the amount of time between when a packet arrives at port 253 and leaves on another port 276. During the time between the packet entering and the packet leaving, as described, the subsystem 200 makes a switching decision (determination) and then performs the transmission function. In the standard Ethernet IEEE world, a store and forward architecture is used to perform the switching function, which necessarily has variable latency. Under variable latency conditions, there is no guarantee that when a packet is received at time zero on the incoming port 253 (104, 105), the packet will leave at a fixed (a priori known) time on a different port (e.g., 276, 245). At least one benefit of the subsystem 200 is that the classification engine 232 makes it known that if a packet is received at time zero, then the packet will be sent out through another port (e.g., 245) within a predetermined (deterministic) period. In at least one example, this period is 1 microsecond. In at least one example, when a component (e.g., slice_0201) has such a short switching time, the component is considered a real-time component, capable of performing its assigned function in 'real time'. In examples of the present invention, real-time computing (RTC) describes hardware and software systems that are subject to "real-time constraints" (for example, from events to system responses). For example, a real-time program must guarantee a response within a specified time constraint (a / k / a 'deadline'). In some examples within the present invention, a real-time response is on the order of milliseconds. In some examples within the present invention, a real-time response is on the order of microseconds.

[0100] Examples of the present invention relate to a communication bridge that operates in a real-time system. A communication bridge is a real-time control system in which input data and output data are exchanged in a deterministic manner. Examples of the present invention include a control device (e.g., 217 (287), 244) and a plurality of slave devices (not shown) or devices (not shown) that consume input / output data from the control device 217 (287), 244 in real time. The real-time system 100, 200 has a communication bridge 255 real-time capability. Therefore, the amount of time used to forward a packet is deterministic, with minimal jitter and latency. In at least one example, jitter and latency are minimized (to a few nanoseconds range) by a hardware timer (not shown) that defines the time when a packet leaves a physical port 253, 252 (255). The real-time operability of the subsystem 200 is different from standard Ethernet, in which jitter of at least tens of microseconds is common. In such conventional systems, the amount of time spent making forwarding / routing decisions varies depending on when the packet arrives, the rate at which the data packets are received, and the content of the packet. In the real-time system (e.g., 200) of the present invention, there is a cyclic execution of the switching function. For example, new data may be exchanged in subsystem 200 every 31 microseconds. A predetermined exchange rate (e.g., 31 microseconds) is used as a time reference. Depending on when a packet comes in (e.g., via port 253), the packet is forwarded with a deterministic latency (in this example, 31 microseconds), or alternatively the data packet is handled according to a store-and-forward approach, as described above for conventional systems. Thus, the packet arrival time may be a discriminator for how a given data packet will be handled by subsystem 200. Another factor considered by receive (RX) classifier 232 when determining what to do with an incoming packet is the data (transmission) rate typically associated with the type of packet in question. For example, if the average data rate of the received packets exceeds a certain data rate threshold, the system may discard (less important) data packets to help ensure that there is sufficient bandwidth for higher priority packets. In at least one example, classifier 232 determines the importance of a given data packet based at least in part on the payload of the packet.

[0101] In at least one example, classifier 232 examines packet contents by first accessing a location in the packet, such as an Ethernet media access control (MAC) address of the packet. A device's MAC address is a unique identifier assigned to a network interface controller (NIC) for communications at the data link layer of a network segment. MAC addresses are used as network addresses for most IEEE 802 network technologies, including Ethernet, Wi-Fi, and Bluetooth. In at least one example, MAC addresses are used in the media access control protocol sublayer of subsystem 200. According to the present invention, a MAC address is recognizable as six groups of two hexadecimal numbers separated by hyphens, colons, or using other symbol systems.

[0102] The data packet may be filtered by the filter 106 based on the designated delivery address (not shown) of the data packet. The data packet includes a six-byte source and destination address. In at least one example, the interface circuit 225 (295) filters (106) the packet based on the information. For example, the interface circuit 225 (295) may read the network address of the packet and determine whether to accept the packet, forward the packet, or discard the packet. In at least one example, the accept-forward-discard decision may be based on the MAC header of the packet. In at least one example, when making the accept-forward-discard determination, the interface circuit may further reach into the packet, reach the payload, and make a filter 106 determination based on the name in the payload. In some implementations of the SoC 200, the device name is concatenated in the payload, and then the content filter 106 looks at the payload.

[0103] In embodiments of the present invention, a data packet will typically contain multiple datagrams. This datagram multiplicity requires that a packet or a portion thereof be delivered to multiple addresses. In other words, multiple subpackets may exist in an Ethernet packet. Since the subpackets may each have their own address, the addresses must be parsed. In the case where multiple addresses exist in one packet, the subsystem 200 will restart parsing whenever a subaddress is detected. Therefore, the interface circuit 225 (295) will have a variable starting offset for the filter 106 to enable the interface circuit 225 (295) to place multiple subpackets in a single Ethernet packet. In at least one example, this means that subpackets derived from a single data packet are sent to different devices (e.g., via the peripheral interface 217 (287)); in examples of the present invention, a single Ethernet packet may contain subpackets, one or more of which are intended for (addressed to) different devices. Unless otherwise indicated, the communication (packet switching) of the present invention is not point-to-point communication. The communication of the present invention is based on a master-to-slave architecture. In an embodiment of the present invention, a single master device (eg, host 246) controls tens, hundreds, or even thousands of slave devices.

[0104] Because of this asymmetric relationship between the master and slaves (1 to N, where N can be a very large number) and the requirement that the communication occur in real time, an interface circuit 225 (295) including ingress filter hardware 106 is provided. The ingress filter 106 (and its accompanying logic) in conjunction with the ingress classifier 232 implements hardware decisions for real-time forwarding and processing. In an example of the present invention, all the information that must be read in order for forwarding and reception determinations regarding a packet to occur is located in the first 32 bytes in the packet. Once the first 32 bytes of the packet are read, PRU_0 219 can look up the header and additional headers depending on the protocol to which the packet conforms. The header can be looked up in real time (e.g., in the filter database 251). Therefore, once the interface circuit 225 (295) has received the first 32 bytes of the packet, the interface circuit 225 (295) has sufficient information to determine whether to forward the packet or whether to receive the packet, as described above. It should be noted that the 32-byte header size described is an exemplary header size. The systems 100, 200 of the present invention may be configured to work with packets having other header sizes.

[0105] As described, the (packet) receive processing is done in real time. In an embodiment of the present invention, AUX_PRU_0 205, PRU_0 219 and interface circuit 225 (295) are programmable and configured so that all packet processing is completely deterministic. Receiving 32 bytes of header information is done in interface circuit 225 (295) at 64 Gbit / s, which enables interface circuit 225 (295) to send 32 bytes of information forward or receive 32 bytes of information. The filter 106 of the present invention is very flexible in that the filter can be moved to filter specific portions of a packet. If there are multiple sub-packets, the filter 106 can be reloaded by interface circuit 225 (295) as needed. In addition, interface circuit 225 (295) can apply masks to set packet ranges or addresses in packets and / or sub-packets. By using greater than and less than operations to group packets, interface circuit 225 (295) may, for example, determine that a packet is to be received when it has an address number from 15 to 29. In some examples, a binary mask may be applied so that sub-packets with addresses starting with an even number, such as 8-7, are forwarded, and sub-packets with addresses starting with an odd number are not forwarded (at least not immediately). Thus, having greater than / less than operations for sub-packet address classification may be advantageous. In some examples, different filters (e.g., 106 and 107) may be operatively combined with other components (e.g., MAC 206 (266), 220 (290)) to further process the packet by its MAC address.

[0106] As described, multiple filters may be combined to allow the interface circuit 225 (295) to make a switching determination. Additional logic may also be applied. For example, the classifier 232 may classify packets and apply classification-dependent logic, such as 'For packet type A, if conditions one, two, and three are true, then the packet will be received'. As another example, in the case where a packet is classified as type B, if condition one is true and condition two is false, then the packet will be discarded. The subsystem 200 may be configured so that the conditions may also include a time window in which the packet is received. For example, the interface circuit 225 (295) may determine that at a particular point in time, the interface circuit 225 (295) will only allow very important (higher priority) input / output data to be forwarded. The interface circuit 225 (295) may be configured so that during a specified period (e.g., after a predetermined event has occurred), a set of filter combinations will be applied, while during other times, all types of data traffic may be allowed. This described programmability is advantageous in industrial environments because industrial communications operate based on hard time windows (in contrast to, for example, teleconferencing).

[0107] In an example of the present invention, multiple hardware filters may be combined with rate filter 107 so that data packets may also be classified according to rate. The filters 106, 107 and hardware 220 (290) operations used may be performed incrementally. Packets may be filtered using any combination of content, time, and rate (all in real time). A given filter 106 may be restarted multiple times for a packet. A filter 106 may have a start address whose value is determined based at least in part on the content and / or content type of a given packet / subpacket.

[0108] In at least one example of the present invention, the interface circuit 225 (295) is configured to automatically detect whether a packet contains a virtual local area network (VLAN) tag. Some Ethernet packets have a tag for a tag byte in the middle of the packet or at the trailing MAC address. It can happen that if a filter is applied to the data of the trailing MAC address, the MAC address will be shifted by four bytes undesirably. The example interface circuit 225 (295) of the present invention solves this problem by automatically detecting whether a packet has a VLAN tag, and if the packet does contain a VLAN tag, restarting the relevant filter 106 using the location of the VLAN tag as the starting address. Thereafter, the interface circuit 225 (295) uses combinatorial logic to make a determination (e.g., whether to accept or discard the packet), which combinatorial logic may involve any appropriate combination of AND, OR, and filter flags. In one or more examples of the present invention, the rate counter 107, which may be a hardware rate counter, determines the rate depending on the type of traffic in question and a predetermined time window for the type of packet. Thus, there may be a specific time for high priority packets and a different time for non-real time packets, and different filters may be applied depending on the situation. In some examples, filters 106 that produce immediate results during receive time (on-the-fly) processing will forward the packet in question regardless of the length of the packet. This operational capability is in stark contrast to conventional Ethernet, where a packet is first received, one or more lookup tables are consulted, and then a switching decision is ultimately made. In some examples of the present invention, the packet size is predetermined and communication occurs at a fixed rate per packet. In other examples, information about the packet length is contained within the header of the packet. In either case, the packet length is determined in hard real time.

[0109] At least one technical benefit of the architecture described in the present invention is that the architecture enables switching / forwarding determinations to be completed within a single microsecond, even for packets with a length of up to twelve microseconds. The time- and data-rate-based combinational logic of the interface circuit 225 (295) enables the classification engine 232 to execute in a robust manner. The ability of the subsystem 200 to restart the filter 106 to apply the filter 106 multiple times in a packet enhances the ability of the subsystem 200 to make packet switching decisions in real time. In an exemplary embodiment, the length of the filter 106 is limited. If the packet is longer than the filter, the filter 106 will need to be reloaded. If the Ethernet contains sub-packets, the filter 106 can be reused for multiple locations with a single packet. In some instances, the sub-packets will each have their own address. For example, if three sub-packets are included, the address filter 106 can be loaded three times to apply the same address filter 106 to each sub-packet. PRU_0 219 writes the data to TX_L2 via interface 252 (255), and the data then leaves slice_0 201 along communication path 253. The described real-time processing supports the resource availability and allocation management described below.

[0110] As described, aspects of the present invention and components of ICSS200 relate to motor control. Application site communication can be used to transmit motor control signals. In industrial environments, devices and components can transmit input / output data between each other according to one or more Ethernet protocols. In the case of motor drive and motor control, there is always an application side of this input / output data. The motor can be driven by multiple pulse width modulated signals. Pulse width modulation is used to control motor applications in backgrounds such as robots, machine tools, and conveyor belts. Proper pulse width modulation of mechanical devices like these is an important factor in maintaining safe operation in places such as factories and work sites. One aspect of safety is device error mitigation. Another aspect of safety is device error minimization. One way to mitigate and minimize device errors is to understand the causes and effects of past errors. One or more examples of the present invention are directed to identifying and tracking the source of errors (sometimes called 'transient fluctuations') and tracking when transient fluctuations occur. Examples of the present invention include systems and methods for safely controlling pulse width modulation driven devices (such as motors) in the presence of transient fluctuations, thereby mitigating any damage that may be caused by such transient fluctuations.

[0111] As mentioned, a pulse width modulator (e.g. Figure 2BThe PWM 244 in the embodiment of the present invention controls the motor. In an example of the present invention, the PWM drives the motor at a specific speed and a specific torque by controlling the motor using a pulse width modulated signal. In industrial applications, there are usually six pulse width modulated signals for driving a three-phase electric machine (such as a three-phase motor). In addition, there is a signal called a trip signal, which is sent to the PWM to cause the PWM to shut down the motor power stage. As previously explained, the pulse width modulated signal is converted into a high power signal to drive a high power motor. The trip signal can reach the power unit from the control unit, such as the PWM.

[0112] One way to enhance safety in environments involving industrial applications (e.g., robotics, server drives, computer numerical control (CNC)) is to be able to quickly (and safely) shut down the power stages of such applications. Examples of power stages within the present invention are metal oxide field effect transformers (MOSFETs), insulated gate bipolar transistors (IGBTs), and other electronic devices that drive motors.

[0113] The duty cycle or power cycle is the portion of a period (T) in which a signal or system is active. The period is the time it takes for a signal to complete an on-off cycle. The duty cycle (D) is the ratio of the pulse width (PW) (pulse active time) to the period (T). The duty cycle (D) can be defined according to the following formula: D = PW / T. The nature of the duty cycle of PWM means that for a three-phase motor, up to six of those pulse width modulated signals are necessary for control. Within the present invention, the trip signal is the signal sent by the pulse width modulator 244 to cut off the power stage in the event of a fault condition.

[0114] There are many conditions where it may be necessary to stop the power generating hardware. A trip signal indicates that such a condition exists. For example, there may be a fault condition in the power stage itself, such as a short circuit. A trip signal may be issued because the temperature in a component is too high, or there is too much current flowing. A trip signal may be issued because one or more motors are in an incorrect position, or because the motors are running at the wrong speed.

[0115] In some industrial environments, there may be a large amount of electromagnetic interference, which may affect the signal output of electronic devices. Changes in signal output can be interpreted as indicating that there are transient fluctuations and errors in the components from which the signal output comes. Sometimes, this can cause false alarms in error detection. In addition, not all error detections necessarily require power level closure. As will be described in more detail below, examples of the present invention include systems and methods for filtering transient fluctuation indication signals. In some instances, transient fluctuation filtering is performed by one or more logic blocks, and the one or more logic blocks are configured to distinguish between PTOS that require power level closure and PTOS that do not require power level closure. In some instances, combining multiple PTOS into a single PTOS is an aspect of transient fluctuation filtering.

[0116] Aspects of the present invention relate to capturing data for diagnostic purposes. For example, if a fault condition (transient fluctuation) is detected once for a component, it may be appropriate to ignore the fault condition, while if the same fault condition is detected three times in close succession, it may be appropriate to investigate the cause of the transient fluctuation. In one or more examples of the present invention, PTOS is recorded and summarized. In this way, PTOS data from different information sources is fed to a transient fluctuation filter (which may be a state machine) to improve the operational accuracy of the transient fluctuation filter over time. In some examples, the filter logic can be reprogrammed based on the described transient fluctuation analysis. In some examples, the transient fluctuation data is analyzed and fed back to the transient fluctuation filter in real time.

[0117] The signals between the PWM and the motor driven by the PWM are motor side communications. Motor side communications are done according to a motor side communications protocol which is not an Ethernet protocol. Motor side communications are serial based, but are real time communications of position data to a control unit and then motor currents, which are typically bit streams from an analog / digital computer using a delta-sigma method 216, with data about current values ​​contained within the bit stream. Some motor side communications are protocol based communications (like position feedback signals), while other motor side communications (like motor currents) are sent in a bit stream. Pulse width modulated signals are examples of digital control signals.

[0118] In at least one example of the invention, a filter state machine receives a signal indicating that one or more events have occurred. The filter state machine may have a static trip configuration or a dynamic trip configuration. A filter operating in a static configuration (or mode) will issue a trip signal when a specific event (such as a transient fluctuation) is detected. A filter state machine operating in a dynamic mode may detect a pattern of events. For example, a dynamically configured filter may issue a trip signal if the same error is detected multiple times (depending on the severity of the error) in a particular cycle.

[0119] In at least one example of the present invention, the transient fluctuation filter can be programmed to issue a trip event indication signal (TEIS) depending on what event signal the filter receives. The signal (412A, 422) input to the transient fluctuation filter (412, 417) through the logic block (414) or amplifier (417A) or other components can be subject to impulse noise, where the signal briefly switches from one state to another state and then returns. For example, from inactive to active, and then quickly returns to inactive. The transient fluctuation filter (412, 417) will remove short-term state changes in the inactive input signal (for example, low) and ensure that the output signal from the filter remains inactive (does not switch to the incoming state), assuming that the active input signal is within the predefined transient fluctuation width.

[0120] In one or more instances, the transient fluctuation filter has an active state and a reset state. When the ICSS 200 is powered on, the components of the ICSS need to enter a defined reset state. After the reset state, the components (such as motor applications) can enter the active state. The timing of the reset state is controlled by the state machine. The state machine (421) can be programmed for single detection. When programmed for single detection, once the state machine (421) determines that an event or combination of events worthy of a trip signal has occurred (as long as the state machine receives a valid and unmasked (active) trip input (411 to 420)), and as a result, a trip signal is output (becomes a predefined value, becomes active), the output signal (408) will remain active (also called 'latched'), even if the input trip signal returns to an inactive state.

[0121] The state machine may be programmed so that the detection and trip output settings are reset with the cycle time of the period of the motor control cycle. In this cycle-by-cycle mode, when the inputs (411 to 420) disappear, the trip signal (408) will end and the PWM (244) will resume normal operation. Single detection helps ensure that the power stage is completely shut down and the motor current goes to zero (until reset externally, albeit manually). Single detection is more suitable for critical fault conditions such as short circuit detection or position error faults. Note that in some examples, the state machine (421) can be configured to handle some trip inputs in a single manner, while for other trip inputs, when these other inputs become inactive in the next cycle, the state machine will stop issuing the trip signal (408). Therefore, the ICSS can be tailored according to the needs of the user. In some embodiments, the state machine can scan for transient fluctuations within one or more multiples of 31.25 microseconds. In at least one embodiment, the transient fluctuation filter scans the transient fluctuation signal at a rate of 60 kHz. In at least one embodiment, the transient filter scans the transient signal at a rate of 80 kHz.

[0122] Unlike conventional systems, the ICSS 200 manages all aspects of the protection source and pulse width modulated power control. In one or more embodiments, the transient fluctuation filter component of the ICSS 200 is highly customizable because it is programmable and configurable to operate in varying environments. Despite the versatility and programmability of the transient fluctuation filter, the transient fluctuation filter also has low latency. In one or more instances, information is moved through the ICSS 200 at five nanosecond intervals. In some instances, the information is communicated to the ICSS 200 via one or more communication interfaces (e.g., Figure 2B 270, 271 and 272 in the ICSS 200 to communicate position information (regarding an external device, such as a motor). This position information may be real-time information. In some instances, since the position information is received in real-time, if the position information indicates that an error exists, information about the positioning error is transmitted to the hardware state machine. If the hardware state machine is configured (for example) to trigger on a position error, the hardware state machine will immediately output a trip signal. In at least one instance of the ICSS 200, there is a combination of a hardware state machine and computational logic that resides in the real-time processing and communication domain of the ICSS 200. This arrangement is different from conventional solutions in which communications about control functions are controlled by an external ASIC or SPGA and information about control functions is passed to the control PRU through an interface.

[0123] In at least one example of the invention, low latency in ICSS 200 is enhanced by integrating all trip inputs into one hardware device. Management of all trip inputs occurs in a single hardware state machine (421).

[0124] Figure 3 The diagram illustrates aspects of pulse width generation 301 according to an example of the present invention. Figure 3 , nine complementary pulse width modulated outputs are matched to three motors 311. Pulse width modulated signals 308 and pulse width modulated signals 309 are generated by pulse width modulator (PWM) 244. For example, the 'x' suffix in the 'PWMx' indicator (308) and the ' / PWMx' indicator (309) reflects the fact that more than one pair of pulse width modulated signals (272) are used to drive a three-phase motor. Control signal 305 and comparator signal 306 are generated by IEP0 241. Control signal 305 and comparator signal 306 go to PWM 244. Also shown is a trip output signal 307 (425) that goes to PWM 244 when a specific type of event occurs, as will be shown in FIG. Figure 4A and Figure 4BThe control signal 305 and the pulse width modulation signal 308 and the pulse width modulation signal 309 are generated by the PWM 244. The position event indicator 302 is an indication that an error event has occurred. The position event indicator 303 is an indication that another error event has occurred. The PRU 219 and the peripheral interface 217 form a feedback system that tracks the position data of the motor and generates a No. 5 trip event indication signal (420) when a position error is detected. The sawtooth signal 305 is output from the compare0 register (402). Also in Figure 3 2. A cycle 304 of signal 305 is shown in FIG. 2. Trip event indicator 307 indicates that external output pin 432 has sent a signal indicating that trip event-2 has occurred (TEIS-2). Pin 432 is connected to PWM 244. Delta-sigma current measurement 312 is generated by sigma-delta 216 and PRU of FIG.

[0125] Figure 4A A logic configuration 400 of a pulse width modulation monitor and controller of an example ICSS (200) is illustrated. Figure 4B The diagram illustrates the trip signal logic circuit 421 of the ICSS (200) interacting with the logic configuration 400. Figure 4B As shown in and as discussed above, each trip signal logic circuit 421 can generate a single trip output signal 425. The value of the selector signal 426 specifies whether the trip signal logic circuit 421 is to operate in a single-shot mode or, alternatively, in a cycle-by-cycle mode, as explained above. Figure 4B In the example illustrated in , the trip signal logic circuit 421 is configured to track five trip input signals that each correspond to a trip event.

[0126] Figure 4A4 monitors the PWM output signal 308 of the PWM terminal 430 and the PWM output signal 309 of the PWM terminal 431. If both the signal 308 and the signal 309 are active (high), the gate 414 outputs the event indication signal No. 1 (EIS-1) 412A to the transient fluctuation filter 412. Depending on how the transient fluctuation filter is configured, when the transient fluctuation filter 412 receives the EIS-1 412A, the transient fluctuation filter 412 sends the trip event indication signal No. 1 (TEIS-1) 411 to the trip signal logic circuit 421. As described, the PWM (244) generates nine complementary pulse width modulation outputs for each group of three motors. Based on the EIS 412A from the gate 414, the TEIS-1 411 monitors the pulse width modulation signals generated by the PWM (244) to ensure that the pulse width modulation signals 308, 309 are complementary to each other (are in phase, two transistors are not activated at the same time, etc.). Transient filter 412 can be configured using configuration memory mapped registers 413 to filter or block EIS-1 412A (which does not meet a certain threshold, such as when the trip signal is too brief) from gate 414. Transients such as these are reflected in small spikes of 1 or 0, which are usually caused by external electromagnetic interference.

[0127] Event Indication Signal No. 2 (EIS-2) 432A ( Figure 4A432A) corresponds to a signal from an external source 432. For example, an external power board may be configured to send EIS-2 432A if the temperature of the power board exceeds a certain threshold. As in the case of TEIS-1 411, a transient fluctuation filter 417 is inserted between the external source 432 and the input 415A of TEIS-2 415 (corresponding to trip event-2), and the transient fluctuation filter may be configured 416 to filter error signals (such as EIS-2 432A) indicating false alarms. If the EIS-2 432A from the external source 432 meets certain customizable criteria, the transient fluctuation filter 417 only sends the trip event indication signal (TEIS-2) 415 to the trip signal logic circuit 421. In practice, the filters 412 and 417 will be programmed based on the needs of the environment in which the ICSS (200) is operating. For example, if a signal error such as chattering or ringing occurs while a robotic arm is being used to spray paint, such a signal error is more likely to indicate a true fault than if it occurs in a welding environment (where electromagnetic interference is not uncommon). The programmability of the filters 412, 417 allows the sensitivity of error detection in the ICSS to be finely tuned. The trip event indication signal No. 3 418 indicates that the Σ-Δ (216) has detected a short circuit. The trip event indication signal No. 4 419 indicates that an overcurrent has been detected in one or more motors controlled by (for example) the ICSS (200). The trip event indication signal No. 5 (TEIS-5) 420 is based on feedback received by the PRU 219 (using a serial-based protocol). If the PRU determines that an external component controlled by the ICSS (200) is in an incorrect position, the PRU 219 sends the TEIS-5 420 to the trip signal logic circuit 421. The trip signal logic circuit 421 may be configured 427 to mask one or more trip input signals, meaning that the trip signal logic circuit 421 may be configured to send a trip output signal 425 that, for example, will cause the motor to shut down (only for desired trip event combinations).

[0128] Figure 4AThe trip capture block 401, comparator 0 403, counter 403, drift compensation input 404, comparator 1 405 and comparator 2 409 illustrated in are components of IEP0 (241). A hit signal 405A is sent from comparator 405 of IEP0 241 to input PWM1 of PWM 244. An output buffer 407 is inserted between IEP0 and PWM 244. Buffer trigger 406, output buffer 407, buffer 410, transient fluctuation filter 412, configuration input 413, gate 414, trip event second input 415A, transient fluctuation filter configuration input 416, buffer 417 and trip signal logic circuit 421 are components of PWM 244. Output pin 430 and output pin 431 are output pins of PWM 244. Signal 308 is sent from output pin 430 and signal 309 is sent from output pin 431. Comparator 1 405 compares its programmed value (cmp_1) to the value (IEP_counter) in counter 403. If the value in comparator 1 405 is equal to the value in counter 403, then comparator 1 will issue a hit signal 405A.

[0129] In at least one embodiment, when comparator 1 405 hits signal 405A (see Figure 3 306) is sent to PWM 244, the hit signal forms a rising edge in signal 308. Similarly, when comparator 2 409 sends hit signal 409A to PWM 244, the hit signal forms a rising edge in signal 309. IEP counter 403 counts errors and the number of errors detected is represented by the rising edge of sawtooth waveform 305. Like comparator 1 405, comparator 2 409 compares its programmed cycle value (cmp_0) with the value in IEP counter 403 (iep_counter). When the number of errors in IEP counter 403 reaches the value in comparator 402, IEP counter 403 is reset to zero. (If the values ​​in comparator 2 409 and IEP counter 403 are the same, then the value of IEP counter 403 is reset to zero.)

[0130] In at least one example of the present invention, it may be beneficial to synchronize the pulse width modulated signal from PWM 244 with other cycles, such as a communication cycle. Figure 4A, drift compensation 404 is used to shift the output signals 308, 309 from PWM 244 to keep the output signals in phase with other components (e.g., an external clock). PWM 244 has an active mode 406A and an initialization mode 406B; input 406 selects the operating mode 406A, 406B of PWM 244. During initialization mode 406B, the pulse width modulated output signal 272 is set to high impedance H or low impedance L. If PWM 244 receives a hit signal 405A at input buffer 407 when PWM 244 is in active mode 406A, then PWM 244 will output 272 a high impedance signal H or a low impedance signal L or will switch output 430 (272) from one (current) output signal (H or L) binary state to another output signal, depending on how input buffer 407 is programmed. In one or more examples, the input buffer 407 can be easily reprogrammed as desired by the user and / or the environment in which the ICSS 200 operates. The trip signal 408 is transmitted by the trip signal logic circuit 421 (when a trip condition is determined by the trip signal logic circuit 421) and enters the input buffer 407 as shown. When the PWM 244 is in the active mode 406A, the trip signal 408 will cause the output 430 of the PWM 244 to be high impedance (Z), high (H) or low (L), depending on how the buffer 407 is configured. The trip signal 408 will overrule the hit signal 405A. Comparator-2 409 has the same function as comparator-1, but is used for negated pulse width modulation signal 309. Comparator-2 409 of IEP0 241, when asserted, sends a hit signal 409A to filter 410, which, depending on the settings of the filter, outputs the hit signal 409A to output 431 of PWM 244 via signal 410A. Signal 410A also goes to gate 414. If both signals 410A and 407A are active, gate 414 will generate an EIS at 412, which will trigger TEIS 411 at transient fluctuation filter 412, which will cause trip logic 421 to issue a trip signal 408, which will in turn cause PWM (244) to enter an inactive state. The condition where both (complementary) PWM signals PWM1 and / PWM1 are active is catastrophic because this will turn on both the high-side and low-side switches in the power stage and create a short circuit therein. This condition is called shoot-through and should be avoided due to the possible damage or injury that may result from a short circuit in the power stage.

[0131] The filter 410 is controlled by a state machine (421), as will be explained in more detail below. During a first state (initialization) of the filter 410, the signal 410A is an initialization signal, during a second (active) state, the signal 410A corresponds to the hit signal 409A, and during a third (error) state, the signal 410A is set according to the trip signal 408.

[0132] TEIS-1 411 corresponds to an error condition in which both the output signal 308 from the PWM 244 terminal 430 and the output signal 309 from the PWM 244 are active (high). If both the output signal 308 from the PWM 244 terminal 430 and the output signal 309 from the PWM 244 are in an active state (for example, both are high), the power stage of the motor being driven by the PWM 244 may be damaged (due to a short circuit). The gate 414 monitors the PWM output terminal 430 and the PWM output terminal 431. If the gate 414 determines that the PWM output terminal 430 and the PWM output terminal 431 have the same high output, which means that a trip event one has occurred, then in this case, the gate 414 sends EIS-1 412A to the transient fluctuation filter 412. (When both signal 308 and signal 309 are low, it is not an error condition.) If transient fluctuation filter 412 determines that EIS-1 412A corresponds to a true error or fault condition rather than a transient fluctuation, then Figure 4A The transient fluctuation filter 412 sends TEIS-1 411 to Figure 4B The trip signal logic circuit 421.

[0133] Filter 412 may be configured, for example, to ignore EIS-1 412A when EIS-1 412A drops below a threshold. For example, in a robot and machine environment, if there is a minor trip, it may be attributed to electromagnetic interference (a momentary fluctuation) in the environment, rather than a true error condition that warrants shutting down the power level of the device being driven by PWM 244. Again, the sensitivity of PWM 244 to momentary fluctuations may be adjusted by configuring momentary fluctuation filter 412 (and momentary fluctuation filter 417). Momentary fluctuation filter 412 may be configured 413 to mask (or shield) EIS-1 412A that is shorter than a threshold period; the threshold period may be set to 10 nanoseconds or 100 nanoseconds, and any period between 10 nanoseconds and 100 nanoseconds. Configuration memory mapped registers store the thresholds for momentary fluctuation filter 412. The transient fluctuation filter 417 can be configured using the configuration memory mapped register 416 to mask (or shield) event indication signals (e.g., EIS-2 432A) that are shorter than a threshold period; the threshold period can be set to 10 nanoseconds or 100 nanoseconds, and any period between 10 nanoseconds and 100 nanoseconds. The configuration memory mapped register 416 stores the threshold value for the transient fluctuation filter 417.

[0134] In at least one example, the trip signal logic circuit 421 may receive five trip signals. TEIS-1 411 is from the transient fluctuation filter 412 and indicates that the output terminals 430, 431 of the PWM 244 are simultaneously high. The trip event-1 input 411a is labeled '[2..0]' because the three-phase motor is driven by three pairs of pulse width modulation signals 308, 309, 430, 431. The second trip event indication signal 415 indicates that there is a fault in the external component 432. The third trip event indication signal 418 is from the PRU 219 and the Σ-Δ accelerator 216 and indicates that there is a short circuit in the SoC 246, of which the ICSS200 is a component. The fourth trip event indication signal 419 is from the PRU 219 and the Σ-Δ accelerator 216 and indicates that there is an overcurrent in the SoC 246, of which the ICSS200 is a component. The trip event indication signal five 420 comes from the PRU 219 and the peripheral interface 217 and may indicate that the device being controlled by the ICSS 200 is in an incorrect position. The mask input 427 and the compare-0 input 426 are used to configure the trip signal logic circuit 421.

[0135] Figure 5 The diagram illustrates a system 500 according to an example of the present invention. Block 501 highlights Figures 2A to 2C Control PRU-1 502 corresponds to Figure 2APRU 215. Interface PRU-1 503 corresponds to Figure 2A PRU 219. Control PRU-2504 corresponds to Figure 2C PRU 265. Interface PRU-2 503 corresponds to Figure 2C PRU 289. IEP Timer-1506 corresponds to Figure 2B IEP0 241. IEP Timer-2 corresponds to Figure 2B The system 500 (200) includes four multiplication units 508. The system 500 includes a combination of a broadside random access memory and a triangular lookup table 509. The task manager 510 corresponds to Figure 2A Task Manager 209 and 223 and Figure 2C The task managers 269 and 293. The interrupt controller 511 corresponds to Figure 2B The PWM block-1 512 and the PWM block-2 513 illustrate the fact that the ICSS 200 includes the same Figure 2B The PWM 244 of FIG. 5 illustrates the fact that the PRU 219 and the accelerator 216 are capable of generating nine sigma-delta signals (418, 419). The sigma-delta block 513 illustrates the fact that: Figure 2A The PRU 219 and accelerator 216 of FIG. 5 are each capable of generating nine sigma-delta error signals ( 418 , 419 ). The delta-sigma block 514 illustrates the following fact: Figure 2C The PRU 265 and accelerator 286 are also each capable of generating nine sigma-delta error signals (418, 419). The encoder block 516 illustrates that the peripheral interface 217 utilizes three encoders for motor position measurement. Similarly, the encoder block 517 illustrates that the peripheral interface 287 utilizes three encoders for motor position measurement.

[0136] Figure 6 It is a display Figure 4A6. The state diagram 600 of the relationship of the possible states of the buffer 407 is shown in FIG. 6. Upon power-up, the buffer 407 immediately enters the initialized state 601. When the buffer 407 is in the initialized state 601, the output 407A of the buffer 407 may be high impedance (Z), high (H), or low (L). After the initialization 601 of the buffer 407 is completed, the buffer 407 may enter the active (operational) state 602. When the buffer 407 is in the active state 602, if the buffer 407 receives a hit signal 405A, the hit signal 405A will cause the output 407A of the buffer 407 to be high (H), low (L), or the hit signal 405A will cause the value of the output signal 407A to be toggled (if the output 407A is high, the output 407A will switch to low; if the output 407A is low, the output 407A will switch to high). Regardless of whether the buffer 407 is in the initialized state 601 or in the active state 602, when the buffer 407 receives the trip signal 408, the buffer will be placed in the safe mode 603. In the safe mode, the value of the output signal 407A will be high impedance (Z), high (H), or low (L), depending on how the buffer 407 is programmed. Note again that the buffer 407 can be reconfigured based on the needs of the user.

[0137] Figure 7 FIG. 4 is a block diagram of a state machine 700 (421) according to an example of the present invention. Figure 7 , block 701 represents the inputs (411 to 420) of the state machine (421), the trip input being analyzed by the state machine 700 and causing the state machine 700 to send a trip signal 703 to an input-output port 702, which includes the buffer 407 and the output terminal 430 of the PWM 244. Block 704 illustrates the configurable logic of the state machine 700, which determines how the state machine 700 will handle an existing trip signal 703 depending on whether the state machine 700 is in a one-shot mode or a cycle-by-cycle mode, as previously described.

[0138] Although SoC is primarily used throughout the above disclosure as an example type of chip, it will be appreciated that the techniques described herein may be applied to design other types of IC chips. For example, such IC chips may include general or application specific (ASIC) processors based on x86, RISC or other architectures, field programmable gate arrays (FPGAs), graphics processors (GPUs), digital signal processors (DSPs), single chip system (SoC) processors, microcontrollers, and / or related chipsets.

[0139] Specific terms are used throughout this specification and claims to refer to specific system components. As will be appreciated by those skilled in the art, different parts may refer to a component by different names. This document does not intend to distinguish between components that are different in name but the same in function. In the present invention and claims, the terms "including" and "comprising" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". Moreover, the term "couple" or "couples" is intended to mean an indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. The statement "based on" is intended to mean "based at least in part on". Thus, if X is based on Y, then X may be based on Y and any number of other factors.

[0140] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, a person skilled in the art will appreciate numerous changes and modifications. It is intended that the appended claims be interpreted as encompassing all such changes and modifications.

Claims

1. A device comprising: A controller comprising: a set of inputs receiving a set of event indication signals associated with motor operation; a set of fluctuation filters coupled to the set of inputs such that each fluctuation filter in the set of fluctuation filters is configured to generate a respective trip signal in the set of trip signals in response to a respective event indication signal in the set of event indication signals; and a logic circuit coupled to the set of fluctuation filters to receive the set of trip signals and configured to provide a trip output signal configured to disable the operation of the motor in response to the set of trip signals; and a pulse width modulator coupled to the controller, wherein the pulse width modulator comprises: a set of outputs providing a set of complementary signals configured to control the operation of the motor, wherein the set of outputs is coupled to a subset of the set of inputs of the controller; and An input is coupled to the logic circuit to receive the trip output signal.

2. The device of claim 1, wherein the pulse width modulator is configured to disable the set of complementary signals in response to the trip output signal.

3. The apparatus of claim 1, further comprising a power stage, the power stage comprising: a set of inputs coupled to the set of outputs of the pulse width modulator to receive the set of complementary signals; as well as An output is configured to be coupled to the motor to control the operation of the motor in response to the set of complementary signals.

4. The device according to claim 1, wherein: The logic circuit is a first logic circuit; The controller includes a second logic circuit coupled to the subset of the set of inputs of the controller to receive the set of complementary signals; as well as The second logic circuit is configured to assert a first event indication signal in the set of event indication signals in response to each signal in the set of complementary signals being simultaneously asserted. 5 . The apparatus of claim 1 , wherein the set of event indication signals comprises at least one of a processor event signal, a short circuit event signal, an over current event signal, or a position error event signal.

6. The device according to claim 1, wherein: The logic circuit includes an input for receiving a mask; as well as The logic circuit is configured to mask a first subset of the set of trip signals based on the mask such that the trip output signal is provided in response to a second subset of the set of trip signals.

7. The apparatus of claim 1 , wherein the logic circuit comprises an input for receiving a control signal; and The logic circuit is configured to select, based on the control signal, between asserting the trip output signal prior to receiving a reset signal or asserting the trip output signal prior to a change in the set of trip signals.

8. The device of claim 7, wherein the logic circuit is configured to select, based on the control signal: asserting the trip output signal in response to a first subset of the set of trip signals prior to receiving a reset signal; and The trip output signal is asserted in response to a second subset of the set of trip signals before a change occurs in the second subset of the set of trip signals.

9. The apparatus of claim 1, wherein each fluctuation filter in the set of fluctuation filters comprises a configuration input for receiving a filter threshold.

10. The apparatus of claim 9, wherein each fluctuation filter in the set of fluctuation filters is configured to compare a duration that the corresponding event indication signal is asserted to the corresponding filter threshold to determine whether to assert the corresponding trip signal.

11. A method comprising: Receive mask; A controller receives a set of event indication signals associated with the operation of the motor; for each event signal in the set of event indication signals, applying a fluctuation filter to the corresponding event signal to generate a corresponding trip signal in a set of trip signals; masking, by the controller, a first subset of the set of trip signals; as well as Based on the mask, a trip output signal is provided by the controller in response to a second subset of the set of trip signals not including the first subset, wherein the trip output signal is configured to disable operation of the motor.

12. The method according to claim 11, further comprising: receiving a set of complementary signals associated with phases of the motor from a pulse width modulator; detecting whether the set of complementary signals are asserted simultaneously; as well as Based on whether the set of complementary signals are simultaneously asserted, it is determined whether to assert a first event indication signal in the set of event indication signals.

13. The method of claim 12, further comprising determining whether to disable the set of complementary signals based on the trip output signal. 14 . The method of claim 11 , wherein the set of event indication signals comprises at least one of a processor event signal, a short circuit event signal, an over current event signal, or a position error event signal.

15. The method according to claim 11, further comprising: receiving a control signal; as well as A determination is made based on the control signal whether to assert the trip output signal before receiving a reset signal or to assert the trip output signal before a change in the set of trip signals.

16. The method of claim 15, wherein the control signal specifies that the trip output signal is asserted before the reset signal is received for a third subset of the set of trip signals, and specifies that the trip output signal is asserted before a change in the set of trip signals occurs for a fourth subset of the set of trip signals. 17 . The method of claim 11 , wherein applying the fluctuation filter to the corresponding event signal to generate the corresponding trip signal comprises applying an independent threshold to the corresponding event signal.

18. The method of claim 17, wherein the independent threshold of each fluctuation filter is within 10 and 100 nanoseconds.

19. An apparatus comprising: A controller comprising: a set of inputs receiving a set of event indication signals associated with the operation of the motor; a set of fluctuation filters coupled to the set of inputs such that each fluctuation filter in the set of fluctuation filters is configured to generate a respective trip signal in a set of trip signals in response to a respective event indication signal in the set of event indication signals; and a logic circuit coupled to the set of fluctuation filters to receive the set of trip signals, wherein the logic circuit includes an input to receive a mask and is configured to: masking a first subset of the set of trip signals based on the mask; and A trip output signal is provided, the trip output signal configured to disable operation of the motor in response to a second subset of the set of trip signals not including the first subset.

20. The apparatus of claim 19, wherein the set of event indication signals comprises at least one of a processor event signal, a short circuit event signal, an over current event signal, or a position error event signal.

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