Push-pull voltage output stage circuit, voltage regulator circuit and chip

Abstract

The present disclosure provides a push-pull voltage output stage circuit, a voltage regulator circuit and a chip, including an output drive branch and an output mirror branch; the output drive branch includes an output NMOS tube and an output PMOS tube connected in sequence; the output mirror branch includes a first NMOS tube and a first PMOS tube connected in sequence; the drain of the output NMOS tube and the first NMOS tube is connected to a first input voltage, and the gate of the output NMOS tube and the first NMOS tube is connected to a second input voltage; the gate of the output PMOS tube and the first PMOS tube, and the drain of the first PMOS tube are grounded via a current source circuit. The push-pull voltage output stage circuit and the voltage regulator circuit disclosed in the present disclosure not only have a fast response speed, but also use a push-pull circuit, whether it is established from a high voltage to a low voltage, or from a low voltage to a high voltage, it can quickly establish the output voltage to a required target voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and in particular to a push-pull voltage output stage circuit, a voltage regulator circuit and a chip. Background Art

[0002] For the normal operation of the internal circuit of the chip, the required analog voltage must be generated inside the chip. For many chips, the voltages required by different modules inside the chip or the same module during different operations are different. This means that a circuit that can provide different voltage values ​​is needed. Different application scenarios and different chips require different voltage values. The required voltage value can be lower than the power supply voltage, equivalent to the power supply voltage, or higher than the power supply voltage.

[0003] If the required voltage value needs to be lower than the power supply voltage VDD under certain working conditions, and needs to be higher than VDD or equal to VDD under certain working conditions, it can be achieved in the following two ways:

[0004] 1. It is composed of a linear amplifier, a high-voltage circuit structure and an analog switch. The high-voltage circuit structure usually includes a charge pump, a comparator, an oscillator, and a resistor divider string.

[0005] 2. High voltage circuit structure plus high voltage regulator, such as Figure 1 As shown, the high-voltage circuit structure always outputs a high-voltage signal Vhv, and uses this voltage as the power supply of the high-voltage regulator. The required output voltage is configured by adjusting the high-voltage regulator. Figure 1 There are many ways to implement the high-voltage regulator in the circuit. It can be a single-power supply circuit or a dual-power supply circuit. The most common single-power supply circuits are two types, namely PMOS (P-Channel-Oxide-Semiconductor) output stage linear regulator and NMOS (N-Metal-Oxide-Semiconductor) output stage linear regulator.

[0006] Both structures have three common disadvantages when used in high-voltage systems: 1. High-voltage linear regulators consume a certain amount of static operating current, which comes from the charge pump circuit. If the current is large, the charge pump area is large and the overall power consumption is large; 2. The speed of Vout switching from high to low will be relatively slow; 3. The output capacitive load will introduce a non-negligible pole, affecting the loop response speed.

[0007] One existing method to address the above shortcomings is to use an open-loop design method for the output stage, such as Figure 2As shown in the figure, the first-stage error amplifier circuit and the second-stage follower form a closed-loop circuit, and the output node Vout connected to the load circuit is open-loop. Therefore, the bandwidth of the two-stage operational amplifier composed of the first error amplifier circuit and the second-stage follower is wider, and the loop response speed is faster. R2 of the output stage circuit is a variable resistor. When the output voltage is established from high to low, R2 is reduced. When Vout is close to the target voltage value, R2 is increased to reduce the current load of the charge pump. However, if the resistance value of R2 needs to be precisely controlled, a detection circuit is required to detect the Vout value in real time, which increases the complexity of the circuit.

[0008] Another open-loop voltage regulator is Figure 3 As shown in the figure, the resistor string samples the high voltage signal to generate Vhg, and connects it to the gate of NMOS tube N0, so that Vout=Vhg-Vgsn0 is obtained, and Vgsn0 is the gate-source voltage of N0. The advantage of this structure is that the circuit is simple to implement, but there are two disadvantages: 1. Vout will have a certain deviation with the change of temperature and process; 2. When Vout is established from high voltage to low voltage, there is still a problem of limited establishment speed. Summary of the invention

[0009] The technical problem to be solved by the present disclosure is to overcome the defects in the prior art and provide a push-pull voltage output stage circuit, a voltage regulator circuit and a chip with short high and low voltage establishment time.

[0010] The present invention solves the above technical problems through the following technical solutions:

[0011] A push-pull voltage output stage circuit comprises an output drive branch and an output mirror branch;

[0012] The output drive branch comprises a push-pull structure; the output mirror branch comprises a mirror push-pull structure which is mirrored to the push-pull structure of the output drive branch;

[0013] The output driving branch includes an output NMOS tube N0 and an output PMOS tube P0 connected in sequence;

[0014] The output mirror branch includes a first NMOS transistor N1 and a first PMOS transistor P1 connected in sequence;

[0015] The drains of the output NMOS transistor N0 and the first NMOS transistor N1 are connected to the first input voltage Vhv, and the gates of the output NMOS transistor N0 and the first NMOS transistor N1 are connected to the second input voltage Vhg;

[0016] The gates of the output PMOS transistor P0 and the first PMOS transistor P1, and the drain of the first PMOS transistor P1 are grounded via a current source circuit.

[0017] Preferably, the current source circuit further comprises a bias circuit for providing a static operating current for the output mirror branch.

[0018] Preferably, the output driving branch further includes an enabling switch, and the enabling switch is driven based on an enabling signal En.

[0019] Preferably, an initialization switch is further provided between the output drive branch and the output mirror branch, and the initialization switch is driven based on an enable signal En.

[0020] Preferably, when the first input voltage Vhv is higher than the power supply voltage VDD, the enable signal is connected to a level conversion circuit, and is connected to the initialization switch after being converted into a voltage in the first input voltage Vhv domain by the level conversion circuit.

[0021] Preferably, the drain of the first PMOS transistor P1 is grounded through a third NMOS transistor N3;

[0022] The bias circuit includes a current source and a fourth NMOS transistor N4 connected in sequence, and the third NMOS transistor N3 and the fourth NMOS transistor N4 form a mirror current mirror.

[0023] Preferably, the enabling switch comprises a second NMOS transistor N2, the drain of the output PMOS transistor P0 is grounded via the second NMOS transistor N2, and the gate of the second NMOS transistor N2 is connected to the enabling signal.

[0024] Preferably, the initialization switch includes a second PMOS tube P2, a gate of the second PMOS tube P2 is connected to the enable signal, a source of the second PMOS tube P2 is connected to the output mirror branch, and a drain of the second PMOS tube P2 is connected to the output drive branch.

[0025] Another aspect of the present disclosure provides a voltage regulator circuit, comprising an error amplifier circuit, a second-stage follower circuit, and any one of the above-mentioned push-pull voltage output stage circuits.

[0026] The input terminal of the error amplifier circuit and the first input terminal of the second-stage follower circuit are connected to the first input voltage Vhv;

[0027] The output end of the error amplifier circuit is connected to the second input end of the second-stage follower circuit, and the output end of the error amplifier circuit outputs the second input voltage Vhg.

[0028] Preferably, the first input end of the second-stage follower circuit is connected to the drain of the first NMOS tube N1, the second input end of the second-stage follower circuit is connected to the gate of the first NMOS tube N1, and the output end of the second-stage follower circuit is connected to the source of the first NMOS tube N1.

[0029] Another aspect of the present disclosure provides a voltage regulator circuit, comprising a voltage division sampling circuit and any one of the above-mentioned push-pull voltage output stage circuits, wherein the voltage division sampling circuit samples the first input voltage Vhv to generate the second input voltage Vhg.

[0030] Another aspect of the present disclosure provides a chip, wherein the chip includes any one of the push-pull voltage output stage circuits described above, or any one of the voltage regulator circuits described above.

[0031] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0032] The positive improvement effect of the present disclosure is that the push-pull voltage output stage circuit, voltage regulator circuit and chip of the present disclosure not only have a fast response speed, but also utilize a push-pull circuit to quickly establish the output voltage to the required target voltage, whether it is from a high voltage to a low voltage, or from a low voltage to a high voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a voltage regulator circuit provided by the prior art;

[0034] Figure 2 A schematic diagram of a linear voltage regulator circuit of an NMOS output stage circuit with an open-loop output stage provided by the prior art;

[0035] Figure 3 A schematic diagram of another open-loop voltage regulator circuit provided in the prior art;

[0036] Figure 4 A schematic diagram of a push-pull voltage output stage circuit provided in Embodiment 1 of the present disclosure;

[0037] Figure 5 A schematic diagram of a push-pull voltage output stage circuit provided in Embodiment 2 of the present disclosure;

[0038] Figure 6 A schematic diagram of a push-pull voltage output stage circuit provided in Embodiment 3 of the present disclosure;

[0039] Figure 7 A schematic diagram of a voltage regulator circuit with a push-pull voltage output stage circuit provided in Embodiment 4 of the present disclosure;

[0040] Figure 8 A schematic diagram of another voltage regulator circuit with a push-pull voltage output stage circuit provided in Embodiment 4 of the present disclosure;

[0041] Fig. 9 A schematic diagram of a voltage regulator circuit with a push-pull voltage output stage circuit provided in Embodiment 5 of the present disclosure;

[0042] Fig.10 A schematic diagram of a voltage regulator circuit with a push-pull voltage output stage circuit provided in Example 6 of the present disclosure. DETAILED DESCRIPTION

[0043] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0044] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0045] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0046] Example 1

[0047] Figure 4 A schematic diagram of a push-pull output stage circuit provided in Embodiment 1 of the present disclosure, the push-pull voltage output stage circuit comprising an output drive branch and an output mirror branch;

[0048] The output drive branch comprises a push-pull structure; the output mirror branch comprises a mirror push-pull structure which is mirrored to the push-pull structure of the output drive branch;

[0049] The output driving branch includes an output NMOS tube N0 and an output PMOS tube P0 connected in sequence; specifically, the source of the output NMOS tube N0 is connected to the source of the output PMOS tube P0 and is connected to the output terminal Vout, and the output terminal Vout is connected to the large capacitive load C load One end of the large capacitive load C load The other end is grounded.

[0050] The output mirror branch includes a first NMOS transistor N1 and a first PMOS transistor P1 connected in sequence; specifically, the source of the first NMOS transistor N1 is connected to the source of the first PMOS transistor P1.

[0051] The drains of the output NMOS tube N0 and the first NMOS tube N1 are connected to a first input voltage Vhv, and the gates of the output NMOS tube N0 and the first NMOS tube N1 are connected to a second input voltage Vhg; the first input voltage Vhv is the chip power supply voltage or the voltage generated by the high-voltage module in the chip, and the second input voltage is the target voltage obtained by the previous circuit through Vhv.

[0052] The gates of the output PMOS tube P0 and the first PMOS tube P1, and the drain of the first PMOS tube P1 are grounded via a current source circuit. Specifically, the gate of the first PMOS tube P1 is connected to the drain of the first PMOS tube P1, and the drain of the first PMOS tube P1 is connected to one end of the current source circuit, and the other end of the current source circuit is grounded.

[0053] Since the second input voltage Vhg is connected to the gates of the output NMOS tube N0 and the first NMOS tube N1, the first NMOS tube N1 is a clamping tube, the voltage of the source terminal Net1 of the first NMOS tube N1 is clamped to Vhg-Vgsn1, wherein Vgsn1 is the gate-source voltage of N1, and the first PMOS tube P1 provides a static mirror current bias for the output driver stage; the output NMOS tube N0 and the output PMOS tube P0 form an inverted push-pull driver stage.

[0054] Since the output stage isolates the front stage circuit from the large capacitive load, the front stage circuit can quickly establish the second input voltage Vhg to the target voltage after the circuit is enabled. Since the load of the Net1 node is small, under the joint action of the first NMOS tube N1 and the current source circuit Isunk1, the voltage of the Net1 point can be quickly established to Vhg-Vgsn1, where Vgsn1 is the gate-source voltage of N1. The voltage of the gate-drain point Net2 of the first PMOS tube is quickly established to Vhg-Vgsn1-Vsgp1 at the same time, where Vgsn1 is the gate-source voltage of the first NMOS tube N1, which is jointly determined by the current Isunk1 of the current source circuit and the threshold voltage Vthn1 of the first NMOS tube N1, and Vsgp1 is the source-gate voltage of the first PMOS tube P1, which is jointly determined by the current Isunk1 of the current source circuit and the threshold voltage Vthp1 of the first PMOS tube P1.

[0055] At this time, the gate voltages of the output NMOS tube N0 and the output PMOS tube P0 both reach the target voltage value. If the output voltage switches from low to high, the output NMOS tube N0 provides a large charging current to quickly build Vout to the target voltage. If the output voltage switches from high to low, the output PMOS tube P0 provides a leakage current. When Vout is far from the target voltage, the voltage value of Vsgp0, that is, Vout-Vnet2, is large, and the leakage current of the output PMOS tube P0 is also large. As Vout gradually decreases, the voltage value of Vsgp0 also decreases, and the leakage current also slowly decreases, and finally reaches the mirror current of the current mirror composed of the first PMOS tube P1 and the output PMOS tube P0, that is, Isunk2.

[0056] The current consumption of Vhv by this circuit is controlled by Isunk0, the ratio of N4 and N3, and the ratio of P0 and P1. Of course, in this circuit, the minimum swing of the output voltage needs to be higher than Vdsn3+Vsgp1, where Vdsn3 is the source-drain voltage of NMOS tube N3, and Vsgp1 is the source-gate voltage of PMOS tube.

[0057] Preferably, the NMOS tube in the circuit can be an NMOS tube with a deep N-well process, thereby eliminating the liner bias effect.

[0058] The push-pull voltage output stage circuit of this embodiment not only has a fast response speed, but also can quickly establish the output voltage to the required target voltage by using the push-pull circuit, whether it is from a high voltage to a low voltage or from a low voltage to a high voltage.

[0059] Example 2

[0060] like Figure 5 FIG. 2 is a schematic diagram of a push-pull voltage output stage circuit according to Embodiment 2 of the present disclosure. The circuit structure in this embodiment is based on Embodiment 1, and the current source circuit further includes a bias circuit for providing a static operating current for the output mirror branch.

[0061] Preferably, the drain of the first PMOS tube P1 is grounded through a third NMOS tube N3; specifically, the drain of the first PMOS tube P1 is connected to the drain of the third NMOS tube N3, and the source of the third NMOS tube N3 is grounded.

[0062] The bias circuit includes a current source and a fourth NMOS tube N4 connected in sequence. Specifically, the current of the current source is Isunk0, one end of the current source is connected to the power supply voltage VDD, and the other end is connected to the drain of the fourth NMOS tube N4, the drain of the fourth NMOS tube N4 is connected to the gate, and is connected to the gate of the third NMOS tube N3, and the source of the fourth NMOS tube N4 is grounded.

[0063] The third NMOS transistor N3 and the fourth NMOS transistor N4 form a mirror current mirror. The current Isunk1 passing through the output mirror branch is equal to ((W N3 / L N3 ) / (W N4 / L N4 ))×Isunk0,W N3 / L N3 is the width-to-length ratio of the third NMOS tube, W N4 / L N4 The current consumption of the first input voltage Vhv of this circuit is controlled by the current source current Isunk0, the ratio of the width-to-length ratio of the fourth PMOS tube N4 to the width-to-length ratio of the third PMOS tube N3, and the ratio of the width-to-length ratio of the output PMOS tube P0 to the width-to-length ratio of the first PMOS tube P1.

[0064] The design of the bias circuit can facilitate the adjustment of the current of the output mirror branch, and further facilitate the adjustment of the current of the output drive branch.

[0065] Furthermore, the push-pull voltage output stage circuit also includes an enable switch in the output drive branch, the enable switch is driven based on the enable signal En, the enable switch includes a second NMOS tube N2, the drain of the output PMOS tube P0 is grounded via the second NMOS tube N2, the gate of the second NMOS tube N2 is connected to the enable signal En, the drain of the output PMOS tube P0 is connected to the drain of the second NMOS tube N2, and the source of the second NMOS tube N2 is grounded. The enable switch is used to control the working state of the push-pull voltage output stage circuit.

[0066] Example 3

[0067] On the basis of Examples 1 and 2, Figure 6 , which is a schematic diagram of another push-pull voltage output stage circuit. The circuit also includes an initialization switch, which is arranged between the output drive branch and the output mirror branch, and is driven based on an enable signal En.

[0068] The initialization switch includes a second PMOS tube P2, a gate of the second PMOS tube P2 is connected to the enable signal, a source of the second PMOS tube P2 is connected to the output mirror branch, and a drain of the second PMOS tube P2 is connected to the output drive branch.

[0069] Therefore, when the first input voltage Vhv is higher than the power supply voltage VDD, the enable signal En is connected to the level conversion circuit, and after being converted into a voltage in the first input voltage Vhv domain by the level conversion circuit, is connected to the initialization switch, that is, connected to the gate of the second PMOS tube P2.

[0070] Similarly, when the first input voltage Vhv is a low voltage, the enable signal En is directly connected to the gate of the second PMOS tube P2. The second PMOS tube P2 initializes Net1 and Vout to the same voltage when the circuit is not working. When the circuit starts working, the initial device P2 is turned off, so that the load of the Net1 node is small and can be quickly established to Vhg-Vgsn1. The gate-drain Net2 voltage of the first PMOS tube P1 is quickly established to Vhg-Vgsn1-Vsgp1 at the same time, where Vgsn1 is the gate-source voltage of the first NMOS tube N1, which is jointly determined by the current Isunk1 of the output mirror branch and the threshold voltage Vthn1 of the first NMOS tube N1, and Vsgp1 is the source-gate voltage of the first PMOS tube P1, which is jointly determined by the current Isunk1 of the output mirror branch and the threshold voltage Vthp1 of the first PMOS tube P1.

[0071] At this time, the gate voltages of the output NMOS tube N0 and the output PMOS tube P0 both reach the target voltage value. If the output voltage switches from low to high, the output NMOS tube N0 provides a large charging current to quickly build Vout to the target voltage. If the output voltage switches from high to low, the output PMOS tube P0 provides a leakage current. When Vout is far from the target voltage, the voltage value of Vsgp0, that is, Vout-Vnet2, is large, and the leakage current of the output PMOS tube P0 is also large. As Vout gradually decreases, the voltage value of Vsgp0 also decreases, and the leakage current also slowly decreases, and finally reaches the mirror current of the current mirror composed of the first PMOS tube P1 and the output PMOS tube P0. The current consumption of the first input voltage Vhv of this circuit is controlled by the current source current Isunk0, the ratio of the width-to-length ratio of the fourth PMOS tube N4 to the width-to-length ratio of the third PMOS tube P3, and the ratio of the width-to-length ratio of the output PMOS tube P0 to the width-to-length ratio of the first PMOS tube P1.

[0072] like Figure 6As shown, the level conversion circuit therein can adopt the structure shown in Figure 6, or other structures. Specifically, the level conversion circuit includes a fifth NMOS tube N5, a sixth NMOS tube N6, a third PMOS tube P3 and a fourth PMOS tube P4. The source of the third PMOS tube and the source of the fourth PMOS tube P4 are both connected to the first input voltage Vhv, the drain of the fourth PMOS tube P4 and the gate of the third PMOS tube P3 are both connected to the drain of the sixth NMOS tube N6, and the source of the sixth NMOS tube N6 is grounded. The gate of the sixth NMOS tube N6 is connected to the enable signal En as an input terminal; the drain of the third PMOS tube P3 is connected to the drain of the fifth NMOS tube N5, and the source of the fifth NMOS tube N5 is grounded; the enable signal En is connected to the gate of the fifth NMOS tube N5 through a NOT gate. The gate of the fourth PMOS tube P4 is connected to the drain of the fifth NMOS tube N5, and as the output terminal Net4 of the level conversion circuit, it is connected to the gate of the second PMOS tube P2.

[0073] The circuit, such as Figure 6 As shown, in addition to the initialization switch, there are also an enable switch and a bias circuit. The enable switch and the bias circuit can also be omitted as needed.

[0074] Example 4

[0075] like Figure 7 As shown, it is a schematic diagram of a voltage regulator circuit with a push-pull voltage output stage circuit provided in Example 4; it includes an error amplifier circuit, a second-stage follower circuit and any one of the push-pull voltage output stage circuits in the above-mentioned Examples 1-3. Figure 7 The structure of the push-pull voltage output stage circuit in Embodiment 3 is taken as an example for explanation.

[0076] The input end of the error amplifier circuit and the first input end of the second-stage follower circuit are connected to the first input voltage Vhv; the output end of the error amplifier circuit is connected to the second input end of the second-stage follower circuit, and the output end of the error amplifier circuit outputs the second input voltage Vhg.

[0077] Specifically, the second-stage follower circuit includes a seventh NMOS tube N7, and an adjustable resistor R1 and a resistor R0 are connected to the source of the seventh NMOS tube in sequence, and one end of R0 is grounded. The input end of the error amplifier is connected to the first input voltage Vhv, and the feedback voltage end of the error amplifier is connected between the adjustable resistor R1 and the resistor R0. The first input end of the second-stage follower circuit, that is, the drain of the seventh NMOS tube N7, is connected to the first input voltage Vhv, and the second input end of the second-stage follower circuit, that is, the gate of the seventh NMOS tube N7, is connected to the output end Vhg of the error amplifier circuit, the output end of the error amplifier circuit is grounded through the capacitor C0, and the output end of the error amplifier circuit outputs the second input voltage Vhg.

[0078] The output end of the second-stage follower circuit, that is, the source end of the seventh NMOS tube has a voltage Vol. At this time, the voltage value of the output end of the error amplifier circuit is Vo1+Vgsn7, wherein Vgsn7 is the gate-source voltage of N7. The output end of the error amplifier circuit is connected to the second input voltage of the push-pull voltage output stage circuit. Under the clamping action of the first NMOS tube N1 and the output NMOS tube N0, the Vout voltage is equal to Vhg-Vgsn0, and the voltage at Net1 is equal to Vhg-Vgsn1. By adjusting the size of N7, N1, N0 and the current of each branch, Vgsn7 is made equal to Vgsn1 and Vgsn0, and finally Vout can be obtained to be equal to Vo1.

[0079] The voltage regulator circuit not only has a fast loop response speed, but also utilizes a push-pull voltage output stage circuit to enable the output voltage to quickly establish to a target voltage.

[0080] like Figure 8 FIG. 1 is a schematic diagram of another voltage regulator circuit having a push-pull voltage output stage circuit. Figure 7 On the basis of the circuit, the seventh NMOS tube N7 is shared with the first NMOS tube N1.

[0081] For example, if the seventh NMOS tube N7 is deleted, the first input end of the second-stage follower circuit is connected to the drain of the first NMOS tube N1, the second input end of the second-stage follower circuit is connected to the gate of the first NMOS tube N1, and the output end of the second-stage follower circuit is connected to the source of the first NMOS tube N1.

[0082] Alternatively, the first NMOS transistor N1 is deleted, and the sources of the second PMOS transistor P2 and the third PMOS transistor P3 are connected to the output end of the second-stage follower circuit.

[0083] At the same time, the second follower circuit of the circuit adds an eighth NMOS tube N8 controlled by an enable signal. The eighth NMOS tube N8 is connected between the resistor R0 and the ground, that is, one end of the resistor R0 is connected to one end of the adjustable resistor R1, and the other end is connected to the drain of the eighth NMOS tube N8, the source of the eighth NMOS tube N8 is grounded, and the gate of the eighth NMOS tube is connected to the enable signal.

[0084] The structure of the voltage regulator circuit not only has a fast loop response speed, but also utilizes a push-pull voltage output stage circuit to enable the output voltage to quickly establish to a target voltage.

[0085] Example 5

[0086] like Fig. 9 As shown, it is a structural schematic diagram of a circuit regulator circuit with a push-pull voltage output stage circuit provided in Example 5, and the voltage regulator circuit includes a voltage divider sampling circuit and the push-pull voltage output stage circuit described in any one of Examples 1-3, and the voltage divider sampling circuit samples the first input voltage Vhv to generate the second input voltage Vhg.

[0087] Specifically, the voltage divider sampling circuit includes a first adjustable resistor R3 and a second adjustable resistor R4 connected in series, one end of the first adjustable resistor R3 is connected to a first input voltage Vhv, the other end of the first adjustable resistor R3 is connected to one end of the second adjustable resistor R4, the other end of the second adjustable resistor R4 is grounded, and the sampling end is located between the first adjustable resistor R3 and the second adjustable resistor R4, and is connected to the second input voltage Vhg of the push-pull voltage output branch.

[0088] In this circuit, the second input voltage Vhg is directly determined by the resistance ratio of the resistor divider string, and Vout is equal to Vhg-Vsgn0. Different Vhg voltage values ​​can be obtained by adjusting the voltage divider ratio of the resistor string, thereby obtaining different output voltages.

[0089] The voltage regulator circuit can conveniently adjust the target voltage of the final output, and by utilizing a push-pull voltage output stage circuit, the output voltage can quickly reach the required target voltage.

[0090] Example 6

[0091] like Fig.10 As shown in FIG. 1 , it is a schematic diagram of a voltage regulator circuit having a push-pull voltage output stage circuit; this embodiment is in Figure 8 Based on the above, the circuit is applied to a low voltage circuit. The low voltage regulator includes the push-pull voltage output stage circuit described in any one of embodiments 1-3.

[0092] Since it is a low voltage circuit, Figure 8The level conversion circuit is omitted. Of course, those skilled in the art can also understand that not only Figure 8 The circuit can be used in low voltage circuits. Figure 7 , Fig. 9 The circuit in can also be applied to low voltage circuit scenarios, and only the level conversion circuit needs to be omitted.

[0093] like Fig.10 As shown, the minimum swing of the output voltage is Vdsn3+Vsgp1, and the maximum is Vhg-Vgsn0, where Vdsn3 is the source-drain voltage of the third NMOS tube N3, Vsgp1 is the source-gate voltage of the first PMOS tube P1, Vhg is the second input voltage and also the output voltage of the error amplifier, and Vgsn0 is the gate-source voltage of the output NMOS tube N0.

[0094] Example 7

[0095] In a specific embodiment of the present disclosure, a chip is provided, and the chip includes the push-pull output stage circuit described in any of the above embodiments, or the voltage regulator circuit described in any of the above embodiments.

[0096] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A push-pull voltage output stage circuit, characterized in that: It includes an output driving branch and an output mirror branch; The output drive branch comprises a push-pull structure; the output mirror branch comprises a mirror push-pull structure which is mirrored to the push-pull structure of the output drive branch; The output driving branch includes an output NMOS tube and an output PMOS tube connected in sequence; The output mirror branch includes a first NMOS tube and a first PMOS tube connected in sequence; The drains of the output NMOS tube and the first NMOS tube are connected to a first input voltage, and the gates of the output NMOS tube and the first NMOS tube are connected to a second input voltage; The gates of the output PMOS tube and the first PMOS tube, and the drain of the first PMOS tube are grounded via a current source circuit; An initialization switch is also provided between the output drive branch and the output mirror branch, and the initialization switch is driven based on an enable signal; When the first input voltage is higher than the power supply voltage, the enable signal is connected to the level conversion circuit, and is connected to the initialization switch after being converted into a voltage in the first input voltage domain by the level conversion circuit.

2. The push-pull voltage output stage circuit according to claim 1, characterized in that: The current source circuit also includes a bias circuit for providing a static operating current for the output mirror branch.

3. The push-pull voltage output stage circuit according to claim 1, characterized in that: The output driving branch further includes an enable switch, which is driven based on an enable signal.

4. The push-pull voltage output stage circuit according to claim 2, characterized in that: The drain of the first PMOS tube is grounded through the third NMOS tube; The bias circuit includes a current source and a fourth NMOS tube connected in sequence, and the third NMOS tube and the fourth NMOS tube form a mirror current mirror.

5. The push-pull voltage output stage circuit according to claim 3, characterized in that: The enabling switch comprises a second NMOS tube, the drain of the output PMOS tube is grounded via the second NMOS tube, and the gate of the second NMOS tube is connected to the enabling signal.

6. The push-pull voltage output stage circuit according to claim 1, characterized in that: The initialization switch includes a second PMOS tube, a gate of the second PMOS tube is connected to the enable signal, a source of the second PMOS tube is connected to the output mirror branch, and a drain of the second PMOS tube is connected to the output drive branch.

7. A voltage regulator circuit, characterized in that: The invention comprises an error amplifier circuit, a second-stage follower circuit and a push-pull voltage output stage circuit as described in any one of claims 1 to 6, The input terminal of the error amplifier circuit and the first input terminal of the second-stage follower circuit are connected to the first input voltage; The output end of the error amplifier circuit is connected to the second input end of the second-stage follower circuit, and the output end of the error amplifier circuit outputs the second input voltage.

8. A voltage regulator circuit, characterized in that: The invention comprises a voltage-dividing sampling circuit and a push-pull voltage output stage circuit according to any one of claims 1 to 6, wherein the voltage-dividing sampling circuit samples the first input voltage to generate the second input voltage.

9. A chip, characterized in that: The chip comprises the push-pull voltage output stage circuit according to any one of claims 1 to 6, or the voltage regulator circuit according to claim 7 or 8.

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