A collection circuit and collection method for collecting multiple open input quantities

Abstract

The present invention relates to the technical field of measurement and control systems, and in particular to an acquisition circuit and an acquisition method for acquiring multiple binary input quantities. Specifically disclosed is an acquisition circuit and an acquisition method for acquiring multiple binary input quantities, wherein the acquisition circuit for acquiring multiple binary input quantities comprises a SOC chip, an address comparison chip, a 38 decoder chip and a data acquisition chip; the SOC chip controls the acquisition of binary input signals through multiple address signals; the address comparison chip compares the address signal from the SOC chip with a preset fixed address, and outputs an enable signal to the 38 decoder chip; the 38 decoder chip is used to output a decoding result to control the enable state of the data acquisition chip according to the enable signal of the address comparison chip and the address signal of the SOC chip; the data acquisition chip is used to transmit the corresponding binary input signal to the SOC chip according to the decoding result. The present invention can realize the acquisition of multiple binary input signals without increasing the design cost of the measurement and control system.

Description

Technical Field

[0001] The present invention relates to the technical field of measurement and control systems, and in particular to an acquisition circuit and an acquisition method for acquiring a plurality of binary input quantities. Background Art

[0002] The measurement and control system needs to collect the switch quantity information of the field equipment in real time to monitor the operating status of the equipment. With the expansion of the scale of the measurement and control system, the amount of switch quantity information that needs to be collected is increasing. The existing measurement and control system has limitations when collecting a large number of open input signals, which is mainly reflected in the limited number of pins of the SOC chip. For example, the widely used STM32F103RBT6 chip has only 63 pins, and the STM32F407VET chip has only 100 pins. When the number of open input signals to be collected is large, the number of pins of the chip is often not enough to meet the collection requirements. In order to solve this problem, it is usually necessary to add more SOC chips or select chips with more pins, which significantly increases the design cost of the system and makes the structure of the system more complicated.

[0003] Therefore, it is urgent to propose a collection circuit and a collection method for collecting multiple open-input quantities to solve the above problems. Summary of the invention

[0004] The purpose of the present invention is to provide an acquisition circuit and an acquisition method for acquiring multiple open-input quantities, which can realize the acquisition of multi-channel open-input quantity signals without increasing the design cost of the measurement and control system.

[0005] In order to solve the above technical problems, the present invention provides a collection circuit for collecting multiple binary input quantities, including a SOC chip, an address comparison chip, a 38 decoder chip and a data collection chip;

[0006] The SOC chip controls the collection of binary input signals through multiple address signals;

[0007] The address comparison chip is used to compare a portion of the address signal from the SOC chip with a preset fixed address, and output an enable signal to the 38 decoder chip;

[0008] The 38 decoder chip is used to output a decoding result to control the enable state of the data acquisition chip according to the enable signal of the address comparison chip and another part of the address signal of the SOC chip;

[0009] The data acquisition chip is used to transmit the corresponding binary input signal to the SOC chip according to the decoding result.

[0010] Further, the SOC chip includes a first address pin, a second address pin and a data acquisition pin;

[0011] The first address pin is used to output the first address signal to the address input pin of the 38 decoder chip; the second address pin is used to output the second address signal to the address input pin of the address comparison chip; the data acquisition pin is used to receive the binary input signal transmitted by the data acquisition chip.

[0012] Furthermore, the first address pin includes a plurality of pins for outputting a multi-bit binary address signal; the data acquisition pin includes a plurality of pins for receiving a plurality of open input signals in parallel.

[0013] Further, the address comparison chip includes: a multi-bit address input pin, a multi-bit fixed address pin and an enable output pin;

[0014] The multi-bit address input pin is used to receive the address signal output by the SOC chip; the multi-bit fixed address pin is used to set the preset fixed address; the enable output pin is used to output the valid enable signal when the address signal of the multi-bit address input pin matches the preset fixed address of the multi-bit fixed address pin.

[0015] Furthermore, the 38 decoder chip includes a plurality of enable pins, the plurality of enable pins include a low-level valid input pin and a high-level valid input pin, and the enable signal of the address comparison chip is connected to one of the low-level valid input pins.

[0016] Furthermore, the enable pin of the data acquisition chip is connected to the corresponding output pin of the 38 decoder chip; each of the data acquisition chips has multiple input pins and multiple output pins for simultaneously acquiring multiple open input signals.

[0017] In addition, the present invention also proposes a collection method for collecting multiple binary input quantities, using the collection circuit for collecting multiple binary input quantities as described above, which specifically includes the following:

[0018] Control the SOC chip to output multiple address signals;

[0019] Performing address comparison on a portion of the address signals to obtain an enable signal;

[0020] Decoding is performed according to another part of the address signal and the enable signal to generate a decoding result; and

[0021] The corresponding data acquisition chip is selectively activated according to the decoding result, and the acquired binary input signal is transmitted to the SOC chip.

[0022] Furthermore, the controlling SOC chip to output multiple address signals specifically includes: the SOC chip outputting a first address signal to an address input pin of a 38 decoder chip; and the SOC chip outputting a second address signal to an address input pin of an address comparison chip.

[0023] Furthermore, the address comparison specifically includes: comparing the second address signal output by the SOC chip with a preset fixed address; when the comparison result is equal, outputting a valid signal to the enable pin of the 38 decoder chip.

[0024] Furthermore, the decoding specifically includes: the 38 decoder chip decodes according to the valid signal on the enable pin and the first address signal on the address input pin to generate a decoding result; and outputs the decoding result to the enable pin corresponding to the data acquisition chip.

[0025] Furthermore, the selective activation of the corresponding data acquisition chip according to the decoding result and the transmission of the collected binary input signal to the SOC chip specifically includes: the data acquisition chip detecting the decoding result on the enable pin; when the decoding result is detected to be a low level, the data acquisition chip is enabled and the collected binary input signal is transmitted to the SOC chip.

[0026] Furthermore, it also includes: the SOC chip periodically changes the value of the address signal, activates different data acquisition chips in turn, and polls and collects all input signals; when one of the data acquisition chips is activated, the other data acquisition chips remain in an unactivated state.

[0027] Through the above technical solution, the present invention has the following beneficial effects:

[0028] By adopting a combination of an address comparison chip and a 38 decoder chip, and utilizing the address signal allocation and decoding mechanism, it is possible to use a small number of SOC chip pins to control the collection of multiple open input signals, significantly reducing the demand for the number of SOC chip pins. For example, the present invention only requires 19 SOC chip pins to collect 64 open input signals, and even in specific application scenarios, only 12 pins are needed to complete the same collection task.

[0029] In addition, polling acquisition is achieved by periodically changing the value of the address signal and ensuring that only one data acquisition chip is activated at the same time, which not only ensures the orderly progress of the acquisition process but also avoids data conflicts. In addition, the use of low-level effective enable signal control method improves the system's anti-interference ability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the overall structure of a collection circuit for collecting multiple binary input quantities in one embodiment of the present invention;

[0031] Figure 2 It is a flow chart of a method for collecting multiple input quantities in one embodiment of the present invention;

[0032] Figure 3 It is a schematic diagram of the structure of an address comparison chip in a collection circuit for collecting multiple digital input quantities in one embodiment of the present invention;

[0033] Figure 4 It is a structural schematic diagram of a 38 decoder chip in a collection circuit for collecting multiple binary input quantities in one embodiment of the present invention;

[0034] Figure 5 It is a structural schematic diagram of a first data acquisition chip in an acquisition circuit for acquiring multiple digital input quantities in one embodiment of the present invention;

[0035] Figure 6 It is a structural schematic diagram of a second data acquisition chip in an acquisition circuit for acquiring multiple digital input quantities in one embodiment of the present invention;

[0036] Figure 7 Schematic diagram of the structure of the third data acquisition chip in the acquisition circuit for acquiring multiple digital input quantities in one embodiment of the present invention. DETAILED DESCRIPTION

[0037] A collection circuit and collection method for collecting multiple binary input quantities of the present invention will be described in more detail below in conjunction with the accompanying drawings, wherein preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation to the present invention.

[0038] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0039] like Figure 1 As shown, the embodiment of the present invention provides a collection circuit for collecting multiple open input quantities, including a SOC chip (such as Figure 1 U6 in), address comparison chip (such as Figure 1 U3 in), 38 decoder chip (such as Figure 1 U4 in the Figure 1 U1, U2 and U5 in the diagram).

[0040] Specifically, the SOC chip controls the collection of binary input signals through multiple address signals; the address comparison chip is used to compare the address signal from the SOC chip with a preset fixed address, and output an enable signal to the 38 decoder chip; the 38 decoder chip is used to output a decoding result to control the enable state of the data acquisition chip according to the enable signal of the address comparison chip and the address signal of the SOC chip; the data acquisition chip is used to transmit the corresponding binary input signal to the SOC chip according to the decoding result.

[0041] In this embodiment, the SOC chip includes a first address pin, a second address pin and a data acquisition pin.

[0042] Specifically, the first address pin is used to output the first address signal to the address input pin of the 38 decoder chip; the second address pin is used to output the second address signal to the address input pin of the address comparison chip; the data acquisition pin is used to receive the binary input signal transmitted by the data acquisition chip.

[0043] Among them, the first address pin includes multiple pins for outputting multi-bit binary address signals; the data acquisition pin includes multiple pins for receiving multiple open-input signals in parallel. It is known to those skilled in the art that the number of pins of the first address pin can be set according to actual needs. For example, four pins can be used to achieve sixteen-way decoding output. The second address pin includes eight pins for outputting eight-bit binary address signals to the address input pins of the address comparison chip. The data acquisition pin includes eight pins for receiving eight open-input signals in parallel. In addition, those skilled in the art can select the required model of SOC chip according to actual needs.

[0044] In this embodiment, the address comparison chip includes: a multi-bit address input pin, a multi-bit fixed address pin and an enable output pin.

[0045] Specifically, the multi-bit address input pin is used to receive the address signal output by the SOC chip; the multi-bit fixed address pin is used to set the preset fixed address; the enable output pin is used to output the valid enable signal when the address signal of the multi-bit address input pin matches the preset fixed address of the multi-bit fixed address pin. The multi-bit fixed address pin sets the preset fixed address through a jumper. When the address signal of the multi-bit address input pin matches the preset fixed address of the multi-bit fixed address pin, the enable output pin outputs a low-level valid enable signal. It is known to those skilled in the art that the preset fixed address can also be set by other methods such as a dip switch.

[0046] Preferably, the address comparison chip includes a 74HC688PW chip. In addition, those skilled in the art can select other types of chips according to actual needs.

[0047] In this embodiment, the 38 decoder chip includes multiple enable pins, the multiple enable pins include a low-level valid input pin and a high-level valid input pin, and the enable signal of the address comparison chip is connected to one of the low-level valid input pins.

[0048] In a specific example, the 38 decoder chip includes three address input pins and three enable pins. The three enable pins include two low-level valid input pins and one high-level valid input pin, and the enable signal of the address comparison chip is connected to one of the low-level valid input pins. When the enable pin receives a valid enable signal and the address input pin receives a valid address signal, only one of the eight output pins of the 38 decoder chip outputs a low level, and the remaining output pins all output a high level.

[0049] Preferably, the 38 decoder chip includes a SN74HC138D chip. Those skilled in the art can select other types of chips according to actual needs.

[0050] In this embodiment, the enable pin of the data acquisition chip is connected to the corresponding output pin of the 38 decoder chip; each of the data acquisition chips has multiple input pins and multiple output pins for simultaneously acquiring multiple binary input signals. When the enable pin of the data acquisition chip receives a low-level signal, the data acquisition chip is enabled and transmits the acquired binary input signal to the data acquisition pin of the SOC chip. It is known to those skilled in the art that the number of input pins and output pins can be selected according to actual needs.

[0051] Preferably, the data acquisition chip includes a SN74AHCT245PWR chip. In addition, those skilled in the art can select other types of chips according to actual needs.

[0052] In addition, if Figure 2 As shown, this embodiment also proposes a collection method for collecting multiple binary input quantities, using the collection circuit for collecting multiple binary input quantities as described above, specifically comprising the following steps:

[0053] S1, control SOC chip to output multiple address signals;

[0054] S2, performing address comparison on a portion of the address signals to obtain an enable signal;

[0055] S3, decoding according to another part of the address signal and the enable signal to generate a decoding result; and

[0056] S4. Selectively activate the corresponding data acquisition chip according to the decoding result, and transmit the acquired binary input signal to the SOC chip.

[0057] In step S1, the control SOC chip outputs multiple address signals, specifically including: the SOC chip outputs a first address signal to the address input pin of the 38 decoder chip; the SOC chip outputs a second address signal to the address input pin of the address comparison chip.

[0058] In step S2, the address comparison specifically includes: comparing the second address signal output by the SOC chip with a preset fixed address; when the comparison result is equal, outputting a valid signal to the enable pin of the 38 decoder chip.

[0059] In step S3, the decoding specifically includes: the 38 decoder chip decodes according to the valid signal on the enable pin and the first address signal on the address input pin to generate a decoding result; and outputs the decoding result to the enable pin corresponding to the data acquisition chip.

[0060] In step S4, the corresponding data acquisition chip is selectively activated according to the decoding result, and the collected binary input signal is transmitted to the SOC chip, which specifically includes: the data acquisition chip detects the decoding result on the enable pin; when the decoding result is detected to be a low level, the data acquisition chip is enabled, and the collected binary input signal is transmitted to the SOC chip.

[0061] Preferably, this embodiment also includes: the SOC chip periodically changes the value of the address signal, activates different data acquisition chips in turn, and polls and collects all input signals; when one of the data acquisition chips is activated, the other data acquisition chips remain in an unactivated state.

[0062] In a specific embodiment, for example, a SOC chip can collect multiple (for example, 24 or 64) digital input signals through three first address pins, eight second address pins and eight data acquisition pins, that is, a total of 19 pins. The specific working process is as follows:

[0063] The SOC chip outputs an address signal to the address comparison chip through the second address pin. When the address signal matches the preset fixed address, the address comparison chip outputs a low-level valid signal to the enable pin of the 38 decoder chip. At the same time, the SOC chip outputs a three-bit binary address signal to the address input pin of the 38 decoder chip through the first address pin. The 38 decoder chip decodes according to the received enable signal and address signal, and selects one of its eight output pins to output a low-level signal, thereby enabling the corresponding data acquisition chip. The enabled data acquisition chip transmits the collected eight-way binary input signal to the data acquisition pin of the SOC chip.

[0064] The SOC chip can activate eight data acquisition chips in sequence by periodically changing the value of the first address signal, thereby realizing polling acquisition of multiple input signals. During the polling process, only one data acquisition chip is activated at the same time, and the other data acquisition chips remain in an inactive state. This working mode avoids data conflicts.

[0065] If the number of acquisition channels needs to be further expanded, it can be achieved by adding address comparison chips and corresponding data acquisition chip groups. For example, by setting different preset fixed addresses, the gating control of multiple groups of data acquisition chips can be achieved. Those skilled in the art can flexibly configure the system scale according to actual needs.

[0066] In this embodiment, for example, a 74HC688PW is selected as the address comparison chip. Figure 3 As shown. The address input pins Q0 to Q4 of the address comparison chip are used to receive the comparison address signals BA0 to BA4 output by the SOC chip, and the fixed address pins P0 to P7 are set to preset fixed addresses 0x15 (i.e., P7=0, P6=0, P5=0, P4=1, P3=0, P2=1, P1=0, P0=1) through jumpers. When the address signals BA4=1, BA3=0, BA2=1, BA1=0, BA0=1 output by the SOC chip match the preset fixed address, the enable output pin of the address comparison chip outputs a low-level active signal AD_EN_n.

[0067] Further, for example, SN74HC138D is selected as the 38 decoder chip, such as Figure 4As shown. The 38 decoder chip includes three enable pins E1, E2 and E3, of which E1 and E2 are low-level valid input pins, and E3 is a high-level valid input pin. The enable output pin of the address comparison chip is connected to the enable pin E1 of the 38 decoder chip (that is, the signal AD_EN_n enters the enable pin E1). When E1 and E2 are low levels and E3 is high level, the 38 decoder chip is in an activated state. The address output pins AA1, AA2, and AA3 of the SOC chip are connected to the address input pins of the 38 decoder chip. According to the input address signal, the 38 decoder chip outputs the corresponding decoding results on its output pins Y0 to Y7.

[0068] Furthermore, for example, SN74AHCT245PWR is selected as the data acquisition chip. The enable pin of the data acquisition chip is connected to the corresponding output pin of the 38 decoder chip. When the enable pin receives a low-level signal, the data acquisition chip is enabled, and the binary input signal INx on its input pin Ax is transmitted to the output pin Bx, and then the signal BDx is transmitted to the data acquisition pin of the SOC chip by the Bx pin. For example, Figure 1 , Figure 5 , Figure 6 as well as Figure 7 As shown, there are three data acquisition chips of the same model, namely U1, U2 and U5. The DIR and OE enable pins of the data acquisition chip are connected to the corresponding output pins of the 38 decoder chip. When the enable pin OE receives a low level signal, the data acquisition chip is enabled, that is, Figure 5 The digital input signals IN17-IN24 on the input pins A1-A8 of the data acquisition chip are transmitted to the output pins B1-B8. Figure 6 The digital input signals IN1-IN8 on the input pins A1-A8 of the data acquisition chip are transmitted to the output pins B1-B8. Figure 7 The binary input signals IN9-IN16 on the input pins A1-A8 of the data acquisition chip are transmitted to the output pins B1-B8. The signals BD0-BD7 are then transmitted to the data acquisition pins of the SOC chip by the B1-B8 pins. In this embodiment, by configuring three data acquisition chips, each chip collects 8 signals, and a total of 24 binary input signals are collected. The power pin VCC of each data acquisition chip is connected to a 5V power supply, the GND pin is grounded, and a decoupling capacitor is configured to improve circuit stability.

[0069] Finally, the SOC chip can periodically change the values ​​of the address signals AA1, AA2, and AA3 to activate different data acquisition chips in turn, thereby realizing polling acquisition of all binary input signals. During the entire acquisition process, only when the address comparison results match and the 38 decoder chip is correctly enabled, the corresponding data acquisition chip will be activated and transmit the binary input signal. It is known to those skilled in the art that by increasing the number of data acquisition chips and reasonably configuring the address signals, the number of binary input signals collected can be further expanded, for example, it can be expanded to 64 channels or more.

[0070] Through the above operations, this embodiment realizes the collection of 24-channel digital input signals using only a small number of SOC chip pins, and adopts a low-level effective enable control method, thereby improving the anti-interference ability of the system.

[0071] In summary, the acquisition circuit and acquisition method for acquiring multiple binary input quantities proposed by the present invention have the following advantages:

[0072] By adopting a combination of an address comparison chip and a 38 decoder chip, and utilizing the address signal allocation and decoding mechanism, it is possible to use a small number of SOC chip pins to control the collection of multiple open input signals, significantly reducing the demand for the number of SOC chip pins. For example, the present invention only requires 19 SOC chip pins to collect 64 open input signals, and even in specific application scenarios, only 12 pins are needed to complete the same collection task.

[0073] In addition, polling acquisition is achieved by periodically changing the value of the address signal and ensuring that only one data acquisition chip is activated at the same time, which not only ensures the orderly progress of the acquisition process but also avoids data conflicts. In addition, the use of low-level effective enable signal control method improves the system's anti-interference ability and reliability.

[0074] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A collection circuit for collecting multiple open input quantities, characterized in that: Including SOC chip, address comparison chip, 38 decoder chip and data acquisition chip; The SOC chip controls the collection of binary input signals through multiple address signals; The address comparison chip is used to compare a portion of the address signal from the SOC chip with a preset fixed address, and output an enable signal to the 38 decoder chip; The 38 decoder chip is used to output a decoding result to control the enable state of the data acquisition chip according to the enable signal of the address comparison chip and another part of the address signal of the SOC chip; The data acquisition chip is used to transmit the corresponding binary input signal to the SOC chip according to the decoding result; The SOC chip includes a first address pin, a second address pin and a data acquisition pin; The first address pin is used to output the first address signal to the address input pin of the 38 decoder chip; the second address pin is used to output the second address signal to the address input pin of the address comparison chip; the data acquisition pin is used to receive the binary input signal transmitted by the data acquisition chip.

2. The acquisition circuit for acquiring multiple binary input quantities according to claim 1, characterized in that: The first address pin includes a plurality of pins for outputting a multi-bit binary address signal; the data acquisition pin includes a plurality of pins for receiving a plurality of open input signals in parallel.

3. The acquisition circuit for acquiring multiple binary input quantities according to claim 1, characterized in that: The address comparison chip comprises: a multi-bit address input pin, a multi-bit fixed address pin and an enable output pin; The multi-bit address input pin is used to receive the address signal output by the SOC chip; the multi-bit fixed address pin is used to set the preset fixed address; the enable output pin is used to output the valid enable signal when the address signal of the multi-bit address input pin matches the preset fixed address of the multi-bit fixed address pin.

4. The acquisition circuit for acquiring multiple binary input quantities according to claim 1, characterized in that: The 38 decoder chip includes a plurality of enable pins, the plurality of enable pins include a low-level valid input pin and a high-level valid input pin, and the enable signal of the address comparison chip is connected to one of the low-level valid input pins.

5. The acquisition circuit for acquiring multiple binary input quantities according to claim 1, characterized in that: The enable pin of the data acquisition chip is connected to the corresponding output pin of the 38 decoder chip; each of the data acquisition chips has multiple input pins and multiple output pins for simultaneously acquiring multiple open input signals.

6. A method for collecting multiple binary input quantities, using the collecting circuit for collecting multiple binary input quantities according to any one of claims 1 to 5, characterized in that: The details include: Control the SOC chip to output multiple address signals; Performing address comparison on a portion of the address signals to obtain an enable signal; Decoding is performed according to the address signal and the enable signal of another part to generate a decoding result; as well as The corresponding data acquisition chip is selectively activated according to the decoding result, and the acquired binary input signal is transmitted to the SOC chip.

7. The method for collecting multiple input quantities according to claim 6, characterized in that: The controlling SOC chip to output multiple address signals specifically includes: the SOC chip outputting a first address signal to an address input pin of a 38 decoder chip; and the SOC chip outputting a second address signal to an address input pin of an address comparison chip.

8. The method for collecting multiple input quantities according to claim 7, characterized in that: The address comparison specifically includes: comparing the second address signal output by the SOC chip with a preset fixed address; when the comparison result is equal, outputting a valid signal to the enable pin of the 38 decoder chip.

9. The method for collecting multiple input quantities according to claim 8, characterized in that: The decoding specifically includes: the 38 decoder chip decodes according to the valid signal on the enable pin and the first address signal on the address input pin to generate a decoding result; and outputs the decoding result to the enable pin corresponding to the data acquisition chip.

10. The method for collecting multiple input quantities according to claim 9, characterized in that: The selectively activating the corresponding data acquisition chip according to the decoding result and transmitting the collected binary input signal to the SOC chip specifically includes: the data acquisition chip detecting the decoding result on the enable pin; when the decoding result is detected to be a low level, the data acquisition chip is enabled and the collected binary input signal is transmitted to the SOC chip.

11. The method for collecting multiple input quantities according to claim 6, characterized in that: Also includes: The SOC chip periodically changes the value of the address signal, activates different data acquisition chips in turn, and performs polling and acquisition on all binary input signals; When one of the data acquisition chips is activated, the other data acquisition chips remain in an inactivated state.

Images