Register read-write protection method and system

Abstract

The invention relates to the technical field of electronics, in particular to a register read-write protection method and system. The method comprises the steps that S1, an error correction code converter receives a data message transmitted by an upstream system, extracts address information and control information in the data message and synchronously generates an error correction code; s2, after the data message is received, a bus interface module is started to execute corresponding read-write operation, the bus interface module carries out decoding according to the address to generate multiple sub-interfaces, and read-write data and error correction codes are written into multiple registers correspondingly connected with the sub-interfaces through the sub-interfaces; and S3, after the read-write data are written into the corresponding registers through the bus interface module, parity check protection is carried out on each register. According to the invention, the cyclic redundancy check protection of the data message is synchronously converted into the error correction code protection by arranging the error correction code converter, so that the use of resources is reduced, and the design complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a register read-write protection method and system. Background Art

[0002] In the prior art, in order to monitor the read and write operation status of the internal control register and meet the requirements of functional safety, a redundant backup method is usually adopted. The logic is to make two sets of completely identical modules and compare them with each other. If the output is different, it is judged that an error has occurred. The redundant design under this logic will use more hardware resources, increase product costs and increase system design complexity. Summary of the invention

[0003] The purpose of the present invention is to provide a register read-write protection method to solve the above technical problems;

[0004] The present invention also aims to provide a register read-write protection system to solve the above technical problems.

[0005] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0006] A register read-write protection method, comprising:

[0007] Step S1, an error correction code converter receives a data message transmitted by an upstream system, extracts address information and control information in the data message and synchronously generates an error correction code;

[0008] Step S2, after the data message is received, the bus interface module is started to perform corresponding read and write operations, the bus interface module decodes the address to generate a multi-channel sub-interface, and the read and write data and the error correction code are written into the multi-channel register corresponding to the sub-interface through the sub-interface;

[0009] Step S3: After the read / write data is written into the corresponding register through the bus interface module, parity check protection is performed on each register.

[0010] Preferably, the data message transmitted by the upstream system has cyclic redundancy check protection.

[0011] Preferably, step S1 further includes, when the error correction code converter receives a data message transmitted by an upstream system, detecting a cyclic redundancy check code of the data message, and the error correction code converter completes the detection of the cyclic redundancy check code and the generation of the first error correction code in the same beat.

[0012] Preferably, step S1 further comprises, before the error correction code converter receives the data message, converting the serial protocol of the upstream system into a bus protocol corresponding to the bus interface module to generate a bus interface signal.

[0013] Preferably, in step S1, the error correction code converter combines the bus address signal, write data selection signal, and read / write direction signal in the bus interface signal to generate error correction check protection for the error correction code, performs separate error correction check protection on the write data signal in the bus interface signal, and performs redundant error correction check protection on the bus selection signal in the bus interface signal.

[0014] Preferably, in step S1, the error correction code includes a first error correction code generated by receiving the data message and a second error correction code regenerated using the data message, and an error correction check is performed based on a comparison between the first error correction code and the second error correction code.

[0015] Preferably, in step S2, when the read / write data is transmitted to the corresponding register through the bus interface module, if the error correction code is found to check a single-byte error, error information is reported, and the error data is restored, and the transmission operation continues; if the error correction code is found to check a multi-byte error, error information is reported and the write operation is stopped.

[0016] A register read-write protection system, used to implement the register read-write protection method, comprising:

[0017] The error correction code converter is used to convert the cyclic redundancy check code protection of the data message transmitted by the upstream system into the error correction code protection;

[0018] The bus interface module is connected to the error correction code converter, and the bus interface module generates multiple sub-interfaces connected to the register, and the read and write data of each sub-interface is protected by the error correction code. The bus interface module includes:

[0019] A first bus interface connected to an output end of the error correction code converter;

[0020] A plurality of tapping units, connected to the first bus interface to receive bus interface signals, and used to tap the bus interface signals to correct the timing of the bus interface signals;

[0021] A plurality of second bus interfaces, connected to the tapping units respectively, the second bus interfaces being used to connect to external sub-modules and perform read and write operations on the external sub-modules;

[0022] The plurality of sub-interfaces are connected to at least one of the second bus interfaces and are used to write the read / write data and the error correction code into the register.

[0023] Preferably, the error correction code converter comprises:

[0024] A data message interface, connected to the upstream system, for receiving the data message to extract information in the data message;

[0025] A first error correction code generator, connected to the data message interface, for synchronously generating an error correction code for the address information of the data message;

[0026] a first memory, connected to the first error correction code generator, and used to store data of the first error correction code generator;

[0027] A second error correction code generator, connected to the data message interface, for synchronously generating an error correction code for the read and write length information of the data message;

[0028] a second memory, connected to the second error correction code generator, and used to store data of the second error correction code generator;

[0029] A third error correction code generator, connected to the data message interface, for synchronously generating an error correction code for the read and write information of the data message;

[0030] A third memory, connected to the third error correction code generator, and used to store data of the third error correction code generator;

[0031] A logic combing unit, connected to the data message interface, used for converting the character length of the input data message into the character length of the output data;

[0032] a fourth error correction code, connected to the logic combing unit, for synchronously generating an error correction code for the read and write data of the data message;

[0033] a fourth memory, connected to the fourth error correction code generator, and used to store data of the fourth error correction code generator;

[0034] A first converter and a second converter are connected to the first memory, the second memory, the third memory, and the fourth memory, and receive the data message and the error correction code respectively;

[0035] A first comparator, connected to output ends of the first converter and the second converter, and configured to compare the data message output by the first converter and the second converter with the error correction code;

[0036] a fifth memory, connected to the data message interface, and used to store the read and write control data of the data message;

[0037] A second comparator, one side of which is connected to the first converter and the second converter, for comparing the read requests output by the first converter and the second converter, and the other side of which is connected to the fifth memory, for acquiring the read-write control data based on the read requests output by the first converter and the second converter.

[0038] Preferably, the error correction code converter further comprises:

[0039] A first detector, connected to the data message interface, for detecting a cyclic redundancy check of the data message;

[0040] a second detector, connected to the first memory, for detecting the error correction code in the first memory;

[0041] a third detector, connected to the second memory, for detecting the error correction code in the second memory;

[0042] a fourth detector, connected to the third memory, and configured to detect the error correction code in the third memory;

[0043] a fifth detector, connected to the fourth memory, and configured to detect the error correction code in the fourth memory;

[0044] A collector, whose input end is connected to the first detector, the second detector, the third detector, and the fourth detector, and receives error information; and whose output end is connected to the first converter and the second converter, and sends the error information;

[0045] The sixth detector is connected to the data message interface and is used to detect the error correction code of the externally input read data.

[0046] The beneficial effects of the present invention are as follows: Due to the adoption of the above technical scheme, the present invention converts the cyclic redundancy check protection of the data message into error correction code protection synchronously by setting an error correction code converter. There is no need to provide two sets of identical backup devices for checking and detecting the error correction code, thereby reducing the use of resources and reducing the complexity of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of the steps of a register read-write protection method according to an embodiment of the present invention;

[0048] Figure 2 This is an architecture diagram of a register read-write protection system in an embodiment of the present invention;

[0049] Figure 3 It is a structural diagram of a bus interface module in an embodiment of the present invention;

[0050] Figure 44 is a structural diagram of an error correction code converter in an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0053] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0054] A register read-write protection method, such as Figures 1 to 4 As shown, including,

[0055] Step S1, an error correction code converter 1 receives a data message transmitted by an upstream system, extracts address information and control information in the data message and synchronously generates an error correction code, and stores the received data message in a buffer;

[0056] Step S2, after the data message is received, the bus interface module 2 is started to perform the corresponding read and write operations, the bus interface module 2 decodes the address to generate a multi-channel sub-interface 24, and the read and write data and error correction code are written into the multi-channel register 3 corresponding to the sub-interface 24 through the sub-interface 24;

[0057] Step S3 , after the read / write data is written into the corresponding register 3 through the bus interface module 2 , parity check protection is performed on each register 3 .

[0058] The present invention uses error correction and checking protection (ECC) nesting technology to seamlessly connect the cyclic redundancy check protection (CRC) of the upstream system and the error correction and checking protection (ECC) of the bus protocol APB and the parity protection (parity) of register 3, thereby realizing end-to-end security protection of register 3.

[0059] Specifically, when the error correction code converter 1 receives a data message from the upstream system, it extracts the address information and control information in the message and generates an error correction code (ECC Code) synchronously, and stores the written data in the buffer and generates the corresponding error correction code synchronously; when the message information is received and there is no problem with the message cyclic redundancy check detection, the register 3 read-write protection system will start the APB bus and perform the corresponding read-write operation. Since a system generally has multiple modules, each module has an APB interface, the system will perform decoding operations on the APB bus according to the address to generate a multi-channel sub-interface 24. During decoding, the error correction code will also be synchronously output to the corresponding sub-interface 24, so the present invention supports the protection of the entire address domain. When data is transmitted to the corresponding module through the APB bus, if the error correction code checks a single-byte error, the system will report an error message, restore the error data, and continue to execute the operation. If the error correction code checks a multi-byte error, the system will report an error message and stop the operation, thereby achieving system security. When the data is written to the corresponding register 3 through the APB bus, the system will perform parity check protection on each register 3. Once an error is found during system operation, the system will generate a corresponding error signal for use by the safety controller.

[0060] In a preferred embodiment, the data message transmitted by the upstream system has cyclic redundancy check protection.

[0061] In a preferred embodiment, step S1 also includes, when the error correction code converter 1 receives the data message transmitted by the upstream system, detecting the cyclic redundancy check code of the data message, and the error correction code converter 1 completes the detection of the cyclic redundancy check code and the generation of the first error correction code in the same beat.

[0062] In a preferred embodiment, step S1 further includes, before the error correction code converter 1 receives the data message, converting the serial protocol of the upstream system into a bus protocol corresponding to the bus interface module 2 to generate a bus interface signal.

[0063] Specifically, the present invention aims at the problem that traditional chips cannot monitor the read and write operation status of the internal control register 3. The present invention provides a register 3 read and write protection method and system to protect the internal control register 3, especially the vehicle-mounted register 3. The present invention receives a data message transmitted from an external upstream system. The data message transmitted by the upstream system will have a cyclic redundancy check protection (CRC). The present invention converts the CRC protection of the data message into the error correction check protection (ECC) of the bus protocol APB through an error correction code converter 1, and generates a corresponding error correction code (ECC Code). Therefore, after the data message is written to the error correction code converter 1, it will not have CRC protection, and the CRC check and the generation of the error correction code are performed in the same beat.

[0064] In the entire data path, the integrity of the data of the entire data chain is required to be protected. The entire data message transmitted from the upstream system has CRC protection. After being written down by the error correction code converter 1, it is taken over by the bus interface module 2, and the data message is further processed and stored in the memory. Therefore, the present invention realizes the protection of the bus link in the whole process from reading data from the upstream system to writing data out.

[0065] In a preferred embodiment, in step S1, the error correction code converter 1 combines the bus address signal, write data selection signal, and read and write direction signal in the bus interface signal to generate error correction code error correction protection, performs separate error correction protection on the read data signal and write data signal in the bus interface signal, and performs redundant error correction protection on the bus selection signal in the bus interface signal.

[0066] Specifically, the present invention generates different ECC protections for different data in the bus interface signal.

[0067] The present invention provides a redundant protection for the bus selection signal (PSEL), and does not provide redundant protection for other signals; further, the bus address signal (PADDR), the write data selection signal (PSTRB), and the read / write direction signal (PWRITE) in the bus interface signal are combined to perform error correction check protection for generating an error correction code, and the read data signal (PRDATA) and the write data signal (PWDATA) are separately provided with error correction check protection;

[0068] Furthermore, the selected signal (PSEL), enable signal (PENABLE), ready signal (PREADY), and transmission failure indication signal (PSLVERR) in the bus interface signal will change during decoding, so each module in the data transmission path ensures that its output is reliable without error correction protection.

[0069] In a preferred embodiment, in step S1, the error correction code includes a first error correction code generated by receiving a data message and a second error correction code regenerated using the data message, and an error correction check is performed based on a comparison between the first error correction code and the second error correction code.

[0070] In a preferred embodiment, in step S2, when the read / write data is transmitted to the corresponding register 3 through the bus interface module 2, if a single-byte error is found in the error correction code check, error information is reported, and the error data is restored, and the transmission operation continues; if a multi-byte error is found in the error correction code check, error information is reported and the write operation is stopped.

[0071] In a preferred embodiment, in step S2, after the data message is received, it is also determined whether there is an error in the cyclic redundancy check code. If not, the bus interface module 2 is started to perform the corresponding read and write operations; otherwise, an error is reported and the read and write operations are stopped.

[0072] A register read / write protection system is used to implement the register read / write protection method in any one of the embodiments, such as Figures 2 to 4 Shown include,

[0073] Error correction code converter 1, used for converting the cyclic redundancy check code protection of the data message transmitted by the upstream system into the generated error correction code protection;

[0074] The bus interface module 2 is connected to the error correction code converter 1. The bus interface module 2 generates multiple sub-interfaces 24 connected to the register 3. The read and write data of each sub-interface 24 are protected by the error correction code. The bus interface module 2 includes:

[0075] A first bus interface 21 connected to an output end of the error correction code converter 1;

[0076] A plurality of beating units 22, connected to the first bus interface 21 to receive the bus interface signal, and used to bet on the bus interface signal and correct the timing of the bus interface signal;

[0077] A plurality of second bus interfaces 23, connected to the tapping units 22 respectively, the second bus interfaces 23 are used to connect to external submodules and perform read and write operations to the external submodules;

[0078] The plurality of sub-interfaces 24 are connected to at least one of the second bus interfaces 23 and are used to write the read / write data and the error correction code into the register 3 .

[0079] Specifically, the present invention is implemented through hardware design. Of course, pure software can also realize the detection of register 3, but the error correction code of the software and the read and write operations of the control information have a long initialization time. In the vehicle environment, there is a time requirement from the user powering on to the lighting of the screen function. Pure software is slow and has poor use effect.

[0080] Registers 3 are divided into several different types, such as read-only, write-only, and read-write. Different circuit structures can be designed for different registers 3, and they can be distinguished according to the number of modules. Furthermore, in addition to the two-level interface distinction between the second bus interface 23 and the sub-interface 24, the bus interface level of the present invention can be infinitely distinguished and protected step by step, and different error correction codes can be generated for protection. According to the address information of the sub-interface 24, the error correction code will also be synchronously output to the corresponding sub-interface 24 during decoding, so the present invention supports protection of the entire address domain.

[0081] In a preferred embodiment, the error correction code converter 1 comprises:

[0082] A data message interface 110, connected to the upstream system, for receiving the data message to extract information in the data message;

[0083] A first error correction code generator 121, connected to the data message interface 110, for synchronously generating an error correction code for the address information of the data message;

[0084] A first memory 131, connected to the first error correction code generator 121, and used to store data of the first error correction code generator 121;

[0085] A second error correction code generator 122, connected to the data message interface 110, for synchronously generating an error correction code for the read and write length information of the data message;

[0086] A second memory 132, connected to the second error correction code generator 122, and used to store data of the second error correction code generator 122;

[0087] A third error correction code generator 123, connected to the data message interface 110, for synchronously generating an error correction code for the read and write information of the data message;

[0088] A third memory 133, connected to the third error correction code generator 123, used to store data of the third error correction code generator 123;

[0089] A logic combing unit 140, connected to the data message interface 110, for converting the character length of the input data message into the character length of the output data;

[0090] A fourth error correction code generator 124, connected to the logic combing unit 140, for synchronously generating an error correction code for the read and write data of the data message;

[0091] a fourth memory 134, connected to the fourth error correction code generator 124, and used to store data of the fourth error correction code generator 124;

[0092] The first converter 151 and the second converter 152 are connected to the first memory 131, the second memory 132, the third memory 133, and the fourth memory 134, and receive the data message and the error correction code respectively;

[0093] A first comparator 161, connected to output ends of the first converter 151 and the second converter 152, and configured to compare the data message output by the first converter 151 and the second converter 152 with the error correction code;

[0094] A fifth memory 135, connected to the data message interface 110, and used to store the read and write control data of the data message;

[0095] A second comparator 162, one side of which is connected to the first converter 151 and the second converter 152, and is used to compare the read requests output by the first converter 151 and the second converter 152, and the other side of which is connected to the fifth memory 135, and obtains the read-write control data based on the read requests output by the first converter 151 and the second converter 152.

[0096] Specifically, in the present invention, the first error correction code generator 121, the second error correction code generator 122, and the third error correction code generator 123 are connected to the data message interface 110, and are used to synchronously generate error correction codes related to the control information;

[0097] Further, the fourth error correction code generator 123 is used to synchronously generate an error correction code related to the data information;

[0098] The first memory 131, the second memory 132, the third memory 133 and the fourth memory 134 can use storage devices such as registers to store data, the fifth memory 135 uses FIFO memory, and the logic combing unit 140 is used for format conversion. The data message interface 110 receives a data message in ACMP format, for example, and the character length is usually 8 bits, while the character length of the ABP protocol is 32 bits per character. The logic combing unit 140 controls the rhythm obtained every four beats for format conversion.

[0099] The first converter 151 and the second converter 152 are redundantly set, and the first comparator 161 compares the data message and the error correction code of the first converter 151 and the second converter 152. If any byte is different in the same timing, an error is triggered, thereby improving the accuracy and reliability of the system;

[0100] The result output by the first comparator includes a bus selection signal (PSEL), an enable signal (PENABLE), a read / write direction signal (PWRITE), a read data signal (PRDATA), a bus address signal (PADDR), and respective corresponding error correction codes;

[0101] The second comparator 162 compares the read requests output by the first converter 151 and the second converter 152, and only confirms that the request is valid when the comparison results are at the same timing, thereby ensuring the accuracy of the request.

[0102] In a preferred embodiment, the error correction code converter 1 further includes:

[0103] A first detector 111, connected to the data message interface 110, for detecting a cyclic redundancy check of the data message;

[0104] A second detector 112, connected to the first memory 131, for detecting the error correction code in the first memory 131;

[0105] A third detector 113, connected to the second memory 132, for detecting the error correction code in the second memory 132;

[0106] a fourth detector 114, connected to the third memory 133, and configured to detect the error correction code in the third memory 133;

[0107] a fifth detector 115, connected to the fourth memory 134, and configured to detect the error correction code in the fourth memory 134;

[0108] The collector is connected to the first detector 111, the second detector 112, the third detector 113, and the fourth detector 114 to receive error information. The output end of the collector is connected to the first converter 151 and the second converter 152 to send error information.

[0109] A sixth detector 116, connected to the data message interface 110, for detecting an error correction code of externally input read data;

[0110] Specifically, when external read data enters and requests to read the data message of the data message interface 110, the sixth detector 116 detects the error correction code to determine whether the data is flipped;

[0111] Specifically, the first detector 111 is used to detect the CRC protection of the data message, and the second detector 112, the third detector 113, the fourth detector 114, and the fifth detector 115 respectively detect the error correction codes generated corresponding to the different types of data placed in each storage device. When an error is detected, the error information is uploaded to the collector, which is sorted and sent to the first comparator 161 and the second comparator 162. Since the error has been detected in the first comparator 161 and the second comparator 162, the first comparator 161 and the second comparator 162 search for the corresponding data message and error correction code according to the error information, and no longer compare the results of the search, thereby saving resources and improving efficiency.

[0112] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A register read-write protection method, characterized in that: include, Step S1, an error correction code converter receives a data message transmitted by an upstream system, extracts address information and control information in the data message and synchronously generates an error correction code; Step S2, after the data message is received, the bus interface module is started to perform corresponding read and write operations, the bus interface module decodes the address to generate a multi-channel sub-interface, and the read and write data and the error correction code are written into the multi-channel register corresponding to the sub-interface through the sub-interface; Step S3: After the read / write data is written into the corresponding register through the bus interface module, parity check protection is performed on each register.

2. The register read-write protection method according to claim 1, characterized in that: The data message transmitted by the upstream system has cyclic redundancy check protection.

3. The register read-write protection method according to claim 2, characterized in that: Step S1 also includes that when the error correction code converter receives a data message transmitted by an upstream system, the data message is checked for cyclic redundancy check code, and the error correction code converter completes the detection of the cyclic redundancy check code and the generation of the first error correction code in the same beat.

4. The register read-write protection method according to claim 1, characterized in that: Step S1 also includes that, before the error correction code converter receives the data message, the serial protocol of the upstream system is converted into a bus protocol corresponding to the bus interface module to generate a bus interface signal.

5. The register read-write protection method according to claim 4, characterized in that: In step S1, the error correction code converter combines the bus address signal, write data selection signal, and read / write direction signal in the bus interface signal to generate the error correction check protection of the error correction code, performs a separate error correction check protection on the write data signal in the bus interface signal, and performs redundant error correction check protection on the bus selection signal in the bus interface signal.

6. The register read-write protection method according to claim 5, characterized in that: In step S1, the error correction code includes a first error correction code generated by receiving the data message and a second error correction code regenerated using the data message, and an error correction check is performed based on a comparison between the first error correction code and the second error correction code.

7. The register read-write protection method according to claim 5, characterized in that: In step S2, when the read / write data is transferred to the corresponding register through the bus interface module, if a single-byte error is found in the error correction code check, error information is reported, and the error data is restored, and the transfer operation is continued; If it is found that the error correction code checks multiple bytes, error information is reported and the write operation is stopped.

8. A register read / write protection system, used to implement the register read / write protection method according to any one of claims 1 to 7, characterized in that: include, The error correction code converter is used to convert the cyclic redundancy check code protection of the data message transmitted by the upstream system into the error correction code protection; The bus interface module is connected to the error correction code converter, and the bus interface module generates multiple sub-interfaces connected to the register, and the read and write data of each sub-interface is protected by the error correction code. The bus interface module includes: A first bus interface connected to an output end of the error correction code converter; A plurality of tapping units, connected to the first bus interface to receive bus interface signals, and used to tap the bus interface signals to correct the timing of the bus interface signals; A plurality of second bus interfaces, connected to the tapping units respectively, the second bus interfaces being used to connect to external sub-modules and perform read and write operations on the external sub-modules; The plurality of sub-interfaces are connected to at least one of the second bus interfaces and are used to write the read / write data and the error correction code into the register.

9. The register read-write protection system according to claim 8, characterized in that: The error correction code converter comprises, A data message interface, connected to the upstream system, for receiving the data message to extract information in the data message; A first error correction code generator, connected to the data message interface, for synchronously generating an error correction code for the address information of the data message; a first memory, connected to the first error correction code generator, and used to store data of the first error correction code generator; A second error correction code generator, connected to the data message interface, for synchronously generating an error correction code for the read and write length information of the data message; a second memory, connected to the second error correction code generator, and used to store data of the second error correction code generator; A third error correction code generator, connected to the data message interface, for synchronously generating an error correction code for the read and write information of the data message; A third memory, connected to the third error correction code generator, and used to store data of the third error correction code generator; A logic combing unit, connected to the data message interface, used for converting the character length of the input data message into the character length of the output data; a fourth error correction code, connected to the logic combing unit, for synchronously generating an error correction code for the read and write data of the data message; a fourth memory, connected to the fourth error correction code generator, and used to store data of the fourth error correction code generator; A first converter and a second converter are connected to the first memory, the second memory, the third memory, and the fourth memory, and receive the data message and the error correction code respectively; A first comparator, connected to output ends of the first converter and the second converter, and configured to compare the data message output by the first converter and the second converter with the error correction code; a fifth memory, connected to the data message interface, and used to store the read and write control data of the data message; A second comparator, one side of which is connected to the first converter and the second converter, and is used to compare the read requests output by the first converter and the second converter, and the other side of which is connected to the fifth memory, and obtains the read-write control data based on the read requests output by the first converter and the second converter.

10. The register read-write protection system according to claim 9, characterized in that: The error correction code converter further comprises: A first detector, connected to the data message interface, for detecting a cyclic redundancy check of the data message; a second detector, connected to the first memory, for detecting the error correction code in the first memory; a third detector, connected to the second memory, for detecting the error correction code in the second memory; a fourth detector, connected to the third memory, and configured to detect the error correction code in the third memory; a fifth detector, connected to the fourth memory, and configured to detect the error correction code in the fourth memory; A collector, whose input end is connected to the first detector, the second detector, the third detector, and the fourth detector, and receives error information; and whose output end is connected to the first converter and the second converter, and sends the error information; The sixth detector is connected to the data message interface and is used to detect the error correction code of the externally input read data.

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