USB signal integrity test method, port configuration method and related equipment

Abstract

The invention discloses a USB signal integrity test method, a port configuration method and related equipment. The USB signal integrity test method comprises the following steps: a UEFI application sets a working mode of a corresponding USB port as a test mode; the corresponding USB port enters a test mode and periodically sends waveform data of USB signal test; and the oscilloscope detects the waveform data so as to carry out signal integrity analysis on the corresponding USB port. The working mode of the USB port corresponding to the to-be-tested ARM platform product is set to be the test mode by means of the UEFI application under the ARM platform, packet sending setting of the corresponding USB port is achieved, the corresponding USB port can periodically send the waveform data of the USB signal test, then a tester can rapidly obtain the waveform data of the USB signal test, and the test efficiency is improved. And the USB signal integrity test efficiency can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of communication testing, and in particular to a USB signal integrity testing method, a port configuration method and related equipment. Background Art

[0002] USB (Universal Serial Bus) interface signal integrity test is a key test method to measure the quality of USB signals. The test principle is: use software to set the Port TestControl register of the corresponding USB controller to prompt the USB controller to enter the test mode; in the test mode, the USB controller will continuously and periodically send test waveforms, and then use a professional oscilloscope to detect the sent waveforms to analyze the USB signal integrity.

[0003] When conducting USB signal integrity testing, the X86 (a complex instruction set CPU architecture) platform can use the USB HSET tool to perform packet operations. However, the ARM (Advanced RISC Machines, a reduced instruction set CPU architecture) platform does not have a corresponding signal integrity packet sending tool. Therefore, when conducting USB signal integrity testing, it can only be done by manually finding and setting multiple corresponding registers to put the corresponding USB port into test mode. Since the USB ports of different ARM platform products vary greatly, the port configuration operation is extremely complicated, so it is difficult to achieve efficient and convenient USB signal integrity testing. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a USB signal integrity testing method, a port configuration method and related equipment which can improve the testing efficiency.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A first aspect of the present invention provides a USB signal integrity test method, which is used to perform a signal integrity test on a USB port corresponding to an ARM platform product to be tested. The USB signal integrity test method comprises the following steps: a UEFI application sets the working mode of the corresponding USB port to a test mode; the corresponding USB port enters the test mode and periodically sends waveform data of a USB signal test; an oscilloscope detects the waveform data and then performs a signal integrity analysis on the corresponding USB port.

[0007] Preferably, the UEFI application sets the working mode of the corresponding USB port to the test mode further comprising: the UEFI application accesses the corresponding USB port through the PCI protocol; clears BIT9 of the PORTSC register and turns off the power of the PortPower register; clears BIT0 of the USBCMD register and waits for BIT0 of the USBSTS register to be set; after BIT0 of the USBSTS register is successfully set, sets BIT28 to BIT31 of the PORTPMSC register to the corresponding test mode.

[0008] Preferably, the UEFI application accessing the corresponding USB port through the PCI protocol further includes: running the UEFI application and inputting the VendorID and DeviceID of the corresponding USB controller; the UEFI application lists the USB controller list corresponding to the VendorID and DevceID by comparing the PCI device list to obtain the corresponding ControllerID; running the UEFI application and inputting the VendorID, DeviceID, ControllerID and PortID of the corresponding USB controller, and the UEFI application accesses the corresponding USB port through the PCI protocol.

[0009] The second aspect of the present invention provides a port configuration method for configuring a USB port corresponding to an ARM platform product to be tested, the port configuration method comprising the following steps: accessing the corresponding USB port through a UEFI application; clearing BIT9 of a PORTSC register and turning off the power of a PortPower register; clearing BIT0 of a USBCMD and waiting for BIT0 of a USBSTS register to be set; after BIT0 of a USBSTS register is successfully set, setting BIT28 to BIT31 of a PORTPMSC register to a corresponding test mode.

[0010] Preferably, accessing the corresponding USB port through the UEFI application further includes: running the UEFI application and inputting the VendorID and DeviceID of the corresponding USB controller to obtain the corresponding ControllerID; running the UEFI application and inputting the VendorID, DeviceID, ControllerID and PortID of the corresponding USB controller, and the UEFI application accesses the corresponding USB port through the PCI protocol.

[0011] The third aspect of the present invention provides a port configuration device for configuring the USB port corresponding to the ARM platform product to be tested, characterized in that the port configuration device includes: a port access module for accessing the corresponding USB port through a UEFI application; a first setting module for clearing BIT9 of the PORTSC register and turning off the power of BIT9; a second setting module for clearing BIT0 of the USBCMD and waiting for BIT0 of the USBSTS register to be set; a third setting module for setting BIT28 to BIT31 of the PORTPMSC register to the corresponding test mode after BIT0 of the USBSTS register is successfully set.

[0012] A third aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores program instructions, and when the program instructions are executed by a processor, the port configuration method described above is implemented.

[0013] The beneficial technical effect of the present invention is that: the present invention uses the UEFI application under the ARM platform to set the working mode of the USB port corresponding to the ARM platform product to be tested to the test mode, realizes the packet sending setting of the corresponding USB port, so that the corresponding USB port can periodically send the waveform data of the USB signal test, thereby enabling the tester to quickly obtain the waveform data of the USB signal test, which can greatly improve the efficiency of the USB signal integrity test. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of a USB signal integrity test method according to the present invention;

[0015] Figure 2 A flowchart showing the steps of setting the working mode of the corresponding USB port to the test mode by the UEFI application of the present invention;

[0016] Figure 3 A schematic diagram of a flow chart of a port configuration method of the present invention;

[0017] Figure 4 It is a structural block diagram of the port configuration device of the present invention. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to more clearly understand the objectives, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0019] The invention provides a USB signal integrity test method, which is used for performing a signal integrity test on a USB port corresponding to an ARM platform product to be tested.

[0020] like Figure 1 As shown, in one embodiment of the present invention, the USB signal integrity test method includes the following steps S1 to S3:

[0021] S1. The UEFI application sets the working mode of the corresponding USB port to the test mode.

[0022] During specific implementation, under the UEFI shell, an application tool under UEFI (Unified Extensible Firmware Interface) is developed so that the UEFI application can set the working mode of the corresponding USB port to the test mode.

[0023] like Figure 2 As shown, this step S1 further includes steps S11 to S14:

[0024] S11. The UEFI application accesses the corresponding USB port through the PCI protocol.

[0025] During the specific implementation, first run the UEFI application and input the VendorID (manufacturer ID), DeviceID (device ID) and other parameters of the corresponding USB controller. The UEFI application will compare the PCI device list, list the USB controller list corresponding to the VendorID and DevceID, and obtain the corresponding ControllerID (USB controller ID); then, run the UEFI application again and input the VendorID, DeviceID, ControllerID, PortID (port ID) and other parameters of the corresponding USB controller. After the UEFI application obtains these parameters, it will access the corresponding USB port through the PCI (Peripheral Component Interconnect) protocol.

[0026] S12. Clear BIT9 of the PORTSC register and turn off the power of the PortPower register.

[0027] The UEFI application clears BIT9 of the PORTSC register of the USB port corresponding to the PCI protocol, so that the PortPower register is in a power-off state.

[0028] S13, clear BIT0 of the USBCMD register, and wait for BIT0 of the USBSTS register to be set.

[0029] After the PortPower register is powered off, BIT0 (Run / Stop) of the USBCMD register is set to 0, that is, BIT0 of the USBCMD register is cleared to terminate the current USB transmission. Once BIT0 (Run / Stop) is cleared, the system will automatically set BIT0 (HCHalted: the register name corresponding to BIT0 in the CPU) of the USBSTS register.

[0030] S14. After BIT0 of the USBSTS register is set successfully, BIT28 to BIT31 of the PORTPMSC register are set to the corresponding test mode.

[0031] After HCHalted is set successfully, set BIT28 to BIT31 of the PORTPMSC register to 4, and then set BIT28 to BIT31 of the PORTPMSC register to the corresponding test mode Test Packet (Test Packet: the corresponding state name after the register is set).

[0032] S2. The corresponding USB port enters the test mode and periodically sends waveform data of the USB signal test.

[0033] When the working mode of the USB port is set, the corresponding USB port can enter the test mode and send a periodic waveform so that the oscilloscope can perform integrity analysis.

[0034] S3. An oscilloscope detects the waveform data, and then performs signal integrity analysis on the corresponding USB port.

[0035] The oscilloscope receives and detects the periodic waveform sent by the corresponding USB port, and then performs signal integrity analysis on the corresponding USB port according to the detection result, thereby completing the signal integrity test of the USB port corresponding to the ARM platform product under test.

[0036] The USB signal integrity test method in the embodiment of the present invention, with the help of the UEFI application under the ARM platform, sets the working mode of the USB port corresponding to the ARM platform product to be tested to the test mode, realizes the packet sending setting of the corresponding USB port, so that the corresponding USB port can periodically send the waveform data of the USB signal test, thereby enabling the tester to quickly obtain the waveform data of the USB signal test, which can greatly improve the efficiency of the USB signal integrity test.

[0037] The present invention also provides a port configuration method, which is used to configure the USB port corresponding to the ARM platform product to be tested.

[0038] like Figure 3As shown, in one embodiment of the present invention, the port configuration method includes the following steps S10 to S40:

[0039] S10. Access the corresponding USB port through the UEFI application.

[0040] During the specific implementation, first run the UEFI application and input the VendorID (manufacturer ID), DeviceID (device ID) and other parameters of the corresponding USB controller. The UEFI application will compare the PCI device list, list the USB controller list corresponding to the VendorID and DevceID, and obtain the corresponding ControllerID (controller ID); then, run the UEFI application again and input the VendorID, DeviceID, ControllerID, PortID (port ID) and other parameters of the corresponding USB controller. After obtaining these parameters, the UEFI application will access the corresponding USB port through the PCI protocol.

[0041] S20. Clear BIT9 of the PORTSC register and turn off the power of the PortPower register.

[0042] The UEFI application clears BIT9 of the PORTSC register of the USB port corresponding to the PCI protocol, so that the PortPower register is in a power-off state.

[0043] S30, clear BIT0 of USBCMD, and wait for BIT0 of USBSTS register to be set.

[0044] After the PortPower register is powered off, BIT0 (Run / Stop) of the USBCMD register is set to 0, that is, BIT0 of the USBCMD register is cleared to terminate the current USB transmission. Once BIT0 (Run / Stop) is cleared, the system will automatically set BIT0 (HCHalted: the register name corresponding to BIT0 in the CPU) of the USBSTS register.

[0045] S40. After BIT0 of the USBSTS register is successfully set, BIT28 to BIT31 of the PORTPMSC register are set to the corresponding test mode.

[0046] After HCHalted is set successfully, set BIT28 to BIT31 of the PORTPMSC register to 4, and then set BIT28 to BIT31 of the PORTPMSC register to the corresponding test mode Test Packet (Test Packet: the corresponding state name after the register is set).

[0047] The port configuration method in the embodiment of the present invention configures the USB port corresponding to the ARM platform product to be tested with the help of the UEFI application under the ARM platform, sets the working mode of the USB port corresponding to the ARM platform product to be tested to the test mode, and realizes the packet sending setting of the corresponding USB port, so that the corresponding USB port can periodically send the waveform data of the USB signal test, thereby enabling the tester to quickly obtain the waveform data of the USB signal test, which can greatly improve the efficiency of the USB signal integrity test.

[0048] based on Figure 3 In the port configuration method in the illustrated embodiment, the present invention further provides a port configuration device for configuring the USB port corresponding to the ARM platform product to be tested.

[0049] like Figure 4 As shown, in one embodiment of the present invention, the port configuration device includes a port access module 10 , a first setting module 20 , a second setting module 30 and a third setting module 40 .

[0050] The port access module 10 is used to access the corresponding USB port through the UEFI application; that is, to execute Figure 3 Step S10 in the port configuration method in the illustrated embodiment.

[0051] The first setting module 20 is used to clear BIT9 of the PORTSC register and turn off the power of BIT9; that is, to execute Figure 3 Step S20 in the port configuration method in the illustrated embodiment.

[0052] The second setting module 30 is used to clear BIT0 of USBCMD and wait for BIT0 of USBSTS register to be set; that is, to execute Figure 3 Step S30 in the port configuration method in the illustrated embodiment.

[0053] The third setting module 40 is used to set BIT28 to BIT31 of the PORTPMSC register to the corresponding test mode after BIT0 of the USBSTS register is successfully set; that is, to perform Figure 3 Step S40 in the port configuration method in the illustrated embodiment.

[0054] The port configuration device in the embodiment of the present invention configures the USB port corresponding to the ARM platform product to be tested with the help of the UEFI application under the ARM platform, sets the working mode of the USB port corresponding to the ARM platform product to be tested to the test mode, and realizes the packet sending setting of the corresponding USB port, so that the corresponding USB port can periodically send the waveform data of the USB signal test, thereby enabling the tester to quickly obtain the waveform data of the USB signal test, which can greatly improve the efficiency of the USB signal integrity test.

[0055] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores program instructions, and when the program instructions are executed by a processor, the various steps of the above-mentioned port configuration method are implemented. The computer-readable storage medium can be a memory including program instructions, and the memory can be implemented by one or more volatile or non-volatile storage devices of any type or a combination thereof, such as static random access memory (Static Random Access Memory, referred to as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, referred to as EEPROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, referred to as EPROM), programmable read-only memory (Programmable Read-Only Memory, referred to as PROM), read-only memory (Read-Only Memory, referred to as ROM), magnetic memory, flash memory, magnetic disk or optical disk. The above-mentioned program instructions can be executed by a processor to complete Figure 3 The various steps of the port configuration method in the illustrated embodiment.

[0056] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Those skilled in the art can make various equivalent changes and improvements based on the above embodiments, and all equivalent changes or modifications made within the scope of the claims should fall within the protection scope of the present invention.

Claims

1. A USB signal integrity test method, used to perform signal integrity test on a USB port corresponding to an ARM platform product to be tested, characterized in that: The following steps are involved: S1. The UEFI application sets the working mode of the corresponding USB port to the test mode; S2, the corresponding USB port enters the test mode and periodically sends the waveform data of the USB signal test; S3. An oscilloscope detects the waveform data, and then performs signal integrity analysis on the corresponding USB port.

2. The USB signal integrity testing method according to claim 1, wherein: The step S1 further comprises: S11, UEFI application accesses the corresponding USB port through PCI protocol; S12, clear BIT9 of the PORTSC register and turn off the power of the PortPower register; S13, clear BIT0 of the USBCMD register, and wait for BIT0 of the USBSTS register to be set; S14. After BIT0 of the USBSTS register is set successfully, BIT28 to BIT31 of the PORTPMSC register are set to the corresponding test mode.

3. The USB signal integrity testing method according to claim 2, wherein: The step S11 further comprises: Run the UEFI application and enter the VendorID and DeviceID of the corresponding USB controller; The UEFI application compares the PCI device list and lists the USB controllers corresponding to the VendorID and the DevceID to obtain the corresponding ControllerID; Run the UEFI application and enter the VendorID, DeviceID, ControllerID, and PortID of the corresponding USB controller. The UEFI application accesses the corresponding USB port through the PCI protocol.

4. A port configuration method for configuring a USB port corresponding to an ARM platform product to be tested, characterized in that: The following steps are involved: S10, accessing the corresponding USB port through the UEFI application; S20, clear BIT9 of the PORTSC register and turn off the power of the PortPower register; S30, clear BIT0 of USBCMD and wait for BIT0 of USBSTS register to be set; S40. After BIT0 of the USBSTS register is successfully set, BIT28 to BIT31 of the PORTPMSC register are set to the corresponding test mode.

5. The port configuration method according to claim 4, characterized in that: The step S10 further comprises: Run the UEFI application and enter the VendorID and DeviceID of the corresponding USB controller to obtain the corresponding ControllerID; Run the UEFI application and enter the VendorID, DeviceID, ControllerID, and PortID of the corresponding USB controller. The UEFI application accesses the corresponding USB port through the PCI protocol.

6. A port configuration device, used to configure the USB port corresponding to the ARM platform product to be tested, characterized in that: The port configuration device comprises: A port access module, used to access the corresponding USB port through a UEFI application; The first setting module is used to clear BIT9 of the PORTSC register and turn off the power of BIT9; The second setting module is used to clear BIT0 of USBCMD and wait for BIT0 of USBSTS register to be set; The third setting module is used to set BIT28 to BIT31 of the PORTPMSC register to the corresponding test mode after BIT0 of the USBSTS register is successfully set.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program instructions, and when the program instructions are executed by a processor, the port configuration method according to claim 4 or 5 is implemented.

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