Verification system, transaction-level modeling method, verification method, and storage medium

Abstract

The invention provides a verification system, a transaction-level modeling method, a verification method, a transaction-level modeling device and a computer readable storage medium. The verification system comprises a transaction-level modeling-based verification platform, the verification platform is used for verifying a chip with a plurality of cores, and the verification platform comprises a plurality of calculation modules used for simulating the plurality of cores; and the control module is in communication connection with the plurality of calculation modules through a transaction-level interface, and the control module is used for scheduling the plurality of calculation modules to execute the calculation task according to the sequential relationship among the plurality of cores. In the embodiment of the invention, the control module can schedule the plurality of calculation modules to execute the calculation task according to the time sequence relationship among the plurality of cores, and compared with a traditional function verification scheme in which each core independently serves as a verification object to perform function verification one by one, the time sequence relationship among the plurality of cores is favorably verified.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a verification system, a transaction-level modeling method, a verification method, and a computer-readable storage medium. Background Art

[0002] The focus of the traditional functional verification method is whether the computing task executed by each core is correct. Therefore, in the traditional functional verification scheme, each core will be independently verified as a verification object one by one. For example, in the traditional functional verification scheme, a core (for example, core 0) in the chip can be simulated through the design under test (DUT), and an excitation signal (i.e., the input of the computing task) can be input to core 0. Correspondingly, the DUT can output a calculation result. If the calculation result output by the DUT matches the ideal calculation result, it can be considered that the functional verification of core 0 has passed. On the contrary, if the calculation result output by the DUT does not match the ideal calculation result, it can be considered that the functional verification of core 0 has failed. And so on, until the functional verification of each core in the chip passes, the functional verification of the chip passes.

[0003] However, this solution of independently verifying the function of each core cannot verify the timing relationship between the computing tasks performed by multiple cores in the chip, which is an important factor in evaluating whether the chip's computing power is effectively utilized. Summary of the invention

[0004] The embodiments of the present application are dedicated to providing a verification system, a transaction-level modeling method, a verification method, a transaction-level modeling device, and a computer-readable storage medium, which are introduced below from the following aspects.

[0005] In a first aspect, a verification system is provided, the verification system comprising a verification platform based on transaction-level modeling, the verification platform being used to verify a chip having multiple cores, the verification platform comprising: multiple computing modules, the multiple computing modules being used to simulate the multiple cores; a control module, the control module being communicatively connected to the multiple computing modules via a transaction-level interface, and the control module being used to schedule the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores.

[0006] In a second aspect, a transaction-level modeling method is provided, which is used to build a verification platform, and the verification platform is used to verify a chip with multiple cores. The method includes: building multiple computing modules, and the multiple computing modules are used to simulate the multiple cores; building a control module, and the control module is communicatively connected to the multiple computing modules through a transaction-level interface, and the control module is used to schedule the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores.

[0007] According to a third aspect, a verification method is provided, which verifies a chip having multiple cores based on a verification platform, wherein the verification platform is a verification platform based on transaction-level modeling, and the verification platform comprises: multiple computing modules, wherein the multiple computing modules are used to simulate the multiple cores; and a control module, wherein the control module is communicatively connected to the multiple computing modules via a transaction-level interface; the verification method comprises: based on the control module, scheduling the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores; and generating performance information of the multiple cores according to the execution results of the computing tasks.

[0008] In a fourth aspect, a transaction-level modeling device is provided, which is used to build a verification platform, and the verification platform is used to verify a chip with multiple cores. The device includes: a processing unit, which is used to build multiple computing modules, and the multiple computing modules are used to simulate the multiple cores; and a control module, which is communicatively connected to the multiple computing modules through a transaction-level interface, and the control module is used to schedule the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores.

[0009] According to a fifth aspect, a computer program product is provided, the computer program product comprising: a computer program code, when the computer program code is run on a computer, the computer executes the methods in the above aspects.

[0010] According to a sixth aspect, a computer-readable medium is provided, wherein the computer-readable medium stores a program code, and when the computer program code runs on a computer, the computer executes the methods in the above aspects.

[0011] In an embodiment of the present application, the control module in the verification platform can be connected to multiple computing modules in the verification platform through a transaction-level interface communication, and the control module can schedule multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores. Compared with the traditional functional verification scheme, each core is independently used as a verification object for functional verification one by one, which helps to verify the timing relationship between multiple cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A schematic diagram of a chip with multiple cores.

[0013] Figure 2 It is a schematic diagram of a possible topological structure of a neural network model.

[0014] Figure 3 A schematic diagram of the timing relationship between multiple cores in a chip that executes a neural network model.

[0015] Figure 4 It is a schematic diagram of the functional verification scheme.

[0016] Figure 5 It is a schematic diagram of a verification system according to an embodiment of the present application.

[0017] Figure 6 It is a schematic diagram of a verification system in an embodiment of the present application.

[0018] Figure 7 It is a schematic flowchart of the transaction-level modeling method of an embodiment of the present application.

[0019] Figure 8 It is a schematic flowchart of a transaction-level modeling method according to another embodiment of the present application.

[0020] Fig. 9 It is a schematic flow chart of the verification method of an embodiment of the present application.

[0021] Fig.10 It is a schematic diagram of a device for transaction-level modeling according to an embodiment of the present application.

[0022] Fig.11 It is a schematic block diagram of a device according to another embodiment of the present application. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0024] Figure 1 A chip with multiple cores is shown. Figure 1 As shown, the chip 100 integrates multiple complete computing engines (also called "cores" or "kernels"), namely core 0 to core 3. Each core can execute independent instructions, so multiple tasks can be processed in parallel to improve the performance and efficiency of the computer. Chips with multiple cores are usually used for high-performance computing, large-scale data processing, multimedia processing and other applications that require a lot of computing. In some implementations, multiple cores can be connected to each other for information exchange.

[0025] In an embodiment of the present application, the chip having multiple cores may be a multi-core processor, for example, a neural network processing unit (NPU).

[0026] At present, with the increase in the number of computing tasks to be executed, higher requirements are placed on the computing power of chips. If the computing power of chips is increased blindly by increasing the number of cores in the chip, the chip area may be larger. Therefore, how to make full use of the computing power of chips has become one of the main research directions.

[0027] In order to effectively utilize the computing power of the chip, when assigning computing tasks to the chip, we will try to assign independent computing tasks to different cores to execute, so that different cores can execute independent computing tasks in parallel. Among them, independent computing tasks can be understood as multiple computing tasks that have no dependencies. Figure 2 Make an introduction.

[0028] For ease of understanding, the following takes the NPU running the computing task in the neural network model as an example. Figure 2 Introduce a solution for chips with multiple cores to perform computing tasks. Figure 2 shows a possible topology of a neural network model. Figure 2 As shown, the neural network model 200 may include two branches: branch 0 and branch 1. Branch 0 includes layer 0 and layer 1, wherein the input of layer 0 is input 0 and input 1 in the input layer, and the output of layer 0 can be used as the input of layer 1. Branch 1 includes layer 2 and layer 3, wherein the input of layer 2 can be input 2 in the input layer, and accordingly, the output of layer 2 can be the input of layer 3.

[0029] Afterwards, the output of layer 1 in branch 0 can be used as the input of layer 4 in neural network model 200, and the output of layer 3 in branch 1 can be used as the input of layer 4 in neural network model 200. At this time, layer 4 can be regarded as a junction. Accordingly, the output of layer 4 can be used as the output of neural network model 200.

[0030] In some implementations, each layer in the neural network model can perform calculations based on the input of the layer and obtain the output of the layer. In the embodiments of the present application, the computing tasks performed in the above-mentioned layers are not limited. For example, when the layer in the neural network model is a convolutional layer, the computing tasks corresponding to the layer may include convolution operations. For another example, when the layer in the neural network model is a pooling layer, the computing tasks corresponding to the layer may include pooling operations.

[0031] In addition, the types of calculations performed between the above layers may be the same or different, and the embodiments of the present application do not limit this. For example, the type of calculation performed by layer 1 in branch 0 and the type of calculation performed by layer 3 in branch 1 may both be pooling operations. For another example, the type of calculation performed by layer 2 in branch 1 and the type of calculation performed by layer 3 in branch 1 may both be quantization operations.

[0032] Based on the above introduction to each layer in the neural network model 200, it can be seen that for branch 0 and branch 1, the input of branch 0 and the input of branch 1 are independent of each other, so the computing tasks contained in branch 0 and the computing tasks contained in branch 1 can be understood as being independent of each other and having no dependency. Therefore, the computing tasks corresponding to branch 0 and the computing tasks corresponding to branch 1 can be executed in parallel by different cores, respectively, which helps to effectively utilize the computing power of the chip.

[0033] In addition, for the computing task corresponding to layer 4, the input of the computing task is the output of layer 1 and the output of layer 3, that is, only when the computing task corresponding to layer 1 is executed and output is obtained, and the computing task corresponding to layer 3 is executed and output is obtained, the computing task corresponding to layer 4 can start to execute. Therefore, the computing task corresponding to layer 4 depends on the execution of the computing task corresponding to layer 1 and the computing task corresponding to layer 3. In some implementations, the computing task corresponding to layer 4 can be assigned to be executed by an independent core in the chip.

[0034] by Figure 1 Taking the chip 100 as an example, the computing task corresponding to branch 0 can be assigned to be executed by core 0, and the computing task corresponding to branch 1 can be assigned to be executed by core 1. The computing task corresponding to layer 4 can be assigned to be executed by core 2. Figure 3 The timing relationship between the computing tasks performed by cores 0 to 2 is introduced. In some scenarios, when the neural network model 200 performs a prediction task, multiple rounds of computing processes may be involved. Figure 3 Taking the prediction task involving n rounds of calculation process as an example, the timing relationship between the execution of calculation tasks by cores 0 to 2 is explained, where n is a positive integer greater than or equal to 1.

[0035] Assume that the time required for the computation task to be performed by core 0 can be expressed by T n-0 It means that the time required for the computational task to be performed by core 1 can be expressed as T n-1 It means that the time required for the computational task to be performed by core 2 can be expressed as T n-2 Indicates that, n represents the number of rounds of the current calculation process, and T n-0 >T n-1 >T n-2 In addition, the time interval between multiple computing tasks executed by each core can be represented by t.

[0036] See also Figure 3 As shown, in time period 1, core 0 can 1-0 Core 1 can execute the computation task corresponding to branch 0 in T 1-1 The computational task corresponding to branch 1 is executed in the internal. Among them, T 1-1 The starting time and T 1-2 The start time of each branch is the same. That is to say, in time period 1, core 0 and core 1 can execute computing tasks in parallel. In addition, since the output of layer 1 in branch 0 and the output of layer 3 in branch 1 are not calculated in time period 1, that is, the computing task corresponding to layer 4 has no input, core 2 is idle in time period 1 and does not execute the computing task corresponding to layer 4.

[0037] In with T 1-0 T of interval time t 2-0 In the same time frame as T 1-1 T of interval time t 2-1 In time period 1, core 1 can execute the computing task corresponding to branch 1. In addition, since the output of layer 1 in branch 0 and the output of layer 3 in branch 1 have been calculated after time period 1, the computing task corresponding to layer 4 can be executed in time period 2. The time T for core 2 to execute the computing task corresponding to layer 4 is 1-2 The start time can be equal to T 1-0 The end time of the calculation process is deduced in the same way for other rounds. For the sake of brevity, each round of calculation process will not be described in detail below.

[0038] In time period N, assume that the computing tasks corresponding to core 0 and core 1 have been completed. Then, in time period N, only core 2 needs to execute the computing tasks corresponding to layer 4. Core 2 can perform the computing tasks corresponding to layer 4 based on the output of layer 1 and layer 3 in time period (n-1). n-2 Execute computational tasks.

[0039] Usually, in order to ensure that the above computing tasks can be correctly executed in the chip, the chip function can be verified by simulation. Figure 3 Introduce the functional verification scheme. Functional verification can be understood as the function verification of DUT. The significance of functional verification is to continuously provide iterative key opinions for the design process of DUT. For example, problems such as unsatisfactory performance, functional bugs in design code, and integration errors found during the functional verification process can be fed back to the chip design process to improve the efficiency of the chip design process.

[0040] Figure 4 This section describes the functional verification method. Figure 4In the process of functional verification of DUT 410, stimulus signal 420 may be input as an input signal into DUT 410, and then the response of DUT 410 to stimulus signal 420, i.e., output result 430, is observed. Finally, it is determined whether output result 430 is similar to the expected output result. If output result 430 is similar to the expected output result, it can be considered that the functional verification of DUT 410 is passed. If output result 430 is not similar to the expected output result, it can be considered that the functional verification result of DUT 410 is failed.

[0041] Functional verification for verification Figure 1 Taking the chip shown as an example, the above-mentioned excitation signal 410 can be the input of the computing task introduced above. The above-mentioned output result can be the output of the computing task introduced above. The focus of the traditional functional verification method is whether the computing task executed by each core is correct. Therefore, in the traditional functional verification scheme, each core is independently verified as a verification object one by one. For example, in the traditional functional verification scheme, the core 0 in the chip can be simulated by the design to be tested, and the excitation signal (i.e., the input of the computing task) is input to the core 0. Correspondingly, the DUT can output a calculation result. If the calculation result output by the DUT matches the ideal calculation result, it can be considered that the functional verification of core 0 has passed. On the contrary, if the calculation result output by the DUT does not match the ideal calculation result, it can be considered that the functional verification of core 0 has failed. And so on, until the functional verification of each core in the chip passes, the functional verification of the chip passes.

[0042] However, this solution of independently verifying the function of each core cannot verify the timing relationship between the computing tasks performed by multiple cores in the chip, which is an important factor in evaluating whether the chip's computing power is effectively utilized.

[0043] In addition, with the widespread application of functional verification, more and more solutions can be used for functional verification. At present, mainstream functional verification can be divided into three categories. Different types of functional verification processes have different problems. The following introduces different types of functional verification.

[0044] In the first type of functional verification, the SV language (system cerilog) can be used to build a verification model to perform functional verification on each core in the chip. This type of verification process can write a reference model according to the register transfer level description language code (register transfer level) design rules, and then use the output of the reference model as the ideal output to perform functional verification on the core simulated by the DUT. Although this SV language-based hardware modeling solution can better verify the details of the core, it is difficult to apply to the early verification of the chip due to its high development difficulty and long development cycle.

[0045] In the second type of functional verification, traditional high-level programming languages ​​(e.g., C++, Python) can be used to build a simulation model of the chip, that is, to use software languages ​​to describe the hardware behavior in the chip. Currently, the modeling scheme based on traditional high-level programming languages ​​can simulate the entire chip function very well, but it is difficult to simulate the timing relationship between multiple cores in the chip.

[0046] In the third type of functional verification, models can be built based on modeling frameworks such as GEM5 and spike testing to simulate chips. Currently, this method provides many standard interfaces to simplify the chip simulation process. However, for chips with higher custom instruction sets (for example, NPU), interfaces still need to be re-established, which is not very user-friendly. In addition, this type of software has a certain threshold for use.

[0047] Therefore, in response to the above problems, an embodiment of the present application provides a verification platform, in which a control module can be communicated with multiple computing modules through a transaction-level interface, and the control module can schedule multiple computing modules to perform computing tasks according to the timing relationship between multiple cores, which helps to verify the timing relationship between multiple cores.

[0048] For ease of understanding, the following Figure 5 A verification system including a verification platform according to an embodiment of the present application is introduced. Figure 5 It is a schematic diagram of a verification system according to an embodiment of the present application. Figure 5 The verification system 500 shown includes a verification platform 510, which is used to verify a chip with multiple cores.

[0049] In some implementations, the verification platform may be a verification platform based on transaction-level modeling (TLM), for example, the verification platform may be a verification platform built on System C. TLM is an advanced digital system modeling method that can model module communication and functions separately, which helps accelerate the collaborative development of software and hardware.

[0050] In some implementations, the verification platform 510 includes: multiple computing modules 511 and a control module 512, wherein the control module 512 and the multiple computing modules 511 can be connected to each other through a transaction-level interface. The multiple computing modules 511 are used to simulate multiple cores. The control module 512 is used to schedule the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores.

[0051] In some implementations, the timing relationship between the multiple cores can be understood as the timing relationship between computing tasks executed by the multiple cores in the chip, wherein the timing relationship can include a parallel timing relationship between the multiple tasks and / or a serial timing relationship between the multiple tasks. Figure 3 Taking the timing relationship shown in FIG. 1 as an example, the timing relationship between multiple cores may include a parallel timing relationship between a computing task executed by core 0 and a computing task executed by core 1. Figure 3 Taking the timing relationship shown as an example, the timing relationship between multiple cores may include a serial timing relationship between a computing task executed by core 2 and a computing task executed by core 1 and a computing task executed by core 0.

[0052] It should be noted that the serial timing relationship in the embodiment of the present application may refer to the serial timing relationship between computing tasks executed by different cores. Of course, the serial timing relationship in the embodiment of the present application may refer to the serial timing relationship between computing tasks executed by the same core.

[0053] Taking the verification platform built on System C as an example, the control module 512 can send instructions (e.g., notification instructions) to multiple computing modules 511 through the transaction-level interface to trigger multiple computing modules to execute events corresponding to computing tasks. Figure 6 For the sake of brevity, the specific introduction will not be repeated here.

[0054] On the one hand, the verification platform of the embodiment of the present application can simulate the multi-core scheduling situation, and based on the TLM, it can verify the possible design vulnerabilities of the multi-core scheduling design at an early stage, and help evaluate the performance benefits brought by multi-core scheduling.

[0055] On the other hand, during the chip verification stage, the verification platform of the embodiment of the present application can be provided as a reference model to the RTL for data comparison to assist in the verification of the RTL.

[0056] On the other hand, since the configuration of multi-core scheduling is generally provided by the compiler, the verification platform of the embodiment of the present application can assist in verifying problems that arise in the compiler's configuration of parameters for multi-core scheduling.

[0057] In some scenarios, the controller used by the control module to simulate not only controls the chip with multiple cores, but also needs to control other chips. Accordingly, in order to better simulate the hardware structure, the control module can also control the modules used to simulate other chips. Figure 6 The processing module 680 is specifically introduced in detail, and for the sake of brevity, it will not be repeated here.

[0058] In the embodiment of the present application, the above-mentioned other chips are not specifically limited. For example, the other chips may include a digital signal processor (DSP). For another example, the other chips may include a direct memory access / bridge subsystem for peripheral component interconnect express (XDMA).

[0059] In some implementations, multiple computing modules are used to simulate multiple cores of a neural network processing unit, and multiple computing modules execute parallel computing tasks in a time sequence, which helps to simulate the time sequence of executing parallel computing tasks. Taking the neural network model 200 as an example, it is assumed that computing module 0 among multiple computing modules is used to simulate core 0 in chip 100, and computing module 1 among multiple computing modules is used to simulate core 1 in chip 100. Based on the above introduction, it can be known that computing module 0 is used to execute the computing task corresponding to branch 0, and computing module 1 is used to execute the computing task corresponding to branch 1. At this time, computing module 0 and computing module 1 execute parallel computing tasks.

[0060] In some scenarios, there is a dependency between the computing tasks performed by different computing modules in the multiple computing modules. Therefore, in order to realize communication between the multiple computing modules, the multiple computing modules can be connected in communication. For example, the communication connection may include connection in the form of direct memory access (DMA) to simplify the process of data transmission. Of course, in the embodiment of the present application, the communication connection may also include other communication methods.

[0061] In some implementations, the above-mentioned multiple computing modules may be provided with ports, and accordingly, the communication connection between the multiple computing modules may be achieved by binding the ports in the multiple computing modules to each other.

[0062] In some implementations, the above-mentioned communication connection can be used to transmit data. Accordingly, a storage module can be provided in the computing module, so that when the computing unit receives data transmitted by other computing units, the data can be stored in the storage module within the computing unit.

[0063] Taking the neural network model 200 as an example, it is assumed that the computing module 0 among the multiple computing modules is used to simulate the core 0 in the chip 100, the computing module 1 among the multiple computing modules is used to simulate the core 1 in the chip 100, and the computing module 2 among the multiple computing modules is used to simulate the core 2 in the chip 100. Based on the above introduction, it can be known that the computing module 0 is used to execute the computing task corresponding to the branch 0, the computing module 1 is used to execute the computing task corresponding to the branch 1, and the computing module 2 is used to execute the computing task corresponding to the layer 4. At this time, the input of the computing task in the computing module 2 is the output of the computing module 0 and the output of the computing module 1. Therefore, after the computing modules 0 and 1 are calculated, the output of the computing module 0 and the output of the computing module 1 can be stored in the computing module 2, so that the computing module 2 performs the computing task based on the output of the computing module 0 and the output of the computing module 1.

[0064] In some implementations, the verification platform also includes a processing module, which is connected to the control module and multiple computing modules through a transaction-level interface, and the processing module is used to receive instructions from the control module and schedule multiple computing modules to perform computing tasks according to the instructions of the control module. In other words, the processing module can be used to directly schedule multiple computing modules, so the level where the processing module is located can be regarded as the top level of multiple computing modules. Taking multiple computing modules used to simulate multiple cores in an NPU as an example, the level where the processing module is located can be called "NPU_TOP".

[0065] The above introduces the functions of each module in the verification platform of the embodiment of the present application, and the following introduces the hierarchical relationship between different modules in the verification platform of the embodiment of the present application.

[0066] In some implementations, the level at which the control module is located may be higher than the level at which the multiple computing modules are located.

[0067] In the implementation of this application, the relationship between the levels of the above two modules is not specifically limited. For example, the level where the control module is located can be the upper level of the level where the multiple computing modules are located. For another example, the level where the control module is located and the level where the multiple computing modules are located can be separated by another level (for example, the level where the processing module described below is located).

[0068] In some implementations, the level where the processing module is located may be located between the level where the control module is located and the level where the multiple computing modules are located. For example, the control module is located at the top layer of the verification platform, the processing module is located at the next level of the top layer, and the multiple computing modules are located at the next level of the level where the processing module is located.

[0069] In some implementations, the level of the module for simulating other chips in the verification platform may be lower than the level of the control module. For example, the level of the module for simulating other chips may be the same as the level of the processing module.

[0070] In order to simulate a multi-core chip more vividly, in some implementations, a memory module and / or cache module shared by multiple cores may be instantiated at the level where the processing module is located. Of course, in the embodiment of the present application, the above-mentioned memory module and / or cache module may not be instantiated in the verification platform.

[0071] In some implementations, the instantiated memory module can be used to simulate the memory in the chip (e.g., system cache). For example, the memory module can be used to store the original input of multiple computing tasks. For another example, the memory module can also be used to store the output results of multiple computing tasks.

[0072] In some implementations, the cache module can be used to simulate a cache in a chip (e.g., a double data rate synchronous dynamic random access memory (DDRSDRAM)). For example, the cache module can be used to store intermediate data during the calculation process of multiple computing tasks.

[0073] For ease of understanding, the following takes the simulation of NPU as an example. Figure 6 The verification system of the embodiment of the present application is introduced. Figure 6 6 is a schematic diagram of a verification system in an embodiment of the present application. The verification system 600 may include a verification platform 610. The verification platform 610 includes a control module 620, a processing module 630, a plurality of calculation modules 640-670 and a processing module 680 for simulating a DSP.

[0074] The control module 620 is used to allocate the tasks to be executed between the processing module 680 and the processing module 630. If the tasks to be executed are computing tasks to be executed by the processing module 630, the control module 620 can trigger the processing module 630 to execute the computing tasks through a notification message. In some implementations, the notification message can carry core information so that the processing module 630 can determine the cores to be notified, wherein the core information can be used to determine the weight, input and other information of the computing tasks to be executed.

[0075] The processing module 630 is used to distribute the tasks to be executed among the plurality of computing modules 640 to 670. The processing module 630 and the computing modules 640 to 670 can interact with each other in the form of events and notifications.

[0076] The above-mentioned multiple computing modules 640-670 are used to perform computing tasks. In some implementations, the computing module 640 may include an interface module P0, the computing module 650 may include an interface module P1, the computing module 660 may include an interface module P2, and the computing module 670 may include an interface module P3. Accordingly, the above-mentioned interface modules may be bound to each other so that the corresponding computing modules can interact through the bound interfaces. Among them, data can be transmitted between the multiple computing modules 640-670 in a DMA manner through the interface.

[0077] Combination of the above Figures 1 to 6 The verification platform of the embodiment of the present application is introduced. Figure 7 The transaction level modeling method of the embodiment of the present application is introduced. It should be noted that: Figure 7 The method shown can be used to build any verification platform introduced above. The usage of the verification platform and each module in the verification platform can be found in the above introduction, and will not be repeated below for the sake of brevity.

[0078] Figure 7 It is a schematic flowchart of the transaction-level modeling method of an embodiment of the present application. Figure 7 The method shown includes steps S710 to S720.

[0079] In step S710, multiple computing modules are constructed.

[0080] The above multiple computing modules are used to simulate multiple cores. For the relevant introduction of computing modules, please refer to the above text, and for the sake of brevity, it will not be repeated here.

[0081] In step S720, a control module is constructed.

[0082] In some implementations, the control module is communicatively connected to the multiple computing modules via a transaction-level interface, and the control module is used to schedule the multiple computing modules to perform computing tasks according to a timing relationship between the multiple cores.

[0083] In some implementations, before step S720, the method further includes: constructing a processing module, the processing module being communicatively connected to the control module and multiple computing modules through a transaction-level interface, and the processing module being used to receive instructions from the control module and scheduling multiple computing modules to perform computing tasks according to the instructions from the control module.

[0084] In some implementations, the control module is located at the top level of the verification platform, the processing module is located at the next level of the top level, and the multiple computing modules are located at the next level of the level where the processing module is located.

[0085] In some implementations, the method further includes: instantiating a memory module and / or a cache module shared by multiple cores at the level where the processing module is located.

[0086] For ease of understanding, the following Figure 6 Taking the verification system 600 shown in FIG. as an example, Figure 8 The transaction-level modeling method of the embodiment of the present application is introduced. Figure 8 It is a schematic flowchart of a transaction-level modeling method according to another embodiment of the present application. Figure 8 The method shown includes steps S810 to S840.

[0087] In step S810 , a control module 620 is constructed at the top level (ie, the first level) of the verification platform.

[0088] In step S820 , the processing module 630 is constructed at a second level, wherein the second level is lower than the first level.

[0089] In some implementations, a cache module and / or a memory module may be instantiated at the second level so as to be shared by the computing modules 640 - 670 .

[0090] In step S830 , calculation modules 640 ˜ 670 are constructed at the third level.

[0091] See also Figure 6 As shown, the verification platform includes four computing modules, so four computing units can be instantiated in the process of constructing computing modules 640 to 670. Generally, in the process of instantiating computing units, corresponding identifiers (e.g., core_id) can be passed in for different instances to distinguish different computing modules, so that the subsequent control module and / or processing module can schedule them based on the identifiers.

[0092] In step S840, ports of different computing modules among the plurality of computing modules are connected at the fourth level so that the plurality of computing modules can communicate with each other through the connected ports.

[0093] See also Figure 6 As shown, port P0 of computing module 640 is connected to port P2 of computing unit 660, so that computing module 640 transmits the output of computing task to computing unit 660. Port P1 of computing module 650 is connected to port P2 of computing unit 660, so that computing module 650 transmits the output of computing task to computing unit 660.

[0094] The transaction level modeling method of the embodiment of the present application is introduced above. Fig. 9 The verification method of the embodiment of the present application is introduced. It should be understood that Fig. 9 The method shown can be executed by any verification platform introduced above, wherein the introduction of each module in the verification platform can be found above, and for the sake of brevity, it will not be repeated below.

[0095] Fig. 9 It is a schematic flow chart of the verification method of an embodiment of the present application. Fig. 9 The method shown includes steps S910 to S920.

[0096] In step S910, based on the control module, multiple computing modules are scheduled to perform computing tasks according to the timing relationship between multiple cores.

[0097] In step S920, performance information of multiple cores is generated according to the execution result of the computing task.

[0098] In some implementations, the above performance information can be used to indicate the timing relationship between multiple computing modules performing computing tasks. For example, taking the chip 100 used in the verification platform to simulate and run the neural network model 200 as an example, if the timing relationship between the multiple computing modules performing computing tasks indicated by the performance information is the same as Figure 3 If the timing relationship of the multiple computing modules in the performance information indicates that the timing relationship of the computing tasks is consistent with Figure 3 If the timing relationship shown does not match, it means that the verification result is not passed. Of course, in the embodiment of the present application, the above performance information can be used to calculate the utilization rate of the computing power of the chip with multiple cores simulated by the verification platform.

[0099] In the embodiment of the present application, the above mismatch is not limited. For example, the above mismatch may include that the performance information indicates that the calculation module 660 is not executed in the second round of calculation, and Figure 3As another example, the mismatch may include that during the first round of calculation, the start time of the calculation task executed by the calculation module 640 is different from the start time of the calculation task executed by the calculation module 650.

[0100] In an embodiment of the present application, the performance information of the above-mentioned multiple cores can be used to evaluate the performance benefits brought by the multiple cores in the chip simulated by the verification platform.

[0101] In some implementations, the above step S910 includes: the control module sends a notification message to the processing module, the notification message is used to instruct the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores; the processing module schedules the multiple computing modules to perform computing tasks based on the notification message. The transmission method of the notification message can refer to the above introduction.

[0102] In some implementations, the processing module schedules multiple computing modules to perform computing tasks based on a notification message, including: in response to the notification message, a target computing module among the multiple computing modules can determine whether to perform the computing task scheduled by the notification message based on preset conditions.

[0103] In some implementations, the preset condition may include whether the target computing module is executing a computing task, and / or the preset condition may include whether the target computing module obtains the input of the computing task to be executed.

[0104] In some implementations, if the above-mentioned preset conditions are met, the target computing module may execute the computing task scheduled by the notification message, and / or, if the above-mentioned preset conditions are not met, the target computing module may not execute the computing task scheduled by the notification message.

[0105] For ease of understanding, the verification process of the embodiment of the present application is introduced below by taking the verification platform 610 as an example of a chip 100 for simulating the operation of the neural network 200. Assume that the computing module 640 is used to simulate the core 0 in the chip 100, the computing module 650 is used to simulate the core 1 in the chip 100, and the computing module 660 is used to simulate the core 2 in the chip 100. In other words, the computing module 640 is used to execute the computing task corresponding to branch 0, the computing module 650 is used to execute the computing task corresponding to branch 1, and the computing module 660 is used to execute the computing task corresponding to layer 4, and the input of the computing task in computing module 2 is the output of computing module 0 and the output of computing module 1.

[0106] In the first round of calculation, the control module 620 may notify the processing module 630 to schedule the calculation module 640 to perform the corresponding calculation task and the calculation module 650 to perform the corresponding calculation task. Accordingly, in response to the notification, the processor module 630 notifies the calculation module 640 and the calculation module 650 to perform the corresponding calculation task.

[0107] After the calculation module 640 completes the calculation task corresponding to branch 0, the calculation module 540 can write the calculation result to the calculation module 660 in a DMA manner, and send a notification to the control module 620 to indicate that the first round of calculation process is over. Accordingly, the control module 620 continues to send a notification to the processing module 630 to notify the calculation module 640 to enter the next round of calculation process through the processing module 630.

[0108] After the calculation module 650 completes the calculation task corresponding to branch 1, the calculation module 650 can write the calculation result to the calculation module 660 in a DMA manner, and send a notification to the control module 620 to indicate that the first round of calculation process is over. Accordingly, the control module 620 continues to send a notification to the processing module 630 to notify the calculation module 650 to enter the next round of calculation process through the processing module 630.

[0109] In the first round of calculation, the control module 620 can notify the processing module 630 to schedule the calculation task corresponding to the calculation module 660, and inform the calculation module 660 of the weight and other information required to perform the calculation task. Accordingly, after receiving the notification sent by the control module 620 through the processing module 630, the calculation module 660 can determine whether the input corresponding to the calculation task has been obtained. If the input corresponding to the calculation task has been obtained, the calculation module 560 can perform the corresponding calculation task. On the contrary, if the input corresponding to the calculation task is not obtained, the calculation module 560 can wait until the input corresponding to the calculation task is obtained, and then perform the corresponding calculation task. Therefore, in the first round of calculation, since the calculation module 660 does not obtain the above-mentioned input, the calculation task is not performed.

[0110] In the second round of calculation, the scheduling and / or execution process of the calculation module 640 and the calculation module 650 are similar to the first round of calculation process, and the above description can be referred to. The following mainly introduces the scheduling and / or execution process of the calculation module 660. When the calculation module 660 detects that the above input has been written locally, the calculation module 660 can execute the calculation task corresponding to layer 4 based on the output of the calculation module 640 and the output of the calculation module 650. After the calculation task corresponding to layer 4 is executed, a notification is sent to the control module 620 to indicate the end of the second round of calculation.

[0111] Accordingly, after receiving the notification sent by the calculation module 660, the control module 620 can schedule the calculation module 660 to perform the next round of calculation process through the processing module 630. In some implementations, the control module 660 can notify the processing module 630 of the weights and other information used by the calculation module 660 to perform the next round of calculation process.

[0112] It should be noted that, in the embodiment of the present application, after receiving the notification sent by the control module 620 through the processing module 630, the calculation module 640 and / or the calculation module 650 determines whether to execute the calculation task scheduled by the notification based on the first condition. For example, if the calculation module 640 receives the above notification and detects that the calculation module 640 is in a calculation state (for example, the previous round of calculation tasks has not ended), at this time, the calculation module 640 can wait for the calculation task to end before executing the calculation task scheduled by the above notification. Of course, in the embodiment of the present application, the above calculation module 640 and / or the calculation module 650 may not perform detection. For example, after receiving the above notification, the calculation module 640 immediately executes the calculation task scheduled by the notification.

[0113] Combination of the above Figures 8 to 9 , describes the method embodiment of the present application in detail, and the following is combined with Figure 10 to Figure 11 , describes the device embodiment of the present application in detail. It should be understood that the description of the method embodiment corresponds to the description of the device embodiment, so the parts not described in detail can refer to the previous method embodiment.

[0114] Fig.10 It is a schematic diagram of a device for transaction-level modeling according to an embodiment of the present application. Fig.10 The illustrated apparatus 1000 comprises a processing unit 1010 .

[0115] The processing unit 1010 is used to construct multiple computing modules, and the multiple computing modules are used to simulate multiple cores.

[0116] The processing unit 1010 is used to construct a control module, which is connected to multiple computing modules through a transaction-level interface communication, and the control module is used to schedule multiple computing modules to perform computing tasks according to the timing relationship between multiple cores.

[0117] In some implementations, the processing unit 1010 is used to: construct a processing module, the processing module is communicated with the control module and multiple computing modules through a transaction-level interface, and the processing module is used to receive instructions from the control module and schedule multiple computing modules to perform computing tasks according to the instructions of the control module.

[0118] In some implementations, the control module is located at the top level of the verification platform, the processing module is located at the next level of the top level, and the multiple computing modules are located at the next level of the level where the processing module is located.

[0119] In some implementations, the processing unit 1010 is used to: instantiate a memory module and / or a cache module shared by multiple cores at the level where the processing module is located.

[0120] In an optional embodiment, the processing unit 1010 may be a processor 1120, and the device 1000 may further include an input / output interface 1130 and a memory 1110. Fig.11 shown.

[0121] Fig.11 It is a schematic block diagram of a device according to another embodiment of the present application. Fig.11 The device 1100 shown may include: a memory 1110, a processor 1120, and an input / output interface 1130. The memory 1110, the processor 1120, and the input / output interface 1130 are connected via an internal connection path, the memory 1110 is used to store instructions, and the processor 1120 is used to execute the instructions stored in the memory 1120 to control the input / output interface 1130 to receive input data and information and output data such as operation results.

[0122] It should be understood that in the embodiment of the present application, the processor 1120 can adopt a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits to execute relevant programs to implement the technical solution provided in the embodiment of the present application.

[0123] The memory 1110 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1120. A portion of the processor 1120 may also include a nonvolatile random access memory. For example, the processor 1120 may also store information on the device type.

[0124] During the implementation process, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 1120 or an instruction in the form of software. The method for requesting uplink transmission resources disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in the processor for execution. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1110, and the processor 1120 reads the information in the memory 1110 and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0125] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0126] It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0127] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0128] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0129] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0130] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0131] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0132] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that can be read by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0133] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A verification system, characterized in that: The verification system includes a verification platform based on transaction level modeling, and the verification platform is used to verify a chip with multiple cores. The verification platform comprises: A plurality of computing modules, the plurality of computing modules being used to simulate the plurality of cores; A control module is connected to the plurality of computing modules via a transaction-level interface, and is used to schedule the plurality of computing modules to perform computing tasks according to a timing relationship between the plurality of cores.

2. The verification system according to claim 1, characterized in that: The verification platform also includes: A processing module, wherein the processing module is communicatively connected with the control module and the plurality of computing modules through a transaction-level interface, and the processing module is used to receive instructions from the control module and schedule the plurality of computing modules to perform computing tasks according to the instructions from the control module.

3. The verification system according to claim 2, characterized in that: The control module is located at the top layer of the verification platform, the processing module is located at the next layer of the top layer, and the multiple computing modules are located at the next layer of the layer where the processing module is located.

4. The verification system according to claim 3, characterized in that: The layer where the processing module is located also instantiates a memory module and / or a cache module shared by the multiple cores.

5. The verification system according to any one of claims 1 to 4, characterized in that: The multiple computing modules are communicatively connected with each other.

6. The verification system according to any one of claims 1 to 4, characterized in that: The multiple computing modules are used to simulate multiple cores of a neural network processing unit, and the multiple computing modules execute parallel computing tasks according to the timing.

7. The verification system according to any one of claims 1 to 4, characterized in that: The verification platform is a verification platform built based on System C.

8. A transaction-level modeling method, characterized in that: The method is used to construct a verification platform, and the verification platform is used to verify a chip with multiple cores. The method comprises: constructing a plurality of computing modules, wherein the plurality of computing modules are used to simulate the plurality of cores; A control module is constructed, wherein the control module is communicatively connected with the plurality of computing modules via a transaction-level interface, and the control module is used for scheduling the plurality of computing modules to perform computing tasks according to a timing relationship between the plurality of cores.

9. The method according to claim 8, characterized in that The method further comprises: A processing module is constructed, wherein the processing module is communicatively connected with the control module and the multiple computing modules through a transaction-level interface, and the processing module is used to receive instructions from the control module and schedule the multiple computing modules to perform computing tasks according to the instructions from the control module.

10. The method according to claim 9, characterized in that The control module is located at the top layer of the verification platform, the processing module is located at the next layer of the top layer, and the multiple computing modules are located at the next layer of the layer where the processing module is located.

11. The method according to claim 10, characterized in that The method further comprises: A memory module and / or a cache module shared by the multiple cores is instantiated at the level where the processing module is located.

12. The method according to any one of claims 8 to 11, characterized in that The multiple computing modules are communicatively connected with each other.

13. The method according to any one of claims 8 to 11, characterized in that: The multiple computing modules are used to simulate multiple cores of a neural network processing unit, and the multiple computing modules execute parallel computing tasks according to the timing.

14. The method according to any one of claims 8 to 11, characterized in that: The verification platform is a verification platform built based on SystemC.

15. A verification method, characterized in that: The verification method verifies a chip with multiple cores based on a verification platform, wherein the verification platform is a verification platform based on transaction-level modeling. The verification platform comprises: A plurality of computing modules, the plurality of computing modules being used to simulate the plurality of cores; A control module, wherein the control module is communicatively connected with the plurality of computing modules via a transaction level interface; The verification method comprises: Based on the control module, scheduling the multiple computing modules to perform computing tasks according to the timing relationship between the multiple cores; According to the execution result of the computing task, performance information of the multiple cores is generated.

16. A computer-readable storage medium, characterized in that: The method comprises a program code for executing the method according to any one of claims 8 to 15.

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