IO expansion circuit

Abstract

The present invention provides an I / O expansion circuit suitable for connection between an MCU and an interface chip for expanding the MCU's I / O. The I / O expansion circuit includes signal pins, a channel input / output management module, a signal channel, a register configuration interface, an interrupt interface, and a DMA interface. The signal pins are used to connect the interface chip to the channel input / output management module and drive information exchange between the interface chip and the MCU. The channel input / output management module is used to manage the input and output signals of the signal channel, transmitting signals output by the signal channel to the signal pins and signals input by the signal pins to the signal channel. The signal channel is used to control the sending and receiving of data. The I / O expansion circuit of the present invention eliminates the need for the CPU or communication port to drive the interface chip to send data and compare received data, thus saving CPU resources and preventing data omission or data transmission timeouts.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an IO expansion circuit. Background Art

[0002] With the growing popularity of electric vehicles and autonomous driving, automotive microcontroller (MCU) application systems are becoming increasingly complex. This has led to a significant increase in the demand for on-chip MCU input and output (IO) resources. At the same time, due to factors such as area, power consumption, cost, and product positioning, the MCU itself cannot provide sufficient IO resources for all applications. Therefore, IO expansion has become indispensable. The main purpose of IO expansion is to strengthen external input and output control when the MCU's on-chip IO resources are scarce. For example, it can compare the input of external parallel IO and control external IO through parallel output. Currently, the most common method for expanding IO resources is to add an interface chip to the MCU. Interface chips include parallel interface chips, serial interface chips, I2C bus chips, SPI bus chips, and interrupt controller chips.

[0003] There are two common approaches to communication between an MCU and an interface chip. The first involves direct CPU intervention, driving on-chip GPIOs to periodically send data to the interface chip to drive external circuits, receive I / O data from the interface chip, and store the received data in its own memory. The CPU also triggers actions based on the received data or changes in the data. This approach consumes significant CPU resources and, due to other CPU tasks, can lead to slow interface chip drive speeds and long time intervals, resulting in data loss or I / O data transmission timeouts. Furthermore, if double-data rate (DDR) transmission is implemented in this approach, differential transmission is typically used to reduce electromagnetic interference (EMI). If single-data rate (SDR) transmission is used, spread spectrum clocking (SSC) is typically used to reduce electromagnetic interference (EMI). Both of these data transmission methods, considering EMC considerations, increase CPU resource consumption and may result in clock rate limitations and poor accuracy. The second approach is to use communication ports such as SPI and I2C to receive IO data from the interface chip. Although this solution reduces CPU intervention, the communication rate of the communication port cannot be changed in real time, the received data is limited, and the data cannot be compared in real time. After receiving a certain amount of IO data, the CPU is still required to participate in detecting and comparing the data, and based on the comparison results, it is determined whether to start the communication port again to obtain IO data. Therefore, this solution may still miss IO data and occupy some CPU resources. In addition, communication ports such as I2C generally only have SDR mode, do not support DDR mode, and cannot be adapted to interface chips that support DDR mode. Secondly, this type of communication port generally cannot achieve the ability to implement clock spread spectrum, and the generated clock signal is easily affected by electromagnetic interference, reducing the stability of the system. Summary of the Invention

[0004] The object of the present invention is to provide an IO expansion circuit that does not require the CPU or communication port to drive the interface chip to send and receive data, thereby saving CPU resources and preventing data from being missed or timed out.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides an IO expansion circuit, which is suitable for being connected between an MCU and an interface chip, and is used to expand the IO of the MCU. The IO expansion circuit includes a signal pin, a channel input and output management module, a signal channel, a register configuration interface, an interrupt interface, and a DMA interface. The signal pin, the channel input and output management module, and the signal channel are connected in sequence. The signal channel is connected to the register configuration interface, the interrupt interface, and the DMA interface, and the register configuration interface, the interrupt interface, and the DMA interface are all connected in pairs. The signal pin is used to connect the interface chip to the channel input and output management module to drive the interface chip to exchange information with the MCU. The channel input and output management module is used to connect the interface chip to the channel input and output management module to drive the interface chip to exchange information with the MCU. The device is used to manage the input and output signals of the signal channel, transmit the signal output by the signal channel to the signal pin, and also transmit the signal input by the signal pin to the signal channel; the signal channel is used to control the sending and receiving of data; the register configuration interface is used to accept user configuration parameters, conditions, and functions, send the user configuration to the signal channel and start the signal channel operation, receive the status flag and data of the signal channel for user query; the interrupt interface is used to judge whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user and generate an interrupt request to send to the MCU; the DMA interface is used to judge whether the DMA trigger condition is met according to the DMA trigger condition configured by the user and generate a DMA request to send to the MCU.

[0007] In one embodiment, the signal pins have multiple groups, each connected to a different type of interface chip; and the signal channels have multiple groups, corresponding one-to-one to the groups of signal pins.

[0008] In one embodiment, each group of signal pins includes a clock signal, a control signal, and multiple data signals. Each data signal is connected to an interface chip of the same type, and multiple interface chips of the same type share the clock signal and the control signal.

[0009] In one embodiment, the signal channel includes a synchronizer, a shift position control generation module, a clock generation module, a control logic module, a receiving FIFO, a transmitting FIFO, a shifter and a comparator. The synchronizer is connected to the register configuration interface, the shift position control generation module, the clock generation module and the control logic module. The shift position control generation module and the clock generation module are also connected to the channel input and output management module. The control logic module is connected to the shift position control generation module, the clock generation module, the shifter and the comparator. The shifter is also connected to the receiving FIFO, the transmitting FIFO, the clock generation module, the comparator and the channel input and output management module. The synchronizer is used to synchronize the signal sent from the register configuration interface to the clock domain inside the signal channel, and also The signal inside the signal channel is synchronized to the register configuration interface; the shift position control generation module is used to generate a control signal under the management of the control logic module, and the control signal can drive the interface chip to latch the data on the external IO connected to the interface chip into the interface chip, or drive the interface chip to send the data sent by the MCU to the external IO connected to the interface chip; the clock generation module is used to generate a clock signal to drive the interface chip under the management of the control logic module; the shifter module cooperates with the sending FIFO and the receiving FIFO, and sends and receives data under the clock signal generated by the clock generation module and the management of the control logic module, with SDR and DDR modes; the comparator is used to receive the data input by the shifter, and compare it under the management of the control logic module to generate a corresponding interrupt request or DMA request.

[0010] In one embodiment, the comparator includes a converter, a cache unit, a comparison unit, a rising edge detection unit, a falling edge detection unit, an OR gate, a logic and judgment unit, a logic or judgment unit, a first selector, a second selector, and a third selector. The converter is connected to the shifter, the control logic module, the cache unit, and the comparison unit, receives the data sent by the shifter, converts the data according to the length of the data to be compared and the data bit to be compared sent by the control logic module, outputs the converted data, and sends it to the cache unit and the comparison unit; the comparison unit is also connected to the third selector. , compare the converted data with the preset value, generate an intermediate comparison result and send it to the third selector; the cache unit is connected to the rising edge detection unit and the falling edge detection unit, receives the converted data, and outputs the first data to be compared, the second data to be compared, and the edge detection enable signal after receiving the two sets of converted data, and sends them to the rising edge detection unit and the falling edge detection unit; the rising edge detection unit is also connected to the OR gate and the first selector, and generates a rising edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal and sends it to the rising edge detection unit and the falling edge detection unit. to the OR gate and the first selector; the falling edge detection unit is also connected to the OR gate and the first selector, and generates a falling edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal, and sends it to the OR gate and the first selector; the first selector is also connected to the logic AND judgment unit and the logic OR judgment unit, and generates an edge detection result according to the rising edge detection result, the falling edge detection result, the output of the OR gate, and the edge detection type signal, and outputs it to the logic AND judgment unit and the logic OR judgment unit; the logic AND judgment unit is also connected to the second selector, and generates a logic AND judgment result according to the edge detection result and sends it to the second selector; the logic OR judgment unit is also connected to the second selector, and generates a logic OR judgment result according to the edge detection result and sends it to the second selector; the second selector is also connected to the third selector, and generates a logic judgment result according to the logic AND judgment result, the logic OR judgment result, and the logic judgment type signal, and sends it to the third selector; the third selector generates a final comparison result according to the intermediate comparison result, the logic judgment result, and the comparison type signal.

[0011] In one embodiment, the clock generation module has two working modes: a global clock mode and a real-time clock mode. The global clock mode generates a clock based on the period and duty cycle information of the global clock configured by the user in the global clock configuration register. The real-time clock mode generates a clock based on the period and duty cycle information of the global clock configured by the user in the global clock configuration register and the period, duty cycle, and clock sequence number information of the real-time clock configured in the real-time clock configuration register. The global clock configuration register and the real-time clock configuration register are both located in the register configuration interface.

[0012] In one embodiment, the clock generation module has a clock spreading function unit, and the clock spreading function unit provides three types of spreading: intermediate spreading, downward spreading, and upward spreading.

[0013] In one embodiment, the clock spreading function unit has a spreading rate, and the spreading rate can be configured as a fixed value or a random value.

[0014] In one embodiment, the IO expansion circuit is integrated into the MCU; or the IO expansion circuit is a separate and independent circuit.

[0015] In one embodiment, the interface chip includes a parallel interface chip, a serial interface chip, an I2C bus chip, an SPI bus chip, or an interrupt controller chip.

[0016] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0017] The IO expansion circuit of the present invention does not require the CPU or the communication port to drive the interface chip to send data and compare received data, thus saving CPU resources and preventing data omission or data transmission timeout. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A structural block diagram of an IO expansion circuit provided in a first embodiment of the present invention;

[0020] Figure 2 for Figure 1 Schematic diagram of the internal circuit of the comparator;

[0021] Figure 3 This is a timing diagram of the interface chip in one embodiment of the present invention;

[0022] Figure 4 This is a timing diagram of a driver interface chip according to an embodiment of the present invention;

[0023] Figure 5 A timing diagram for configuring a driving interval according to an embodiment of the present invention;

[0024] Figure 6 A timing diagram for adjusting the clock period and duty cycle in real time according to an embodiment of the present invention;

[0025] Figure 7 This is a timing diagram showing the clock spread spectrum function being enabled according to an embodiment of the present invention;

[0026] Figure 8 This is a timing diagram of an embodiment of the present invention supporting DDR mode;

[0027] Figure 9 A timing diagram for selecting a specific IO for comparing data according to an embodiment of the present invention;

[0028] Figure 10 A timing diagram showing comparison data with expected values ​​according to an embodiment of the present invention;

[0029] Figure 11 A timing diagram for comparing full data edge matching according to an embodiment of the present invention;

[0030] Figure 12 FIG. 1 is a timing diagram for comparing arbitrary matching of data edges according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present invention. In the following embodiments, the description of each embodiment has its own emphasis. For the parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0032] See also Figure 1As shown, the first embodiment of the present invention provides an IO expansion circuit, which is suitable for connecting between an MCU and an interface chip, and is used to expand the IO of the MCU. The IO expansion circuit includes a signal pin 10, a channel input and output management module 20, a signal channel 30, a register configuration interface 40, an interrupt interface 50, and a DMA interface 60. The signal pin 10, the channel input and output management module 20, and the signal channel 30 are connected in sequence. The signal channel 30 is connected to the register configuration interface 40, the interrupt interface 50, and the DMA interface 60, and the register configuration interface 40, the interrupt interface 50, and the DMA interface 60 are all connected in pairs; the signal pin 10 is used to connect the interface chip to the channel input and output management module to drive the interface chip to exchange information with the MCU; the channel The input and output management module 20 is used to manage the input and output signals of the signal channel 30, transmit the signal output by the signal channel 30 to the signal pin 10, and also transmit the signal input by the signal pin 10 to the signal channel 30; the signal channel 30 is used to control the sending and receiving of data; the register configuration interface 40 is used to accept user configuration parameters, conditions, and functions, send the user's configuration to the signal channel 30 and start the signal channel 30 to work, receive the status flag and data of the signal channel 30 for user query; the interrupt interface 50 is used to determine whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user and generate an interrupt request to send to the MCU, and the DMA interface 60 is used to determine whether the DMA trigger condition is met according to the DMA trigger condition configured by the user and generate a DMA request to send to the MCU.

[0033] The IO expansion circuit of the present invention controls the sending and receiving of data through its own signal channel 30, and does not require the CPU or communication port to drive the interface chip to send and receive data, thereby saving CPU resources and preventing data omission or data transmission timeout.

[0034] The IO expansion circuit of the present invention can be integrated into the MCU or can be independently integrated, and the selection can be made according to actual needs.

[0035] The interface chip may include any one or more of a parallel interface chip, a serial interface chip, an I2C bus chip, an SPI bus chip or an interrupt controller chip.

[0036] In one embodiment, the signal pins 10 are provided in multiple groups, each connected to a different type of interface chip. The signal channels 30 are provided in multiple groups, corresponding one-to-one with the groups of signal pins 10. That is, signal pin group 10 group 0 can be connected to interface chip 0, signal pin group 10 group 1 to driver interface chip 1, and so on. This application scenario can improve the utilization of the IO expansion system and enhance the performance of the application system. In one embodiment, each group of signal pins 10 includes a clock signal, a control signal, and multiple data signals. Each data signal is connected to a corresponding interface chip of the same type, and multiple interface chips of the same type share the clock signal and control signal. Users can select the corresponding number of signal pin groups 10 and the number of data signals on the signal pins 10 through configuration (register configuration interface 40) based on the type and number of interface chips to be connected.

[0037] The channel input and output management module 20 is used to manage the input and output signals of all signal channels 30 in the device, send the output signals of all signal channels 30 in the device to the signal pins 10, and also receive the signals input from the signal pins 10 and distribute them to the corresponding signal channels 30.

[0038] The register configuration interface 40 allows the user to configure various parameters, conditions, and functions of the device (the IO expansion circuit of the present invention), such as the output clock frequency, duty cycle, control signal setup and hold times, and data comparison size and type. The register configuration interface 40 interacts with the signal channels 30 to transmit the user's configuration to the corresponding signal channels 30 and activate them. It also receives status flags and received data from all signal channels 30 for easy user query.

[0039] The interrupt interface 50 determines whether the interrupt trigger conditions configured by the user are met, wherein the interrupt trigger conditions include, for example, a transmission completion trigger interrupt, a reception completion trigger interrupt, an empty transmission FIFO 37 of the signal channel 30, or a full reception FIFO 38 of the signal channel 30. The interrupt interface 50 obtains the status flag of the device from the register configuration interface 40, and determines whether the interrupt trigger conditions are met, thereby determining whether to generate an interrupt request.

[0040] The DMA interface 60 determines whether the DMA trigger conditions configured by the user are met. For example, the DMA trigger conditions include: the transmit FIFO 37 of the signal channel 30 is empty; the receive FIFO 38 of the signal channel 30 is full. The DMA interface 60 obtains the status flag of the device from the register configuration interface 40 and determines whether the DMA trigger conditions are met, thereby determining whether to generate a DMA request and send it to the DMA controller of the MCU.

[0041] The signal channels 30 are described in detail below. There are multiple signal channels 30, corresponding to the number of groups of signal pins 10, that is, one signal channel 30 corresponds to one group of signal pins 10. All signal channels 30 have the same structure, and any signal channel 30 is used as an example below. In one embodiment, the signal channel 30 includes a synchronizer 31, a shift position control generation module 32, a clock generation module 33, a control logic module 34, a receiving FIFO 38, a transmitting FIFO 37, a shifter 36 and a comparator 35. The synchronizer 31 is connected to the register configuration interface 40, the shift position control generation module 32, the clock generation module 33, and the control logic module 34. The shift position control generation module 32 and the clock generation module 33 are also connected to the channel input and output management module 20. The control logic module 34 is connected to the shift position control generation module 32, the clock generation module 33, the shifter 36, and the comparator 35. The shifter 36 is also connected to the receiving FIFO 38, the transmitting FIFO 37, the clock generation module 33, the comparator 35, and the channel input and output management module 20. The synchronizer 31 is used to synchronize the signal sent by the register configuration interface 40 to the clock domain inside the signal channel 30, and also synchronizes the signal inside the signal channel 30 to the register configuration interface 40; the shift position control generation module 32 is used to generate a control signal under the management of the control logic module 34, and the control signal can drive the interface chip to latch the data on the external IO connected to the interface chip into the interface chip, or drive the interface chip to send the data sent by the MCU to the external IO connected to the interface chip; the clock generation module 33 is used to generate a clock signal to drive the interface chip under the management of the control logic module 34; the shifter 36 module cooperates with the sending FIFO 37 and the receiving FIFO 38, and sends and receives data under the clock signal generated by the clock generation module 33 and the management of the control logic module 34, with SDR and DDR modes; the comparator 35 is used to receive the data input by the shifter 36, and compare it under the management of the control logic module 34 to generate a corresponding interrupt request or DMA request.

[0042] The synchronizer 31 is used to synchronize the control signal sent from the register configuration interface 40 to the clock domain inside the signal channel 30, and also synchronize the signal inside the signal channel 30 to the register configuration interface 40 to avoid signal metastable propagation.

[0043] The shift control generation module 32 is used to generate a control signal that can drive the interface chip to latch data from the connected external I / O device into the interface chip, or drive the interface chip to transmit data sent by the device to the connected external I / O device. The control signal generation process involves the shift control generation module 32 first obtaining the relevant configuration from the register configuration interface 40, and then, under the management of the control logic module 34, generating the control signal required by the user. The polarity of the control signal is user-configurable, meaning the user can configure the initial level of the control signal to be high, with low active, or low, with high active. Furthermore, the user can configure the timing of the control signal generation, for example: 1. the control signal needs to be generated before the clock, 2. the control signal needs to be generated after all current clocks have completed, or 3. the control signal needs to be generated after a specific current clock. Furthermore, when configuring the control signal generation timing, the user can configure the interval between the control signal and the clock signal to meet the interface chip's setup and hold times. Furthermore, the user can configure the width of the control signal generation. For example, if the initial level is configured as high, with low active, the user can configure the width of the low level. These configurations are all stored in the register configuration interface 40 .

[0044] The clock generation module 33 is used to generate clock signals to drive external interface chips. This module obtains relevant configurations from the register configuration interface 40 and, under the management of the control logic module 34, generates the required clock signals. This module also generates corresponding clock signals for the shifter 36 to receive and transmit data. This device provides a global clock configuration register for configuring the period and duty cycle of the global clock. In addition, this device provides a series of real-time clock configuration registers, supporting up to eight, for real-time adjustment of the period and duty cycle of specific clocks. Each real-time clock configuration register contains information such as period, duty cycle, and clock sequence number, and is used to configure the period and duty cycle of a specific clock. The clock generation module 33 has two operating modes: 1. The real-time clock adjustment function is disabled (i.e., global clock mode). The user configures the global clock configuration, and the clock generation module 33 generates the clock based on the period and duty cycle information in the global clock configuration. 2. The real-time clock adjustment function is enabled (i.e., real-time clock mode). The user configures both the global and real-time clock configurations, and the clock generation module 33 selects a specific period and duty cycle configuration based on these configurations to generate the clock. In addition, the clock polarity can also be configured, and the user can configure the clock to be high-active or low-active. These configuration registers are also located in the register configuration interface 40.

[0045] In one embodiment, the clock generation module 33 includes a clock spreading function unit (SSC), which provides three types of spreading: intermediate spreading, downward spreading, and upward spreading.

[0046] The clock spread spectrum function unit provides a clock spread spectrum function, which can effectively reduce the EMI of the clock signal and reduce the impact of EMC to cope with complex application systems. It should be noted that when using this function, it is recommended to turn off the real-time clock adjustment function.

[0047] The clock spread function supports three types of spread: intermediate, downward, and upward spread, with a spread rate of δ. The spread rate can be generated in two ways: 1. The user writes a fixed value through register configuration interface 40, which is linear spread; 2. The user writes the spread rate through register configuration interface 40 and enables the random spread rate generation function (random value). The device then uses pseudo-random numbers to randomly generate a value within the spread rate range for clock signal generation. It should be noted that in the second method, the period and duty cycle of each clock signal are randomly generated (within the spread rate range), and the spread rate applies to both period and duty cycle. Intermediate spread refers to the device obtaining information such as frequency fc (i.e., clock period information), duty cycle ŋ, spread rate, and the number of clocks in the drive cycle. It then generates a set of clock signals with frequencies between (1-δ)fc and (1+δ)fc and duty cycles between (1-δ)ŋ and (1+δ)ŋ. The downward spread spectrum device, after obtaining information such as the frequency fc, the duty cycle ŋ, the spreading ratio, and the number of clocks in the drive cycle, will generate a set of clock signals with frequencies between (1-δ)fc and fc and duty cycles between (1-δ) ŋ and ŋ. The upward spread spectrum device, after obtaining information such as the frequency fc, the duty cycle ŋ, the spreading ratio, and the number of clocks in the drive cycle, will generate a set of clock signals with frequencies between fc and (1+δ)fc and duty cycles between ŋ and (1+δ)ŋ.

[0048] The control logic module 34 is the main core control unit inside the signal channel 30. The control logic module 34 cooperates with the shift position generation module, clock generation module 33, shifter 36 and comparator 35 inside the signal channel 30 to generate specific clock signals and control signals to realize data sending, receiving and comparison, etc.

[0049] The shifter 36 works in conjunction with the transmit FIFO 37, receive FIFO 38, clock generation module 33, and control logic module 34 to implement data transmission and reception, supporting both SDR and DDR modes. The number of shift registers within the shifter 36 corresponds to the number of data signals in the signal channel 30. The number of data signals in the signal channel 30 is configurable, for example, the number of data signals is 3. The user can configure any combination of the input and output of these three data signals, for example, data signal 0 is transmit data, and data signals 1 and 2 are receive data. The transmit FIFO 37 and receive FIFO 38 are carriers for storing data, and their stored content is data and a data signal identifier. The data signal identifier is used to distinguish which data signal the data belongs to.

[0050] The following example illustrates the data transmission and reception process, using a data bit count of 32. The data transmission process for signal channel 30 is as follows: The user sequentially writes transmit data into transmit FIFO 37 through register configuration interface 40. The data write size ranges from 1 to 32 bits at a time, with any upper bits less than 32 bits padded with zeros. Shifter 36 sequentially reads transmit data based on the number of transmit data signals and stores them in the corresponding shift register. The clock generation module 33 feeds a clock signal into shifter 36. The control logic module 34, based on user configuration, drives shifter 36 on the rising, falling, or both edges (in DDR mode) of the clock, outputting the data bit by bit onto the data signal.

[0051] The data reception process of signal channel 30 is as follows: Clock generation module 33 inputs a clock signal into shifter 36. Control logic module 34 latches the data signal into the corresponding shifter 36 at the rising edge, falling edge, or both edges (DDR mode) of the clock, according to user configuration. If the write function of receive FIFO 38 is enabled and the received data has reached 32 bits, shifter 36 will sequentially write the data signal, plus the data signal identifier, into receive FIFO 38.

[0052] The comparator 35 is mainly used to compare the changes in the received data and generate corresponding interrupt requests or DMA requests. The comparator 35 receives the data input by the shifter 36 and obtains the size and type of the data from the control logic module 34 to compare the received data.

[0053] See also Figure 2As shown, in one embodiment, the comparator 35 includes a converter 351, a cache unit 353, a comparison unit 352, a rising edge detection unit 354, a falling edge detection unit 355, an OR gate 356, a logic and judgment unit 358, a logic or judgment unit 359, a first selector 357, a second selector 361, and a third selector 362. The converter 351 is connected to the shifter 36, the control logic module 34, the cache unit 353, and the comparison unit 352, receives the data sent by the shifter 36, converts the data according to the length of the data to be compared and the data bits to be compared sent by the control logic module 34, outputs the converted data, and sends it to the cache unit. The comparison unit 352 is connected to the third selector 362, and compares the converted data with the preset value, generates an intermediate comparison result and sends it to the third selector 362; the cache unit 353 is connected to the rising edge detection unit 354 and the falling edge detection unit 355, receives the converted data, and outputs the first data to be compared, the second data to be compared, and the edge detection enable signal to the rising edge detection unit 354 and the falling edge detection unit 355 after receiving the two sets of converted data; the rising edge detection unit 354 is also connected to the OR gate 356 and the first selector 357, and generates an edge detection enable signal according to the first set of data to be compared. The comparison data, the second data to be compared, and the edge detection enable signal generate a rising edge detection result and send it to the OR gate 356 and the first selector 357; the falling edge detection unit 355 is also connected to the OR gate 356 and the first selector 357, and generates a falling edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal and sends it to the OR gate 356 and the first selector 357; the first selector 357 is also connected to the logic and judgment unit 358 and the logic or judgment unit 359, and generates a falling edge detection result according to the rising edge detection result, the falling edge detection result, the output of the OR gate 356, and the edge detection type. The edge detection result generated by the type signal is output to the logic and judgment unit 358 and the logic or judgment unit 359; the logic and judgment unit 358 is also connected to the second selector 361, and generates a logic and judgment result based on the edge detection result and sends it to the second selector 361; the logic or judgment unit 359 is also connected to the second selector 361, and generates a logic or judgment result based on the edge detection result and sends it to the second selector 361; the second selector 361 is also connected to the third selector 362, and generates a logic judgment result based on the logic and judgment result, the logic or judgment result and the logic judgment type signal and sends it to the third selector 362;The third selector 362 generates a final comparison result (hereinafter also referred to as a match signal) and outputs it based on the intermediate comparison result, the logic judgment result, and the comparison type signal.

[0054] The comparator 35 can compare various data sizes, not limited to 8 / 16 / 32 bits. It supports comparison of specific data. For example, if the data comparison size is 8 bits, the user can configure the comparison of any combination of the 8-bit data, such as bit0 / bit3 or bit1 / bit3 / bit7.

[0055] Comparator 35 supports two types of comparisons: 1. Whether the data matches an expected value; 2. Whether the data has changed before or after. The second type can be further divided into three types of changes: 1. Rising edge change (0->1); 2. Falling edge change (1->0); and 3. Any edge change. For the second type, the user can set the specific change for each bit, such as a falling edge change for bit 0, a rising edge change for bit 3, and any edge change for bit 7. Comparator 35 will then detect whether the received data has changed accordingly. Furthermore, comparator 35 supports two other data comparison requirements: 1. Comparison of all bits meeting the change requirement; 2. Comparison of any bit meeting the change requirement. For example, if the data size to be compared is 8 bits and the comparison bits are bit 0 / bit 3 / bit 7, the user can configure the comparison to succeed only if all bits 0 / bit 3 / bit 7 meet the change requirement, or if any one or more of bits 0 / bit 3 / bit 7 meet the change requirement. Comparator 35 also updates the data comparison status in real time and ultimately sends the status to register configuration interface 40.

[0056] Signal channel 30 supports automatic driving of the interface chip and real-time comparison of received data, both of which can be used simultaneously. When both functions are enabled, signal channel 30 will compare received data (comparison conditions are user-configured). Specifically, during the first drive cycle, signal channel 30 drives the interface chip, obtains received data, and feeds it into comparator 35. A drive cycle occurs when signal channel 30 generates a control signal, several clock signals, and receives all data latched within the interface chip. After receiving data during a drive cycle, shifter 36 feeds the received data into comparator 35 for real-time comparison. It should be noted that if the user configures the comparison condition to determine whether the received data matches an expected value, comparator 35 will perform a comparison each time. However, if the user configures the comparison condition to determine whether the data has changed, comparator 35 will only begin comparison after receiving two batches of data. Furthermore, comparator 35 only compares the most recent two batches of data, comparing the changes between the two most recent batches. Furthermore, if the data meets the comparison conditions, the device will generate an interrupt request or DMA request to report to the system. It is important to note that even after the data meets the comparison conditions, since the automatic drive interface chip function is enabled, the device will continue to drive the interface chip, obtaining real-time data that is fed into comparator 35 for real-time comparison. The data comparison status will be updated in real time, without losing the previous comparison status. Furthermore, the user can set the interval between two drive cycles. That is, after the first drive cycle ends, signal channel 30 will delay for a certain time interval (user-configured and implemented by control logic module 34) before starting the next drive cycle. If the automatic drive interface chip is disabled but the real-time data comparison function is enabled, the device will stop driving the interface chip once the data meets the expected conditions.

[0057] The following will take a mainstream interface chip as a specific embodiment, and combine Figure 3-Figure 12 The function of the IO expansion circuit of the present invention is described below. The interface chip is an interface chip that supports 8 IO parallel inputs / serial inputs and one serial output. The timing diagram of the interface chip is Figure 3 .exist Figure 3As shown in the figure, the interface chip latches I / O data when the sh / ld signal (control signal) is low, and shifts the internally latched data to the device on the rising edge of the clock. The io_data in the figure represents the I / O data connected to the interface chip, and its changes are related to the external I / O. q in the figure represents the output of the interface chip. The data changes and speeds of io_data in the figure are for ease of understanding and illustration only and do not represent actual I / O changes. In theory, the frequency of external I / O changes should be slower than the internal clock frequency (clk). The application scenario of this interface chip is to connect eight external I / Os in parallel to the interface chip. The MCU periodically controls the interface chip to latch the levels of the eight I / Os and generates a clock to store these eight I / O levels in the MCU. If the MCU detects a discrepancy between the eight I / O levels or that one I / O data is the expected value, it will execute the corresponding action. Common solutions for driving the interface chip include: 1. The CPU drives the GPIO to control the interface chip; 2. Controlling the interface chip through a communication port such as SPI. The first solution consumes a significant amount of CPU resources to drive the GPIO, significantly reducing MCU performance. The second solution does not support automatic comparison of IO level status, clock spread spectrum function, or DDR mode, and requires CPU intervention after reception. This device circuit can better drive the interface chip, has flexible configuration, and does not occupy CPU resources.

[0058] In this embodiment, the user generates the required clock frequency and SH / LD control signal by configuring the device to meet the setup time and hold time of the interface chip. At the same time, the comparison function and the automatic drive interface chip function are turned on, and the comparison size and type of the IO data are configured. After the configuration is completed, the circuit of the device will automatically drive the interface chip in a loop, receive the IO data and compare it. When the comparison conditions are met, the driving of the interface chip will be stopped, and the CPU or DMA will be notified. When the comparison conditions are not met, the circuit of the device will drive the interface chip again, obtain the latest IO data status in real time and compare it, such as Figure 4 .

[0059] Figure 4 Only two complete processes of obtaining IO data are shown. Subsequently, the device will automatically drive the interface chip again, compare the received data in real time, and notify the CPU or DMA when the data meets the comparison conditions. Figure 4 The automatic drive interface chip function is turned on in the , that is, the device will repeatedly drive the interface chip until the device is turned off or the configuration is changed, compare the data in real time, and save the comparison status. In these two drive cycles, the clock frequency and duty cycle are fixed. Figure 4 In each complete cycle, the device obtains 8 IO data. The data obtained for the first time is 00010001, and the data obtained for the second time is 01010101. Figure 4 The second drive cycle starts after the first drive cycle ends, and the time interval is 0. This interval depends on the application requirements and is user-configurable.

[0060] The user can configure the interval between the two driving cycles, such as Figure 5 The second driving cycle starts after the first driving cycle ends with a delay of 3 clock signals.

[0061] Users can also flexibly change the period and duty cycle of each clock in each driving cycle, supporting up to 8 clocks. Figure 6 As shown in the figure, the third clock period and duty cycle in the first drive cycle are specially configured by the user and are different from the remaining six clock periods. In the second drive cycle, the period and duty cycle of the second clock are also specially configured by the user and are different from the third clock period in the first drive cycle.

[0062] Users can also enable the clock spread spectrum function, such as Figure 7 In the first drive cycle, the clock spread spectrum function is turned on, and the spread spectrum value of each clock is randomly generated by the device (within the user configuration range). Figure 7 It can be seen that within a driving cycle, the period and duty cycle of the clock signal change randomly.

[0063] Since the interface chip does not support double data rate mode, the above figure only shows that one IO data is received in one clock cycle. However, the circuit of this device supports DDR mode, and its possible received data is as follows: Figure 8 As shown. Figure 8 In SPI, data changes occur on both the rising and falling edges of the clock.

[0064] The user can configure the configuration of comparator 35, such as configuring the specific serial number of the IO data to be compared. Since the interface chip supports a maximum of 8 IO inputs (i.e. 8-bit IO data), if the user only wants to compare IO0 / IO3 / IO7 (i.e. bit0 / bit3 / bit7), the number of IO data comparisons can be configured as 8, and the mask value can be configured as 0x89 to only compare IO0 / IO3 / IO7. Figure 9 As shown, in the first driving cycle, the device receives 8-bit data of 00010001. Since only IO0 / IO3 / IO7 are compared, the comparison data is 00000001. Only the comparison data bit is retained, and the remaining bits are 0, even if there is data on IO4.

[0065] In addition, users can configure two comparison types: 1. Compare whether the IO data is the expected value; 2. Compare whether the IO data has changed compared to the previous time.

[0066] To compare whether the IO data is the expected value, the user only needs to write the expected value in advance and start the device. The circuit of this device will periodically obtain the IO data through the interface chip and compare it. When it is the same as the expected value, it will notify the CPU. Figure 10 .exist Figure 10 In the example, the expected value set by the user is 0x88, and the comparison IO is the value of all 8 IOs. Figure 10 It can be seen that when the second received IO data is 0x88, the device will generate a match signal match and report it to the CPU or DMA.

[0067] For the second scenario, IO data changes can be categorized into: 1. Rising edge change (0->1); 2. Falling edge change; and 3. Any edge change. Each IO data can be configured with a specific edge change. For example, IO0 must meet the rising edge change requirement, while IO5 must meet the falling edge change requirement. When comparator 35 detects that the IO0 / IO5 level states in the two preceding and following data meet these requirements, it generates a match signal to notify the CPU or DMA.

[0068] In addition, when comparing multiple IO data, it can be divided into all IOs being satisfied or any one or more of the IOs being satisfied. For example, the interface chip supports a maximum of 8 IO parallel inputs, and the user only wants to compare IO0 / IO4 / IO7. At this time, the user can configure the change requirements of these three IO data (rising edge / falling edge / any edge), and at the same time, can configure the satisfaction conditions to be that these three IO data changes are established at the same time or as long as one or more of these three IO data meet the conditions. After the circuit of this device detects the change of IO data, it compares it with the comparison conditions. If it meets the conditions, it notifies the CPU or DMA processing. Otherwise, it will continue to drive the interface chip to obtain real-time IO data. When the IO size is set to 8bit, the comparison IO is IO1 / IO3 / IO6, the comparison type is to compare IO data changes and meet IO1 is a rising edge, IO3 is a falling edge, IO6 is a falling edge, and IO1 / IO3 / IO6 need to be met at the same time. For example Figure 11 As shown in the figure, the data received by this device for the first time is 01001101, and the data received for the second time is 00110111. Since only IO1 / IO3 / IO6 are compared, and the rising edge of IO1 and the falling edge of IO3 / IO6 are satisfied at the same time, other IO data are ignored. Therefore, after the second data reception is completed and the comparison is successful, a match signal is generated to notify the CPU or DMA. When the user configuration only requires any one of IO1 / IO3 / IO6 to meet the change, such as Figure 12The first data received by this device is 01001101, and the second data received is 01110101. It can be seen that only IO3 meets the falling edge change condition, and IO1 / IO6 do not meet the condition. However, since match_typ is 0, as long as any one of IO1 / 3 / 6 meets the condition, a match signal is generated to the CPU or DMA after the second data reception is completed and the comparison is successful.

[0069] Therefore, the IO expansion circuit of the present invention can be configured flexibly by the user to meet the needs of expanding IO for different interface chips.

[0070] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0071] The IO expansion circuit of the present invention does not require the CPU or communication port to drive the interface chip to send data and compare received data, which saves CPU resources and does not cause data omission or data transmission timeout. In addition, the IO expansion circuit of the present invention supports clock spread spectrum function, supports DDR mode, supports automatic driving of the interface chip, obtains IO real-time data, and compares the data according to the user-configured comparison type to see if it meets the requirements. The comparison conditions of the circuit of this device are diverse, basically covering the mainstream application needs, and shortening the time interval of the sampling data, reducing the probability of missing data. Compared with the current mainstream IO expansion solution, the circuit of this device has high flexibility, strong anti-interference ability, automation capability and higher efficiency.

[0072] The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. In addition, the principle and implementation of the present invention are explained in detail in the specification using specific examples. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. The content of this specification should not be understood as limiting the present invention.

Claims

1. An IO expansion circuit, suitable for connecting between an MCU and an interface chip, for expanding the IO of the MCU, characterized in that: The IO expansion circuit includes a signal pin, a channel input and output management module, a signal channel, a register configuration interface, an interrupt interface, and a DMA interface. The signal pin, the channel input and output management module, and the signal channel are connected in sequence. The signal channel is connected to the register configuration interface, the interrupt interface, and the DMA interface, and the register configuration interface, the interrupt interface, and the DMA interface are all connected in pairs. The signal pin is used to connect the interface chip to the channel input and output management module to drive the interface chip to exchange information with the MCU. The channel input and output management module is used to manage the input and output signals of the signal channel, transmit the signal output from the signal channel to the signal pin, and also transmit the signal input from the signal pin to the signal channel. The signal channel is used to control the sending and receiving of data. The register configuration interface is used to accept user configuration parameters, conditions, and functions, send the user's configuration to the signal channel and start the signal channel, and receive the status flag and data of the signal channel for user query. The interrupt interface is used to determine whether the interrupt trigger condition is met according to the interrupt trigger condition configured by the user and generate an interrupt request to send to the MCU. The DMA interface is used to determine whether the DMA trigger condition is met according to the DMA trigger condition configured by the user and generate a DMA request to send to the MCU. The signal path includes a clock generation module, a control logic module, a receiving FIFO, a transmitting FIFO, a shifter and a comparator; The shifter cooperates with the transmit FIFO and the receive FIFO to transmit and receive data under the management of the clock signal generated by the clock generation module and the control logic module, and has two modes: SDR and DDR; The comparator is used to receive the data input by the shifter and compare it under the management of the control logic module to generate a corresponding interrupt request or DMA request. When the comparison condition is met, the driver interface chip will be stopped and the CPU or DMA will be notified. The comparator supports two types of comparison: whether the data is an expected value, and whether the data has changed before and after; The IO expansion circuit is integrated into the MCU or is a separate and independent circuit; The interface chip includes any one or more of a parallel interface chip, a serial interface chip, an I2C bus chip, an SPI bus chip or an interrupt controller chip.

2. The IO expansion circuit according to claim 1, wherein: There are multiple groups of signal pins, which are respectively connected to different types of interface chips; there are multiple signal channels, which correspond one to one to the groups of signal pins.

3. The IO expansion circuit according to claim 2, wherein: Each group of signal pins includes a clock signal, a control signal, and multiple data signals. Each data signal is connected to an interface chip of the same type, and multiple interface chips of the same type share the clock signal and control signal.

4. The IO expansion circuit according to claim 2, wherein: The signal channel includes a synchronizer, a shift position control generation module, a clock generation module, a control logic module, a receiving FIFO, a transmitting FIFO and a comparator. The synchronizer is connected to the register configuration interface, the shift position control generation module, the clock generation module and the control logic module. The shift position control generation module and the clock generation module are also connected to the channel input and output management module. The control logic module is connected to the shift position control generation module, the clock generation module, the shifter and the comparator. The shifter is also connected to the receiving FIFO, the transmitting FIFO, the clock generation module, the comparator and the channel input and output management module. The synchronizer is used to synchronize the signal sent from the register configuration interface to the clock domain inside the signal channel, and also synchronize the signal inside the signal channel to the register configuration interface. The shift position control generation module is used to generate a control signal under the management of the control logic module. The control signal can drive the interface chip to latch the data on the external IO connected to the interface chip into the interface chip, or drive the interface chip to send the data sent by the MCU to the external IO connected to the interface chip; the clock generation module is used to generate a clock signal to drive the interface chip under the management of the control logic module.

5. The IO expansion circuit according to claim 4, characterized in that: The comparator includes a converter, a cache unit, a comparison unit, a rising edge detection unit, a falling edge detection unit, an OR gate, a logic and judgment unit, a logic or judgment unit, a first selector, a second selector, and a third selector. The converter is connected to the shifter, the control logic module, the cache unit, and the comparison unit, receives the data sent by the shifter, converts the data according to the length of the data to be compared and the data bits to be compared sent by the control logic module, outputs the converted data, and sends it to the cache unit and the comparison unit; the comparison unit is also connected to the third selector, compares the converted data with the preset value, generates an intermediate comparison result, and sends it to the third selector; the cache unit is connected to the rising edge detection unit and the falling edge detection unit, receives the converted data, and outputs the first data to be compared, the second data to be compared, and the edge detection enable signal to the rising edge detection unit and the comparison unit after receiving the two sets of converted data. a falling edge detection unit; the rising edge detection unit is also connected to the OR gate and the first selector, and generates a rising edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal, and sends it to the OR gate and the first selector; the falling edge detection unit is also connected to the OR gate and the first selector, and generates a falling edge detection result according to the first data to be compared, the second data to be compared, and the edge detection enable signal, and sends it to the OR gate and the first selector; the first selector is also connected to the logic and judgment unit and the logic or judgment unit, and generates an edge detection result according to the rising edge detection result, the falling edge detection result, the output of the OR gate, and the edge detection type signal, and outputs it to the logic and judgment unit and the logic or judgment unit; the logic and judgment unit is also connected to the second selector, and generates a logic and judgment result according to the edge detection result and sends it to the second selector; The logic or judgment unit is also connected to the second selector, and generates a logic or judgment result according to the edge detection result and sends it to the second selector; the second selector is also connected to the third selector, and generates a logic judgment result according to the logic and judgment result, the logic or judgment result and the logic judgment type signal and sends it to the third selector; The third selector generates a final comparison result output according to the intermediate comparison result, the logic judgment result and the comparison type signal.

6. The IO expansion circuit according to claim 4, characterized in that: The clock generation module has two working modes: global clock mode and real-time clock mode. The global clock mode generates a clock according to the period and duty cycle information of the global clock configured by the user in the global clock configuration register. The real-time clock mode generates a clock according to the period and duty cycle information of the global clock configured by the user in the global clock configuration register and the period, duty cycle, and clock sequence number information of the real-time clock configured in the real-time clock configuration register. The global clock configuration register and the real-time clock configuration register are both located in the register configuration interface.

7. The IO expansion circuit according to claim 4, characterized in that: The clock generation module has a clock spread spectrum function unit, and the clock spread spectrum function unit provides three types of spread spectrum: intermediate spread spectrum, downward spread spectrum, and upward spread spectrum.

8. The IO expansion circuit according to claim 7, characterized in that: The clock spreading function unit has a spreading rate, and the spreading rate can be configured as a fixed value or a random value.

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