Package substrate size optimization method, computer equipment and storage medium

Abstract

The invention relates to the technical field of chip packaging design, and discloses a packaging substrate size optimization method, computer equipment and a storage medium, and the method comprises the steps: providing a packaging planning canvas in a display image of a terminal; receiving a first layout drawing operation for the packaging device on the packaging substrate; in response to the first layout drawing operation, displaying a first layout graph of the package substrate in a package planning canvas in a two-dimensional tiling form to plan the size of the package substrate; wherein the first layout pattern is used for representing the placement condition of the packaging device arranged on the packaging substrate or the preset panel area according to the chip design requirement, and prompting the adjustment and optimization direction of the packaging substrate. The method has the beneficial effects that the probability of repeatedly adjusting the size of the packaging substrate can be reduced, and the design efficiency of chip packaging is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip packaging design, and in particular to a method for optimizing the size of a packaging substrate, a computer device, and a storage medium. Background Art

[0002] During the chip package design process, the size of the package substrate needs to be evaluated. The package substrate is the material that supports and protects the integrated circuit (IC) chip. Its main functions include providing electrical connections, mechanical support, heat dissipation management, and protecting the chip from environmental influences. The design of the package substrate is critical to chip performance and reliability.

[0003] In the related art, the size of the package substrate is determined based on the die area, the number of dies, the packaging process requirements, the signal scale, etc. However, if the chip layout on the package substrate changes, the size of the package substrate also needs to be redesigned. It can be seen that the size of the package substrate may need to be adjusted repeatedly, and this repetitive process will have a certain impact on the design efficiency. Summary of the invention

[0004] The present application provides a method for optimizing the size of a packaging substrate, a computer device, and a storage medium, which can reduce the probability of repeated adjustment of the size of the packaging substrate and improve the design efficiency of chip packaging.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of the present application provides a method for optimizing the size of a package substrate, the method comprising:

[0007] Providing a package planning canvas in a display screen of a terminal;

[0008] Receiving a first layout drawing operation for a packaged device on the packaged substrate; wherein the packaged device is a component inside a chip for realizing chip functions and ensuring chip performance;

[0009] In response to the first layout drawing operation, a first layout graphic of the packaging substrate is displayed in a two-dimensional tiled form in the packaging planning canvas to plan the size of the packaging substrate; wherein the first layout graphic is used to characterize the placement of the packaging devices arranged according to the chip design requirements on the packaging substrate or on a preset panel area, and prompt the adjustment and optimization direction of the packaging substrate.

[0010] In the technical solution provided in the present application, the packaged device is drawn on the package planning canvas to obtain a layout graphic displayed in a two-dimensional tiled manner, which can quickly and intuitively plan the size of the package substrate. The layout graphic represents the placement of the packaged device on the package substrate or the preset panel area according to the chip design requirements, and prompts the adjustment and optimization direction of the package substrate. The package substrate size is optimized according to the prompted adjustment and optimization direction, which can reduce unnecessary repeated design to a certain extent and improve design efficiency.

[0011] In one embodiment, the first layout pattern includes a plurality of rectangles arranged according to the chip design requirements, and a boundary box surrounding the plurality of rectangles;

[0012] The rectangle is used to represent the placement area of ​​the packaged device on the packaged substrate and / or to represent the placement area of ​​the gaps between the packaged devices on the packaged substrate.

[0013] In the embodiment of the present application, a rectangle is used to represent the packaged devices on the packaged substrate and / or the gaps between the packaged devices, so as to display the placement of the packaged devices on the packaged substrate in an intuitive and quick manner. Furthermore, based on the first layout graph, the design and work risks can be pre-evaluated to save development costs.

[0014] In one embodiment, the size of the packaging substrate is planned according to the boundary size of the first layout pattern.

[0015] In the embodiment of the present application, the size of the packaging substrate is planned by the boundary size of the first layout graphic, which provides a data basis for determining the panel utilization, thereby being able to judge whether the current packaging substrate size meets the preset layout requirements, and then determine whether to stop debugging and optimizing the packaging substrate.

[0016] In one of the embodiments, the first layout graphic includes a first layout pattern; the first layout pattern is used to represent the layout of the packaging substrate in a preset panel area.

[0017] In the embodiment of the present application, the layout situation on the preset panel area is intuitively displayed through the first layout pattern, which can prompt the adjustment and optimization direction of the package substrate. Based on the adjustment and optimization direction, the pertinence of the package substrate optimization is improved, and the design efficiency is improved.

[0018] In one embodiment, the method further includes: in response to a second layout drawing operation for the adjusted packaged device, displaying a second layout graphic of the adjusted packaged substrate in a two-dimensional tiled manner; wherein the panel utilization corresponding to the second layout graphic is better than the panel utilization corresponding to the first layout graphic.

[0019] In the embodiment of the present application, the size of the packaging substrate is adjusted and optimized according to the adjustment optimization direction suggested by the first layout figure to obtain the second layout figure, and the panel utilization corresponding to the second layout figure is better than the panel utilization corresponding to the first layout figure. It can be seen that adjusting and optimizing according to the suggested adjustment optimization direction can improve the utilization rate of the panel, reduce the waste of panel raw materials, and improve the production capacity and efficiency of integrated circuit manufacturing.

[0020] In one embodiment, the panel utilization corresponding to the first layout graphic is determined based on the number of layouts corresponding to the first layout graphic or the utilization rate of the preset panel area; the panel utilization corresponding to the second layout graphic is determined based on the number of layouts corresponding to the second layout graphic or the utilization rate of the preset panel area.

[0021] In one embodiment, after the packaging substrate is debugged and optimized multiple times, the method further includes: determining a target layout graphic that meets preset layout requirements in the layout graphic corresponding to each debugging and optimization; wherein the size of the packaging substrate corresponding to the target layout graphic is used to carry out subsequent packaging design.

[0022] In the embodiment of the present application, a target layout result that meets a preset layout requirement is determined in the layout result corresponding to each debugging optimization, thereby ensuring panel utilization and increasing the number of substrates that can be manufactured by the panel.

[0023] In one embodiment, the adjustment optimization direction includes at least one of adjusting the die area, adjusting the die arrangement, adjusting the packaging process rules, and adjusting the substrate arrangement.

[0024] In one embodiment, the actual size of the packaged device is displayed in the first layout diagram in the same size or in equal proportion.

[0025] In a second aspect, an embodiment of the present application provides a device for optimizing the size of a package substrate, the device comprising:

[0026] A planning canvas providing module, used for providing a packaged planning canvas in a display screen of a terminal;

[0027] A drawing operation receiving module, used to receive a first layout drawing operation for a packaged device on the packaged substrate; wherein the packaged device is a component inside a chip used to realize chip functions and ensure chip performance;

[0028] A layout graphic display module is used to display the first layout graphic of the packaging substrate in a two-dimensional tiled form in the packaging planning canvas in response to the first layout drawing operation to plan the size of the packaging substrate; wherein the first layout graphic is used to represent the placement of the packaging device arranged according to the chip design requirements on the packaging substrate or on a preset panel area, and prompt the adjustment optimization direction of the packaging substrate.

[0029] In a third aspect, an embodiment of the present application provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the above-mentioned method for optimizing the size of a packaging substrate by executing the computer instructions.

[0030] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the above-mentioned method for optimizing the size of a packaging substrate.

[0031] In a fifth aspect, an embodiment of the present application provides a computer program product, including computer instructions, wherein the computer instructions are used to enable a computer to execute the above-mentioned method for optimizing the size of a packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1a A schematic diagram of a device layout diagram provided for an example scenario of this application;

[0034] Figure 1b A schematic diagram of a bounding box of a package substrate provided for an example scenario of the present application;

[0035] Figure 1c A schematic diagram of a substrate layout pattern provided for an example scenario of this application;

[0036] Figure 1d A schematic diagram of the adjusted substrate layout pattern provided for the example scenario of this application;

[0037] Figure 2a A schematic flow chart of a method for optimizing the size of a package substrate provided in an embodiment of the present application;

[0038] Figure 2bA schematic diagram of a first layout diagram provided in an embodiment of the present application;

[0039] Figure 3a A schematic diagram of placing multiple dies on a packaging substrate provided in an embodiment of the present application;

[0040] Figure 3b A schematic diagram of placing an interposer on a packaging substrate provided in an embodiment of the present application;

[0041] Figure 3c A schematic diagram of placing multiple interposers on a packaging substrate provided in an embodiment of the present application;

[0042] Figure 4a A schematic diagram of a multi-die arrangement layout of a packaging substrate provided in an embodiment of the present application;

[0043] Figure 4b A schematic diagram of a package substrate with multiple bare chips arranged in an optimized manner according to an embodiment of the present application;

[0044] Figure 4c A schematic diagram of the arrangement layout of multiple interposer layers of a packaging substrate provided in an embodiment of the present application;

[0045] Figure 4d A schematic diagram of a package substrate provided in an embodiment of the present application after multiple interposer layers are arranged and optimized;

[0046] Figure 5a A schematic diagram of a preset panel area provided in an embodiment of the present application;

[0047] Figure 5b A schematic diagram of a process of drawing a first layout graphic provided in an embodiment of the present application;

[0048] Figure 5c A schematic diagram of a process of drawing a second layout graphic provided in an embodiment of the present application;

[0049] Figure 5d A schematic diagram of a third layout diagram provided in an embodiment of the present application;

[0050] Figure 6 A schematic diagram of the structure of a device for optimizing the size of a packaging substrate provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0053] In the related art, since the chip information and quantity placed on the package substrate may change before the package design, it is difficult to determine the package substrate size (or package substrate area) in the early stage of package design, and it is even more difficult to optimize the package substrate size and select the preferred layout scheme. If the size of the package substrate is not optimized, the number of substrates that can be manufactured on a panel (Pannel) is small, resulting in waste of raw materials and poor production capacity and efficiency of integrated circuit manufacturing. In addition, even if the area is determined later, it may be necessary to change the design of the area, which will affect the design efficiency.

[0054] Based on this, an embodiment of the present application provides a method for optimizing the size of a packaging substrate. Through this optimization method, the packaging device is drawn on the packaging planning canvas to obtain a layout graphic displayed in a two-dimensional tiled manner, which can quickly and intuitively plan the size of the packaging substrate. The layout graphic represents the placement of the packaging device on the packaging substrate or on the preset panel area according to the chip design requirements, and prompts the adjustment and optimization direction of the packaging substrate. According to the prompted adjustment and optimization direction, unnecessary repeated designs can be reduced to a certain extent, and design efficiency can be improved. Furthermore, by optimizing the size of the packaging substrate, more packaging substrates can be planned using the panel to improve the production capacity and efficiency of integrated circuit manufacturing.

[0055] An embodiment of the present application provides a scenario example of a method for optimizing the size of a packaging substrate. In this scenario example, before designing the packaging substrate, software with a drawing function can be opened in the terminal, and the drawing interface of the software is displayed in the display interface of the terminal. The drawing area in the screen interface provides the user with a packaging planning canvas. First, the user can draw a rectangle of the same size or proportion as the area of ​​the packaging device and the spacing between the packaging devices on the packaging planning canvas, and use the drawn rectangle to represent the packaging device and the spacing between the packaging devices. After the rectangle is drawn, multiple rectangles are displayed on the packaging planning canvas to obtain a device layout diagram. The layout diagram represents the placement of the packaging devices arranged on the packaging substrate according to the chip design requirements. For example, single-die packaging is used as an example for explanation. Please refer to Figure 1a,A rectangle 102 representing the bare die area, a rectangle 104 representing the electronic component area, a rectangle 106 representing the gap area between the bare die and the electronic components, a rectangle 108 representing the gap area between the electronic components and the metal cover or the reinforcement foot, and a rectangle 110 representing the area of ​​the metal cover or the reinforcement foot are drawn on the package planning canvas.

[0056] Next, the user draws bounding boxes around multiple rectangles on the package planning canvas to represent the size of the package substrate. Figure 1b , a bounding box 112 is drawn around rectangle 102 , rectangle 104 , rectangle 106 , rectangle 108 , and rectangle 110 on the package planning canvas.

[0057] Next, a preset panel area is determined in the package planning canvas, and the user issues a simulated layout operation on the preset panel area. In response to the simulated layout operation on the boundary box, the substrate layout pattern of the boundary box is displayed in the preset panel area. For example, see Figure 1c , the panel 114 is divided into four preset panel areas 116. For each preset panel area 116, a plurality of boundary boxes 112 are simulated and arranged in the preset panel area 116 to obtain a substrate layout pattern on the preset panel area 116, and the number of initial package substrates on the preset panel area 116 is determined by the number of boundary boxes in the substrate layout pattern.

[0058] Next, the substrate layout pattern on the preset panel area 116 is used to indicate the adjustment optimization direction of the package substrate. Figure 1c After the simulated layout of the preset panel area 116 for the boundary box 112, there is a remaining area in the Y direction. Under this prompt, any of the following adjustment strategies is executed to optimize the size of the packaging substrate so that the optimized packaging substrate can utilize the remaining area in the Y direction, thereby increasing the number of packaging substrates and panel utilization.

[0059] 1) Adjust the arrangement of the substrates, maintain the area of ​​the package substrate unchanged, extend the size of the package substrate in the Y direction, and shorten the size of the package substrate in the X direction.

[0060] 2) Adjust the die area or shape, change the size of the package substrate in the Y direction, and / or change the size in the X direction, so that the adjusted package substrate can utilize the remaining area in the Y direction.

[0061] 3) Adjust the arrangement of the bare chips, change the size of the package substrate in the Y direction, and / or adjust the size in the X direction, so that the adjusted package substrate can utilize the remaining area in the Y direction.

[0062] 4) Adjusting the packaging process rules, adjusting the size of the packaging substrate in the Y direction, and / or adjusting the size in the X direction, so that the adjusted packaging substrate can utilize the remaining area in the Y direction.

[0063] Finally, after determining the adjustment strategy, the adjusted package substrate is determined by redrawing the rectangle representing the adjusted package device and the boundary box representing the adjusted package substrate. Resimulate the layout of the adjusted package substrate and display the adjusted substrate layout pattern in the preset panel area. The number of adjusted package substrates on the preset panel area is determined by the adjusted substrate layout pattern. For example, refer to Figure 1d , a plurality of adjusted boundary boxes 118 are re-simulated and arranged in the preset panel area 116 to obtain an adjusted substrate layout pattern on the preset panel area 116, and the number of adjusted package substrates on the preset panel area 116 is determined by the number of adjusted boundary boxes in the adjusted substrate layout pattern. The number of adjusted package substrates on the preset panel area is greater than the initial number of package substrates on the preset panel area.

[0064] It is understandable that the debugging and optimization of the package substrate needs to be repeated multiple times. Each debugging and optimization adopts at least one of the above adjustment strategies for optimization, then redraws the optimized package components and re-simulates the layout, and finally evaluates the number of package substrates or panel utilization. After multiple debugging and optimization, the package substrate size that meets the preset layout requirements is determined in the simulation layout results generated by each debugging and optimization, and is used in the subsequent package design process.

[0065] According to an embodiment of the present application, an embodiment of a method for optimizing the size of a packaging substrate is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0066] In this embodiment, a method for optimizing the size of a package substrate is provided, which can be used for the above-mentioned terminal. Figure 2a is a flow chart of a method for optimizing the size of a package substrate according to an embodiment of the present application, such as Figure 2a As shown, the process includes the following steps:

[0067] S110: providing a packaging planning canvas in a display screen of a terminal.

[0068] Specifically, the terminal is installed with software with a drawing function, which may be any one of presentation software (such as PPT), word processing software (such as word), drawing software (such as visio, drawing software), computer-aided design software (such as CAD), and chip design auxiliary software (such as EDA). In response to the start-up operation of the software, the operation interface of the software is displayed, and a package planning canvas is provided in the displayed operation interface.

[0069] S120, receiving a first layout drawing operation for a packaging device on a packaging substrate, where the packaging device is a component inside a chip for realizing chip functions and ensuring chip performance.

[0070] S130. In response to the first layout drawing operation, a first layout graphic of the packaging substrate is displayed in a two-dimensional tiled form in the packaging planning canvas to plan the size of the packaging substrate; the first layout graphic is used to represent the placement of packaging components arranged according to chip design requirements on the packaging substrate or on a preset panel area, and prompt the adjustment and optimization direction of the packaging substrate.

[0071] Wherein, if conventional packaging technology is adopted, the packaged device may include a bare chip, an electronic component, a metal cover or a reinforcement foot. If advanced packaging technology is adopted, the packaged device may include an interposer, an electronic component, a metal cover or a reinforcement foot. The first layout drawing operation may include drawing a first plane shape representing the packaged device in a corresponding area according to chip design requirements, and the first layout figure includes a plurality of first plane shapes. The first layout drawing operation may include drawing a second plane shape representing the gap between the packaged devices in a corresponding area according to chip design requirements, and the first layout figure includes a plurality of second plane shapes. The first layout drawing operation may also include drawing a first plane shape representing the packaged device and a second plane shape representing the gap between the packaged devices in a corresponding area according to chip design requirements, and the first layout figure includes a plurality of first plane shapes and a plurality of second plane shapes. The first layout drawing operation may also include drawing a layout pattern of the packaged device on the packaged substrate according to chip design requirements and drawing a layout pattern of the packaged substrate according to preset layout requirements, and the first layout figure includes a layout pattern of the packaged substrate. The preset panel area may be at least a partial area on the panel, or obtained by dividing the panel. For example, the preset panel area may be a quarter area of ​​the panel.

[0072] In one embodiment, a user draws a first planar shape on the package planning canvas according to chip design requirements, and the first layout graphic displayed in the package planning canvas 202 is composed of the first planar shape representing the packaged device. Figure 2b, rectangle 102, rectangle 104 and rectangle 110 are drawn on the package planning canvas 202. Rectangle 102 represents the placement area of ​​the bare chip, rectangle 104 represents the placement area of ​​the electronic components, and rectangle 110 represents the placement area of ​​the metal cover or the reinforcement foot. It should be noted that since rectangle 102, rectangle 104 and rectangle 110 are drawn according to the chip design requirements, and since the relative positions between these rectangles are fixed, the gaps between the rectangles do not need to be drawn. It is understandable that the user can also draw a second planar shape on the package planning canvas according to the chip design requirements to represent the placement area of ​​the gaps between the packaged devices on the package substrate. That is, the first layout figure displayed in the package planning canvas includes a second planar shape representing the gaps between the packaged devices.

[0073] In another embodiment, a user draws a first plane shape and a second plane shape on a package planning canvas according to chip design requirements, so that the package planning canvas displays a first plane shape representing a packaged device and a second plane shape representing a gap between packaged devices, that is, the first layout graphic includes the first plane shape and the second plane shape. For example, please continue to refer to Figure 1a and Figure 1b , rectangle 102 representing the bare die area, rectangle 104 representing the electronic component area, rectangle 106 representing the gap area between the bare die and the electronic components, rectangle 108 representing the gap area between the electronic components and the metal cover or reinforcement feet, and rectangle 110 representing the area of ​​the metal cover or reinforcement feet.

[0074] In another embodiment, the layout pattern of the packaged device on the package substrate is determined by drawing the first planar shape and the second planar shape. And the first layout graphic is displayed by simulating the layout of the layout pattern on the preset panel area. The first layout graphic is composed of the layout pattern of the package substrate. Exemplarily, the layout pattern of the packaged device on the package substrate is determined by drawing the first planar shape and the second planar shape. After determining the layout pattern on the package substrate, the layout pattern on the package substrate is simulated and arranged, and the layout pattern of the package substrate is displayed on the package planning canvas. Alternatively, after determining the layout pattern on the package substrate, the layout pattern of the package substrate is displayed on the package planning canvas by simulating the arrangement of the boundary box of the layout pattern.

[0075] Furthermore, when a first layout drawing operation is received on the package planning canvas, a first layout graphic of the package substrate is displayed. Since the first layout drawing operation is issued according to the chip design requirements, the actual size of the packaged device is reflected in the first layout graphic, so that the size of the packaged substrate can be planned according to the drawing size of the packaged substrate in the first layout graphic. Specifically, the first layout graphic can be drawn in the same size or in proportion, that is, the actual size of the packaged device can be displayed in the first layout graphic in the same size or in proportion.

[0076] It is understandable that in this embodiment, the placement of the packaged device on the package substrate or the layout of the package substrate on the preset panel area is intuitively displayed through the first layout graphic. The displayed placement or layout is regarded as prompt information to prompt the adjustment and optimization direction of the package substrate, which can optimize the package substrate in a targeted manner, thereby reducing the blindness of the optimization of the package substrate, reducing the number of repeated adjustments to the size of the package substrate, and improving design efficiency.

[0077] It should be noted that if traditional packaging technology is used, the packaged devices may include bare chips, electronic components, metal covers or reinforcement feet. The gaps between packaged devices may be the spacing areas between bare chips, the spacing areas between bare chips and electronic components, and the spacing areas between electronic components and metal covers or reinforcement feet. If advanced packaging technology is used, the packaged devices include interposers, electronic components, metal covers or reinforcement feet. The gaps between packaged devices may be the spacing areas between interposers, the spacing areas between interposers and electronic components, and the spacing areas between electronic components and metal covers or reinforcement feet.

[0078] The embodiment of the present application provides a method for optimizing the size of a packaging substrate. Through this optimization method, the packaging device can be drawn on the packaging planning canvas to obtain a layout graphic displayed in a two-dimensional tiled manner, which can quickly and intuitively plan the size of the packaging substrate. The layout graphic represents the placement of the packaging device on the packaging substrate or on the preset panel area according to the chip design requirements, and prompts the adjustment and optimization direction of the packaging substrate. According to the prompted adjustment and optimization direction, unnecessary repeated designs can be reduced to a certain extent, and design efficiency can be improved. Furthermore, since the layout graphic can prompt the adjustment and optimization direction of the packaging substrate, the number of substrates that can be manufactured by the panel can be increased by optimizing the size of the packaging substrate, and the panel utilization rate can be improved.

[0079] In some embodiments, the first layout pattern includes a plurality of rectangles arranged according to chip design requirements and a boundary box surrounding the plurality of rectangles. The rectangle is used to represent the placement area of ​​the packaged device on the package substrate and / or to represent the placement area of ​​the gap between the packaged devices on the package substrate.

[0080] The rectangle may be a rectangle or a square. Specifically, a rectangle drawing operation is issued on the package planning canvas, and in response to the rectangle drawing operation, multiple rectangles drawn are arranged on the package planning canvas according to the chip design requirements. The rectangle may be used to represent the placement area of ​​the packaged device on the package substrate, and / or the rectangle may also be used to represent the placement area of ​​the gap between the packaged devices on the package substrate.

[0081] After the rectangle drawing operation is completed, the package planning canvas displays the placement of the packaged device on the package substrate, a bounding box drawing operation is issued on the package planning canvas, and in response to the bounding box drawing operation, a bounding box surrounding the plurality of rectangles is displayed on the package planning canvas. Therefore, after the first layout drawing operation is completed, the first layout graphic displayed in a two-dimensional tiled form in the package planning canvas includes a plurality of rectangles arranged according to the chip design requirements and a bounding box surrounding the plurality of rectangles.

[0082] For example, Figure 3a A schematic diagram of a multi-die package substrate is shown. Figure 3a ,A package substrate can be placed with multiple dies of the same or different shapes. The package substrate is arranged with die 302, die 304, die 306, die 308, electronic components 310 and metal cover or reinforcement foot 312. Rectangle 314 is the gap between the dies. Rectangle 316 is the gap between the die and the electronic components. Rectangle 318 is the gap between the electronic components and the metal cover or reinforcement foot. It can be understood that there can also be rectangles between the die and the metal cover or reinforcement foot to represent the gap between the two.

[0083] For example, Figure 3b The figure shows a schematic diagram of placing an interposer on a package substrate. An interposer 320, an electronic component 310 and a metal cover or reinforcement foot 312 are arranged on the package substrate. Rectangle 322 is the gap between the interposer and the electronic component. Rectangle 324 is the gap between the electronic component and the metal cover or reinforcement foot. It can be understood that there may also be a rectangle between the bare die and the metal cover or reinforcement foot to represent the gap between the two.

[0084] For example, Figure 3c The schematic diagram of placing multiple interposers on a package substrate is shown. Multiple interposers 320, electronic components 310, and metal covers or reinforcement feet 312 are arranged on the package substrate. Rectangle 322 is the gap between the interposer and the electronic components. Rectangle 326 is the gap between the interposers 320. Rectangle 324 is the gap between the electronic components and the metal covers or reinforcement feet. It can be understood that there may also be rectangles between the bare die and the metal covers or reinforcement feet to represent the gap between the two.

[0085] In the embodiment of the present application, a rectangle is used to represent the packaged devices on the packaged substrate and / or the gaps between the packaged devices, so as to display the placement of the packaged devices on the packaged substrate in an intuitive and quick manner. Furthermore, based on the first layout graph, the design and work risks can be pre-evaluated to save development costs.

[0086] In some embodiments, the first layout pattern includes a first layout pattern. The first layout pattern is used to represent the layout of the package substrate in a preset panel area.

[0087] Specifically, a simulated layout operation is performed on the package substrate on the package planning canvas, and a first layout pattern of the package substrate is displayed on the package planning canvas. The first layout pattern represents the layout of the package substrate on the preset panel area.

[0088] In the embodiment of the present application, the layout situation on the preset panel area is intuitively displayed through the first layout pattern, which can prompt the adjustment and optimization direction of the package substrate. Based on the adjustment and optimization direction, the pertinence of the package substrate optimization is improved, and the design efficiency is improved.

[0089] In some embodiments, the size of the package substrate is planned according to the boundary size of the first layout pattern.

[0090] Specifically, the first layout pattern may be composed of a plurality of rectangles arranged according to the chip design requirements. The length of the plurality of rectangles in the X direction is determined as the length of the first layout pattern, and the height of the plurality of rectangles in the Y direction is determined as the height of the first layout pattern. The basic size of the package is planned based on the length and width of the first layout pattern. It should be noted that the area of ​​the package substrate can be planned based on the size of the bounding box of the first layout pattern.

[0091] It is understandable that, in addition to the multiple rectangles arranged according to chip design requirements, the first layout figure may also include a boundary box surrounding the multiple rectangles, and the size of the package substrate is planned based on the size of the boundary box of the first layout figure.

[0092] In the embodiment of the present application, the size of the packaging substrate is planned by the boundary size of the first layout graphic, which provides a data basis for determining the panel utilization, thereby being able to judge whether the current packaging substrate size meets the preset layout requirements, and then determine whether to stop debugging and optimizing the packaging substrate.

[0093] In some embodiments, if the package substrate needs to be debugged and optimized, the package device is adjusted according to the adjustment optimization direction, and accordingly, the size of the package substrate and the layout result on the preset panel area are adjusted. The optimization method of the package substrate size may also include: in response to the second layout drawing operation for the adjusted package device, displaying the second layout graphic of the adjusted package substrate in a two-dimensional tiling manner. The panel utilization corresponding to the second layout graphic is better than the panel utilization corresponding to the first layout graphic.

[0094] Specifically, if the first layout figure and the second layout figure are used to characterize the placement of the packaged device on the packaged substrate, respectively, the adjustment is performed according to the adjustment optimization direction suggested by the first layout figure. First, a rectangle drawing operation of the adjusted packaged device is received, and in response to the rectangle drawing operation of the adjusted packaged device, the rectangle of the adjusted packaged device on the adjusted packaged substrate is displayed in a two-dimensional tiled manner. Secondly, a boundary drawing operation of the rectangle of the adjusted packaged device is received, that is, for the boundary drawing operation of the adjusted packaged substrate, in response to the boundary drawing operation of the rectangle of the adjusted packaged device, the boundary box of the adjusted packaged substrate is displayed, that is, the second layout figure of the adjusted packaged substrate is displayed in a two-dimensional tiled manner. The second layout figure includes a rectangle of the adjusted packaged device and a boundary box of the adjusted packaged substrate. The area of ​​the packaged substrate is evaluated using the boundary box of the adjusted packaged substrate, and the panel utilization corresponding to the second layout figure is predicted based on the evaluated packaged substrate area and the area of ​​the preset panel area. Since the area of ​​the packaged substrate after adjustment is better than the area of ​​the packaged substrate before adjustment, accordingly, the panel utilization corresponding to the second layout figure is better than the panel utilization corresponding to the first layout figure.

[0095] If the first layout graphic and the second layout graphic are used to characterize the layout of the package substrate on the preset panel area, respectively, the adjustment is performed according to the adjustment optimization direction suggested by the first layout graphic. First, a rectangle drawing operation of the adjusted packaged device is received, and in response to the rectangle drawing operation of the adjusted packaged device, the rectangle of the adjusted packaged device on the adjusted packaged substrate is displayed. Secondly, a boundary drawing operation of the rectangle of the adjusted packaged device is received, that is, a boundary drawing operation for the adjusted packaged substrate, and in response to the boundary drawing operation of the rectangle of the adjusted packaged device, a boundary box of the adjusted packaged substrate is displayed. Finally, in response to the simulated layout operation for the boundary box of the adjusted packaged substrate, the layout pattern of the adjusted packaged substrate is displayed in a two-dimensional tiling manner, that is, the second layout graphic of the adjusted packaged substrate is displayed in a two-dimensional tiling manner. The second layout graphic includes the layout pattern of the adjusted packaged substrate. The layout pattern of the adjusted packaged substrate is used to evaluate the layout quantity of the packaged substrate. The panel utilization corresponding to the second layout graphic is predicted based on the layout quantity of the adjusted packaged substrate. Since the number of layouts using the adjusted packaging substrate is greater than the number of layouts using the adjusted packaging substrate, accordingly, the panel utilization corresponding to the second layout pattern is better than the panel utilization corresponding to the first layout pattern.

[0096] In some embodiments, the panel utilization corresponding to the first layout pattern is determined based on the number of layouts corresponding to the first layout pattern or the utilization rate of a preset panel area. The panel utilization corresponding to the second layout pattern is determined based on the number of layouts corresponding to the second layout pattern or the utilization rate of a preset panel area.

[0097] In the embodiment of the present application, the size of the packaging substrate is adjusted and optimized according to the adjustment optimization direction suggested by the first layout figure to obtain a second layout figure, and the panel utilization corresponding to the second layout figure is better than the panel utilization corresponding to the first layout figure. It can be seen that adjusting and optimizing according to the suggested adjustment optimization direction can improve the utilization rate of the panel, reduce the waste of panel raw materials, and improve the production capacity and efficiency of integrated circuit manufacturing.

[0098] In some embodiments, after multiple debugging and optimization of the packaging substrate, the method may further include: determining a target layout result that meets preset layout requirements in the layout results corresponding to each debugging and optimization; wherein the size of the packaging substrate corresponding to the target layout result is used to carry out subsequent packaging design.

[0099] Among them, the preset layout requirements can be determined by comprehensively considering the design requirements, packaging plant process requirements, reliability requirements, mass production requirements, cost requirements and other aspects. Among them, the design requirements are to be able to complete signal fan-out, power supply and other purposes. The packaging plant process requirements are to meet the purpose of bare chip mounting. The reliability requirements need to meet the purpose of area control. The mass production requirements need to meet the purpose of process feasibility and mass production experience. The cost requirements need to meet the purpose of opening the maximum number of substrates, having a mold opening size, and reasonable utilization.

[0100] Specifically, in response to the first layout drawing operation, the first layout graphic is displayed. Under the prompt of the first layout graphic, the packaging substrate is adjusted for the first time, and the second layout drawing operation for the packaging device is performed to obtain the second layout graphic after the first adjustment. Under the prompt of the second layout graphic, the packaging substrate is adjusted for the second time, and the third layout drawing operation for the packaging device is performed to obtain the third layout graphic after the second adjustment. And so on, the packaging substrate is debugged and optimized according to the layout graphic after the last adjustment to obtain the corresponding layout graphic.

[0101] In this embodiment, each debugging optimization generates a layout graphic, and the typesetting result corresponding to each debugging optimization is determined according to each layout graphic. For example, the target typesetting result that meets the preset typesetting requirements is determined in the typesetting result corresponding to each debugging optimization according to the typesetting quantity corresponding to the layout graphic. Exemplarily, the preset typesetting requirement is to require the maximum typesetting quantity, then the package substrate size in the layout graphic corresponding to the maximum typesetting quantity is used as a reference for subsequent package design. For another example, the target typesetting result that meets the preset typesetting requirements is determined in the typesetting result corresponding to each debugging optimization according to the panel utilization corresponding to the layout graphic. Exemplarily, the preset typesetting requirement is to require the maximum panel utilization, then the package substrate size in the layout graphic corresponding to the maximum panel utilization is used as a reference for subsequent package design.

[0102] It should be noted that after determining the size of the packaging substrate corresponding to the target layout result, even if the chip design is changed later, the layout drawing operation for the packaging device on the packaging substrate in the embodiment of the present application can be used to intuitively and quickly display the changed layout graphics of the packaging substrate. Compare the size of the packaging substrate corresponding to the changed layout graphics with the size of the packaging substrate corresponding to the target layout result. If the former is less than or equal to the latter, no layout change is required. If the former is larger than the latter, the layout change can be quickly made based on the changed layout graphics. It is understandable that if the former is smaller than the latter, in order to further improve the panel utilization, the layout change can also be quickly made based on the changed layout graphics.

[0103] In the embodiment of the present application, a target layout result that meets a preset layout requirement is determined in the layout result corresponding to each debugging optimization, thereby ensuring panel utilization and increasing the number of substrates that can be manufactured by the panel.

[0104] In some embodiments, adjusting the optimization direction includes at least one of adjusting the die area, adjusting the die arrangement, adjusting the packaging process rules, and adjusting the substrate arrangement.

[0105] Specifically, adjusting the die area includes at least one of reducing the die size and changing the die aspect ratio. Adjusting the die arrangement includes at least one of changing the chip architecture and changing the die spacing. Adjusting the packaging process rules includes at least one of optimizing the packaging design and improving the packaging process. Adjusting the substrate arrangement includes at least one of changing the arrangement of the packaging substrate in the preset panel area and changing the size of the packaging substrate.

[0106] In this embodiment, the die area is adjusted according to the adjustment optimization direction suggested by the first layout figure, for example, the die area is optimized. Exemplarily, if the die area is large, the die area can be reduced by floorplan or logic function optimization. The die area can also be optimized according to the adjustment optimization direction suggested by the first layout figure to optimize the length-to-width ratio of the die, reducing the probability of the die being too long or too wide.

[0107] In this embodiment, the die arrangement is adjusted according to the adjustment optimization direction suggested by the first layout graph, such as the arrangement adjustment of multiple dies. Figure 4a and Figure 4b , taking traditional packaging technology as an example, changing the layout of multiple dies, Figure 4a The four dies in the array are arranged in two rows (two dies in each row). After the arrangement is optimized, Figure 4b The four dies are arranged in three rows (one die on the first row, two dies on the second row, and one die on the third row). For example, the arrangement of multiple dies can be adjusted by changing the die spacing, or by changing the chip architecture. For example, see Figure 4c and Figure 4d , taking advanced packaging technology as an example, changing the layout of multiple interposers. Figure 4c There are four interposers placed on the package substrate in the package, and the chip architecture is changed to Figure 4c The die arrangement in is adjusted to obtain Figure 4d The arrangement of two interposers placed on the package substrate shown in FIG.

[0108] In this embodiment, the package design is optimized according to the adjustment and optimization direction suggested by the first layout pattern, such as optimizing at least one of the capacitor area and the compressed wiring space. Alternatively, the package process is improved according to the adjustment and optimization direction suggested by the first layout pattern, such as at least one of the die spacing, device spacing, and leadfoot width.

[0109] In this embodiment, the arrangement of the substrates is adjusted by way of example. Figure 5a , the length of the panel is L, the width is W, and the panel is divided into 4 areas of the same shape, which are recorded as preset panel areas. The package substrate is arranged on the preset panel area. Among them, the length and width of the preset panel area are recorded as D, and the spacing between the preset panel areas is recorded as W. The distance from the preset panel area to the panel boundary is recorded as WE.

[0110] See also Figure 5b In the process of drawing the first layout pattern, the size of the package substrate P1 is recorded as the initial width W1 and the initial length H1. The spacing between the package substrates P1 and the package substrates P1 is recorded as M. The area S1 of the package substrate P1 in the first layout pattern is the product of the initial width W1 and the initial length H1. The package substrate P1 is arranged in the preset panel area, and the remaining area in the preset panel area is obtained, which can prompt the debugging optimization direction for the first layout pattern.

[0111] See also Figure 5c , the package substrate P1 is adjusted according to the debugging optimization direction prompted by the first layout figure, and in the process of drawing the second layout figure, the adjusted package substrate P2 is obtained, and the spacing between the package substrates P2 and the package substrates P2 is recorded as M. The size of the package substrate P2 is recorded as the initial width W2 and the initial length H2. The area S2 of the package substrate P2 in the second layout figure is the product of the initial width W2 and the initial length H2.

[0112] See also Figure 5d , the package substrate P2 is adjusted according to the debugging optimization direction prompted by the second layout figure, and in the process of drawing the third layout figure, the adjusted package substrate P3 is obtained, and the spacing between the package substrates P3 and the package substrates P3 is recorded as M. The size of the package substrate P3 is recorded as the initial width W3 and the initial length H3. The area S3 of the package substrate P3 in the third layout figure is the product of the initial width W3 and the initial length H3.

[0113] For example, after two optimizations, Figure 5d From the layout pattern of the packaging substrate shown, it can be seen that the size of the packaging substrate P3 can better utilize the raw materials of the preset panel area and reduce raw material waste.

[0114] It should be noted that, in this example, the packaging substrate P1 can be adjusted while maintaining S1 unchanged to obtain the packaging substrate P2, and the area S2 of the packaging substrate P2 is equal to the area S1 of the packaging substrate P1. The packaging substrate P2 can be adjusted while maintaining S1 unchanged to obtain the packaging substrate P3, and the area S3 of the packaging substrate P3 is equal to the area S1 of the packaging substrate P1. Alternatively, the packaging substrate P1 is adjusted, and the area S2 of the packaging substrate P2 can be smaller than the area S1 of the packaging substrate P1. The packaging substrate P2 is adjusted, and the area S3 of the packaging substrate P3 can be smaller than the area S2 of the packaging substrate P2.

[0115] The present application also provides a device for optimizing the size of a package substrate. Figure 6 , the package substrate size optimization device 600 may include:

[0116] The planning canvas providing module 610 is used to provide a package planning canvas in the display screen of the terminal;

[0117] The drawing operation receiving module 610 is used to receive a first layout drawing operation for a packaged device on the package substrate; wherein the packaged device is a component inside the chip for realizing chip functions and ensuring chip performance;

[0118] The layout graphic display module 630 is used to respond to the first layout drawing operation and display the first layout graphic of the packaging substrate in a two-dimensional tiled form in the packaging planning canvas to plan the size of the packaging substrate; wherein the first layout graphic is used to represent the placement of the packaging device arranged according to the chip design requirements on the packaging substrate or on a preset panel area, and prompt the adjustment optimization direction of the packaging substrate.

[0119] In some embodiments, the device may also include a graphic adjustment drawing module for displaying a second layout graphic of the adjusted packaging substrate in a two-dimensional tiled manner in response to a second layout drawing operation for the adjusted packaging device; wherein the panel utilization corresponding to the second layout graphic is better than the panel utilization corresponding to the first layout graphic.

[0120] In some embodiments, the device may also include a target layout determination module, which is used to determine a target layout graphic that meets preset layout requirements in the layout graphic corresponding to each debugging and optimization after multiple debugging and optimization of the packaging substrate; wherein the size of the packaging substrate corresponding to the target layout graphic is used to carry out subsequent packaging design.

[0121] The further functional description of each of the above modules is the same as that of the above corresponding embodiments and will not be repeated here.

[0122] The packaging substrate size optimization device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0123] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0124] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0125] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0126] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0127] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0128] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means, and FIG. X takes the bus connection as an example.

[0129] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0130] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0131] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0132] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0133] The systems, devices or modules described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0134] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0135] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0136] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0137] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0138] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0139] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0140] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0141] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0142] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for optimizing the size of a packaging substrate, characterized in that: The method comprises: Providing a package planning canvas in a display screen of a terminal; Receiving a first layout drawing operation for a packaged device on the packaged substrate; wherein the packaged device is a component inside a chip for realizing chip functions and ensuring chip performance; In response to the first layout drawing operation, a first layout graphic of the packaging substrate is displayed in a two-dimensional tiled form in the packaging planning canvas to plan the size of the packaging substrate; wherein the first layout graphic is used to characterize the placement of the packaging devices arranged according to the chip design requirements on the packaging substrate or on a preset panel area, and prompt the adjustment and optimization direction of the packaging substrate.

2. The method according to claim 1, characterized in that The first layout pattern includes a plurality of rectangles arranged according to the chip design requirements, and a boundary box surrounding the plurality of rectangles; The rectangle is used to represent the placement area of ​​the packaged device on the packaged substrate and / or to represent the placement area of ​​the gaps between the packaged devices on the packaged substrate.

3. The method according to claim 1, characterized in that The size of the packaging substrate is planned according to the boundary size of the first layout pattern.

4. The method according to claim 1, characterized in that The first layout pattern includes a first layout pattern; The first layout pattern is used to represent the layout of the packaging substrate in a preset panel area.

5. The method according to claim 1, characterized in that The method further comprises: In response to a second layout drawing operation for the adjusted packaged device, a second layout graphic of the adjusted packaged substrate is displayed in a two-dimensional tiling manner; wherein the panel utilization corresponding to the second layout graphic is better than the panel utilization corresponding to the first layout graphic.

6. The method according to claim 5, characterized in that The panel utilization corresponding to the first layout graphic is determined based on the number of layouts corresponding to the first layout graphic or the utilization rate of the preset panel area; The panel utilization corresponding to the second layout graphic is determined based on the number of layouts corresponding to the second layout graphic or the utilization rate of the preset panel area.

7. The method according to claim 5, characterized in that After the packaging substrate is debugged and optimized multiple times, the method further includes: A target layout graphic that meets the preset layout requirements is determined in the layout graphic corresponding to each debugging optimization; wherein the size of the packaging substrate corresponding to the target layout graphic is used to carry out subsequent packaging design.

8. The method according to any one of claims 1 to 7, characterized in that: The adjustment and optimization direction includes at least one of adjusting the die area, adjusting the die arrangement, adjusting the packaging process rules, and adjusting the substrate arrangement.

9. The method according to any one of claims 1 to 7, characterized in that: In the first layout diagram, the actual size of the packaged device is displayed in the same size or in equal proportion.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 9 by executing the computer instructions.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 9.

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