RISC-V-based ecg classification detection convolutional neural network coprocessor

Abstract

The application discloses an ECG classification detection convolutional neural network coprocessor based on RISC-V, and belongs to the technical field of calculation, reckoning or counting. The core is the design of a RISC-V architecture accelerator platform for ECG classification detection convolution. Meanwhile, the application relates to the design of a coprocessor instruction system based on NICE, so that data exchange for ECG classification detection is better. The design of the RISC-V architecture accelerator platform includes the design optimization of various sub-modules, such as a state processing unit, a memory controller, a weight cache, an input / output buffer, an input register, an output register, a PE array, activation and pooling. The application successfully realizes a one-dimensional CNN efficient processing structure for ECG detection signal characteristics, and combines a RISC-V extension instruction for ECG data convolution, so that the execution efficiency of the convolutional neural network coprocessor for ECG classification detection is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of coprocessors, in particular to an ECG classification detection convolutional neural network coprocessor based on RISC-V, and belongs to the technical field of calculation, estimation or counting. BACKGROUND

[0002] Arrhythmia is a major disease that threatens the health and life of the people in China. Investigations show that about 544,000 people die of sudden death caused by arrhythmia every year in China. Therefore, how to correctly use electrocardiogram (ECG) for clinical diagnosis of arrhythmia is of great significance.

[0003] Convolutional Neural Networks (CNN) are widely used in classification tasks in various fields such as image recognition and speech recognition due to their extensive learning ability and stability. CNN has many advantages for recognition tasks, but deploying CNN models to wearable devices with limited computing resources and memory space is still limited. Given the good and stable classification characteristics of CNN, designing a one-dimensional convolutional neural network system specifically for ECG classification detection has important practical significance and wide application prospects.

[0004] However, CNN also has some inherent defects. First, the conventional operation generally uses 32-bit floating-point numbers, so if there are a large number of floating-point operations, there will be a lot of power consumption; second, saving the CNN model requires a large amount of memory space, and neural network models generally occupy a large space. These inherent defects make CNN have the defect of high power consumption when used for ECG classification. In order to overcome the inherent defects of CNN, the existing technology proposes an accelerator for ECG classification detection. The existing accelerator for ECG classification detection still has deficiencies in computing efficiency, adaptability, etc.; the existing accelerator for ECG classification detection generally uses a general CNN accelerator architecture, so the efficiency is low when processing one-dimensional convolution, resulting in high power consumption and large delay; the general CNN accelerator architecture cannot well adapt to the characteristics of ECG signals, and the classification accuracy and stability are insufficient; the integration of the accelerator for ECG classification detection with other components of the system is low, resulting in the overall performance cannot be fully utilized.

[0005] Therefore, the present application aims to propose an ECG classification detection convolutional neural network coprocessor based on RISC-V to overcome the defects of the accelerator for ECG classification detection. SUMMARY

[0006] The application aims to solve the problems of low computing efficiency, poor adaptability and low system integration of existing ECG classification detection accelerators.

[0007] The application achieves the above-mentioned application purposes by adopting the following technical solutions.

[0008] The RISC-V-based ECG classification detection convolutional neural network coprocessor comprises a state processing unit, a memory controller, a weight cache, an input / output buffer, an input register, a PE array, an output register, an activation module and a pooling module; the state processing unit is used to control forward inference of the coprocessor and convolution calculation in the forward inference process; the memory controller receives ECG signals, weights and network parameters from a host processor, calculates storage addresses of the ECG signals, the weights and the network parameters, and enables the weight cache, the input / output buffer, the input register, the PE array, the output register, the activation module and the pooling module; the weight cache is used to cache weights of each layer of the neural network; the input / output buffer is used to cache ECG signals from the host processor and ECG input feature maps completed by the PE array after each layer of convolution operation; the input register is used to cache the ECG input feature maps completed by the PE array after each layer of convolution operation; the PE array is used to pulse transfer the ECG input feature maps of the current layer of convolution operation, read the weights of the current layer from the weight cache, and output the convolution result of the current layer; the output register is used to cache the convolution result of the current layer output by the PE array; the activation module is used to perform activation operation on the convolution result of the current layer output by the PE array; and the pooling module is used to perform pooling operation on the activation data of the convolution result of the current layer, and obtain the ECG input feature maps completed by the PE array after the next layer of convolution operation.

[0009] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the state processing unit comprises a main state machine and a calculation state machine; the main state machine is used to control the coprocessor to work in a loop process comprising an idle state, a parameter acquisition state and a forward inference state; and the calculation state machine is used to control the PE array to complete one layer of convolution operation when the coprocessor works in the forward inference state.

[0010] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the memory controller receives the ECG signals, the weights and the network parameters from the host processor through the NICE protocol.

[0011] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the memory controller receives the ECG signal, the weight and the network parameter from the host processor through the NICE protocol, specifically: the ECG signal, the weight and the network parameter from the host processor are loaded into the row data buffer through the lbuf instruction; the data in the row data buffer is accumulated through the rowsum instruction, and the accumulated value is returned to the host processor; the data in the row data buffer is stored to the memory of the host processor through the sbuf instruction.

[0012] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the ECG signal, the weight and the network parameter from the host processor are transmitted through the control of the maximum bit width of the two registers, and the signal of the data transmission of the two registers is controlled by calling the custom instruction set.

[0013] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the first column of the PE array receives the ECG signal from the host processor or the ECG input feature map of the current layer convolution operation, the data received by the first column of the PE array is input to each column of the PE array in turn, the first row of the PE array receives the weight of the current layer, each column of the PE array shares the weight of the current layer received by the first row of each column, and the calculation result of each column of the PE array is transmitted to the first row output.

[0014] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the weight cache is an on-chip cache containing 8 banks; the input / output buffer is an on-chip cache composed of 2 SRAMs, each SRAM contains 8 banks.

[0015] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the input register inputs the ECG input feature map data of each layer convolution operation of the PE array for input multiplexing; the output register outputs the current layer convolution result of the PE array for output multiplexing including writing, shifting and filling.

[0016] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the activation module performs truncation processing on the current layer convolution result output by the PE array.

[0017] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the pooling module performs maximum pooling processing on the activation data of the current layer convolution result.

[0018] The application has the following beneficial effects:

[0019] (1) The application combines the RISC-V architecture accelerator platform with the NICE custom instruction system, designs a one-dimensional CNN efficient processing structure for ECG detection signal characteristics, forms a complete coprocessor and system design, and the system not only supports efficient convolution calculation, but also can process complex ECG classification tasks, has strong practicability and wide application prospect.

[0020] (2) The application designs a pulsatile array processing unit for ECG data convolution, reduces the memory bottleneck and improves the data throughput, and improves the detection accuracy and processing speed. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The application is proposed Hardware architecture diagram of an ECG classification detection convolutional neural network coprocessor .

[0022] Figure 2 The application is proposed In an ECG classification detection convolutional neural network coprocessor Schematic diagram of PE array loading data. DETAILED DESCRIPTION

[0023] The following detailed description of the RISC-V-based ECG classification detection convolutional neural network coprocessor of the application is made with reference to the accompanying drawings and specific embodiments.

[0024] Embodiment 1: as shown in the accompanying drawings Figure 1 The embodiment provides a RISC-V-based ECG classification detection convolutional neural network coprocessor, which is realized by designing a RISC-V architecture accelerator platform for ECG classification detection convolution. The accelerator platform integrates a specially designed RISC-V extension instruction set, so that the one-dimensional convolutional neural network can be efficiently executed at the hardware level. The RISC-V extension instruction set provides hardware support for key operations such as convolution, activation function, and pooling operation, so that these operations can be executed with low delay and high parallelism in the PE array. The design of the RISC-V architecture accelerator platform for ECG classification detection convolution includes optimization of the state processing unit, the memory controller, the weight cache, the input / output buffer, the input register, the output register, the PE array, the activation module, and the pooling module.

[0025] The state processing unit is used for controlling the working state of the accelerator, which is composed of two state machines, i.e., a main state machine and a calculation state machine; wherein the calculation state machine is controlled by the main state machine, and the control of the convolution calculation process is realized; the main state machine controls the forward inference of the accelerator as a whole, and when entering the state of CONV_CAL, the calculation state is entered to execute the convolution calculation and the activation pooling operation. The state change process of the main state machine is as follows: the initial state is IDLE idle state, and the parameter acquisition is waited; after the parameter address is acquired, the ECG signal is waited to be loaded into the input / output buffer through the memory controller, and the weight data of all network layers is saved to the weight cache. After the preparation work is completed, the accelerator starts the inference calculation, the calculation state machine is started, the accelerator is controlled to perform the data reading and writing and the convolution calculation of the current layer, during which the main state machine judges whether the current layer is calculated, if the current layer is calculated and is not the last layer, the inference of the next layer is continued to be looped until the ECG detection classification result is output. The calculation state machine represents the calculation process of each layer, and since a feature data graph needs multiple batches of convolution calculation, the state machine loops multiple times of convolution calculation in the OR_CAL state until the whole convolution layer completes the calculation. The state transition process of the calculation state machine is as follows: the default is IDLE idle state, then the state of loading weight is entered, and whether the weight is loaded is judged; after the weight is loaded, the calculation state is entered, otherwise the OR_FT_WT state is continued; in the convolution calculation state, whether the current layer convolution calculation is completed is constantly judged, if yes, the calculation end state is entered, otherwise the OR_CAL state is continued, after the current layer convolution calculation is completed, the IDLE state is returned and the next cycle is waited.

[0026] The memory controller receives the ECG signal from the CPU through the NICE interface, controls the reading and transmission of different data including feature map, current layer weight and network parameter to the input register, PE array and weight cache, and is also responsible for the enablement of each module. The specific functions include: a, reading SPI input ECG data; b, reading network layer configuration parameters; c, reading network layer weight; d, calculating the input / output buffer address for writing; e, calculating the input / output buffer address for writing to the input register.

[0027] The on-chip cache includes the weight cache and the input / output buffer, which are mainly used for storing the weight data and feature map data which occupy the main part, and the weight cache and the input / output buffer are divided into 8 banks for parallel output of data to improve the efficiency, and the details are as follows:

[0028] (a) The weight buffer is composed of 8 banks, each bank has a size of 2048 byte, 8 input / output ports are used to receive and output weight values, in a certain order, for example, the systolic array outputs in turn and the difference between adjacent banks is one clock cycle, and the output weight values are calculated in the PE array;

[0029] (b) The input / output buffer is composed of 2 pieces of 4096*8bit SRAM, each piece has 8 banks, and 8 input / output ports provided by 8 banks are used to receive the original ECG signal and output the convolution result of each layer of the register output, and output the data in the SRAM to the input register, and the two pieces of SRAM are used for ping-pong operation to improve the running efficiency.

[0030] The input / output buffer involves data input and output, wherein the data input is generated by the Pooling2IOB module, Bm(8) data are written at a time according to the map format each time, and only the Pooling2IOB module controls the writing address, which is generated by the memory controller. The data input sequence is as follows: the first part of input Map0, the first part of input Map1, the first part of input Map2, and so on until the first part of input MapN; then start inputting the second part of data of the Map; repeat the above operation until all the input Map writing is completed, and the data is output to the input register, Bm data are input at a time according to the map format each time. The data output sequence is as follows: (1) the first part of output InMap0, the first part of output InMap1, the first part of output InMap2, and so on until the first part of InMapN is output; (2) the second part of InMap0-M is output in turn, and the operation is repeated ceil(Hu / Bm) times; (3) repeat the operation; (4) until the transmission of all parts of InMap is completed.

[0031] The input register is used to buffer all the input data used by the systolic array in the next calculation, and plays a role in data input multiplexing. At the same time, in the case of convolution kernel size K>convolution kernel step S, the use of the input register can avoid repeated access to on-chip cache, and the register stack of the input register can also realize parallel output, so as to meet the subsequent PE array calculation process. According to the number of data Hu required by the PE array for one calculation, the data is extracted from the input buffer.

[0032] Wherein, Hu is the number of input data involved in a calculation of the pulsating array, related to the convolution kernel size K of the current layer, the convolution kernel step S and the feature map input port number R of the PE array, and the size of the PE array is R*C=16*8, the calculation formula of Hu is as formula (1)

[0033] (1)

[0034] According to the neural network parameters in Table 1, the size of each layer of convolution operation Hu can be obtained, so as to determine the size of the register stack in the input register and improve the resource utilization rate, and finally determine the size of the input register, as shown in Table 2.

[0035]

[0036] Table 1 neural network parameter table

[0037]

[0038] Table 2 input regfile size of different network layers

[0039] The output register makes the convolution output of each layer orderly input to the pooling module, and plays the role of output multiplexing. According to the first layer POOL_K=7 and POOL_S=2, the output register is explained as follows,

[0040] There are mainly three steps, process 1 is mainly data writing, because the maximum pooling size is 7, so the register stack size of the output register is set to 7, and the output data of the PE array is arranged according to the maximum pooling bit width of 7, 7*8bit data is stored each time, and once 7 data is written, it is output, and the remaining bits are filled with zero; Process 2 is a shift, after the output of process 1, the data needs to be shifted right by 2 units to provide space for the following data, at this time the data is not filled, so no output is performed; Process 3 is filling, the output value of the PE array is continuously written in the empty space after shifting, and once 7 data is written, it is output.

[0041] The PE array contains 128 PE units in total, arranged in a 16-row 8-column rectangle, the first column of PE receives 16-bit parallel ECG signals or input data and pulsates into the array from left to right; The weight data is received by the first row of PE, and the weight data does not pulsate, but is shared by the same column of PE units, as shown by the green line, and the weight data stream of each column is received at an interval of one clock cycle, as shown by the blue line; The final calculation result data stream is transmitted from bottom to top to the first row of output, and each column of output is at an interval of one clock cycle, as shown by the red line, and each column will have 16 outputs. The specific process is shown in Figure 2 .

[0042] In the activation module, Relu is used as the activation function, and the output of the PE array is truncated. There are two activation modes [0:2] and [0:1], that is, greater than the upper limit, taking the upper limit, less than the lower limit, taking itself in the region, the first two layers use the [0:2] mode, and the last four layers use the [0:1] mode. The pooling module uses the maximum pooling method, and the maximum result is taken in P.

[0043] Embodiment 2: This embodiment designs a coprocessor instruction system based on NICE. Inline assembly syntax asm volatile("instructions") in C / C++ is used to embed assembly in C code, and the lbuf, sbuf, and rowsum instructions are modified to pass in the convolution parameters. Convolutional neural network is used to realize ECG classification and detection, which mainly includes convolution, activation, pooling, and fully connected layer. The coprocessor loads data from the main processor memory to the row data cache through the lbuf instruction, stores the data in the row data cache to the main processor memory through the sbuf instruction, and realizes the row accumulation operation through the rowsum instruction and returns the accumulated value to the main processor memory. The coprocessor responds to these instructions and realizes efficient transmission and calculation of convolution layer parameters in the CNN calculation process.

[0044] Specifically, in order to make full use of the register bit width, the custom instruction set of the coprocessor uses two registers rs1 and rs2 to pass the relevant parameters of the CNN. Since each register is 32 bits, the maximum parameter transmission width is only 64 bits at a time, so we only need to transmit the parameters of each layer twice. In order to ensure efficient convolution calculation, the system completes parameter transmission and control through four special signals:

[0045]

[0046] In each convolution layer calculation, the system transmits parameters through rs1 and rs2 registers, and according to the requirements of the hierarchical structure and convolution operation, it passes each parameter to the coprocessor. This design based on custom instructions not only optimizes the convolution operation of CNN at the hardware level, but also effectively reduces the data transmission time, thereby improving the overall system operation efficiency.

[0047] The above shows and describes the basic principles, main features and advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above specific embodiments, and the above specific embodiments and the description in the specification are only for further illustrating the principles and preparation effects of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A RISC-V based ECG classification detection convolutional neural network co-processor, comprising: The application relates to a neural network forward reasoning accelerator, which comprises the following parts: a state processing unit for controlling the forward reasoning of the coprocessor and the convolution calculation in the forward reasoning process; a memory controller for receiving the ECG signal, the weight and the network parameter from the host processor, calculating the storage address of the generated ECG signal, the weight and the network parameter, enabling the weight cache, the input / output buffer, the input register, the PE array, the output register, the activation module and the pooling module, wherein the memory controller receives the ECG signal, the weight and the network parameter from the host processor through the NICE protocol: the ECG signal, the weight and the network parameter from the host processor are loaded into the row data cache through the lbuf instruction, the data in the row data cache is accumulated through the rowsum instruction, and the accumulated value is returned to the host processor; and the data in the row data cache is stored into the memory of the host processor through the sbuf instruction; a weight cache for caching the weight of each layer of the neural network; an input / output buffer for caching the ECG signal from the host processor and the ECG input feature map completed by the PE array after each layer of convolution operation; an input register for caching the ECG input feature map completed by the PE array after each layer of convolution operation; a PE array for pulsating the ECG input feature map of the current layer of convolution operation, reading the weight of the current layer from the weight cache and outputting the convolution result of the current layer; an output register for caching the convolution result of the current layer output by the PE array; an activation module for performing the activation operation on the convolution result of the current layer output by the PE array; and a pooling module for performing the pooling operation on the activation data of the convolution result of the current layer and obtaining the ECG input feature map completed by the PE array after the next layer of convolution operation.

2. The RISC-V based ECG classification detection convolutional neural network coprocessor according to claim 1, wherein, The state processing unit comprises a main state machine and a calculation state machine; the main state machine is used for controlling the coprocessor to work in a cycle process comprising an idle state, a parameter acquisition state and a forward reasoning state; and the calculation state machine is used for controlling the PE array to complete one layer of convolution operation when the coprocessor works in the forward reasoning state.

3. The RISC-V based ECG classification detection convolutional neural network co-processor of claim 1, wherein, The ECG signal, the weight and the network parameter from the host processor are transmitted through the control of the maximum bit width of two registers, and the signal of the data transmission of the two registers is controlled through the calling of the self-defined instruction set.

4. The RISC-V based ECG classification detection convolutional neural network coprocessor of claim 3, wherein, The first column of the PE array receives the ECG signal from the host processor or the ECG input feature map of the current layer of convolution operation, the data received by the first column of the PE array is sequentially and pulsatingly input into each column of the PE array, the first row of the PE array receives the weight of the current layer, each column of the PE array respectively shares the weight of the current layer received by the first row of each column, and the calculation result of each column of the PE array is transmitted to the first row for output.

5. The RISC-V based ECG classification detection convolutional neural network coprocessor according to any one of claims 1 to 4, characterized in that, The weight cache is an on-chip cache comprising eight banks; and the input / output buffer is an on-chip cache composed of two SRAMs, each of which comprises eight banks.

6. The RISC-V based ECG classification detection convolutional neural network coprocessor according to any one of claims 1 to 4, characterized in that, The input register inputs and multiplexes the ECG input feature map data completed by the PE array after each layer of convolution operation; and the output register outputs, multiplexes and fills the convolution result of the current layer output by the PE array.

7. The RISC-V based ECG classification detection convolutional neural network co-processor of any one of claims 1 to 4, wherein, The activation module performs truncation processing on the current layer convolution result output by the PE array.

8. The RISC-V based ECG classification detection convolutional neural network co-processor of any one of claims 1-4, wherein, The pooling module performs maximum pooling processing on the activation data of the current layer convolution result.

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