Integer multiplication via 32-bit channel alignment of multiple multipliers per channel

Abstract

An integer multiplication of 32 bit channel alignment via multiple multipliers per channel is provided. A graphics processor is described herein that includes an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements includes functional units configured to provide integer pipelines to execute instructions to perform operations on integer data elements. The integer pipeline includes a first multiplier and a second multiplier configured to perform an operation for a single instruction.

Description

Technical Field

[0001] The present disclosure relates generally to data processing via a graphics processor, and more particularly, to an integer pipeline of a graphics processor. Background Art

[0002] The register architecture of a graphics processor represents a large portion of the silicon area and power consumption. The graphics processor register file tends to be larger to accommodate the large amount of data being processed simultaneously by the graphics processor. Optimizations to simplify the efficiency of the graphics processor register file can achieve significant savings in power consumption and silicon area consumed. However, in some extreme cases, this optimization may have a performance tradeoff. In addition to new instructions and instruction types, optimizations in instruction execution can mitigate potential performance losses that may occur in some cases. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Embodiments described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements, and in which:

[0004] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figure 2A-2D illustrates parallel processor components;

[0006] Figure 3A-3C is a block diagram of a graphics multiprocessor and a multiprocessor-based GPU;

[0007] Figure 4A-4F illustrates an exemplary architecture in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors;

[0008] Figure 5 Diagram of the graphics processing pipeline;

[0009] Figure 6 Diagram of the machine learning software stack;

[0010] Figure 7 Illustration of a general purpose graphics processing unit;

[0011] Figure 8 Diagram of a multi-GPU computing system;

[0012] Figure 9A-9B illustrates the layers of an exemplary deep neural network;

[0013] Fig.10 illustrates an exemplary recurrent neural network;

[0014] Fig.11 Illustration of the training and deployment of deep neural networks;

[0015] Fig. 12A is a block diagram illustrating distributed learning;

[0016] Fig. 12B is a block diagram illustrating a programmable network interface and a data processing unit;

[0017] Fig.13 An exemplary inference system on a chip (SOC) suitable for performing inference using a trained model is illustrated;

[0018] Fig.14 is a block diagram of the processing system;

[0019] Figure 15A-Figure 15C Graphics computing systems and graphics processors;

[0020] Figure 16A-16C A block diagram illustrating an additional graphics processor and computing accelerator architecture;

[0021] Fig.17 is a block diagram of a graphics processing engine of a graphics processor;

[0022] Figures 18A-18C The diagram includes thread execution logic for an array of processing elements employed in a graphics processor core;

[0023] Fig.19 illustrates a slice of a multi-chip processor according to an embodiment;

[0024] Fig. 20 is a block diagram illustrating a graphics processor instruction format;

[0025] Fig.21 is a block diagram of the attached graphics processor architecture;

[0026] Figure 22A-22B Illustrate the graphics processor command format and command sequence;

[0027] Fig.23 illustrates an exemplary graphical software architecture for a data processing system;

[0028] Fig.24A is a block diagram illustrating an IP core development system;

[0029] Fig. 24B illustrates a cross-sectional side view of an integrated circuit package assembly;

[0030] Fig.24C illustrates a package assembly including a hardware logic chiplet (e.g., base die) of multiple units connected to a substrate;

[0031] Fig.24DThe illustration includes a package assembly including interchangeable chiplets;

[0032] Fig.25 is a block diagram illustrating an exemplary system-on-chip integrated circuit;

[0033] Figure 26A-26B is a block diagram illustrating an exemplary graphics processor for use within a SoC;

[0034] Fig. 27 is a block diagram of a data processing system according to an embodiment;

[0035] Fig.28 illustrates a processing resource architecture for a graphics processor according to an embodiment;

[0036] Figures 29A-29B illustrates an integer unit according to an embodiment;

[0037] Fig.30 An algorithm for executing a MUL / MAD instruction according to an embodiment is illustrated, wherein the MUL / MAD instruction outputs the lower 32 bits of the result;

[0038] Fig.31 An algorithm for executing a MULLH instruction according to an embodiment is illustrated, and the MULLH instruction outputs the upper 32 bits and the lower 32 bits of a result;

[0039] Fig.32 illustrating a method of executing a 32-bit lane-aligned integer multiplication instruction according to an embodiment;

[0040] Fig.33 illustrating a method of executing 32-bit lane-aligned integer multiplication / addition instructions according to an embodiment;

[0041] Figure 34-Figure 35 illustrates a method of executing a 32-bit lane aligned integer multiply low / high instruction according to an embodiment; and

[0042] Fig.36 is a block diagram of a computing device including a graphics processor according to an embodiment. DETAILED DESCRIPTION

[0043] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data. More recently, however, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations to process vertex and fragment data.

[0044] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency. A general overview of software and hardware for the SIMT architecture can be found in Shane Cook's "CUDA Programming", Chapter 3, pages 37-51 (2013).

[0045] A graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate, for example, graphics operations, machine learning operations, pattern analysis operations, and / or various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to a host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0046] A graphics processor architecture is contemplated in which register file optimization reduces the silicon area and power consumption of the register file architecture, but also reduces the throughput of 32-bit integer multiplication or multiplication / addition operations when outputting a lane-aligned 32-bit result (e.g., a low 32-bit result, an upper 32-bit result, or a low and high (64-bit) result). A processing resource architecture and associated instructions are described herein that implement full throughput 32-bit lane-aligned integer multiplication via the use of multiple multipliers per lane. In one embodiment, a 32-bit×32-bit multiplier and a 16-bit×16-bit multiplier are used for each lane. Instructions utilizing two multipliers per 32-bit lane are also provided. In one embodiment, a 32-bit parallel integer multiplication is provided that outputs the lower 32 bits of the product of two 32-bit integers per lane. In one embodiment, a 32-bit parallel integer multiplication / addition is provided that outputs the lower 32 bits of the product of two 32-bit integers and an additional 32-bit integer for each lane. In another embodiment, a low / high multiplication is provided which, for each 32-bit lane, outputs the high 32 bits and the low 32 bits of the product of two 32-bit integer data elements.

[0047] In the following description, many specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other cases, well-known features are not described to avoid obscuring the details of the present embodiment.

[0048] System Overview

[0049] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 communicating via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component, or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0050] The processing subsystem 101 includes, for example, one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication fabric. The one or more parallel processors 112 can form a parallel or vector processing system in a computational concentration that can include a large number of processing cores and / or processing clusters, such as, for example, many integrated core (MIC) processors. For example, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0051] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, and various other devices that may be added via one or more add-in devices 120. The (one or more) add-in devices 120 may also include, for example, one or more external graphics processor devices, graphics cards, and / or computing accelerators. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radio devices.

[0052] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths for interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol(s), such as NVLink high-speed interconnect, compute express link, or the like.TM (ComputeExpress Link TM ,CXL TM ) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel Quick Path Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) Interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (3GPP Long Term Evolution, LTE) (4G), 3GPP 5G, and variants thereof, or wired or wireless interconnect protocols known in the art. In some examples, data can be copied or stored to a virtualized storage node using a protocol such as non-volatile memory express (NVMe) (NVME-oF) or NVMe over fabrics.

[0053] One or more parallel processors 112 may include circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). Alternatively or additionally, as described in more detail herein, one or more parallel processors 112 may include circuits optimized for general-purpose processing while retaining the underlying computing architecture. The components of the computing system 100 may be integrated on a single integrated circuit with one or more other system elements. For example, one or more parallel processors 112, the memory hub 105, (one or more) processors 102, and the I / O hub 107 may be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system in package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0054] It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (one or more) processors 102, and the number of (one or more) parallel processors 112, may be modified as desired. For example, the system memory 104 may be connected to the (one or more) processors 102 directly rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the (one or more) processors 102. In other alternative topologies, the (one or more) parallel processors are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. It is also possible for two or more groups of processors 102 to be attached via multiple slots, which may be coupled to two or more instances of the (one or more) parallel processors 112.

[0055] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be specific to the Figure 1 Different terminology is used for components that are similar to those illustrated in FIG. 1. For example, memory hub 105 may be referred to as a north bridge in some architectures, while I / O hub 107 may be referred to as a south bridge.

[0056] Figure 2A The illustrated parallel processor 200 may be a GPU, a GPGPU, or the like as described herein. Various portions of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The illustrated parallel processor 200 may be Figure 1 One or more of the parallel processor(s) 112 shown in FIG.

[0057] Parallel processor 200 includes parallel processing unit 202. Parallel processing unit includes I / O unit 204 that enables communication with other devices, including other instances of parallel processing unit 202. I / O unit can be directly connected to other devices. For example, I / O unit 204 is connected to other devices by using a hub or switch interface (such as memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

[0058] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. The scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before the task is distributed to the processing clusters in the processing cluster array 212. The scheduler 210 can be implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 212. Preferably, the host software can confirm the workload for scheduling on the processing cluster array 212 via one of a plurality of graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate the availability of work to be executed. The workload may then be automatically distributed across the processing cluster array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0059] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each cluster 214A-214N in the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may allocate work to the clusters 214A-214N in the processing cluster array 212 using various scheduling and / or work distribution algorithms that may vary depending on the workload that occurs for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during compilation of program logic that is configured to be executed by the processing cluster array 212. Optionally, different clusters 214A-214N in the processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

[0060] Processing cluster array 212 may be configured to perform various types of parallel processing operations. For example, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0061] Processing cluster array 212 is configured to perform parallel graphics processing operations. In such embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing, and then the data may be written back to system memory.

[0062] In embodiments where parallel processing units 202 are used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some of these embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0063] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands that define how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to fetch an index corresponding to the task, or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0064] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar switch 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. The number of partition units 220A-220N may be configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0065] The memory units 224A-224N may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A-224N, allowing the partition units 220A-220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0066] Optionally, any of the clusters 214A-214N in the processing cluster array 212 has the ability to process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment of an embodiment having a memory crossbar switch 216, the memory crossbar switch 216 has connections to a memory interface 218 to communicate with the I / O unit 204 and has connections to a local instance of a parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In general, the memory crossbar switch 216 may be able to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N using virtual channels, for example.

[0067] Although a single instance of parallel processing unit 202 is illustrated within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. For example, parallel processor 200 may be a plug-in device, such as, Figure 1 Plug-in device 120, which can be a graphics card (such as, a discrete graphics card including one or more GPUs), one or more memory devices, and a device-to-device or network or structure interface. Different instances of parallel processing unit 202 can be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. Optionally, some instances of parallel processing unit 202 can include higher precision floating point units relative to other instances. Systems including one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles and / or embedded systems. The orchestrator can use one or more of the following to form a composite node for workload execution: decomposed processor resources, cache resources, memory resources, storage resources, and networking resources.

[0068] In one embodiment, the parallel processing unit 202 can be partitioned into multiple instances. Those multiple instances can be configured to execute workloads associated with different clients in an isolated manner, so that a predetermined quality of service can be provided for each client. For example, each cluster 214A-214N can be divided and isolated from other clusters, thereby allowing the processing cluster array 212 to be divided into multiple computing partitions or instances. In such a configuration, the workload executed on the isolated partition is protected from the failure or error associated with the different workloads executed on different partitions. The partition unit 220A-220N can be configured to enable a dedicated and / or isolated path to the memory for the cluster 214A-214N associated with the corresponding computing partition. This data path isolation enables the computing resources within the partition to communicate with one or more allocated memory units 224A-224N without being disturbed by the activities of other partitions.

[0069] Figure 2B is a block diagram of the partition unit 220. The partition unit 220 may be Figure 2A 220N, and the partition unit 220A-220N is an example of a partition unit. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 is connected to the frame buffer interface 225. Figure 2A The partition unit 220 interfaces with the memory unit 224 in the memory units 224A-224N in the parallel processor memory 222. The partition unit 220 may additionally or alternatively interface with one of the memory units in the parallel processor memory via a memory controller (not shown).

[0070] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes or is coupled to CODEC 227, which includes compression logic for compressing depth or color data written to memory or L2 cache 221 and decompressing depth or color data read from memory or L2 cache 221. The compression logic can be lossless compression logic using one or more of a variety of compression algorithms. The type of compression performed by CODEC 227 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data tile by tile. In one embodiment, CODEC 227 includes compression and decompression logic that can compress and decompress computational data associated with machine learning operations. CODEC 227 may, for example, compress sparse matrix data for sparse machine learning operations. CODEC 227 may also compress sparse matrix data encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (compressed sparse row, CSR), compressed sparse column (compress sparse column, CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data may be decompressed and / or decoded before being processed by a processing element or before a processing element can be configured to consume compressed, encoded, or compressed and encoded data for processing.

[0071] ROP 226 may be included in each processing cluster (e.g., Figure 2A 214A-214N) rather than being included in partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar switch 216. The processed graphics data may be displayed on a display device such as a Figure 1 10B), is routed for further processing by the processor(s) 102, or is routed for processing by the processor(s) 102. Figure 2A The processing is further processed by one of the processing entities within the parallel processor 200.

[0072] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit. For example, a processing cluster is Figure 2AAn instance of a processing cluster in the processing clusters 214A-214N. The processing cluster 214 may be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a set of specific input data. Optionally, a single-instruction, multiple-data (SIMD) instruction issuance technique may be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, a single-instruction, multiple-thread (SIMT) technique may be used to support the parallel execution of a large number of threads that are generally synchronized using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster in the processing cluster. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. Those skilled in the art will appreciate that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0073] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives requests from Figure 2A The graphics multiprocessor 234 may be configured to receive instructions from the scheduler 210 of the graphics multiprocessor 234 and manage the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included within the processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations, including facilitating data exchange between the graphics multiprocessors within the processing cluster 214. The pipeline manager 232 may facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0074] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which new instructions may be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. The same functional unit hardware may be utilized to perform different operations, and different combinations of functional units may exist.

[0075] The instructions transmitted to the processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group may be assigned to a different processing engine within the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle during which the thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing may be performed on consecutive clock cycles. Optionally, multiple thread groups may be executed concurrently on the graphics multiprocessor 234.

[0076] The graphics multiprocessor 234 may include internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor may forgo the internal cache and use cache memory (e.g., level 1 (L1) cache 248) within the processing cluster 214. Each graphics multiprocessor 234 also has a partition unit (e.g., Figure 2A 220A-220N), which are shared between all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 248.

[0077] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 may reside in Figure 2A218. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of the slice, and optionally includes a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache 248 of the processing cluster 214. The physical address is processed to distribute surface data access locality, thereby allowing efficient request interleaving between partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0078] In graphics and compute applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some embodiments, from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A pre-raster operations unit 242 is configured to receive data from the graphics multiprocessor 234, direct the data to ROP units, which may communicate with partition units (e.g., Figure 2A The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0079] It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within a processing cluster 214. Further, while only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of a processing cluster 214. Optionally, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, L2 caches, etc.

[0080] Figure 2DAn example of a graphics multiprocessor 234 is shown, where the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and / or load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268. The graphics multiprocessor 234 may additionally include a tensor and / or ray tracing core 263 that includes hardware logic for accelerating matrix and / or ray tracing operations.

[0081] The instruction cache 252 may receive an instruction stream to be executed from the pipeline manager 232. The instructions may be cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch the instructions as a thread group (e.g., a warp), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 262. The instruction may access any of the local address space, the shared address space, or the global address space by specifying an address within the unified address space. The address mapping unit 256 may be used to convert the address in the unified address space into a different memory address that can be accessed by the load / store unit 266.

[0082] The register file 258 provides a collection of registers for the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for operands of data paths of the functional units connected to the graphics multiprocessor 234 (e.g., GPGPU core 262, load / store unit 266). The register file 258 may be divided between each of the functional units so that each functional unit is assigned a dedicated portion of the register file 258. For example, the register file 258 may be divided between different warps executed by the graphics multiprocessor 234.

[0083] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. In some implementations, the GPGPU cores 262 may include hardware logic that may otherwise reside within the tensor and / or ray tracing cores 263. The GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or enable variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. One or more of the GPGPU cores may also include fixed-function or special-function logic.

[0084] GPGPU core 262 may include SIMD logic capable of executing a single instruction to multiple sets of data. Optionally, GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for GPGPU cores may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads may be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0085] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. For example, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 are very low latency. The shared memory 270 can be used to enable communication between threads executing on the functional units of the graphics multiprocessor 234. The cache memory 272 can be used as a data cache, for example, to cache texture data passed between the functional unit and the texture unit 236. The shared memory 270 can also be used as a managed cached program. The shared memory 270 and the cache memory 272 can be coupled to the data crossbar 240 to enable communication with other components of the processing cluster. Threads executing on GPGPU core 262 can programmatically store data in shared memory in addition to automatically cached data stored in cache memory 272 .

[0086] Figure 3A-3C An additional graphics multiprocessor is illustrated in accordance with an embodiment. Figure 3A-3B Graphics multiprocessors 325, 350 are shown, which are connected to Figure 2C 234, and may be used in place of one of those graphics multiprocessors. Therefore, disclosure of any feature herein in conjunction with graphics multiprocessor 234 also discloses the corresponding combination with graphics multiprocessors 325, 350, but is not limited thereto. Figure 3C A graphics processing unit (GPU) 380 is illustrated, which includes a dedicated collection of graphics processing resources arranged as multi-core groups 365A-365N, which correspond to the graphics multiprocessors 325, 350. The illustrated graphics multiprocessors 325, 350 and multi-core groups 365A-365N may be streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0087] Figure 3A The graphics multiprocessor 325 includes relative Figure 2DThe graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and (one or more) texture units 344A-344B. The graphics multiprocessor 325 also includes a collection of multiple graphics or compute execution units (e.g., GPGPU cores 336A-336B, tensor cores 337A-337B, ray tracing cores 338A-338B) and a collection of multiple load / store units 340A-340B. The execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0088] The components may communicate via an interconnect structure 327. The interconnect structure 327 may include one or more crossbar switches to enable communication between the components of the graphics multiprocessor 325. The interconnect structure 327 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the cores 336A-336B, 337A-337B, and 338A-338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0089] Figure 3B The graphics multiprocessor 350 includes a plurality of execution resource sets 356A-356D, wherein, for example Figure 2D and Figure 3A As shown in FIG. 1 , each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units. Execution resources 356A-356 can work in conjunction with (one or more) texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 353. For example, execution resources 356A-356D can share instruction cache 354 and shared memory 353, as well as multiple instances of texture and / or data cache memory 358A-358B. Various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352.

[0090] Those skilled in the art will understand that Figure 1 , Figure 2A-2D as well as Figure 3A-3BThe architecture described in is illustrative and not limiting in terms of the scope of the current embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit without departing from the scope of the embodiments described herein, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processor units, such as, Figure 2A A parallel processing unit 202, and one or more graphics processors or special processing units.

[0091] The parallel processor or GPGPU described herein can be communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect, such as PCIe, NVLink, or other known protocols, standardized protocols, or proprietary protocols). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0092] Figure 3C A graphics processing unit (GPU) 380 is shown that includes a dedicated collection of graphics processing resources arranged as multi-core groups 365A-365N. Although details of only a single multi-core group 365A are provided, it will be appreciated that other multi-core groups 365B-365N may be equipped with the same or similar collection of graphics processing resources. The details described with respect to multi-core groups 365A-365 may also apply to any of the graphics multiprocessors 234, 325, 350 described herein.

[0093] As illustrated, multi-core group 365A may include a set 370 of graphics cores, a set 371 of tensor cores, and a set 372 of ray tracing cores. Scheduler / dispatcher 368 schedules and dispatches graphics threads for execution on the respective cores 370, 371, 372. A set 369 of register files stores operand values ​​used by cores 370, 371, 372 when executing graphics threads. These register files may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and slice registers for storing tensor / matrix values. Slice registers may be implemented as a combined set of vector registers.

[0094] One or more combined first level (L1) caches and shared memory units 373 store graphics data locally within each multi-core group 365A, such as texture data, vertex data, pixel data, light data, bounding volume data, etc. One or more texture units 374 can also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 375 shared by all multi-core groups 365A-365N or a subset of multi-core groups 365A-365N stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 375 can be shared across multiple multi-core groups 365A-365N. One or more memory controllers 367 couple the GPU 380 to a memory 366, which can be a system memory (e.g., DRAM) and / or a dedicated graphics memory (e.g., GDDR6 memory).

[0095] Input / output (I / O) circuitry 363 couples GPU 380 to one or more I / O devices 362, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple I / O devices 362 to GPU 380 and memory 366. One or more I / O memory management units (IOMMUs) 364 of I / O circuitry 363 directly couple I / O devices 362 to system memory 366. Optionally, IOMMU 364 manages page tables for mapping virtual addresses to multiple sets of physical addresses in system memory 366. I / O devices 362, CPU(s) 361, and GPU(s) 380 may then share the same virtual address space.

[0096] In one implementation of IOMMU 364, IOMMU 364 supports virtualization. In this case, IOMMU 366 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 366). The base address of each of the first set of page tables and the second set of page tables can be stored in a control register and swapped out upon context switch (e.g., so that the new context is provided with access to the relevant set of page tables). Although not described in detail in the prior art, the first set of page tables and the second set of page tables can be stored in a control register and swapped out upon context switch (e.g., so that the new context is provided with access to the relevant set of page tables). Figure 3C , but each of the cores 370, 371, 372 and / or multi-core groups 365A-365N may include a translation lookaside buffer (TLB) that is used to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0097] (One or more) CPU 361, GPU 380 and I / O device 362 can be integrated on a single semiconductor chip and / or chip package. The illustrated memory 366 can be integrated on the same chip, or can be coupled to a memory controller 367 via an off-chip interface. In one implementation, memory 366 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the underlying principles described herein are not limited to this particular implementation.

[0098] Tensor core 371 may include multiple execution units specifically designed to perform matrix operations, which are basic computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations may be used for neural network training and inference. Tensor core 371 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). For example, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to build a high-quality final image.

[0099] In a deep learning implementation, parallel matrix multiplication work can be scheduled for execution on the tensor core 371. The training of neural networks in particular requires a large number of matrix dot product operations. To handle the inner product formulation of the N x N x N matrix multiplication, the tensor core 371 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the slice register, and for each of the N loops, at least one column of the second matrix is ​​loaded. For each loop, there are N dot products that are processed.

[0100] Depending on the specific implementation, matrix elements can be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the tensor core 371 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization to bytes and nibbles). Supported formats additionally include 64-bit floating point (FP64) and non-IEEE floating point formats, such as the bfloat16 format (e.g., Brain floating point format), a 16-bit floating point format with one sign bit, eight exponent bits, and eight significand bits (seven of which are explicitly stored). One embodiment includes support for a reduced precision tensor floating point (TF32) mode that performs calculations using the range of FP32 (8 bits) and the precision of FP16 (10 bits). Reduced-precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs with higher performance relative to FP32 and increased precision relative to FP16. In one embodiment, one or more 8-bit floating point formats (FP8) are supported.

[0101] In one embodiment, the tensor core 371 supports a sparse operation mode for matrices in which the vast majority of values ​​are zero. The tensor core 371 includes support for sparse input matrices encoded in sparse matrix representations (e.g., coordinate list encoding (COO), compressed sparse rows (CSR), compressed sparse columns (CSC), etc.). The tensor core 371 also includes support for compressed sparse matrix representations in the case where the sparse matrix representation can be further compressed. Compressed matrix data, encoded matrix data, and / or compressed and encoded matrix data and associated compression and / or encoding metadata can be read by the tensor core 371, and non-zero values ​​can be extracted. For example, for a given input matrix A, non-zero values ​​can be loaded from at least a portion of the compressed and / or encoded representation of matrix A. Based on the position of the non-zero value in matrix A (which can be determined from the index or coordinate metadata associated with the non-zero value), the corresponding value in the input matrix B can be loaded. Depending on the operation to be performed (e.g., multiplication), if the corresponding value is a zero value, the loading of the value from the input matrix B can be bypassed. In one embodiment, the pairing of values ​​for certain operations (such as multiplication operations) can be pre-scanned by the scheduler logic, and only operations between non-zero inputs are scheduled. Depending on the dimensions of matrix A and matrix B and the operations to be performed, the output matrix C can be dense or sparse. In the case where the output matrix C is sparse and depending on the configuration of the tensor core 371, the output matrix C can be output in a compressed format, sparse coding, or compressed sparse coding.

[0102] The ray tracing core 372 can accelerate ray tracing operations for both real-time ray tracing implementations and non-real-time ray tracing implementations. Specifically, the ray tracing core 372 may include a ray traversal / intersection circuit that uses a bounding volume hierarchy (BVH) to perform ray traversals and identify intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 372 may also include circuits for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing core 372 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least portions of which may be performed on the tensor core 371. For example, the tensor core 371 may implement a deep learning neural network to perform denoising on frames generated by the ray tracing core 372. However, the CPU(s) 361, graphics core 370, and / or ray tracing core 372 may also implement all or a portion of the denoising and / or deep learning algorithms.

[0103] In addition, as described above, a distributed approach to noise reduction may be employed, wherein GPU 380 is in a computing device coupled to other computing devices via a network or high-speed interconnect. According to the distributed approach, the interconnected computing devices may share neural network learning / training data to improve the speed at which the entire system learns to perform noise reduction for different types of image frames and / or different graphics applications.

[0104] The ray tracing core 372 can handle all BVH traversals and / or ray-primitive intersections, thereby preventing the graphics core 370 from being overloaded with thousands of instructions for each ray. For example, each ray tracing core 372 includes a first set of specialized circuits for performing bounding box tests (e.g., for traversal operations) and / or a second set of specialized circuits for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, for example, the multi-core group 365A can simply initiate a ray probe, and the ray tracing core 372 independently performs ray traversals and intersections and returns hit data (e.g., hits, no hits, multiple hits, etc.) to the thread context. While the ray tracing core 370 performs traversal and intersection operations, the other cores 371, 372 are freed up to perform other graphics or computational work.

[0105] Optionally, each ray tracing core 372 may include a traversal unit for performing BVH test operations and / or an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response, which it provides to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 370 and tensor core 371) are freed up to perform other forms of graphics work.

[0106] In one optional embodiment described below, a hybrid rasterization / ray tracing approach is used in which the work is distributed between graphics core 370 and ray tracing core 372 .

[0107] The ray tracing core 372 (and / or other cores 370, 371) may include hardware support for ray tracing instruction sets, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable a unique set of shaders and textures to be assigned to each object. Another ray tracing platform that may be supported by the ray tracing core 372, graphics core 370, and tensor core 371 is the Vulkan API (e.g., Vulkan version 1.1.85 and subsequent versions). However, it is to be noted that the underlying principles described herein are not limited to any particular ray tracing ISA.

[0108] In general, each core 372, 371, 370 may support a ray tracing instruction set including instructions / functions for one or more of the following: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, preferred embodiments include ray tracing instructions for performing one or more of the following functions:

[0109] Light Generation - Ray generation instructions can be executed for each pixel, sample, or other user-defined work assignment.

[0110] Recent Hits - A nearest hit command may be executed to locate the closest intersection of a ray with a primitive within the scene.

[0111] Any hit - Any hit command identifies multiple intersections between rays and primitives within the scene, thereby potentially identifying a new closest intersection point.

[0112] intersect ——The intersection instruction performs a ray-primitive intersection test and outputs the result.

[0113] Per-primitive bounding box construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0114] miss - Indicates that the ray missed the scene or all geometry within a specified region of the scene.

[0115] visit ——Indicates the subvolume that the ray will traverse.

[0116] abnormal - Includes various types of exception handlers (e.g., called for various error conditions).

[0117] In one embodiment, the ray tracing core 372 may be adapted to accelerate general computing operations that can be accelerated using computing techniques similar to ray intersection testing. A computing framework may be provided that enables shader programs to be compiled into low-level instructions and / or primitives that perform general computing operations via the ray tracing core. Exemplary computing problems that may benefit from computing operations performed on the ray tracing core 372 include calculations involving the propagation of beams, waves, rays, or particles within a coordinate space. Interactions associated with that propagation may be calculated relative to a geometry or mesh within the coordinate space. For example, calculations associated with the propagation of electromagnetic signals through an environment may be accelerated using instructions or primitives that are executed via the ray tracing core. Refraction and reflection of signals through objects in the environment may be calculated as direct ray tracing simulations.

[0118] The ray tracing core 372 can also be used to perform calculations that are not directly similar to ray tracing. For example, the ray tracing core 372 can be used to accelerate mesh projection, mesh refinement, and volume sampling calculations. General coordinate space calculations, such as nearest neighbor calculations, can also be performed. For example, a set of points near a given point can be found by defining a bounding box around the given point in the coordinate space. The BVH and ray detection logic in the ray tracing core 372 can then be used to determine the intersection of the set of points within the bounding box. The intersection constitutes the origin and the nearest neighbor of that origin. The calculations performed using the ray tracing core 372 can be performed in parallel with the calculations performed on the graphics core 372 and the tensor core 371. The shader compiler can be configured to compile a compute shader or other general graphics processing program into a low-level primitive that can be parallelized across the graphics core 370, the tensor core 371, and the ray tracing core 372.

[0119] Technologies for GPU to host processor interconnect

[0120] Figure 4A The diagram shows a plurality of GPUs 410-413 (e.g., such as Figure 2A200) is communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440A-440D (e.g., buses, point-to-point interconnects, etc.). Depending on the implementation, high-speed links 440A-440D may support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles described herein are not limited to any particular communication protocol or throughput.

[0121] Two or more of the GPUs 410-413 may be interconnected via high-speed links 442A-442B, which may be implemented using the same or different protocols / links as those used for high-speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 443, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in the can be implemented using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles described herein are not limited to any particular type of interconnect technology.

[0122] Each of the multi-core processors 405 and 406 may be communicatively coupled to the processor memories 401-402 via memory interconnects 430A-430B, respectively, and each GPU 410-413 may be communicatively coupled to the GPU memories 420-423 via GPU memory interconnects 450A-450D, respectively. The memory interconnects 430A-430B and 450A-450D may utilize the same or different memory access technologies. As an example and not by way of limitation, the processor memories 401-402 and the GPU memories 420-423 may be volatile memories such as dynamic random-access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D Xpoint / Optane or Nano-Ram. For example, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy). The memory subsystem described herein may be compatible with several memory technologies, such as the double data rate version published by JEDEC (Joint Electronic Device Engineering Council).

[0123] As described below, although each processor 405-406 and GPU 410-413 may be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each include 64GB of system memory space, and GPUs 420-423 may each include 32GB of system memory address space (thus yielding a total of 256GB of addressable memory in this example).

[0124] Figure 4B Additional optional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 are illustrated. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0125] The illustrated processor 407 includes a plurality of cores 460A-460D, each of which has a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data, which are not illustrated to avoid obscuring the underlying principles of the components described herein (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A-462D may include first-level (L1) caches and second-level (L2) caches. In addition, one or more shared caches 456 may be included in the cache hierarchy and shared by the set 460A-460D of cores. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441, which may include the processor memories 401-402.

[0126] Coherence is maintained for data and instructions stored in each cache 462A-462D, 456 and system memory 441 via inter-core communications over coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles described herein.

[0127] A proxy circuit 425 may be provided that communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in a cache coherence protocol as a peer of the core. Specifically, an interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and an interface 437 connects the graphics acceleration module 446 to the high-speed link 440.

[0128] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 431, 432, ..., N of the graphics acceleration module 446. The graphics processing engines 431, 432, ..., N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, ..., N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer (BLIT) engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, ..., N, or the graphics processing engines 431-432, ..., N may be separate GPUs integrated on a common package, line card, or chip. The graphics processing engines 431-432, ..., N may be configured with any graphics processor or computing accelerator architecture described herein.

[0129] The accelerator integrated circuit 436 may include a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and a memory access protocol for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431, 432, ..., N. The data stored in the cache 438 and the graphics memories 433-434, ..., M may be kept consistent with the core caches 462A-462D, 456 and the system memory 441. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, ..., M (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A-462D, 456, and receiving updates from cache 438).

[0130] The set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, ..., N, and the context management circuit 448 manages these thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore the context of each thread during a context (e.g., where a first thread is saved and a second thread is restored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, the context management circuit 448 may store the current register value to a specified area in memory (e.g., identified by a context pointer). When returning to the context, it may then restore the register value. The interrupt management circuit 447 may, for example, receive an interrupt from a system device and process the interrupt received from the system device.

[0131] In one implementation, the virtual / effective address from the graphics processor engine 431 is converted to an actual / physical address in the system memory 441 by the MMU 439. Optionally, the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407, or may be shared between multiple applications. Optionally, a virtualized graphics execution environment is provided in which the resources of the graphics processing engines 431-432, ..., N are shared with multiple applications, virtual machines (VMs), or containers. Resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications or based on a predetermined partitioned profile of the graphics accelerator module 446. VMs and containers may be used interchangeably herein.

[0132] A virtual machine (VM) can be software that runs an operating system and one or more applications. A VM can be defined by specifications, configuration files, virtual disk files, non-volatile random access memory (NVRAM) settings files, and log files, and is backed up by the physical resources of the host computing platform. A VM can include an operating system (OS) or application environment installed on software that mimics dedicated hardware. End users have the same experience on a virtual machine as they would on dedicated hardware. Specialized software called a hypervisor completely simulates the CPU, memory, hard disk, network, and other hardware resources of a PC client or server, allowing virtual machines to share resources. A hypervisor can simulate multiple virtual hardware platforms that are isolated from each other, allowing virtual machines to run on the same underlying physical host. Server, VMware ESXi, and other operating systems.

[0133] A container is a package of applications, configurations, and dependencies so that the application runs reliably from one computing environment to another. Containers can share an operating system installed on a server platform and run as isolated processes. A container is a package of software that contains everything the software needs to run, such as system tools, libraries, and settings. Containers are not installed like traditional software programs, which allows them to be isolated from other software and from the operating system itself. The isolated nature of containers provides several benefits. First, the software in a container will run the same way in different environments. For example, a container that includes PHP and MySQL can be run in the same way in different environments. Computer and The machines run in exactly the same way. Second, containers provide increased security because the software will not affect the host operating system. While installed applications will change system settings and modify resources (such as the Windows registry), containers can only modify settings within the container.

[0134] Thus, the accelerator integrated circuit 436 acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory caching services. In one embodiment, to facilitate the bridging function, the accelerator integrated circuit 436 may also include a shared I / O 497 (e.g., PCIe, USB, or other element) and hardware to enable system control of voltage, clock control, performance, heat, and security. The shared I / O 497 may utilize separate physical connections or may span the high-speed link 440. In addition, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0135] Since the hardware resources of the graphics processing engines 431-432, ..., N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. An optional function of the accelerator integrated circuit 436 is to physically separate the graphics processing engines 431-432, ..., N so that they appear as independent units to the system.

[0136] One or more graphics memories 433-434, ..., M may be respectively coupled to each of the graphics processing engines 431-432, ..., N. Graphics memories 433-434, ..., M store instructions and data being processed by each of the graphics processing engines 431-432, ..., N. Graphics memories 433-434, ..., M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D Xpoint / Optane, Samsung Z-NAND, or Nano-Ram.

[0137] To reduce the amount of data traffic on high-speed link 440, biasing techniques may be used to ensure that the data stored in graphics memory 433-434, ..., M is data that will be used most frequently by graphics processing engines 431-432, ..., N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the core (and preferably not by graphics processing engines 431-432, ..., N) within the core's cache 462A-462D, 456 and system memory 441.

[0138] according to Figure 4C In the variant shown in FIG. 4 , the accelerator integrated circuit 436 is integrated within the processor 407. The graphics processing engines 431-432, ..., N communicate directly to the accelerator integrated circuit 436 via the high-speed link 440, via the interface 437 and the interface 435 (which again may utilize any form of bus or interface protocol). The accelerator integrated circuit 436 may perform the same operations as the reference Figure 4B The operations are the same as those described, but given the close proximity of the accelerator integrated circuit 436 to the coherency bus 464 and caches 462A-462D, 456, it is potentially able to perform the operations at a higher throughput.

[0139] The described embodiments may support different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0140] In an embodiment of a dedicated process model, graphics processing engines 431, 432, ..., N can be dedicated to a single application or process under a single operating system. A single application can leak other application requests to graphics engines 431, 432, ..., N, thereby providing virtualization within a VM / partition.

[0141] In a dedicated process programming model, graphics processing engines 431, 432, ..., N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, ..., N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, ..., N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, ..., N to provide access to each process or application.

[0142] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431-432, ..., N use a process handle to select a process element. The process element may be stored in the system memory 441 and may be addressable using the effective address to real address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, ..., N (i.e., calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0143] Figure 4D An exemplary accelerator integrated slice 490 is illustrated. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within the system memory 441 stores process elements 483. Process elements 483 may be stored in response to a GPU call 481 from an application 480 executed on a processor 407. Process elements 483 contain a process state for the corresponding application 480. A work descriptor (WD) 484 contained in the process element 483 may be a single job requested by an application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0144] The graphics acceleration module 446 and / or the individual graphics processing engines 431-432, ..., N can be shared by all processes in the system or a subset of processes in the system. For example, the technology described herein can include an infrastructure for establishing a process state and sending a WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0145] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0146] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be completed by one of the graphics processing engines in the graphics acceleration module 446. As shown, data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 448. For example, the MMU 439 may include a segment / page walkthrough circuit for accessing the segment table / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431-432, ..., N is converted into an actual address by the MMU 439.

[0147] The same register set 445 may be replicated for each graphics processing engine 431-432, ..., N and / or graphics acceleration module 446 and may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in an accelerator integrated slice 490. In one embodiment, each graphics processing engine 431-432, ..., N may be presented to a hypervisor 496 as a different graphics processor device. QoS settings may be configured for clients of a particular graphics processing engine 431-432, ..., N, and data isolation between clients of each engine may be enabled. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0148] Table 1 - Registers initialized by the hypervisor

[0149] 1 Slice Control Register 2 Real Address (RA) scheduled process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0150] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0151] Table 2 - Registers initialized by the operating system

[0152] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) accelerator uses record pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission Mask 6 Job Descriptor

[0153] Each WD 484 may be specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, ..., N. It contains all the information needed by the graphics processing engine 431-432, ..., N to do its job, or it may be a pointer to a memory location where a command queue where an application has set up work to be done is located.

[0154] Figure 4E The diagram illustrates additional optional details of the sharing model. It includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engine to the operating system 495.

[0155] The shared programming model allows all processes or a subset of processes from all partitions in the system or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sharing and graphics-directed sharing.

[0156] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the system 496, the graphics acceleration module 446 may comply with the following requirements: 1) The application's job requests must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests are guaranteed by the graphics acceleration module 446 to complete within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt processing of jobs. 3) The graphics acceleration module 446 must be guaranteed fairness between processes when operating in a directed sharing programming model.

[0157] For the directed sharing model, the application 480 may be required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type may be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446, and the WD may take the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure for describing the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value is passed to the operating system similar to the application setting the AMR. If the accelerator integrated circuit 436 and graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 483. The CSRP may be one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to use to save and restore context state. This pointer is optional if no state is required to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0158] Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and has been given permission to use the graphics acceleration module 446. The operating system 492 then calls the hypervisor 496 with the information shown in Table 3.

[0159] Table 3 - OS call parameters to the hypervisor

[0160]

[0161] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 in a linked list of process elements for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0162] Table 4 - Process element information

[0163] 1 Work Descriptor (WD) 2 The authority mask register (AMR) value (potentially masked). 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optionally thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 The virtual address of the storage segment table pointer (SSTP) 7 Logical interrupt service number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters. 9 Status register (SR) value 10 Logical partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0164] The hypervisor may initialize registers 445 of the plurality of accelerator integrated slices 490 .

[0165] like Figure 4F As shown in , in an optional implementation, a unified memory addressable via a common virtual memory address space is employed, which is used to access physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402 and vice versa, thereby simplifying programmability. A first portion of the virtual / effective address space may be allocated to processor memory 401, a second portion may be allocated to second processor memory 402, a third portion may be allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) can thus be distributed across each of processor memory 401-402 and GPU memory 420-423, allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0166] Bias / coherency management circuits 494A-494E within one or more of the MMUs 439A-439E may be provided that ensure cache coherency between the caches of the host processor (e.g., 405) and the caches of the GPUs 410-413 and implement biasing techniques that indicate the physical memory in which certain types of data should be stored. Figure 4F Multiple instances of bias / consistency management circuits 494A- 494E are illustrated in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0167] The GPU-attached memory 420-423 can be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but does not suffer from the typical performance drawbacks associated with full system cache coherence. The ability of the GPU-attached memory 420-423 to be accessed as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU migration. This arrangement allows the host processor 405 to set up operation objects and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of the migrated calculation. For example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead may significantly reduce the effective write bandwidth seen by the GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU migration.

[0168] The selection between GPU bias and host processor bias may be driven by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure (i.e., controlled at the granularity of a memory page) comprising 1 or 2 bits per GPU-attached memory page. The bias table may be implemented in a stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., for caching entries of the bias table that are frequently / recently used). Alternatively, the entire bias table may be maintained within the GPU.

[0169] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed prior to the actual access to the GPU memory, resulting in the following operations. First, local requests from the GPU 410-413 for pages that find them in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU for pages that find them in the host bias are forwarded to the processor 405 (e.g., as discussed above, over a high-speed link). Optionally, requests from the processor 405 for pages that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests involving pages in the GPU bias may be forwarded to the GPU 410-413. If the GPU is not currently using the page, the GPU may then convert the page to the host processor bias.

[0170] The bias state of a page may be changed by a software-based mechanism, or by a hardware-assisted software-based mechanism, or for a limited set of situations by a purely hardware-based mechanism.

[0171] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU directing the GPU to change the bias state and perform a cache flush operation in the host for some transitions. A cache flush operation is required for a transition from host processor 405 bias to GPU bias, but not for the reverse transition.

[0172] Cache coherency may be maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant immediate access, depending on the implementation. Therefore, to reduce communication between host processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are those pages that are needed by the GPU but not by host processor 405, and vice versa.

[0173] Graphics Processing Pipeline

[0174] Figure 5 5. A graphics processing pipeline 500 is shown. A graphics multiprocessor (such as Figure 2D Graphics multiprocessor 234, Figure 3A Graphics multiprocessor 325, Figure 3B The graphics multiprocessor 350 of FIG. 5 may implement the illustrated graphics processing pipeline 500. The graphics multiprocessor may be included in a parallel processing subsystem as described herein, such as a parallel processing subsystem. Figure 2AThe parallel processor 200 can be used with Figure 1 The parallel processors 112 are related and can be used instead of one of those parallel processors. Various parallel processor systems can be implemented via parallel processing units (e.g., Figure 2A The graphics processing pipeline 500 may be implemented using one or more instances of a parallel processing unit 202 of the graphics processing unit. For example, a shader unit (e.g., Figure 2C The graphics multiprocessor 234 of the graphics processor 500 may be configured to perform the functions of one or more of the following: the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by a processing cluster (e.g., Figure 2A Other processing engines and corresponding partition units (e.g., Figure 2A The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. It is also possible that one or more portions of the graphics processing pipeline 500 are executed by parallel processing logic within a general-purpose processor (e.g., a CPU). Optionally, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as a CPU) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 may be Figure 2A The graphics processor pipeline 500 can also be connected via Figure 3C This is achieved using the multi-core group 365A in .

[0175] The data assembler 502 is a processing unit that can collect vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data to the vertex processing unit 504, which includes vertex attributes. The vertex processing unit 504 is a programmable execution unit that executes the vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0176] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0177] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. The control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for use in a surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch into a plurality of geometric primitives (such as line, triangle, or quadrilateral primitives), which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0178] The second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512 as needed, reads the stored vertex attributes, and builds graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. Geometry processing unit 516 can be programmed to tessellate graphics primitives into one or more new graphics primitives and calculate parameters used to rasterize the new graphics primitives.

[0179] The geometry processing unit 516 may be able to add or remove elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and builds graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0180] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 may read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade at a sample, pixel, slice, or other granularity depending on the sampling rate configured for the processing unit.

[0181] Raster operation unit 526 is a processing unit that performs raster operations and outputs pixel data to be stored in graphics memory (e.g., as Figure 2A The parallel processor memory 222 and / or Figure 1 The raster operation unit 526 may be configured to compress z data or color data written to memory and decompress z data or color data read from memory.

[0182] Machine Learning Overview

[0183] The architecture described above can be applied to perform training and inference operations using machine learning models. Machine learning has been successful in solving many types of tasks. The calculations generated when training and using machine learning algorithms (e.g., neural networks) are naturally suitable for efficient parallel implementation. Accordingly, parallel processors such as general purpose graphics processing units (GPGPUs) have played an important role in the actual implementation of deep neural networks. Parallel graphics processors with single instruction multiple threads (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to increase processing efficiency. The efficiency provided by the parallel machine learning algorithm implementation allows the use of high-capacity networks and enables those networks to be trained to larger data sets.

[0184] A machine learning algorithm is an algorithm that is capable of learning based on a set of data. For example, a machine learning algorithm can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0185] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each consecutive layer in the network based on coefficients ("weights") associated with each of the edges connecting these layers. Depending on the specific model being represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0186] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal is propagated backward through the layers of the network, the weights associated with the connections are adjusted to minimize that error. The network is considered "trained" when the error for each of the outputs generated from the instances of the training data set is minimized.

[0187] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Accordingly, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to exploit the parallel processing hardware within general-purpose graphics processing devices.

[0188] Figure 6 600 is a generalized diagram of a machine learning software stack 600. A machine learning application 602 is any logic that can be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. A machine learning application 602 may include training and inference functions for a neural network and / or specialized software that can be used to train a neural network before deployment. A machine learning application 602 may implement any type of machine intelligence, including but not limited to: image recognition, map creation and positioning, autonomous navigation, speech synthesis, medical imaging, or language translation. Example machine learning applications 602 include but are not limited to voice-based virtual assistants, image or facial recognition algorithms, autonomous navigation, and software tools used to train machine learning models used by machine learning applications 602.

[0189] Hardware acceleration for machine learning applications 602 can be enabled via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms will be required to create and optimize the main computing logic associated with the machine learning algorithm, and then re-optimize the computing logic when developing new parallel processors. Instead, machine learning applications can be configured to use primitives provided by the machine learning framework 604 to perform necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations. Examples of machine learning frameworks 604 include, but are not limited to, TensorFlow, TensorRT, PyTorch, MXNet, Caffe, and other advanced machine learning frameworks.

[0190] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate inputs to the computing framework 606. The computing framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 so that the machine learning framework 604 can utilize hardware acceleration via the GPGPU hardware 610 without the machine learning framework 604 being very familiar with the architecture of the GPGPU hardware 610. In addition, the computing framework 606 can enable hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610. Exemplary computing frameworks 606 include CUDA computing frameworks and associated machine learning libraries, such as CUDA Deep Neural Network (cuDNN) libraries. The machine learning software stack 600 can also include a communication library or framework to facilitate multi-GPU and multi-node computing.

[0191] GPGPU machine learning acceleration

[0192] Figure 7 A general purpose graphics processing unit 700 is shown, which may be Figure 2A Parallel processor 200 or Figure 1 The general purpose processing unit (GPGPU) 700 can be configured to provide support for hardware acceleration of primitives provided by machine learning frameworks to accelerate the processing of computational workloads of the type associated with training deep neural networks. In addition, the GPGPU 700 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster, thereby improving the training speed of deep neural networks in particular. Primitives are also supported to accelerate inference operations for deployed neural networks.

[0193] GPGPU 700 includes a host interface 702 for enabling connection to a host processor. Host interface 702 may be a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with those commands to a collection of processing clusters 706A-706H. Processing clusters 706A-706H share cache memory 708. Cache memory 708 may act as a higher level cache for cache memory within processing clusters 706A-706H. The illustrated processing clusters 706A-706H may be connected to Figure 2A Corresponding to the processing clusters 214A-214N in.

[0194] GPGPU 700 includes memory 714A-714B coupled to processing clusters 706A-706H via a set of memory controllers 712A-712B. Memories 714A-714B may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Memories 714A-714B may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM).

[0195] Each of processing clusters 706A-706H may include a collection of graphics multiprocessors, such as, Figure 2D Graphics multiprocessor 234, Figure 3A Graphics multiprocessor 325, Figure 3B The graphics multiprocessor 350 may include Figure 3C The graphics multiprocessors of the computing clusters include multiple types of integer and floating point logic units capable of performing computational operations with a range of precisions including precisions suitable for machine learning computations. For example, at least a subset of the floating point units in each of the processing clusters 706A-706H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0196] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies across embodiments. For example, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709, which couples GPGPU 710 with a GPU link 710, which enables direct connection to other instances of GPGPU. GPU link 710 can be coupled to a dedicated GPU-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 700. Optionally, GPU link 710 is coupled to a high-speed interconnect to transmit data to other GPGPUs or parallel processors and receive data from other GPGPUs or parallel processors. Multiple instances of GPGPU 700 can be located in separate data processing systems and can communicate via a network device, which can be accessed via a host interface 702. In addition to or in lieu of host interface 702 , GPU link 710 may be configured to enable connection to a host processor.

[0197] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, alternative configurations of GPGPU 700 can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, relative to the training configuration, GPGPU 700 includes fewer processing clusters in the processing clusters 706A-706H. In addition, the memory technology associated with the memory 714A-714B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer or floating point dot product instructions, which are typically used during inference operations for deployed neural networks.

[0198] Figure 8 A multi-GPU computing system 800 is illustrated. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. The host interface switch 804 may be a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 can communicate with the set of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be Figure 7806A-806D may be interconnected via a set 816 of high-speed point-to-point GPU-GPU links. The high-speed GPU-GPU links may be connected to each of the GPUs 806A-806D via a dedicated GPU link, such as a Figure 7 P2P GPU link 816 enables direct communication between each of GPGPUs 806A-806D without requiring communication over a host interface bus to which processor 802 is connected. With GPU-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or for communicating with other instances of multi-GPU computing system 800, for example, via one or more network devices. Figure 8 806A-806D are connected to processor 802 via host interface switch 804, but processor 802 may additionally include direct support for P2P GPU link 8056 and connect directly to GPGPU 806A-806D. In one embodiment, P2P GPU link 806 enables multi-GPU computing system 800 to operate as a single logical GPU.

[0199] Machine Learning Neural Network Implementation

[0200] The computing architecture described herein can be configured to perform parallel processing of a type particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions having a graph relationship. As is known in the art, there are various types of neural network implementations for machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0201] The second exemplary type of neural network is a convolutional neural network (CNN). CNN is a specialized feedforward neural network for processing data (such as image data) with a known, grid-like topology. Accordingly, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized as a set of "filters" (feature detectors stimulated by the receptive fields found in the retina), and the output of each filter set is propagated to the nodes in the successive layers of the network. The calculation for CNN includes applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized type of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to the convolution layer can be a multidimensional data array defining the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted by the training process for the neural network.

[0202] A recurrent neural network (RNN) is a series of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of serialized data by sharing parameter data across different parts of the neural network. The architecture for RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at a future time, because at least part of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data that can be composed.

[0203] The figures described below present exemplary feedforward networks, CNN networks, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiments described herein, and that the concepts illustrated are generally applicable to deep neural networks and machine learning techniques in general.

[0204] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Unlike shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition that produces reduced output errors relative to shallow machine learning techniques.

[0205] The deep neural network used in deep learning typically includes a front-end network for performing feature recognition, which is coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the mathematical model. Deep learning enables deep learning to be performed without the need to perform manual feature engineering for the model. In contrast, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is usually specialized for a specific task to be performed, and different models will be used to perform different tasks.

[0206] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. Subsequently, the error values ​​are propagated backward until each neuron has an associated error value that roughly represents the contribution of the neuron to the original output. The network can then learn through those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0207] Figure 9A-9B Illustration of an example convolutional neural network. Fig. 9A The diagram shows the various layers within a CNN. Fig. 9A As shown in , an exemplary CNN for modeling image processing may receive an input 902 describing the red, green, and blue (RGB) components of an input image. The input 902 may be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The outputs from the plurality of convolutional layers may optionally be processed by a collection 908 of fully connected layers. As previously described for feedforward networks, neurons in a fully connected layer have full connections to all activations in the previous layer. The outputs from the fully connected layer 908 may be used to generate output results from the network. Activations within the fully connected layer 908 may be calculated using matrix multiplication instead of convolution. Not all CNN implementations utilize the fully connected layer 908. For example, in some implementations, the convolutional layer 906 may generate the output of the CNN.

[0208] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, as shown in the figure, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the node in the receptive field) is input to the nodes of the subsequent layer. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0209] Fig. 9B Schematic diagram of exemplary computational stages within a convolutional layer of a CNN. An input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a successive convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to the CNN.

[0210] Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to specific regions in the input, which can be determined as local regions associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the weight of the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by successive stages of the convolution layer 914.

[0211] The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) so that the threshold of the activation is zero.

[0212] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a small translation to the input does not change the pooled output. The invariance of local translation can be useful in scenarios where the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations are alternative and additional convolution stages with an increased span relative to the previous convolution stage.

[0213] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or a layer in the fully connected layer 908. For example, Fig. 9A The first convolution layer 904 can output to the second convolution layer 906, and the second convolution layer can output to the first layer in the fully connected layer 908.

[0214] Fig.10 An exemplary recurrent neural network 1000 is illustrated. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be established in various ways and using various functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous sequences of inputs. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given previous sequences of words. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing a recurrent function, a feedback mechanism 1005 for enabling 'memory' of previous states, and an output layer 1006 for outputting results. RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected via a feedback mechanism 1005 based on previous time steps. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) may be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). A given state may be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. Function f is generally nonlinear, such as a hyperbolic tangent function (Tanh), or a variant of the correction function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0215] In addition to the basic CNN and RNN networks described, acceleration for variants of those networks can also be enabled. An example RNN variant is a long short term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies, which may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep belief network, which has a similar structure to CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial set of weights for the neural network. In a further embodiment, acceleration for reinforcement learning is enabled. In reinforcement learning, an artificial agent learns by interacting with its environment. The agent is configured to optimize certain objectives to maximize cumulative rewards.

[0216] Fig.11 The training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 1104. The training framework 1104 can access an untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108.

[0217] To start the training process, initial weights can be chosen randomly or by pre-training using a deep belief network. Subsequently, a training cycle is performed in a supervised or unsupervised manner.

[0218] Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training data set 1102 includes an input paired with an expected output of the input, or when the training data set includes an input with a known output and the output of the neural network is manually graded. The network processes the input and compares the resulting output with the expected output or a set of expected outputs. Errors are then propagated back through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 is converging to a model suitable for generating the correct answer based on known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations to generate inference results 1114 based on the input of new data 1112.

[0219] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data that does not have any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how the individual inputs are related to the entire data set. Unsupervised training can be used to generate a self-organizing map, which is a trained neural network 1108 that is capable of performing a type of operation useful in reducing the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0220] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which a mixture of labeled and unlabeled data having the same distribution is included in the training data set 1102. Incremental learning is a variation of supervised learning in which input data is used continuously to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded in the network during initial training.

[0221] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than using a single computing node.

[0222] Fig. 12Ais a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors or one or more general processing nodes such as Figure 7 700 in a highly parallel general purpose graphics processing unit. As shown, distributed learning can be performed with model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1206.

[0223] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers would not fit into the memory of a single node. In some instances, model parallelism can be particularly useful when performing unsupervised training of large neural networks.

[0224] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from different nodes are then combined. Although different ways to implement data parallelism are possible, all data parallel training methods require techniques to combine the results and synchronize the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data, and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, with the exception that updates to the model are transmitted instead of transmitting parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0225] Combined model and data parallelism 1206 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, where separate GPUs within each node are used to train different parts of the model.

[0226] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-GPU data transfers and accelerated remote data synchronization.

[0227] Fig. 12B 1 is a block diagram illustrating a programmable network interface 1210 and a data processing unit. The programmable network interface 1210 is a programmable network engine that can be used to accelerate network-based computing tasks within a distributed environment. The programmable network interface 1210 can be coupled to a host system via a host interface 1270. The programmable network interface 1210 can be used to accelerate network or storage operations for a CPU or GPU of the host system. The host system can be, for example, a node of a distributed learning system for performing distributed training, such as Fig. 12A The host system can also be a data center node in a data center.

[0228] In one embodiment, access to a remote storage device containing model data may be accelerated by the programmable network interface 1210. For example, the programmable network interface 1210 may be configured to present the remote storage device as a local storage device of the host system. The programmable network interface 1210 may also accelerate remote direct memory access (RDMA) operations performed between a GPU of the host system and a GPU of the remote system. In one embodiment, the programmable network interface 1210 may enable storage functions such as, but not limited to, NVME-oF. The programmable network interface 1210 may also accelerate encryption, data integrity, compression, and other operations for the remote storage device on behalf of the host system, thereby allowing the remote storage device to approach the latency of a storage device directly attached to the host system.

[0229] The programmable network interface 1210 may also perform resource allocation and management on behalf of the host system. Storage security operations may be migrated to the programmable network interface 1210 and performed in coordination with the allocation and management of remote storage resources. Network-based operations for managing access to remote storage devices that would otherwise be performed by the processor of the host system may be performed by the programmable network interface 1210 instead.

[0230] In one embodiment, network and / or data security operations may be migrated from the host system to the programmable network interface 1210. Data center security policies for data center nodes may be handled by the programmable network interface 1210 rather than by the processor of the host system. For example, the programmable network interface 1210 may detect and mitigate attempted network-based attacks (e.g., DDoS) on the host system, thereby preventing the attack from disrupting the availability of the host system.

[0231] The programmable network interface 1210 may include a system on chip (SoC 1220) that executes an operating system via multiple processor cores 1222. The processor core 1222 may include a general-purpose processor (e.g., CPU) core. In one embodiment, the processor core 1222 may also include one or more GPU cores. The SoC 1220 may execute instructions stored on a memory device 1240. The storage device 1250 may store local operating system data. The storage device 1250 and the memory device 1240 may also be used to cache remote data for a host system. The network ports 1260A-1260B enable connection to a network or structure and facilitate network access to the SoC 1220, and facilitate network access to the host system via the host interface 1270. The programmable network interface 1210 may also include an I / O interface 1275, such as a USB interface. The I / O interface 1275 may be used to couple an external device to the programmable network interface 1210 or to couple as a debug interface. Programmable network interface 1210 also includes a management interface 1230 that enables software on a host device to manage and configure programmable network interface 1210 and / or SoC 1220. In one embodiment, programmable network interface 1210 may also include one or more accelerators or GPUs 1245 to accept migration of parallel computing tasks from SoC 1220, a host system, or a remote system coupled via network ports 1260A-1260B.

[0232] Example Machine Learning Applications

[0233] Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision is from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, computer vision applications can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously feasible training data sets, and enables reasoning systems to be deployed using low-power parallel processors.

[0234] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described in this article enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0235] Deep neural networks accelerated by parallel processors have enabled machine learning approaches for automatic speech recognition (ASR). ASR involves creating a function that computes the best possible speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled replacements for the hidden Markov models (HMM) and Gaussian mixture models (GMM) previously used for ASR.

[0236] Parallel processor accelerated machine learning can also be used to accelerate natural language processing. The automatic learning process can utilize statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0237] The parallel processing platform for machine learning can be divided into a training platform and a deployment platform. The training platform is generally highly parallel and includes optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 The general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, the deployed machine learning platform generally includes lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0238] In addition, machine learning techniques can also be applied to accelerate or enhance graphics processing activities. For example, a machine learning model can be trained to recognize output generated by a GPU accelerated application and generate an amplified version of that output. Such techniques can be applied to accelerate the generation of high-resolution images for gaming applications. Various other graphics pipeline activities can benefit from the use of machine learning. For example, a machine learning model can be trained to perform tessellation operations on geometric data to increase the complexity of the geometric model, thereby allowing more detailed geometry to be automatically generated from relatively low-detail geometry.

[0239] Fig.13An exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a trained model is illustrated. SOC 1300 may integrate processing components, including a media processor 1302, a visual processor 1304, a GPGPU 1306, and a multi-core processor 1308. GPGPU 1306 may be a GPGPU described herein, such as GPGPU 700, and multi-core processor 1308 may be a multi-core processor described herein, such as multi-core processors 405-406. SOC 1300 may additionally include an on-chip memory 1305, which may enable a shared on-chip data pool that can be accessed by each of the processing components. The processing components may be optimized for low-power operation to enable deployment of various machine learning platforms including autonomous vehicles and autonomous robots. For example, an implementation of SOC 1300 may be used as part of a master control system for an autonomous vehicle. In the case where SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0240] During operation, the media processor 1302 and the visual processor 1304 can work in tandem to accelerate computer vision operations. The media processor 1302 can enable low latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare the frames for processing using a trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for a CNN that is used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0241] The multi-core processor 1308 may include control logic for assisting in sequencing and synchronizing data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor for executing software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and steering logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or computational workloads may be issued to the multi-core processor 1308, which may migrate at least a portion of those operations to the GPGPU 1306.

[0242] GPGPU 1306 may include a computing cluster, such as low-power configuration processing clusters 706A-706H within general purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions specifically optimized to perform inference calculations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision calculations such as 8-bit and 4-bit integer vector operations.

[0243] Additional System Overview

[0244] Fig.14 is a block diagram of processing system 1400 . Fig.14 Elements with the same or similar names as elements of any other figures herein describe the same elements as in the other figures, may operate or run in a similar manner as in the other figures, may include the same components, and may be linked to other entities, such as, but not limited to, those described elsewhere herein. System 1400 may be used in a number of items: a single-processor desktop computer system, a multi-processor workstation system, or a server system with a large number of processors 1402 or processor cores 1407. System 1400 may be a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device, such as, for use in an Internet-of-things (IoT) device with wired or wireless connectivity to a local area network or a wide area network.

[0245] System 1400 may be a system having Figure 1 For example, in different configurations, processor(s) 1402 or processor(s) core(s) 1407 may be associated with Figure 1 The graphics processor(s) 1408 may correspond to the processor(s) 102. Figure 1 The external graphics processor 1418 may be Figure 1 One of the (one or more) plug-in devices 120.

[0246] The system 1400 may include, be coupled with, or be integrated into: a server-based gaming platform; a gaming console, including gaming and media consoles; a mobile gaming console, a handheld gaming console, or an online gaming console. The system 1400 may be part of a mobile phone, a smart phone, a tablet computing device, or a mobile internet-connected device, such as a laptop computer with low internal storage capacity. The processing system 1400 may also include, be coupled with, or be integrated into: a wearable device, such as a smart watch wearable device; smart glasses or clothing that is enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. The processing system 1400 may include, or may be part of a television or set-top box device. System 1400 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a tractor trailer, an automobile, an electric or electrical cycle, an airplane, or a glider (or any combination thereof). An autonomous vehicle may use system 1400 to process the environment sensed around the vehicle.

[0247] The one or more processors 1402 may include one or more processor cores 1407 for processing instructions that, when executed, perform operations for system and user software. At least one of the one or more processor cores 1407 may be configured to process a specific instruction set 1409. The instruction set 1409 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The one or more processor cores 1407 may process different instruction sets 1409, which may include instructions for facilitating emulation of other instruction sets. The processor core 1407 may also include other processing devices, such as a digital signal processor (DSP).

[0248] The processor 1402 may include a cache memory 1404. Depending on the architecture, the processor 1402 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 1402. In some embodiments, the processor 1402 also uses an external cache (e.g., a third level (L3) cache or a last level cache (Last Level Cache, LLC)) (not shown), which can be shared between the processor cores 1407 using known cache coherence techniques. A register file 1406 may additionally be included in the processor 1402 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1402.

[0249] One or more processors 1402 may be coupled to one or more interface buses 1410 to transmit communication signals, such as address, data, or control signals, between the processor 1402 and other components in the system 1400. In one of these embodiments, the interface bus 1410 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. For example, the processor(s) 1402 may include an integrated memory controller 1416 and a platform controller hub 1430. The memory controller 1416 facilitates communication between memory devices and other components of the system 1400, while the platform controller hub (PCH) 1430 provides connections to I / O devices via a local I / O bus.

[0250] The memory device 1420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. The memory device 1420 may, for example, operate as a system memory for the system 1400 to store data 1422 and instructions 1421 for use when one or more processors 1402 execute applications or processes. The memory controller 1416 is also coupled to an optional external graphics processor 1418, which may communicate with one or more graphics processors 1408 in the processor 1402 to perform graphics operations and media operations. In some embodiments, graphics operations, media operations, and / or computing operations may be assisted by an accelerator 1412, which is a coprocessor that may be configured to perform a specialized set of graphics operations, media operations, or computing operations. For example, the accelerator 1412 may be a matrix multiplication accelerator for optimizing machine learning or computing operations. The accelerator 1412 may be a ray tracing accelerator that may be used to perform ray tracing operations in coordination with the graphics processor 1408. In one embodiment, an external accelerator 1419 may be used instead of the accelerator 1412 or in coordination with the accelerator 1412.

[0251] A display device 1411 may be provided and may be connected to the processor(s) 1402. The display device 1411 may be one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). The display device 1411 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0252] The platform controller hub 1430 enables peripheral devices to be connected to the memory device 1420 and the processor 1402 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1446, a network controller 1434, a firmware interface 1428, a wireless transceiver 1426, a touch sensor 1425, a data storage device 1424 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D Xpoint / Optane, etc.). The data storage device 1424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., PCI, PCI Express). The touch sensor 1425 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 1426 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G or Long-Term Evolution (LTE) transceiver. The firmware interface 1428 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). The network controller 1434 can enable network connection to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus 1410. The audio controller 1446 can be a multi-channel high-definition audio controller. In one of these embodiments, the system 1400 includes an optional traditional I / O controller 1440 for coupling a traditional (e.g., personal system 2 (PS / 2)) device to the system. The platform controller hub 1430 can also be connected to one or more Universal Serial Bus (USB) controllers 1442 to connect to input devices, such as a keyboard and mouse 1443 combination, a camera 1444, or other USB input devices.

[0253] It will be appreciated that the illustrated system 1400 is exemplary and not limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 1416 and the platform controller hub 1430 may be integrated into a discrete external graphics processor, such as the external graphics processor 1418. The platform controller hub 1430 and / or the memory controller 1416 may be external to the one or more processors 1402. For example, the system 1400 may include the external memory controller 1416 and the platform controller hub 1430, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 1402.

[0254] For example, a circuit board ("sled") may be used on which components (such as CPUs, memory and other components) are placed and designed to achieve improved thermal performance. Processing components such as processors may be located on the top side of the sled, while nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the enhanced airflow provided by the design, components can operate at higher frequencies and power levels than in typical systems, thereby improving performance. In addition, the sled is configured to blindly mate power and data communication cables in the rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled and / or replaced. Similarly, the various components (such as processors, accelerators, memory and data storage drives) located on the sled are configured to be easily upgraded due to their increased spacing from each other. In an illustrative embodiment, the components additionally include hardware authentication features for proving their authenticity.

[0255] The data center may utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and omni-path. The sleds may be coupled to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center may, in use, centralize physically dispersed resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and data storage drives, and provide them to computing resources (e.g., processors) as needed, thereby enabling the computing resources to access these centralized resources as if the centralized resources were local.

[0256] A power supply or power source may provide voltage and / or current to the system 1400 or any component or system described herein. In one example, the power supply includes an AC-DC (alternating current-direct current) adapter for plugging into a wall socket. Such AC power may be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. The power source or power supply may include wireless charging hardware for charging by approaching a charging field. The power source may include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell source.

[0257] Figure 15A-Figure 15C Illustration of a computing system and a graphics processor. Figure 15A-Figure 15CElements having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0258] Fig.15A 1 is a block diagram of a processor 1500, which may be a variant of one of the processors 1402 and may be used in place of one of those processors. Thus, the disclosure of any feature herein in conjunction with the processor 1500 also discloses the corresponding combination with (one or more) processors 1402, but is not limited thereto. The processor 1500 may have one or more processor cores 1502A-1502N, an integrated memory controller 1514, and an integrated graphics processor 1508. In the case where the integrated graphics processor 1508 is excluded, a system including the processor will include a graphics processor device within a system chipset or coupled via a system bus. The processor 1500 may include additional cores up to and including the additional core 1502N represented by the dashed box. Each of the processor cores 1502A-1502N includes one or more internal cache units 1504A-1504N. In some embodiments, each processor core 1502A-1502N also has access to one or more shared cache units 1506. The internal cache units 1504A-1504N and the shared cache unit 1506 represent a cache memory hierarchy within the processor 1500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a second level (L2), third level (L3), fourth level (L4), or other level of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between each cache unit 1506 and 1504A-1504N.

[0259] The processor 1500 may also include a set of one or more bus controller units 1516 and a system agent core 1510. The one or more bus controller units 1516 manage a set of peripheral buses, such as one or more PCI buses or PCI Express buses. The system agent core 1510 provides management functions for various processor components. The system agent core 1510 may include one or more integrated memory controllers 1514 for managing access to various external memory devices (not shown).

[0260] For example, one or more of the processor cores 1502A-1502N may include support for simultaneous multithreaded operations. The system agent core 1510 includes components for coordinating and operating the cores 1502A-1502N during multithreaded processing. The system agent core 1510 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1502A-1502N and the graphics processor 1508.

[0261] The processor 1500 may additionally include a graphics processor 1508 for performing graphics processing operations. In some of these embodiments, the graphics processor 1508 is coupled to a set of shared cache units 1506 and a system agent core 1510, which includes one or more integrated memory controllers 1514. The system agent core 1510 may also include a display controller 1511 for driving the graphics processor output to one or more coupled displays. The display controller 1511 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1508.

[0262] A ring-based interconnect 1512 may be used to couple internal components of the processor 1500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some of these embodiments with a ring-based interconnect 1512, the graphics processor 1508 is coupled to the ring-based interconnect 1512 via an I / O link 1513.

[0263] Exemplary I / O link 1513 represents at least one of a plurality of various I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance memory module 1518, such as an eDRAM module or a high-bandwidth memory (HBM) module. Optionally, each of processor cores 1502A-1502N and graphics processor 1508 can use high-performance memory module 1518 as a shared last-level cache.

[0264] The processor cores 1502A-1502N may be, for example, isomorphic cores that execute the same instruction set architecture. Alternatively, the processor cores 1502A-1502N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 1502A-1502N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. The processor cores 1502A-1502N may be heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. As another example, the processor cores 1502A-1502N are heterogeneous in terms of computing power. In addition, the processor 1500 may be implemented on one or more chips, or as a SoC integrated circuit having the illustrated components in addition to other components.

[0265] Fig. 15B is a block diagram of the hardware logic of the graphics processor core block 1519 according to some embodiments described herein. In some embodiments, Fig. 15B Elements having the same reference numbers (or names) as elements of any other figure herein may operate or function in a manner similar to that described elsewhere herein. In one embodiment, graphics processor core block 1519 is an example of a partition of a graphics processor. Graphics processor core block 1519 may be included in Fig.15A The graphics processor described herein may include multiple graphics core blocks based on a target power and performance envelope. Each graphics processor core block 1519 may include a functional block 1530 coupled to multiple graphics cores 1521A-1521F, and the graphics cores 1521A-1521F include modular blocks of fixed function logic and general programmable logic. The graphics processor core block 1519 also includes a shared / cache memory 1536 accessible by all graphics cores 1521A-1521F, rasterizer logic 1537, and additional fixed function logic 1538.

[0266] In some embodiments, functional block 1530 includes a geometry / fixed function pipeline 1531 that can be shared by all graphics cores in graphics processor core block 1519. In various embodiments, geometry / fixed function pipeline 1531 includes a 3D geometry pipeline, a video front end unit, a thread generator and a global thread dispatcher, and a unified return buffer manager that manages a unified return buffer. In one embodiment, functional block 1530 also includes a graphics SoC interface 1532, a graphics microcontroller 1533, and a media pipeline 1534. Graphics SoC interface 1532 provides an interface between graphics processor core block 1519 and other core blocks within a graphics processor or computing accelerator SoC. Graphics microcontroller 1533 is a programmable subprocessor that can be configured to manage various functions of graphics processor core block 1519, including thread dispatching, scheduling, and preemption. Media pipeline 1534 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data including image and video data. The media pipeline 1534 implements media operations via requests to computational or sampling logic within the graphics cores 1521-1521F. One or more pixel backends 1535 may also be included within the functional block 1530. The pixel backend 1535 includes a cache memory that stores pixel color values ​​and can perform blending operations and lossless color compression of rendered pixel data.

[0267] In one embodiment, the graphics SoC interface 1532 enables the graphics processor core block 1519 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC or a system host CPU coupled to the SoC via a peripheral interface. The graphics SoC interface 1532 also enables communication with off-chip memory hierarchy elements, such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 1532 may also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomicity, which may be shared between the graphics processor core block 1519 and the CPU within the SoC. The graphics SoC interface 1532 may also implement power management controls for the graphics processor core block 1519 and enable interfaces between the clock domain of the graphics processor core block 1519 and other clock domains within the SoC. In one embodiment, graphics SoC interface 1532 enables receiving command buffers from a command stream converter and global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. When media operations are to be performed, these commands and instructions can be dispatched to media pipeline 1534, and when graphics processing operations are to be performed, these commands and instructions can be dispatched to geometry and fixed function pipeline 1531. When compute operations are to be performed, compute dispatch logic can dispatch commands to graphics cores 1521A-1521F, thereby bypassing the geometry and media pipelines.

[0268] The graphics microcontroller 1533 may be configured to perform various scheduling and management tasks for the graphics processor core block 1519. In one embodiment, the graphics microcontroller 1533 may perform graphics and / or computational workload scheduling on the various vector engines 1522A-1522F, 1524A-1524F and matrix engines 1523A-1523F, 1525A-1525F within the graphics cores 1521A-1521F. In this scheduling model, host software executing on a CPU core of a SoC including the graphics processor core block 1519 may submit a workload to one of a plurality of graphics processor doorbells, which invokes a scheduling operation to the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to a command stream converter, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In one embodiment, the graphics microcontroller 1533 may also facilitate a low power or idle state for the graphics processor core block 1519, thereby providing the graphics processor core block 1519 with the ability to save and restore registers within the graphics processor core block 1519 across low power state transitions, independent of the operating system and / or graphics driver software on the system.

[0269] The graphics processor core block 1519 may have more or less than the illustrated graphics cores 1521A-1521F, up to N modular graphics cores. For each set of N graphics cores, the graphics processor core block 1519 may also include a shared / cache memory 1536, which may be configured as a shared memory or cache memory, a rasterizer logic 1537, and additional fixed function logic 1538 to accelerate various graphics and computational processing operations.

[0270] Within each graphics core 1521A-1521F is a collection of execution resources that can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. Graphics cores 1521A-1521F include multiple vector engines 1522A-1522F, 1524A-1524F, matrix acceleration units 1523A-1523F, 1525A-1525D, cache / shared local memory (SLM), samplers 1526A-1526F, and ray tracing units 1527A-1527F.

[0271] The vector engines 1522A-1522F, 1524A-1524F are general purpose graphics processing units that are capable of performing floating point and integer / fixed point logic operations in the service of graphics, media, or computing operations (including graphics, media, or computing / GPGPU programs). The vector engines 1522A-1522F, 1524A-1524F can operate at variable vector widths using SIMD, SIMT, or SIMT+SIMD execution modes. The matrix acceleration units 1523A-1523F, 1525A-1525D include matrix-matrix and matrix-vector acceleration logic that improves the performance of matrix operations, particularly low-precision and mixed-precision (e.g., INT8, FP16, BF16, FP8) matrix operations for machine learning. In one embodiment, each of the matrix acceleration units 1523A-1523F, 1525A-1525D includes one or more systolic arrays of processing elements that can perform concurrent matrix multiplication or dot product operations on matrix elements.

[0272] Samplers 1526A-1526F can read media or texture data into memory and can sample data differently based on the configured sampler state and the texture / media format being read. Threads executing on vector engines 1522A-1522F, 1524A-1524F or matrix acceleration units 1523A-1523F, 1525A-1525D can utilize caches / SLMs 1528A-1528F within each of graphics cores 1521A-1521F. Caches / SLMs 1528A-1528F can be configured as cache memory or a shared memory pool that is local to each of the respective graphics cores 1521A-1521F. Ray tracing units 1527A-1527F within graphics cores 1521A-1521F include ray traversal / intersection circuitry for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the volume of the BVH. In one embodiment, ray tracing units 1527A-1527F include circuitry for performing depth testing and culling (e.g., using a depth buffer or similar arrangement). In one implementation, ray tracing units 1527A-1527F perform traversal and intersection operations in concert with image denoising, at least a portion of which may be performed using associated matrix acceleration units 1523A-1523F, 1525A-1525D.

[0273] Fig. 15C1 is a block diagram of a general purpose graphics processor unit (GPGPU) 1570 according to an embodiment described herein, which GPGPU 1570 can be configured as a graphics processor (e.g., graphics processor 1508) and / or a computing accelerator. GPGPU 1570 can be interconnected with a host processor (e.g., one or more CPUs 1546) and memories 1571, 1572 via one or more system and / or memory buses. Memory 1571 can be system memory that can be shared with one or more CPUs 1546, while memory 1572 is device memory dedicated to GPGPU 1570. For example, components within GPGPU 1570 and device memory 1572 can be mapped to memory addresses accessible by one or more CPUs 1546. Access to memories 1571 and 1572 can be facilitated via a memory controller 1568. Memory controller 1568 can include an internal direct memory access (DMA) controller 1569, or can include logic for performing operations that would otherwise be performed by a DMA controller.

[0274] GPGPU 1570 includes a plurality of cache memories, including an L2 cache 1553, an L1 cache 1554, an instruction cache 1555, and a shared memory 1556, at least a portion of which may also be partitioned as cache memories. GPGPU 1570 also includes a plurality of compute units 1560A-1560N. Each compute unit 1560A-1560N includes a set 1561 of vector registers, a set 1562 of scalar registers, a set 1563 of vector logic units, and a set 1564 of scalar logic units. Computing units 1560A-1560N may also include a local shared memory 1565 and a program counter 1566. Computing units 1560A-1560N may be coupled to a constant cache 1567, which may be used to store constant data, which is data that will not change during the execution of a kernel or shader program executed on GPGPU 1570. The constant cache 1567 may be a scalar data cache, and the cached data may be fetched directly into the scalar register 1562 .

[0275] During operation, one or more CPUs 1546 may write commands to registers in GPGPU 1570, or to memory in GPGPU 1570 that has been mapped into an accessible address space. Command processor 1557 may read commands from registers or memory and determine how to process those commands within GPGPU 1570. Thread dispatcher 1558 may then be used to dispatch threads to computing units 1560A-1560N to execute those commands. Each computing unit 1560A-1560N may execute threads independently of other computing units. In addition, each computing unit 1560A-1560N may be independently configured for conditional computation, and may conditionally output the results of the computation to memory. Command processor 1557 may interrupt one or more CPUs 1546 when the submitted commands are completed.

[0276] Figure 16A-16C The diagram is described in this article, for example according to Figure 15A-Figure 15C The embodiments provide block diagrams of additional graphics processor and computing accelerator architectures. Figure 16A-16C Elements having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0277] Fig.16A 1 is a block diagram of a graphics processor 1600, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores or other semiconductor devices, such as but not limited to memory devices or network interfaces. Graphics processor 1600 may be a variant of graphics processor 1508 and may be used in place of graphics processor 1508. Therefore, the disclosure of any feature in conjunction with graphics processor 1508 herein also discloses the corresponding combination with graphics processor 1600, but is not limited thereto. The graphics processor may communicate via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. Graphics processor 1600 may include a memory interface 1614 for accessing memory. Memory interface 1614 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0278] Optionally, the graphics processor 1600 also includes a display controller 1602 for driving display output data to a display device 1618. The display controller 1602 includes hardware for compositing one or more overlay planes of a display and multiple layers of video or user interface elements. The display device 1618 can be an internal or external display device. In one embodiment, the display device 1618 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. The graphics processor 1600 may include a video codec engine 1606 for encoding media to one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9), and the Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0279] Graphics processor 1600 may include a block image transfer (BLIT) engine 1603 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, alternatively, 2D graphics operations may be performed using one or more components of a graphics processing engine (GPE) 1610. In some embodiments, GPE 1610 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0280] GPE 1610 may include a 3D pipeline 1612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1612 includes programmable and fixed-function elements that perform various tasks within the element and / or spawn execution threads to 3D / media subsystem 1615. While 3D pipeline 1612 may be used to perform media operations, embodiments of GPE 1610 also include a media pipeline 1616 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0281] The media pipeline 1616 may include fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 1606. The media pipeline 1616 may additionally include a thread generation unit for generating threads for execution on the 3D / media subsystem 1615. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1615.

[0282] 3D / media subsystem 1615 may include logic for executing threads generated by 3D pipeline 1612 and media pipeline 1616. The pipeline may send thread execution requests to 3D / media subsystem 1615, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. Execution resources include an array of graphics execution units for processing 3D threads and media threads. 3D / media subsystem 1615 may include one or more internal caches for thread instructions and data. In addition, 3D / media subsystem 1615 may also include shared memory for sharing data between threads and for storing output data, which includes registers and addressable memory.

[0283] Fig. 16B Graphics processor 1620 is shown, which is a variant of graphics processor 1600 and can be used in place of graphics processor 1600 and vice versa. Therefore, any feature disclosed herein in conjunction with graphics processor 1600 also discloses the corresponding combination with graphics processor 1620, but is not limited thereto. According to the embodiments described herein, graphics processor 1620 has a sliced ​​architecture. Graphics processor 1620 may include graphics processing engine cluster 1622, which has graphics engine slices 1610A-1610D. Fig.16A1624. The graphics processor engine 1610 of the embodiment of the present invention may be a plurality of instances of the graphics processor engine 1610. Each graphics engine slice 1610A-1610D may be interconnected via a set of slice interconnects 1623A-1623F. Each graphics engine slice 1610A-1610D may also be connected to a memory module or memory device 1626A-1626D via a memory interconnect 1625A-1625D. The memory device 1626A-1626D may use any graphics memory technology. For example, the memory device 1626A-1626D may be a graphics double data rate (GDDR) memory. The memory device 1626A-1626D may be a high-bandwidth memory (HBM) module, which may be on the die with its corresponding graphics engine slice 1610A-1610D. The memory devices 1626A-1626D may be stacked memory devices that may be stacked on top of their respective graphics engine slices 1610A-1610D. Each graphics engine slice 1610A-1610D and associated memory 1626A-1626D may reside on separate chiplets that are bonded to a base die or base substrate, such as in Figure 24B-Figure 24D As described in further detail in .

[0284] The graphics processor 1620 may be configured with a non-uniform memory access (NUMA) system in which memory devices 1626A-1626D are coupled to associated graphics engine slices 1610A-1610D. A given memory device may be accessed by a slice different from the graphics engine slice to which the memory device is directly connected. However, when accessing the local slice, the access latency to the memory devices 1626A-1626D may be minimized. In one embodiment, a cache coherent NUMA (ccNUMA) system is enabled that uses slice interconnects 1623A-1623F to enable communication between cache controllers within the graphics engine slices 1610A-1610D to maintain consistent memory mirroring when more than one cache stores the same memory location.

[0285] The graphics processing engine cluster 1622 may be connected to an on-chip or on-package fabric interconnect 1624. In one embodiment, the fabric interconnect 1624 includes a network processor, a network on a chip (NoC), or another switching processor for enabling the fabric interconnect 1624 to function as a packet-switched fabric interconnect for exchanging data packets between components of the graphics processor 1620. The fabric interconnect 1624 may enable communication between the graphics engine slices 1610A-1610D and components such as the video codec 1606 and one or more replica engines 1604. The replica engines 1604 may be used to move data out of the memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory), move data into the memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory), and move data between the memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory). Fabric interconnect 1624 may also be used to interconnect graphics engine slices 1610A-1610D. Graphics processor 1620 may optionally include display controller 1602 to enable connection to external display device 1618. Graphics processor may also be configured as a graphics accelerator or a computing accelerator. In an accelerator configuration, display controller 1602 and display device 1618 may be omitted.

[0286] Graphics processor 1620 may be connected to a host system via host interface 1628. Host interface 1628 may enable communication between graphics processor 1620, system memory, and / or other system components. Host interface 1628 may be, for example, a PCI Express bus or another type of host system interface. For example, host interface 1628 may be an NVLink or NVSwitch interface. Host interface 1628 and fabric interconnect 1624 may collaborate to enable multiple instances of graphics processor 1620 to act as a single logical device. Collaboration between host interface 1628 and fabric interconnect 1624 may also enable individual graphics engine slices 1610A-1610D to be presented to the host system as different logical graphics devices.

[0287] Fig. 16C FIG. 16 shows a computing accelerator 1630 according to an embodiment described herein. The computing accelerator 1630 may include Fig. 16BThe computing engine cluster 1632 may have an architectural similarity to the graphics processor 1620 of the present invention and is optimized for computing acceleration. The computing engine cluster 1632 may include a set 1640A-1640D of computing engine slices, and the set 1640A-1640D of computing engine slices includes execution logic optimized for parallel or vector-based general computing operations. The computing engine slices 1640A-1640D may not include fixed-function graphics processing logic, but in some embodiments, one or more of the computing engine slices 1640A-1640D may include logic for performing media acceleration. The computing engine slices 1640A-1640D may be connected to the memory 1626A-1626D via the memory interconnect 1625A-1625D. The memory 1626A-1626D and the memory interconnect 1625A-1625D may be similar technologies as in the graphics processor 1620, or may be different technologies. The graphics compute engine slices 1640A-1640D may also be interconnected via a set of slice interconnects 1623A-1623F and may be connected to and / or interconnected through a fabric interconnect 1624. In one embodiment, the compute accelerator 1630 includes a large L3 cache 1636 that may be configured as a device-wide cache. The compute accelerator 1630 may also be configured to communicate with Fig. 16B Graphics processor 1620 is similarly connected to a host processor and memory via host interface 1628 .

[0288] The computing accelerator 1630 may also include an integrated network interface 1642. In one embodiment, the integrated network interface 1642 includes a network processor and controller logic that enables the computing engine cluster 1632 to communicate over a physical layer interconnect 1644 without the data having to cross the memory of the host system. In one embodiment, one of the computing engine slices 1640A-1640D is replaced by the network processor logic, and the data to be transmitted or received via the physical layer interconnect 1644 can be directly transmitted to or from the memory 1626A-1626D. Multiple instances of the computing accelerator 1630 can be combined into a single logical device via the physical layer interconnect 1644. Alternatively, each computing engine slice 1640A-1640D can be presented as a different network accessible computing accelerator device.

[0289] Graphics processing engine

[0290] Fig.17 is a block diagram of a graphics processing engine 1710 of a graphics processor according to some embodiments. The graphics processing engine (GPE) 1710 may be Fig.16A A version of the GPE 1610 shown in FIG. 1610 and may also represent Fig. 16B Graphics engine slices 1610A-1610D. Fig.17 Elements with the same or similar names as elements of any other figure herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein. For example, in Fig.17 Also shown in the figure Fig.16A 1710. The 3D pipeline 1612 and the media pipeline 1616 of the GPE 1710. The media pipeline 1616 is optional in some embodiments of the GPE 1710 and may not be explicitly included in the GPE 1710. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 1710.

[0291] The GPE 1710 may be coupled to or include a command stream converter 1703 that provides a command stream to the 3D pipeline 1612 and / or the media pipeline 1616. Alternatively or additionally, the command stream converter 1703 may be directly coupled to a unified return buffer 1718. The unified return buffer 1718 may be communicatively coupled to the graphics core cluster 1714. Optionally, the command stream converter 1703 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. The command stream converter 1703 may receive commands from the memory and send these commands to the 3D pipeline 1612 and / or the media pipeline 1616. These commands are instructions taken from a ring buffer that stores commands for the 3D pipeline 1612 and the media pipeline 1616. The ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for 3D pipeline 1612 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for 3D pipeline 1612 and / or image data and memory objects for media pipeline 1616. 3D pipeline 1612 and media pipeline 1616 process commands and data by performing operations via logic within the corresponding pipelines or by dispatching one or more execution threads to graphics core cluster 1714. Graphics core cluster 1714 may include one or more blocks of graphics cores (e.g., graphics core block 1715A, graphics core block 1715B), each block including one or more graphics cores. Each graphics core includes a collection of graphics execution resources, including: general and graphics-specific execution logic for performing graphics operations and compute operations; and fixed-function texture processing logic and / or machine learning and artificial intelligence acceleration logic.

[0292] In various embodiments, the 3D pipeline 1612 may include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core cluster 1714. The graphics core cluster 1714 provides a unified execution resource block for use in processing these shader programs. The multi-function execution logic (e.g., execution units) within the graphics core blocks 1715A-1715B of the graphics core cluster 1714 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0293] Graphics core cluster 1714 may include execution logic for performing media functions such as video and / or image processing. In addition to graphics processing operations, the execution units may also include general purpose logic that can be programmed to perform parallel general purpose computing operations. The general purpose logic may be performed in parallel or in combination with Fig.14 (one or more) processor cores 1407 or Fig.15A The processing operations are performed by the general logic within cores 1502A-1502N.

[0294] Output data generated by threads executing on graphics core cluster 1714 can output data to memory in unified return buffer (URB) 1718. URB 1718 can store data for multiple threads. URB 1718 can be used to send data between different threads executing on graphics core cluster 1714. URB 1718 can additionally be used for synchronization between threads on graphics core cluster 1714 and fixed function logic within shared function logic 1720.

[0295] Optionally, graphics core cluster 1714 may be scalable such that the array includes a variable number of graphics cores, each with a variable number of execution units based on the target power and performance level of GPE 1710. Execution resources may be dynamically scalable such that execution resources may be enabled or disabled as needed.

[0296] The graphics core cluster 1714 is coupled to shared function logic 1720, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 1720 are hardware logic units that provide specialized, supplementary functions to the graphics core cluster 1714. In various embodiments, the shared function logic 1720 includes, but is not limited to, sampler 1721 logic, math 1722 logic, and inter-thread communication (ITC) 1723 logic. In addition, one or more caches 1725 within the shared function logic 1720 may be implemented.

[0297] Shared functionality is implemented at least in cases where demand for a given specialized functionality is insufficient to include in graphics core cluster 1714. Instead, a single instantiation of that specialized functionality is implemented as an independent entity in shared functionality logic 1720 and shared between execution resources within graphics core cluster 1714. The exact set of functionality shared between graphics core clusters 1714 and included within graphics core cluster 1714 varies from embodiment to embodiment. Specific shared functionality within shared functionality logic 1720 that is widely used by graphics core cluster 1714 may be included within shared functionality logic 1716 within graphics core cluster 1714. Optionally, shared functionality logic 1716 within graphics core cluster 1714 may include some or all of the logic within shared functionality logic 1720. All logic elements within shared functionality logic 1720 may be replicated within shared functionality logic 1716 of graphics core cluster 1714. Alternatively, shared functionality logic 1720 is excluded in favor of shared functionality logic 1716 within graphics core cluster 1714.

[0298] Graphics processing resources

[0299] Figures 18A-18C illustrates execution logic including an array of processing elements employed in a graphics processor according to embodiments described herein; Fig.18A illustrates a graphics core cluster according to an embodiment; Fig.18B illustrates a vector engine of a graphics core according to an embodiment; Fig.18C Illustrated is a matrix engine of a graphics core according to an embodiment. Figures 18A-18C Elements in FIG. 1 having the same reference numerals as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. For example, Fig. 15B The graphics processor core block 1519 and / or Fig.17 Considered in the context of the graphics core blocks 1715A-1715B Figures 18A-18C In one embodiment, Figures 18A-18C The components have Fig.15A Graphics processor 1508 or Fig. 15C The GPGPU 1570 is an equivalent component with similar functionality.

[0300] like Fig.18A As shown in FIG. 1 , in one embodiment, graphics core cluster 1714 includes graphics core block 1715, which may be Fig.17 Graphics core block 1715 may include any number of graphics cores (e.g., graphics core 1815A, graphics core 1815B through graphics core 1815N). Multiple instances of graphics core block 1715 may be included. In one embodiment, the components of graphics cores 1815A-1815N have the same Fig. 15B In such embodiments, graphics cores 1815A-1815N each include circuitry including, but not limited to, vector engines 1802A-1802N, matrix engines 1803A-1803N, memory load / store units 1804A-1804N, instruction caches 1805A-1805N, data caches / shared local memories 1806A-1806N, ray tracing units 1808A-1808N, and samplers 1810A-1810N. The circuitry of graphics cores 1815A-1815N may additionally include fixed function logic 1812A-1812N. The number of vector engines 1802A-1802N and matrix engines 1803A-1803N within a design's graphics core 1815A-1815N may vary based on the workload, performance, and power targets of the design.

[0301] With reference to graphics core 1815A, vector engine 1802A and matrix engine 1803A can be configured to perform parallel computing operations on data in various integer and floating point data formats based on instructions associated with shader programs. Each vector engine 1802A and matrix engine 1803A can act as a programmable general-purpose computing unit that can execute multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. Vector engine 1802A and matrix engine 1803A support processing variable width vectors with various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. Input data elements can be stored in registers as compact data types, and vector engine 1802A and matrix engine 1803A can process various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the vector is processed as four independent 64-bit packed data elements (quad-word (QW)) size data elements), eight independent 32-bit packed data elements (double-word (DW)) size data elements), sixteen independent 16-bit packed data elements (word (W) size data elements) or thirty-two independent 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. In one embodiment, the vector engine 1802A and the matrix engine 1803A can also be configured for SIMT operations on warps or thread groups of various sizes (e.g., 8, 16 or 32 threads).

[0302] Continuing with graphics core 1815A, memory load / store unit 1804A services memory access requests issued by vector engine 1802A, matrix engine 1803A, and / or other components of graphics core 1815A that have access to memory. Memory access requests may be processed by memory load / store unit 1804A to load or store the requested data into or into a register file associated with vector engine 1802A and / or matrix engine 1803A, or from a cache or memory. Memory load / store unit 1804A may also perform prefetch operations. Also refer to Fig.19In one embodiment, memory load / store unit 1804A is configured to provide SIMT scatter / gather prefetches or block prefetches of data stored in memory 1910 from memory local to other slices, or from system memory, via slice interconnect 1908. Prefetches may be performed to a specific L1 cache (e.g., data cache / shared local memory 1806A), L2 cache 1904, or L3 cache 1906. In one embodiment, prefetches to L3 cache 1906 automatically cause the data to be stored in L2 cache 1904.

[0303] Instruction cache 1805A stores instructions to be executed by graphics core 1815A. In one embodiment, graphics core 1815A also includes instruction acquisition and pre-fetch circuits that acquire or pre-fetch instructions into instruction cache 1805A. Graphics core 1815A also includes instruction decoding logic to decode instructions within instruction cache 1805A. Data cache / shared local memory 1806A can be configured as a data cache managed by a cache controller that implements a cache replacement strategy and / or configured as an explicitly managed shared memory. Ray tracing unit 1808A includes circuits that accelerate ray tracing operations. Sampler 1810A provides texture sampling for 3D operations and media sampling for media operations. Fixed function logic 1812A includes fixed function circuits shared between various instances of vector engine 1802A and matrix engine 1803A. Graphics cores 1815B-1815N can operate in a similar manner to graphics core 1815A.

[0304] The functions of instruction caches 1805A-1805N, data caches / shared local memory 1806A-1806N, ray tracing units 1808A-1808N, samplers 1810A-1810N, and fixed function logic 1812A-1812N correspond to equivalent functions in the graphics processor architecture described herein. For example, instruction caches 1805A-1805N may be used in the same manner as Fig. 15C The data cache / shared local memory 1806A-1806N, ray tracing units 1808A-1808N, and samplers 1810A-1810N can operate in a manner similar to the instruction cache 1555 of FIG. Fig. 15B The cache / SLM 1528A-1528F, ray tracing units 1527A-1527F, and samplers 1526A-1526F of the fixed function logic 1812A-1812N may include Fig. 15B In one embodiment, ray tracing units 1808A-1808N include components of geometry / fixed function pipeline 1531 and / or additional fixed function logic 1538. Figure 3C The ray tracing core 372 is a circuit that performs ray tracing acceleration operations.

[0305] like Fig.18B As shown in FIG. 1 , in one embodiment, the vector engine 1802 includes an instruction fetch unit 1837, a general register file array (GRF) 1824, an architectural register file array (ARF) 1826, a thread arbiter 1822, an issue unit 1830, a branch unit 1832, a set of SIMD floating-point units (FPUs) 1834, and a set of integer SIMD ALUs 1835, which in one embodiment includes an integer SIMD ALU. The GRF 1824 and ARF 1826 include a set of general register files and architectural register files associated with each hardware thread that may be active in the vector engine 1802. In one embodiment, the architectural state of each thread is maintained in the ARF 1826, while data used during thread execution is stored in the GRF 1824. The execution state of each thread, including the instruction pointer of each thread, can be saved in thread-specific registers in the ARF 1826. Register renaming can be used to dynamically assign registers to hardware threads.

[0306] In one embodiment, vector engine 1802 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per graphics core, where graphics core resources are divided across logic for executing multiple simultaneous threads. The number of logical threads that can be executed by vector engine 1802 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0307] In one embodiment, the vector engine 1802 can issue multiple instructions together, and these instructions can be different instructions respectively. The thread arbiter 1822 can dispatch instructions to one of the send unit 1830, the branch unit 1832 or (one or more) SIMD FPU 1834 for execution. Each execution thread can access 128 general registers in the GRF 1824, each of which can store 32 bytes and can be accessed as a variable width vector of 32-bit data elements. In one embodiment, each thread has access to 4k bytes in the GRF 1824, although the embodiment is not limited to this, and more or less register resources can be provided in other embodiments. In one embodiment, the vector engine 1802 is partitioned into seven hardware threads, which can perform calculation operations independently, although the number of threads per vector engine 1802 can also vary according to the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment where seven threads can access 4k bytes, the GRF 1824 can store a total of 28k bytes. With 16 threads able to access 4k bytes, the GRF 1824 can store a total of 64k bytes. Flexible addressing modes can permit registers to be addressed together to efficiently construct wider registers or to represent spanning rectangular blocks of data structures.

[0308] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed through message passing send unit 1830. In one embodiment, branch instructions are dispatched to a dedicated branch unit 1832 to facilitate SIMD divergence and eventual convergence.

[0309] In one embodiment, the vector engine 1802 includes one or more SIMD floating-point units (FPUs) 1834 to perform floating-point operations. In one embodiment, (one or more) FPUs 1834 also support integer calculations. In one embodiment, (one or more) FPUs 1834 can perform up to M 32-bit floating-point (or integer) operations, or perform up to 2M 16-bit integers or 16-bit floating-point operations. In one embodiment, at least one FPU in (one or more) FPUs provides extended mathematical capabilities to support high-throughput transcendental mathematical functions and double-precision 64-bit floating points. In some embodiments, there is also a set 1835 of 8-bit integer SIMD ALUs, and it can be specifically optimized to perform operations associated with machine learning calculations. In one embodiment, the SIMD ALU is replaced by a set 1834 of additional SIMD FPUs, which are configurable to perform integer and floating-point operations. In one embodiment, SIMDFPU 1834 and SIMD ALU 1835 are configurable to execute SIMT programs. In one embodiment, combined SIMD+SIMT operations are supported.

[0310] In one embodiment, an array of multiple instances of vector engine 1802 can be instantiated in the graphics core. For scalability, product architects can choose the exact number of vector engines per graphics core grouping. In one embodiment, vector engine 1802 can execute instructions across multiple execution lanes. In a further embodiment, each thread executed on vector engine 1802 executes on a different lane.

[0311] like Fig.18CAs shown in, in one embodiment, the matrix engine 1803 includes an array of processing elements, which are configured to perform tensor operations, including vector / matrix and matrix / matrix operations, such as but not limited to matrix multiplication and / or dot product operations. The matrix engine 1803 is configured with M rows and N columns of processing elements (1852AA-1852MN), which include multipliers and adder circuits organized in a pipelined manner. In one embodiment, the processing elements 1852AA-1852MN constitute the physical pipeline stage of the systolic array of N width and M depth, which can be used to perform vector / matrix or matrix / matrix operations in a data parallel manner, including matrix multiplication, fusion multiplication and addition, dot product or other general matrix-matrix multiplication (general matrix-matrixmultiplication, GEMM) operations. In one embodiment, the matrix engine 1803 supports 16-bit and 8-bit floating point operations, as well as 8-bit, 4-bit, 2-bit and binary integer operations. The matrix engine 1803 can also be configured to accelerate specific machine learning operations. In such embodiments, the matrix engine 1803 can be configured to support the bfloat (brain floating point) 16-bit floating point format or the tensor floating point 32-bit floating point format (TF32), which has a different number of mantissa and exponent bits relative to the Institute of Electrical and Electronics Engineers (IEEE) 754 format.

[0312] In one embodiment, during each cycle, each stage may add the result of the operation performed at that stage to the output of the previous stage. In other embodiments, after a set of computation cycles, the data movement pattern between the processing elements 1852AA-1852MN may vary based on the instruction or macro operation being executed. For example, in one embodiment, partial sum loopback is enabled, and the processing element may instead add the output of the current cycle to the output generated in the previous cycle. In one embodiment, the final stage of the systolic array may be configured with a loopback to the initial stage of the systolic array. In such embodiments, the number of physical pipeline stages may be decoupled from the number of logical pipeline stages supported by the matrix engine 1803. For example, where the processing elements 1852AA-1852MN are configured as a systolic array of M physical stages, a loopback from stage M to the initial pipeline stage may enable the processing elements 1852AA-1852MN to operate as a systolic array of, for example, 2M, 3M, 4M, etc. logical pipeline stages.

[0313] In one embodiment, the matrix engine 1803 includes memories 1841A-1841N, 1842A-1842M, which store input data in the form of row and column data of the input matrix. The memories 1842A-1842M can be configured to store the row elements (A0-Am) of the first input matrix, and the memories 1841A-1841N can be configured to store the column elements (B0-Bn) of the second input matrix. The row and column elements are provided as input to the processing elements 1852AA-1852MN for processing. In one embodiment, before the row and column elements of the input matrix are provided to the memories 1841A-1841N, 1842A-1842M, those elements can be stored in the systolic register file 1840 within the matrix engine 1803. In one embodiment, the systolic register file 1840 is excluded, and the memories 1841A-1841N, 1842A-1842M are removed from the associated vector engine (e.g., Fig.18B The GRF 1824 of the vector engine 1802) or other memory of the graphics core including the matrix engine 1803 (e.g., Fig.18A The results generated by the processing elements 1852AA-1852MN are then output to output buffers and / or written to register files (e.g., systolic register files 1840, GRF 1824, data caches / shared local memories 1806A-1806N) for further processing by other functional units of the graphics processor or output to memory.

[0314] In some embodiments, the matrix engine 1803 is configured in the case of supporting input sparsity, wherein the multiplication operation of the sparse area of ​​the input data can be bypassed by skipping the multiplication operation with zero-valued operands. In one embodiment, the processing element 1852AA-1852MN is configured to skip the execution of certain operations with zero-valued inputs. In one embodiment, the sparsity within the input matrix can be detected, and before being submitted to the processing element 1852AA-1852MN, the operation with a known zero output value can be bypassed. The zero-valued operand can be bypassed to load into the processing element, and the processing element 1852AA-1852MN can be configured to perform multiplication on non-zero-valued input elements. The matrix engine 1803 can also be configured in the case of supporting output sparsity, so that the operation with the result predetermined to be zero is bypassed. For input sparsity and / or output sparsity, in one embodiment, metadata is provided to the processing element 1852AA-1852MN to indicate which processing elements and / or data channels will be active during the cycle for the processing cycle.

[0315] In one embodiment, matrix engine 1803 includes hardware for enabling the operation of sparse data with compressed representation of sparse matrix, and the compressed representation stores non-zero values ​​and metadata, and the location of the non-zero values ​​in the metadata identification matrix. Exemplary compressed representation includes but is not limited to compressed tensor representation, such as, compressed sparse row (compressed sparse row, CSR) representation, compressed sparse column (compressed sparse column, CSC) representation and compressed sparse fiber (compressed sparse fiber, CSF) representation. Support for compressed representation enables operation to be performed on input in compressed tensor format without compressed representation being decompressed or decoded. In such embodiments, operations can be performed only on non-zero input values, and the resulting non-zero output values ​​can be mapped to the output matrix. In some embodiments, hardware support for machine-specific lossless data compression formats is also provided, and these machine-specific lossless data compression formats are used when transmitting data in hardware or transmitting data across system buses. Such data may be retained in a compressed format for sparse input data, and the matrix engine 1803 may use compression metadata for the compressed data to enable operations to be performed on only non-zero values ​​or to enable blocks of zero data input to be bypassed for multiplication operations.

[0316] In various embodiments, the input data may be provided by a programmer in a compressed tensor representation, or the codec may compress the input data into a compressed tensor representation or another sparse data encoding. In addition to supporting compressed tensor representations, stream compression of sparse input data may be performed before the data is provided to the processing elements 1852AA-1852MN. In one embodiment, compression is performed on data written to a cache memory associated with the graphics core cluster 1714, the compression being performed using an encoding supported by the matrix engine 1803. In one embodiment, the matrix engine 1803 includes support for inputs with structured sparsity, in which a predetermined level or pattern of sparsity is applied to the input data. The data may be compressed to a known compression ratio, and the processing elements 1852AA-1852MN process the compressed data based on metadata associated with the compressed data.

[0317] Fig.19 FIG. 19 shows a slice 1900 of a multi-slice processor according to an embodiment. In one embodiment, slice 1900 represents Fig. 16B Graphics engine chip 1610A-1610D or Fig. 16CThe slice 1900 of the multi-slice graphics processor includes an array of graphics core clusters (e.g., graphics core cluster 1714A, graphics core cluster 1714B to graphics core cluster 1714N), each graphics core cluster having an array of graphics cores 515A-515N. The slice 1900 also includes a global dispatcher 1902 for dispatching threads to processing resources of the slice 1900.

[0318] Slice 1900 may include or be coupled with an L3 cache 1906 and a memory 1910. In various embodiments, L3 cache 1906 may be excluded or slice 1900 may include additional levels of cache, such as an L4 cache. In one embodiment, each instance of slice 1900 in a multi-slice graphics processor has an associated memory 1910, such as in Fig. 16B and Fig. 16C In one embodiment, the multi-chip processor can be configured as a multi-chip module, where the L3 cache 1906 and / or memory 1910 reside on a chiplet that is separate from the graphics core cluster 1714A-1714N. In this context, a chiplet is an integrated circuit that is at least partially packaged and includes different logic units that can be assembled with other chiplets into a larger package. For example, the L3 cache 1906 may be included in a dedicated cache chiplet, or may reside on the same chiplet as the graphics core cluster 1714A-1714N. In one embodiment, the L3 cache 1906 may be included in an active substrate die or an active interposer, such as Fig.24C As shown in the figure.

[0319] Memory structure 1903 enables communication between graphics core clusters 1714A-1714N, L3 cache 1906, and memory 1910. L2 cache 1904 is coupled to memory structure 1903 and may be configured to cache transactions executed via memory structure 1903. Slice interconnect 1908 enables communication with other slices on the graphics processor and may be Fig. 16B and Fig. 16C 1623F. In embodiments where L3 cache 1906 is excluded from slice 1900, L2 cache 1904 may be configured as a combined L2 / L3 cache. In a particular implementation, memory structure 1903 may be configured to route data to L3 cache 1906 or a memory controller associated with memory 1910 based on the presence or absence of L3 cache 1906. L3 cache 1906 may be configured as a per-slice cache dedicated to resources of processing slice 1900, or may be a partition of a GPU-wide L3 cache.

[0320] Fig. 20 2000. The graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. In some embodiments, the graphics processor instruction format 2000 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations that result from instruction decoding that is performed once the instruction is processed. Therefore, a single instruction can cause the hardware to perform multiple micro-operations.

[0321] As described herein, the graphics processor execution unit can natively support instructions in the 128-bit instruction format 2010. Based on the selected instructions, instruction options, and the number of operands, a 64-bit compact instruction format 2030 can be used for some instructions. The native 128-bit instruction format 2010 provides access to all instruction options, while some options and operations are limited in the 64-bit format 2030. The native instructions available in the 64-bit format 2030 vary from embodiment to embodiment. The instructions are partially compressed using a set of index values ​​in the index field 2013. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions of the 128-bit instruction format 2010. Instructions of other sizes and formats can be used.

[0322] For each format, the instruction opcode 2012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. The instruction control field 2014 can enable control of certain execution options (such as channel selection (e.g., predication) and data channel order (e.g., swizzle)). For instructions in the 128-bit instruction format 2010, the execution size field 2016 limits the number of data channels that will be executed in parallel. The execution size field 2016 may not be available for the 64-bit compact instruction format 2030.

[0323] Some execution unit instructions have up to three operands, including two source operands src0 2020, src1 2022 and one destination operand (dest 2018). Other instructions (such as, for example, data manipulation instructions, dot product instructions, multiply-add instructions, or multiply-accumulate instructions) may have a third source operand (e.g., src2 2024), and the instruction opcode 2012 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed with the instruction. The execution unit may also support multiple destination instructions, where one or more of the destinations are implicit or implicit based on the instruction and / or the specified destination.

[0324] The 128-bit instruction format 2010 may include an access / addressing mode field 2026 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0325] 128-bit instruction format 2010 can also include access / addressing mode field 2026, which specifies the addressing mode and / or access mode of the instruction. The access mode can be used to limit the data access alignment of the instruction. The access mode including 16-byte aligned access mode and 1-byte aligned access mode can be supported, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in the first mode, the instruction can use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0326] The addressing mode portion of the access / addressing mode field 2026 may determine whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be calculated based on the address register value and the address immediate field in the instruction.

[0327] Instructions can be grouped based on the opcode 2012 bit fields to simplify opcode decoding 2040. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. Move and logic opcode group 2042 can include data movement and logic instructions (e.g., move (mov), compare (cmp)). Move and logic group 2042 can share five least significant bits (least significant bit, LSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. Flow control instruction group 2044 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). Miscellaneous instruction group 2046 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2048 includes component-by-component arithmetic instructions (e.g., addition, multiplication (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math instruction group 2048 performs arithmetic operations in parallel across data channels. The vector math group 2050 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In one embodiment, the illustrated opcode decoding 2040 can be used to determine which portion of the execution unit will be used to execute the decoded instructions. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0328] Graphics Pipeline

[0329] Fig.21 is a block diagram of a graphics processor 2100 according to another embodiment. Fig.21 Elements having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0330] The graphics processor 2100 may include different types of graphics processing pipelines, such as a geometry pipeline 2120, a media pipeline 2130, a display engine 2140, a thread execution logic 2150, and a rendering output pipeline 2170. The graphics processor 2100 may be a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor may be controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2100 through a ring interconnect 2102. The ring interconnect 2102 may couple the graphics processor 2100 to other processing components (such as other graphics processors or general-purpose processors). Commands from the ring interconnect 2102 are interpreted by a command stream converter 2103, which supplies instructions to various components of the geometry pipeline 2120 or the media pipeline 2130.

[0331] The command stream converter 2103 may direct the operation of the vertex fetcher 2105, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2103. The vertex fetcher 2105 may provide the vertex data to the vertex shader 2107, which performs coordinate space transformation and lighting operations on each vertex. The vertex fetcher 2105 and the vertex shader 2107 may execute the vertex processing instructions by dispatching execution threads to the graphics cores 2152A-2152B via the thread dispatcher 2131.

[0332] The graphics cores 2152A-2152B may be an array of vector processors with instruction sets for performing graphics operations and media operations. The graphics cores 2152A-2152B may have an attached L1 cache 2151 that is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0333] The geometry pipeline 2120 may include a tessellation component for performing hardware accelerated tessellation of 3D objects. The programmable shell shader 2111 may configure the tessellation operation. The programmable domain shader 2117 may provide back-end evaluation of the tessellation output. The tessellation 2113 may operate under the direction of the shell shader 2111 and may contain dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the geometry pipeline 2120. In addition, if tessellation is not used, the tessellation component (e.g., the shell shader 2111, the tessellation 2113, and the domain shader 2117) may be bypassed. The tessellation component may operate based on data received from the vertex shader 2107.

[0334] The complete geometric object may be processed by the geometry shader 2119 via one or more threads dispatched to the graphics core 2152A-2152B, or may proceed directly to the clipper 2129. The geometry shader may operate on the entire geometric object, rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2119 receives input from the vertex shader 2107. The geometry shader 2119 may be programmable by a geometry shader program to perform geometry tessellation with the tessellation unit disabled.

[0335] Before rasterization, the clipper 2129 processes the vertex data. The clipper 2129 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. The rasterizer and depth test component 2173 in the render output pipeline 2170 can dispatch a pixel shader to convert the geometric object into a pixel-by-pixel representation. The pixel shader logic can be included in the thread execution logic 2150. Optionally, the application can bypass the rasterizer and depth test component 2173 and access the unrasterized vertex data via the outflow unit 2123.

[0336] The graphics processor 2100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, the graphics core 2152A-2152B and associated logic units (e.g., L1 cache 2151, sampler 2154, texture cache 2158, etc.) are interconnected via data port 2156 to perform memory access and communicate with the rendering output pipeline components of the processor. Sampler 2154, cache 2151, 2158 and graphics core 2152A-2152B can each have a separate memory access path. Optionally, texture cache 2158 can also be configured as a sampler cache.

[0337] The rendering output pipeline 2170 may include a rasterizer and depth test component 2173, which converts vertex-based objects into associated pixel-based representations. The rasterizer logic may include a windower / masker unit for performing fixed-function triangle and line rasterization. In some embodiments, associated rendering buffers 2178 and depth buffers 2179 are also available. Pixel operation components 2177 perform pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 2141, or replaced by the display controller 2143 using an overlay display plane when displayed. A shared L3 cache 2175 may be available for all graphics components, thereby allowing data to be shared without using the main system memory.

[0338] The media pipeline 2130 may include a media engine 2137 and a video front end 2134. The video front end 2134 may receive pipeline commands from the command stream converter 2103. The media pipeline 2130 may include a separate command stream converter. The video front end 2134 may process the media commands before sending them to the media engine 2137. The media engine 2137 may include a thread generation function for generating threads for dispatching to the thread execution logic 2150 via the thread dispatcher 2131.

[0339] The graphics processor 2100 may include a display engine 2140. The display engine 2140 may be external to the processor 2100 and may be coupled to the graphics processor via a ring interconnect 2102, or some other interconnect bus or structure. The display engine 2140 may include a 2D engine 2141 and a display controller 2143. The display engine 2140 may contain dedicated logic that can operate independently of the 3D pipeline. The display controller 2143 may be coupled to a display device (not shown), which may be a system-integrated display device such as in a laptop computer or an external display device attached via a display device connector.

[0340] The geometry pipeline 2120 and the media pipeline 2130 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). Driver software for the graphics processor can convert API calls dedicated to a specific graphics or media library into commands that can be processed by the graphics processor. Support can be provided for all Open Graphics Library (OpenGL), Open Computing Language (OpenCL) and / or Vulkan graphics and computing APIs from the Khronos Group. Support can also be provided for the Direct3D library from Microsoft. Combinations of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). If a mapping from the pipeline of a future API to the pipeline of a graphics processor can be performed, future APIs with compatible 3D pipelines will also be supported.

[0341] Graphics pipeline programming

[0342] Fig.22A is a block diagram illustrating a graphics processor command format 2200 for programming a graphics processing pipeline, such as, for example, in conjunction with Fig.16A , Fig.17 , Fig.21Describe the pipeline. Fig. 22B is a block diagram illustrating a graphics processor command sequence 2210 according to an embodiment. Fig.22A The solid-line boxes in illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.22A An exemplary graphics processor command format 2200 includes fields for identifying the client of the command 2202, a command operation code (opcode) 2204, and a data field 2206. A subopcode 2205 and a command size 2208 are also included in some commands.

[0343] Client 2202 may specify a client unit of a graphics device that processes command data. A graphics processor command parser may check the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. A graphics processor client unit may include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit may have a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 2204 and a subopcode 2205 (if present) to determine the operation to be performed. The client unit uses the information in data field 2206 to execute the command. For some commands, an explicit command size 2208 is expected to specify the size of the command. The command parser may automatically determine the size of at least some of the commands in the command based on the command opcode. Commands may be aligned via multiples of double words. Other command formats may also be used.

[0344] Fig. 22B 2210. The flowchart in 2222 illustrates an exemplary graphics processor command sequence. Software or firmware of a data processing system featuring an exemplary graphics processor may use a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, and the sample command sequence is not limited to these particular commands or command sequences. In addition, commands may be issued as batches of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially concurrent manner.

[0345] The graphics processor command sequence 2210 can begin with a pipeline flush command 2212 to cause any active graphics pipeline to complete currently pending commands for the pipeline. Optionally, the 3D pipeline 2222 and the media pipeline 2224 may not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will suspend command processing until the active paint engines complete pending operations and the associated read caches are invalidated. Optionally, any data marked as "dirty" in the render cache can be flushed to memory. The pipeline flush command 2212 can be used for pipeline synchronization, or can be used before placing the graphics processor in a low power state.

[0346] When a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2213 may be used. A pipeline select command 2213 may be required only once in an execution context before issuing a pipeline command, unless the context is issuing commands for both pipelines. A pipeline flush command 2212 may be required immediately before a pipeline switch via a pipeline select command 2213.

[0347] Pipeline control commands 2214 may configure the graphics pipeline for operation and may be used to program 3D pipeline 2222 and media pipeline 2224. Pipeline control commands 2214 may configure pipeline states for active pipelines. Pipeline control commands 2214 may be used for pipeline synchronization and to clear data from one or more cache memories within an active pipeline before processing a batch of commands.

[0348] Commands associated with return buffer state 2216 may be used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. A graphics processor may also use one or more return buffers to store output data and perform cross-thread communication. Return buffer state 2216 may include selecting the size and number of return buffers to be used for a set of pipeline operations.

[0349] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 2220 , the command sequence is tailored for either 3D pipeline 2222 starting at 3D pipeline state 2230 , or media pipeline 2224 starting at media pipeline state 2240 .

[0350] The commands for configuring the 3D pipeline state 2230 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. The 3D pipeline state 2230 commands may also be able to selectively disable or bypass certain pipeline elements if those elements will not be used.

[0351] 3D primitive 2232 commands can be used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2232 commands are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2232 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. The 3D primitive 2232 commands can be used to perform vertex operations on 3D primitives via vertex shaders. In order to process the vertex shader, the 3D pipeline 2222 dispatches the shader execution thread to the graphics processor execution unit.

[0352] The 3D pipeline 2222 can be triggered via an execute 2234 command or event. A register can be written to trigger a command execution. Execution can be triggered via a "go" or "kick" command in a command sequence. Command execution can be triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0353] When performing media operations, the graphics processor command sequence 2210 may follow the media pipeline 2224 path. In general, the specific purpose and manner of programming the media pipeline 2224 depends on the media or computing operations to be performed. During media decoding operations, specific media decoding operations may be migrated to the media pipeline. The media pipeline may also be bypassed, and the media decoding may be performed in whole or in part using resources provided by one or more general processing cores. The media pipeline may also include elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0354] The media pipeline 2224 can be configured in a similar manner to the 3D pipeline 2222. A collection of commands for configuring the media pipeline state 2240 are dispatched or placed into a command queue, before the media object commands 2242. The commands for the media pipeline state 2240 may include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. The commands for the media pipeline state 2240 may also support the use of one or more pointers to an "indirect" state element that contains a batch of state settings.

[0355] The media object command 2242 may supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains the video data to be processed. Optionally, all media pipeline states must be valid before issuing the media object command 2242. Once the pipeline state is configured and the media object command 2242 is queued, the media pipeline 2224 is triggered via an execute command 2244 or an equivalent execute event (e.g., a register write). The output from the media pipeline 2224 may then be post-processed by operations provided by the 3D pipeline 2222 or the media pipeline 2224. GPGPU operations may be configured and executed in a manner similar to media operations.

[0356] Graphics Software Architecture

[0357] Fig.23 An exemplary graphics software architecture for data processing system 2300 is illustrated. Such a software architecture may include a 3D graphics application 2310, an operating system 2320, and at least one processor 2330. Processor 2330 may include a graphics processor 2332 and one or more general-purpose processor cores 2334. Processor 2330 may be a variant of processor 1402 or any other of the processors described herein. Processor 2330 may be used in place of processor 1402 or any other of the processors described herein. Therefore, the disclosure of any feature in conjunction with processor 1402 or any other of the processors described herein also discloses the corresponding combination with graphics processor 2330, but is not limited thereto. In addition, Fig.23 Elements with the same or similar names as elements of any other figures herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein. Graphics application 2310 and operating system 2320 are each executed in system memory 2350 of the data processing system.

[0358] The 3D graphics application 2310 may include one or more shader programs including shader instructions 2312. The shader language instructions may be in a high-level shader language, such as the High-Level Shader Language (HLSL) of Direct3D, the OpenGL Shader Language (GLSL), etc. The application may also include executable instructions 2314 in a machine language suitable for execution by the general purpose processor core 2334. The application may also include graphics objects 2316 defined by vertex data.

[0359] The operating system 2320 may be a system from Microsoft Corporation. The operating system 2320 may be a graphics API 2322, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 2320 uses a front-end shader compiler 2324 to compile any shader instructions 2312 using HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation, or application executable shader precompilation. During the compilation of the 3D graphics application 2310, high-level shaders may be compiled into low-level shaders. The shader instructions 2312 may be provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0360] The user mode graphics driver 2326 may include a backend shader compiler 2327 to compile shader instructions 2312 into a hardware specific representation. When the OpenGL API is in use, shader instructions 2312 in the GLSL high level language are passed to the user mode graphics driver 2326 for compilation. The user mode graphics driver 2326 may communicate with the kernel mode graphics driver 2329 using the operating system kernel mode functions 2328. The kernel mode graphics driver 2329 may communicate with the graphics processor 2332 to dispatch commands and instructions.

[0361] IP core implementation

[0362] One or more aspects may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each customer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0363] Fig.24A 24 is a block diagram illustrating an IP core development system 2400 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2400 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2430 can generate a software simulation 2410 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 2410 can be used to design, test, and verify the behavior of the IP core using a simulation model 2412. The simulation model 2412 can include functional simulation, behavioral simulation, and / or timing simulation. A register transfer level (RTL) design 2415 can then be created or synthesized from the simulation model 2412. The RTL design 2415 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2415, a lower level design at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can be different.

[0364] The RTL design 2415 or equivalent may be further synthesized by the design facility into a hardware model 2420, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 2440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2465. Alternatively, the IP core design may be transmitted via a wired connection 2450 or a wireless connection 2460 (e.g., via the Internet). The manufacturing facility 2465 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0365] Fig. 24B A cross-sectional side view of an integrated circuit package assembly 2470 is illustrated. The integrated circuit package assembly 2470 illustrates an implementation of one or more processors or accelerator devices as described herein. The package assembly 2470 includes a plurality of hardware logic units 2472, 2474 connected to a substrate 2480. The logic 2472, 2474 may be implemented at least in part in configurable logic or fixed function logic hardware, and may include one or more portions of any of the (one or more) processor cores, (one or more) graphics processors, or other accelerator devices described herein. Each logic unit 2472, 2474 may be implemented within a semiconductor die and coupled to the substrate 2480 via an interconnect organization 2473. The interconnect organization 2473 may be configured to route electrical signals between the logic 2472, 2474 and the substrate 2480, and may include interconnects such as, but not limited to, bumps or pillars. The interconnection organization 2473 can be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 2472, 2474. Optionally, the substrate 2480 can be an epoxy-based laminate substrate. The substrate 2480 can also include other suitable types of substrates. The package assembly 2470 can be connected to other electrical devices via the package interconnect 2483. The package interconnect 2483 can be coupled to the surface of the substrate 2480 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0366] The logic units 2472, 2474 may be electrically coupled to a bridge 2482 configured to route electrical signals between the logic 2472 and the logic 2474. The bridge 2482 may be a dense interconnection fabric that provides routing for electrical signals. The bridge 2482 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic 2472 and the logic 2474.

[0367] Although two logic units 2472, 2474 and bridge 2482 are illustrated, the embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 2482 may be excluded when logic is included on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. In addition, multiple logic units, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

[0368] Fig.24C The illustrated package assembly 2490 includes a hardware logic chiplet (e.g., a base die) of multiple units connected to a substrate 2480. A graphics processing unit, parallel processor, and / or computing accelerator as described herein may be composed of various silicon chiplets manufactured separately. In this context, a chiplet is an integrated circuit that is at least partially packaged, and the at least partially packaged integrated circuit includes different logic units that can be assembled into a larger package with other chiplets. Chipsets with various sets of different IP core logic can be assembled into a single device. In addition, the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. The IP cores can be manufactured using different process technologies and constructed during manufacturing, which avoids the complexity of converging multiple IPs into the same manufacturing process, especially for large SoCs with several styles of IP. Allowing the use of multiple process technologies improves time to market and provides a cost-effective method to create multiple product SKUs. Furthermore, decomposed IP is more easily modified to be independently power gated, and components not in use for a given workload can be shut down, thereby reducing overall power consumption.

[0369] In various embodiments, the package assembly 2490 may include a fewer or greater number of components and chiplets interconnected by structures 2485 or one or more bridges 2487. The chiplets within the package assembly 2490 may have a 2.5D arrangement using chip-on-wafer-on-substrate stacking, where multiple dies are stacked side-by-side on a silicon interposer that includes through-silicon vias (TSVs) to couple the chiplets with a substrate 2480 that includes electrical connections to the package interconnects 2483.

[0370] In one embodiment, the silicon interposer is an active interposer 2489 that includes embedded logic in addition to TSVs. In such embodiments, the chiplets within the package assembly 2490 are arranged on top of the active interposer 2489 using 3D face-to-face die stacking. The active interposer 2489 may include hardware logic for I / O 2491, cache memory 2492, and other hardware logic 2493 in addition to the interconnect structure 2485 and the silicon bridge 2487. The structure 2485 enables communication between the logic chiplets 2472, 2474 and the logic 2491, 2493 within the active interposer 2489. The structure 2485 may be a NoC interconnect or another form of packet switching structure that exchanges data packets between components of the package assembly. For complex components, the structure 2485 may be a dedicated chiplet that enables communication between the hardware logic of the package assembly 2490.

[0371] A bridge structure 2487 within the active interposer 2489 may be used to facilitate point-to-point interconnection between, for example, a logic or I / O chiplet 2474 and a memory chiplet 2475. In some implementations, the bridge structure 2487 may also be embedded within the substrate 2480.

[0372] The hardware logic chiplets may include dedicated hardware logic chiplets 2472, logic or I / O chiplets 2474, and / or memory chiplets 2475. The hardware logic chiplets 2472 and logic or I / O chiplets 2474 may be implemented at least in part in configurable logic or fixed-function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 2475 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory. The cache memory 2492 within the active interposer 2489 (or substrate 2480) may act as a global cache for the package assembly 2490, as part of a distributed global cache, or as a dedicated cache for the structure 2485.

[0373] Each chiplet may be fabricated as a separate semiconductor die and may be coupled to a base die that is embedded within or coupled to a substrate 2480. Coupling to the substrate 2480 may be performed via an interconnect organization 2473. The interconnect organization 2473 may be configured to route electrical signals between the various chiplets and logic within the substrate 2480. The interconnect organization 2473 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect organization 2473 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of logic, I / O, and memory chiplets. In one embodiment, an additional interconnect organization couples the active interposer 2489 to the substrate 2480.

[0374] Substrate 2480 may be an epoxy-based laminate substrate, however, it is not limited thereto, and substrate 2480 may also include other suitable types of substrates. Package assembly 2490 may be connected to other electrical devices via package interconnect 2483. Package interconnect 2483 may be coupled to the surface of substrate 2480 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0375] The logic or I / O chiplet 2474 and the memory chiplet 2475 may be electrically coupled via a bridge 2487 configured to route electrical signals between the logic or I / O chiplet 2474 and the memory chiplet 2475. The bridge 2487 may be a dense interconnection organization that provides routing for electrical signals. The bridge 2487 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I / O chiplet 2474 and the memory chiplet 2475. The bridge 2487 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 2487 is an embedded multi-die interconnect bridge (Embedded Multi-die Interconnect Bridge, EMIB). Alternatively, the bridge 2487 may simply be a direct connection from one chiplet to another chiplet.

[0376] Fig.24DA package assembly 2494 including an interchangeable chiplet 2495 is illustrated according to an embodiment. The interchangeable chiplet 2495 can be assembled into standardized sockets on one or more base chiplets 2496, 2498. The base chiplets 2496, 2498 can be coupled via a bridge interconnect 2497, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. The I / O and logic chiplets can communicate via an interconnect structure. The base chiplets can each support one or more sockets in a standardized format for one of logic or I / O or memory / cache.

[0377] The SRAM and power delivery circuits may be fabricated into one or more of the base chiplets 2496, 2498, which may be fabricated using a different process technology relative to the interchangeable chiplets 2495, which are stacked on top of the base chiplets. For example, the base chiplets 2496, 2498 may be fabricated using a larger process technology, while the interchangeable chiplets may be fabricated using a smaller process technology. One or more of the interchangeable chiplets 2495 may be memory (e.g., DRAM) chiplets. Different memory densities may be selected for the package assembly 2494 based on power and / or performance for the product using the package assembly 2494. In addition, logic chiplets with different numbers of types of functional units may be selected at assembly time based on power and / or performance for the product. In addition, chiplets containing IP logic cores of different types may be inserted into interchangeable chiplet sockets, thereby enabling hybrid processor designs that can mix and match IP blocks of different technologies.

[0378] Exemplary System-on-Chip Integrated Circuit

[0379] Figure 25-26B An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores are shown. Other logic and circuits may be included in addition to what is shown, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores. Figure 25-26B Elements having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, may operate or function in a similar manner as in the other figures, may include the same components, and may be linked to other entities such as, but not limited to, those described elsewhere herein.

[0380] Fig.25is a block diagram illustrating an exemplary system-on-chip integrated circuit 2500 that may be manufactured using one or more IP cores. The exemplary integrated circuit 2500 includes one or more application processors 2505 (e.g., CPUs), at least one graphics processor 2510, which may be a variation of the graphics processors 1408, 1508, 2510, or may be any graphics processor described herein and may be used in place of any of the described graphics processors. Thus, the disclosure of any feature herein in conjunction with a graphics processor also discloses the corresponding combination with the graphics processor 2510, but is not limited thereto. The integrated circuit 2500 may additionally include an image processor 2515 and / or a video processor 2520, either of which may be a modular IP core from the same design facility or from multiple different design facilities. The integrated circuit 2500 may include peripheral or bus logic, including a USB controller 2525, a UART controller 2530, an SPI / SDIO controller 2535, and an I 2 S / I 2 The integrated circuit may include a display device 2545 coupled to a high-definition multimedia interface (HDMI) controller 2550 and a mobile industry processor interface (MIPI) display interface 2555. Storage may be provided by a flash memory subsystem 2560 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2565 to obtain access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2570.

[0381] Figure 26A-26B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. The illustrated graphics processor may be a variation of graphics processor 1408, 1508, 2510, or any other graphics processor described herein. The graphics processor may be used in place of graphics processor 1408, 1508, 2510, or any other of the graphics processors described herein. Thus, any disclosure of features in conjunction with graphics processor 1408, 1508, 2510, or any other of the graphics processors described herein also discloses the corresponding Figure 26A-26B The present invention may be combined with, but not limited to, a graphics processor. Fig.26AAn exemplary graphics processor 2610 of a system-on-chip integrated circuit is illustrated that may be fabricated using one or more IP cores in accordance with an embodiment. Fig.26B An additional example graphics processor 2640 is illustrated of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. Fig.26A Graphics processor 2610 is an example of a low-power graphics processor core. Fig.26B The graphics processor 2640 of FIG. 1 is an example of a higher performance graphics processor core. For example, as mentioned at the beginning of this paragraph, each of the graphics processors in the graphics processor 2610 and the graphics processor 2640 may be Fig.25 A variant of the graphics processor 2510.

[0382] like Fig.26A As shown in , the graphics processor 2610 includes a vertex processor 2605 and one or more fragment processors 2615A-2615N (e.g., 2615A, 2615B, 2615C, 2615D, all the way to 2615N-1 and 2615N). The graphics processor 2610 can execute different shader programs via separate logic, so that the vertex processor 2605 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2615A-2615N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 2605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (One or more) fragment processors 2615A-2615N use the primitive data and vertex data generated by the vertex processor 2605 to generate a frame buffer that is displayed on the display device. The fragment processor(s) 2615A-2615N may be optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0383] The graphics processor 2610 additionally includes one or more memory management units (MMUs) 2620A-2620B, one or more caches 2625A-2625B, and one or more circuit interconnects 2630A-2630B. The one or more MMUs 2620A-2620B provide virtual to physical address mappings for the graphics processor 2610 (including for the vertex processor 2605 and / or (one or more) fragment processors 2615A-2615N), which can reference vertex data or image / texture data stored in memory in addition to vertex data or image / texture data stored in the one or more caches 2625A-2625B. The one or more MMUs 2620A-2620B can be synchronized with other MMUs in the system so that each processor 2505-2520 can participate in a shared or unified virtual memory system, including other MMUs in the system that are associated with Fig.25 One or more MMUs 2620A-2620B may be associated with one or more application processors 2505, image processors 2515, and / or video processors 2520. The components of graphics processor 2610 may correspond to the components of other graphics processors described herein. Figure 2C The vertex processor 2605 and the fragment processors 2615A-2515N may correspond to the graphics multiprocessor 234. According to an embodiment, one or more circuit interconnects 2630A-2630B enable the graphics processor 2610 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection. The one or more circuit interconnects 2630A-2630B may be connected to Figure 2C Further correspondence may be found between similar components of graphics processor 2610 and the various graphics processor architectures described herein.

[0384] like Fig.26B As shown in FIG. , the graphics processor 2640 includes Fig.26AOne or more MMUs 2620A-2620B, one or more caches 2625A-2625B, and one or more circuit interconnects 2630A-2630B of the graphics processor 2610. The graphics processor 2640 includes one or more shader cores 2655A-2655N (e.g., 2655A, 2655B, 26555C, 2655D, 2655E, 2655F, all the way to 2655N-1 and 2655N) that provide a unified shader core architecture in which a single core or a single type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary by embodiment and implementation. In addition, the graphics processor 2640 includes an inter-core task manager 2645 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2655A-2655N and a tiling unit 2658 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches. The shader cores 2655A-2655N may, for example, communicate with Figure 2D Corresponding to the graphics multiprocessor 234 in, or corresponding to the graphics multiprocessors 325, 350.

[0385] Tensor acceleration logic for graphics and machine learning workloads

[0386] Fig. 27 2700 is a block diagram of a data processing system 2700 according to an embodiment. The data processing system 2700 is a heterogeneous processing system having a processor 2702, a unified memory 2710, and a GPGPU 2720 including machine learning acceleration logic. The processor 2702 and the GPGPU 2720 can be any processor and GPGPU / parallel processor described herein. For example, refer to Figure 1 , the processor 2702 may be a variant of and / or share an architecture with one or more processors 102 as shown, and the GPGPU 2720 may be a variant of and / or share an architecture with one or more parallel processors 112 as shown. Fig.14 , processor 2702 may be a variant of and / or share an architecture with one of the illustrated processor(s) 1402, and GPGPU 2720 may be a variant of and / or share an architecture with one of the illustrated graphics processor(s) 1408.

[0387] Processor 2702 may execute instructions for compiler 2715 stored in system memory 2712. Compiler 2715 executes on processor 2702 to compile source code 2714A into compiled code 2714B. Compiled code 2714B may include instructions executable by processor 2702 and / or instructions executable by GPGPU 2720. Using a shader or compute program compiler, such as Fig.23 The shader compiler 2327 and / or shader compiler 2324 in the GPGPU can facilitate the compilation of instructions to be executed by the GPGPU. During compilation, the compiler 2715 can perform operations to insert metadata, including hints about the data parallelism level present in the compiled code 2714B and / or hints about the data locality associated with the threads to be dispatched based on the compiled code 2714B. The compiler 2715 may include the information necessary to perform such operations, or may perform these operations with the help of the runtime library 2716. The runtime library 2716 may also help the compiler 2715 compile the source code 2714A, and may also include instructions linked to the compiled code 2714B at runtime to facilitate the execution of the compiled instructions on the GPGPU 2720. The compiler 2715 may also facilitate register allocation of variables via a register allocator (RA), and generate load and store instructions to move data of variables between memory and registers assigned to the variables.

[0388] Unified memory 2710 represents a unified address space accessible by processor 2702 and GPGPU 2720. Unified memory may include system memory 2712 and GPGPU memory 2718. GPGPU memory 2718 is memory within the address space of GPGPU 2720 and may include some or all of system memory 2712. In one embodiment, compiled code 2714B stored in system memory 2712 may be mapped into GPGPU memory 2718 for access by GPGPU 2720. GPGPU memory 2718 also includes GPGPU local memory 2728 of GPGPU 2720. GPGPU local memory 2728 may include, for example, HBM or GDDR memory.

[0389] GPGPU 2720 includes multiple computing blocks 2724A-2724N, which may include one or more of the various processing resources described herein. The processing resources may be or include various different computing resources, such as, for example, execution units, computing units, streaming multiprocessors, graphics multiprocessors, or multi-core groups. In one embodiment, GPGPU 2720 further includes a tensor accelerator 2723 (e.g., a matrix accelerator), which may include one or more special function computing units designed to accelerate a subset of matrix operations (e.g., dot products, etc.). Tensor accelerator 2723 may also be referred to as a tensor accelerator or tensor core. In one embodiment, the logic components within tensor accelerator 2723 may be distributed across the processing resources of multiple computing blocks 2724A-2724N.

[0390] GPGPU 2720 may also include a set of resources that may be shared by compute blocks 2724A-2724N and tensor accelerator 2723, including, but not limited to, register set 2725, power and performance module 2726, and cache 2727. In one embodiment, register 2725 includes directly and indirectly accessible registers, wherein the indirectly accessible registers are optimized for use by tensor accelerator 2723. Power and performance module 2726 may be configured to adjust the power delivery and clock frequency of compute blocks 2724A-2724N to power gate idle components within compute blocks 2724A-2724N. In various embodiments, cache 2727 may include an instruction cache and / or a lower level data cache.

[0391] GPGPU 2720 may further include an L3 data cache 2730, which may be used to cache data accessed from unified memory 2710 by tensor accelerator 2723 and / or computing elements within compute blocks 2724A-2724N. In one embodiment, L3 data cache 2730 includes shared local memory 2732, which may be shared by computing elements within compute blocks 2724A-2724N and tensor accelerator 2723.

[0392] In one embodiment, the GPGPU 2720 includes instruction handling logic, such as a fetch and decode unit 2721 and a scheduler controller 2722. The fetch and decode unit 2721 includes a fetch unit and a decode unit to fetch and decode instructions executed by one or more of the computational blocks 2724A-2724N or the tensor accelerator 2723. Instructions can be dispatched to appropriate functional units within the computational blocks 2724A-2724N or the tensor accelerator via the scheduler controller 2722. In one embodiment, the scheduler controller 2722 is an ASIC configurable to perform advanced scheduling operations. In one embodiment, the scheduler controller 2722 is a microcontroller or a low-energy processing core that is capable of executing scheduler instructions loaded from a firmware module.

[0393] In one embodiment, some functions to be performed by the computational blocks 2724A-2724N can be directly scheduled to the tensor accelerator 2723 or migrated to the tensor accelerator 2723. In various embodiments, the tensor accelerator 2723 includes processing element logic configured to efficiently perform matrix computation operations, such as multiplication and addition operations and dot product operations used by 3D graphics or computational shader programs. In one embodiment, the tensor accelerator 2723 can be configured to accelerate the operations used by the machine learning framework. In one embodiment, the tensor accelerator 2723 is a dedicated integrated circuit that is explicitly configured to perform a specific set of parallel matrix multiplication and / or addition operations. In one embodiment, the tensor accelerator 2723 is a field programmable gate array (FPGA) that provides fixed-function logic that can be updated between workloads. In one embodiment, the set of computational operations that can be performed by the tensor accelerator 2723 may be limited relative to the operations that can be performed by the computational blocks 2724A-2724N. However, tensor accelerator 2723 can perform parallel tensor operations at a significantly higher throughput relative to compute blocks 2724A-2724N.

[0394] Processing resource architecture with enhanced integer pipeline

[0395] Fig.28 2800 is a diagram illustrating a processing resource architecture for a graphics processor according to an embodiment. The processing resource architecture includes functional units such as Fig.18A Any of the graphics cores 1815A-1815N, including Fig.18B The vector engine 1802 and Fig.18C1803 of the matrix engine 1803. The ready instruction queue set 2802 associated with each hardware thread (T0-Tn) stores instructions that are ready to execute. Each hardware thread is a SIMD thread, which can execute a single instruction on multiple data channels. The data for the instruction can be read from the registers in the set 2810 of register files and written to the registers in the set 2810 of register files. In one embodiment, the set 2810 of register files includes two register files, wherein the first register file stores the even data elements in the data element vector, and the second register file stores the odd data elements in the data element vector.

[0396] Intermediate data for calculation can be stored in the accumulator 2811 array. In various embodiments, the register file 2810 can be configured with the characteristics of other GPU register files described herein (e.g., register file 258, register file 334A-334B, register file 369, register 445, etc.). The register file 2810 may include vector registers (e.g., vector register 1561), and in one embodiment, include a limited number of scalar registers (scalar register 1562). In one embodiment, the register file 2810 may include a general register file array, such as GRF 1824. In one embodiment, the number of hardware threads is configurable, wherein a configurable number of registers within the register file 2810 is assigned to each thread. In one embodiment, SIMT execution is enabled by assigning multiple SIMT threads to a single SIMD hardware thread. Data elements associated with multiple SIMT threads can be mapped to multiple sub-registers within a single SIMD register file. The thread control unit 2832 is executed via hardware thread control instructions. The thread control unit 2832 includes a thread arbiter 2804 that arbitrates which ready instructions are assigned to the instruction queue 2806 associated with the floating point (FPU), integer (INT), or matrix pipeline (Matrix). Fig.32 Additional hardware logic for the thread control unit 2832 is shown in FIG.

[0397] Source read arbiter 2808 arbitrates the access of register stack and accumulator of source operand read stage of instruction execution to instruction in instruction queue 2806.Operation object read from register stack 2810 can be buffered in reuse buffer 2812, and reuse buffer 2812 is coupled with the functional unit of FPU, INT and Matrix pipeline.Reuse buffer 2812 can serve as operation object cache, and it promotes those functional units to reuse operation object data.In one embodiment, reuse buffer 2812 is multi-layer deep, thereby allows caching source operand from multiple instructions.Processing resource architecture 2800 includes multiple different types of functional units, including matrix unit 2814, single precision floating point (FP32) unit 2816, high throughput double precision floating point (FP64) 2817, low throughput FP64 unit 2819 and integer unit 2820. The high-throughput FP64 2817 unit can be configured to execute instructions intended for use with high-performance compute (HPC) and scientific computing workloads, and can be found primarily in graphics processors and computing accelerators designed for servers and / or workstations. The low-throughput FP64 unit 2819 can be found primarily in consumer-grade graphics processors and / or computing accelerators. At least one embodiment may include both the high-throughput FP64 2817 unit and the low-throughput FP64 unit 2819. The processing resource architecture may also include an architecture-specific register file (ARF 2818) containing configuration registers and other non-general purpose registers. The ARF 2818 may be similar to Fig.18B ARF 1826.

[0398] Different instructions are assigned to different functional units based on the instruction type. Matrix operations such as dot product or matrix multiplication operations are assigned to matrix unit 2814, which can be Fig.18C An instance of a matrix engine 1803 of , or another matrix unit described herein, such as Figure 3COne or more tensor cores 371 in. Single-precision floating-point instructions can be executed by FP32 unit 2816 or high-throughput FP64 unit 2817. Double-precision floating-point instructions can be executed by high-throughput FP64 unit 2817 or low-throughput FP64 unit 2819. Integer operations are performed by integer unit 2820. In one embodiment, integer unit 2820 further includes circuits for performing extended mathematical functions, such as transcendental mathematical functions, exponential and / or logarithmic operations. In one embodiment, FP32 unit 2816 and high-throughput FP64 unit 2817 are grouped into a first ALU / FPU (e.g., FPU0), while low-throughput FP64 unit 2819 and integer unit 2820 are grouped into a second ALU / FPU (e.g., FPU1). Outputs from these functional units can be written back to general registers in register file 2810 or stored in one or more accumulators 2811 via destination write arbiter 2822.

[0399] Figures 29A-29B An integer unit according to an embodiment is illustrated. Fig.29A FIG. 1 shows a schematic diagram of an embodiment of the present invention. Fig.28 Additional details of integer unit 2820. Fig.29B The correspondence between the parallel processor data paths and processor lanes of integer unit 2820 is shown.

[0400] like Fig.29A As shown in, in one embodiment, integer unit 2820 may include an input buffer set 2902 coupled to multiple arithmetic logic units (arithmetic logic unit, ALU 2904A-2904N). Each ALU 2904A-2904N may include multiple functional units, including adders and multipliers of different bit widths. In one embodiment, integer unit 2820 is a multi-channel SIMD unit, and each ALU 2904A-2904N represents a 32-bit channel or parallel processing channel of the ALU. Depending on the SIMD width and channel width configured for the instruction, integer unit 2820 can execute multiple SIMD channels of instructions across each ALU 2904A-2904N to execute SIMD instructions. For example, in one embodiment, a single 32-bit channel can be configured to perform operations on four groups of 8-bit data elements or two groups of 16-bit data elements.

[0401] In general, the instruction of multiplying two 32-bit integers can be performed by 32-bit × 32-bit multiplier 2920, and generates up to 64-bit output. A series of multiplication and addition operations to 32-bit integers may need to use 64-bit adders 2921. This article describes the hardware logic and associated instructions for enabling 32-bit integer multiplication via using additional multipliers. These instructions perform native 32-bit integer multiplication (MUL) and multiplication and addition (MAD) operations, which produce 32-bit alignment results per channel. The MUL instruction supports two source operands in the form of 32-bit signed or unsigned integers, and the low 32 bits of the result are output as signed or unsigned 32-bit integers. The MAD instruction supports three source operands in the form of signed or unsigned 32-bit integers, and the low 32 bits of the result are output as signed or unsigned integers. In addition, a multiplication low / high (MULLH) instruction is provided, which supports two 32-bit signed or unsigned integers as input. The MULLH instruction will then output both the upper 32-bit and lower 32-bit results per channel, which are stored in two consecutive destination registers or accumulators in a structure of arrays (SoA) layout, with one parallel array per field. The source and destination operands of the MUL and MAD instructions can specify Fig.28 The MULLH instruction can specify a source operand from register file 2810 and output to register file 2810 or accumulator 2811. The MUL and MAD instructions additionally support input in the form of (immediate number * 16 bits (word)). The MULLH instruction supports input in the form of (immediate number * 32 bits (Dword)).

[0402] The MUL, MAD, and MULLH instructions described herein utilize a 32-bit×16-bit multiplier 2922, as well as an additional 16-bit×16-bit multiplier 2923. In one embodiment, a 48-bit adder 2924 is also used for addition operations. In another embodiment, a 64-bit adder 2921 is used instead of or in addition to the 48-bit adder 2924. The buffer 2926 can be used to store output results from the integer unit 2820, or as temporary storage for multi-cycle instructions. Exemplary source and destination data types for the MUL, MAD, and MULLH instructions are shown below, where D=32-bit data type, W=16-bit data type, and Imm=immediate value. The input operation object can be in the form of a vector of 32-bit integer data elements, a 32-bit immediate value, or a 16-bit immediate value.

[0403] MUL - 32-bit lane-aligned multiplication

[0404] Dst Src0 Src1 *D *D *D *D *D Imm*D

[0405] MAD - 32-bit lane-aligned multiplication / addition

[0406] Dst Src0 Src1 Src2 *D *D *D *D *D Imm*W *D Imm*W *D Imm*W *D *D *D *D *D Imm*W

[0407] MULLH-32 bit lane-aligned multiplication with GRF SoA output

[0408] Dst Src0 Src1 *D(dstanddst+1) *D *D *D(dstanddst+1) *D Imm*D

[0409] According to the SIMD or SIMT programming model, MUL, MAD, and MULLH instructions are parallel processing instructions that can perform instruction operations on multiple data elements. Fig.29B As shown in, each input operation object may include multiple data elements arranged in data lanes 2934A-2934N. For example, Src0, Src1 and Src2 may be vectors of input data, wherein each data element is associated with data lanes 2934A-2934N. Each data lane 2934A-2934N may be mapped to a virtual processor path 2936A-2936N. The number of virtual processor paths 2936A-2936N may correspond to the SIMD width or number of threads associated with the instruction. For example, a SIMD32 instruction may perform operations on 32 data lanes of each operation object, similar to the warp of 32 SIMT threads. The number of physical processor paths 2938A-2938D represents the number of physical ALU channels that can be used to perform operations on data elements. The number of physical processor paths 2938A-2938D may be different from the number of virtual processor paths 2936A-2936N. In one embodiment, for N virtual processor paths 2936A-2936N, there may be D physical processor paths 2938A-2938D, where D=N / 2. For example, a SIMD32 instruction may be executed by 32 virtual processor paths associated with 16 physical processor paths. In such an example, two processing cycles may be used to execute the instruction. In other embodiments, other virtual to physical processor path mappings may be used.

[0410] Fig.30An algorithm 3000 for executing a MUL / MAD instruction according to an embodiment is illustrated, which outputs the lower 32 bits of the result. Algorithm 3000 can be used in a graphics processor implementation to implement full-rate channel-aligned 32-bit multiplication and multiplication / addition operations without using a full 32-bit×32-bit multiplier 2920. Instead, each 32-bit ALU channel of the integer unit 2820 can be configured with a 32-bit×16-bit multiplier 2922 and a 16-bit×16-bit multiplier 2923. The intermediate result will be more than 32 bits, but only the lower 32 bits will be output. A 32-bit per-channel MUL instruction with a lower 32-bit output can be implemented as:

[0411] MUL Result[31:0]=(a[31:0]*b[15:0]+(a[15:0]*b[31:16]<<16))[31:0]

[0412] A 32-bit per channel MAD instruction with a low 32-bit output can be implemented as:

[0413] MAD Result[31:0]=(a[31:0]*b[15:0]+(a[15:0]*b[31:16]<<16)+c[31:0])[31:0]

[0414] The hardware logic configured to execute the MUL or MAD instruction accepts an Src0 input (a) including an upper 16 bits 3002 and a lower 16 bits 3003 and an Src1 input (b) including an upper 16 bits 3004 and a lower 16 bits 3005 for each channel. The "upper bits" refer to the upper word (16 most significant bits) of the 32-bit double word value, and the "lower bits" refer to the lower word of the 32-bit double word value. For the MAD instruction, the hardware logic additionally accepts an Src2 input (c) having an upper 16 bits 3006 and a lower 16 bits 3007. The hardware logic then performs an operation (a.lo*b.lo) 3008, which multiplies the lower 16 bits 3003 of the input (a) by the lower 16 bits 3005 of the input (b), and an operation (a.hi*b.lo) 3010, which multiplies the upper 16 bits 3002 of the input (a) by the lower 16 bits 3005 of the input (b). The operations (a.lo*b.lo) 3008 and (a.hi*b.lo) 3010 are performed via a 32-bit×16-bit multiplier 2922. A 16-bit×16-bit multiplier 2923 performs an addition operation (a.lo*b.hi) 3012, which multiplies the lower 16 bits 3003 of the input (a) by the upper 16 bits 3004 of the input (b). The result of the operation (a.lo*b.hi) 3012 is shifted left by 16 bits. The results of the operations (a.lo*b.lo) 3008, (a.hi*b.lo) 3010, and (a.lo*b.hi) 3012 are added by an adder (e.g., Fig.29A The 64-bit adder 2921 or 48-bit adder 2924 of the input (c) is summed. For the MAD instruction, a 32-bit value (c[31:0]) 3014 including the upper 16 bits 3006 and the lower 16 bits 3007 of the input (c) is also added. The result is a 48-bit result, of which the lower 32 bits 3018 are reserved for output and the remaining upper bits 3016 are discarded. The MUL and MAD instructions each support an execution size of 1, 2, 4, 8, 16, or 32 channels. In one embodiment, the MUL and MAD instructions output vector data, where the data elements are stored in AoS format. Each of the MUL and MAD instructions consumes one execution slot. Consuming one execution slot indicates that the instruction can be executed by a single SIMD ALU in a single cycle and / or has a single execution stage.

[0415] Fig.31The algorithm 3100 for executing a MULLH instruction according to an embodiment is illustrated, and the MULLH instruction outputs the upper 32 bits and the lower 32 bits of the result. The MULLH instruction uses inputs from general registers of the register file 2810 similar to the MUL instruction, but outputs both the upper 32 bits and the lower 32 bits of the result within two consecutive cycles. In one embodiment, the MULLH instruction is implemented as a single hardware atomic operation that cannot be preempted between cycles.

[0416] The algorithm can be implemented as follows:

[0417] Loop 0: {Carry[1:0], Result.Low[31:0]} = (a[31:0]*b[15:0]+((a[15:0]*b[31:16])<<16)[33:0] Loop 1: Result.High[31:0] = (a[31:0]*b[31:16]+((a[31:16]*b[15:0])&0xFFFF0000)

[0418] +(Carry[1:0]<<16))[47:16]

[0419] The algorithm 3100 for the MULLH instruction accepts as inputs the Src0 input (a) including the upper 16 bits 3102 and the lower 16 bits 3103 and the Src1 input (b) including the upper 16 bits 3104 and the lower 16 bits 3105. The Src2 input (c) is not used (e.g., the upper 16 bits 3106, the lower 16 bits 3107). The hardware logic then performs an operation (a.lo*b.lo) 3108, which multiplies the lower 16 bits 3103 of the input (a) by the lower 16 bits 3105 of the input (b), and an operation (a.hi*b.lo) 3110, which multiplies the upper 16 bits 3102 of the input (a) by the lower 16 bits 3105 of the input (b). The operations (a.lo*b.lo) 3108 and (a.hi*b.lo) 3110 are performed via the 32-bit×16-bit multiplier 2922. The 16-bit×16-bit multiplier 2923 performs an addition operation (a.lo*b.hi) 3112, which multiplies the lower 16 bits 3103 of the input (a) by the upper 16 bits 3104 of the input (b), and the result is shifted left by 16 bits. The results of the operations (a.lo*b.lo) 3108, (a.hi*b.lo) 3110, and (a.lo*b.hi) 3112 are obtained by an adder (e.g., Fig.29A The low 32 bits 3114 of the sum are output in cycle 0 of the instruction, with two or more carry bits 3116 being reserved for the next cycle.

[0420] In the next cycle, the operation (a.hi*b.lo) 3117 is performed on bits [31:16] via the 16-bit×16-bit multiplier 2923, where the low bit 3118 is masked. This result is added to the results of the operations (a.lo*b.hi) 3119 and (a.hi*b.hi) 3120 performed by the 32-bit×16-bit multiplier 2922 to generate the high 32 bits 3122 of the output. The high 32 bits 3122 of the output are discarded for results above 3121 and below 3123. In one embodiment, a 48-bit adder (e.g., Fig.29A In such an embodiment, the upper 32 bits 3122 of the output may be generated by outputting bits [47:16] of the adder after generating the sum of the fourth, fifth, and sixth intermediate results. In the case of using a 64-bit adder (e.g., Fig.29A 64-bit adder 2921), the upper 32 bits 3122 are output from bits [63:32] of the adder.

[0421] The MULLH instruction supports execution sizes of 1, 2, 4, 8, and 16 channels. In one embodiment, for a MULLH operation, any unused channels in the destination register will not be affected. For example, a SIMD8 MULLH operation using the lower 8 channels will not use the upper 8 channels. Therefore, the data on these channels of the destination register will remain unaffected. The MULLH instruction consumes two execution slots. Consuming two execution slots indicates that the instruction can be executed by a single SIMD ALU in two cycles and / or has two execution stages.

[0422] In one embodiment, the MULLH instruction is configured to generate a result in a SoA (structure of arrays) format. The SoA arrangement is a structure that stores an array of each individual data element, as shown in the following pseudo code:

[0423]

[0424]

[0425] When stored in graphics processor registers (e.g., in registers of register file 2810 within processing resource architecture 2800), arrays containing structure elements are stored separately. For example, a first register may store an array of x elements, a second register may store an array of y elements, and a third register may store an array of z elements. The SoA layout is contrasted with the AoS (array of structures) layout. The AoS arrangement uses a structure for each data element and stores each of those structures in an array, as shown in the following pseudo code:

[0426]

[0427] When stored in graphics processor registers, each register may store a vector comprising elements of each structure, such that each register stores x, y, and z data elements. There are two options for computing data in AoS format: performing operations in situ on the data in the AoS arrangement, or rearranging the data into an SoA arrangement. Various 3D, compute, and media operations may have specific preferred layouts. For example, in some configurations, vertices for vertex and geometry shaders are stored in AoS form, while pixels for pixel shaders are stored in SoA form. By generating output in SoA format, the MULLH instruction avoids the need to transform AoS layout data output from MUL / MAD instructions.

[0428] Fig.32 3200 is a diagram illustrating a method 3200 for executing a 32-bit lane aligned integer multiply instruction according to an embodiment. Fig.30 , method 3200 may be at least partially comprised of, for example, Fig.28 The method 3200 may be implemented by an integer pipeline of an integer unit 2820 of the processor. The 32-bit lane-aligned integer multiplication may be a SIMD or SIMT instruction, wherein the method is implemented for each 32-bit SIMD lane or SIMT thread. In one embodiment, the method 3200 includes performing an operation of decoding an instruction via decoding logic of a graphics or parallel processor including an integer pipeline, thereby performing a 32-bit lane-aligned integer multiplication on data elements identified by a first operand and a second operand (3202). The graphics or parallel processor may then load the first operand and the second operand into a functional unit of th...

Claims

1. A graphics processor, comprising: Memory interface; and A plurality of processing resources coupled to the memory interface, the plurality of processing resources comprising functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements, the integer pipeline comprising a plurality of parallel processor paths associated with a plurality of data lanes, each of the plurality of parallel processor paths comprising a first multiplier and a second multiplier.

2. The graphics processor of claim 1 , comprising a decode unit configured to decode a first instruction for configuring the integer pipeline to multiply a first plurality of integer data elements to generate a first result comprising 32-bit data elements.

3. The graphics processor of claim 2 , wherein the first instruction is to configure an integer pipeline to load a first data element associated with a first operand and a second data element associated with a second operand, the first data element and the second data element being loaded into a functional unit of the integer pipeline.

4. The graphics processor according to claim 3, wherein in response to the first instruction, the integer pipeline is configured to: multiplying, via a first multiplier, lower 16 bits of a data element of the first data element by lower 16 bits of a corresponding data element of the second data element to generate a first intermediate result; multiplying, via the first multiplier, upper 16 bits of a data element of the first data element by lower 16 bits of a data element of the second data element to generate a second intermediate result; multiplying, via a second multiplier, lower 16 bits of a data element of the first data element by upper 16 bits of a data element of the second data element to generate a third intermediate result; and The third intermediate result is shifted left by 16 bits.

5. The graphics processor of claim 4, wherein in response to the first instruction, the integer pipeline is configured to: adding the first, second, and third intermediate results to produce a sum; and The lower 32 bits of the sum are output.

6. The graphics processor of claim 5, comprising a decode unit configured to decode a second instruction for configuring the integer pipeline to multiply a second plurality of integer data elements to generate an intermediate result comprising 32-bit data elements and to add an additional value to the intermediate result.

7. The graphics processor of claim 6, wherein the additional value is a 32-bit data element.

8. The graphics processor of claim 6, wherein the additional value is a 16-bit immediate value.

9. The graphics processor of any one of claims 1-8, wherein the first multiplier is a 32-bit x 16-bit multiplier and the second multiplier is a 16-bit x 16-bit multiplier.

10. The graphics processor according to any one of claims 1 to 9, wherein each of the plurality of processing resources comprises a plurality of register files and a plurality of reuse buffers coupled to the plurality of register files, the plurality of reuse buffers being coupled to the integer pipeline, and the plurality of reuse buffers being configured to cache operand data read from the plurality of register files from the integer pipeline.

11. A graphics processing system, comprising the graphics processor according to any one of claims 1 to 10.

12. A method comprising: decoding instructions at a graphics processor; and The instructions are executed at an integer pipeline of the graphics processor, the instructions being used to cause the integer pipeline to generate a first 32-bit sum and a second 32-bit sum based on a plurality of intermediate products, the plurality of intermediate products being generated by multiplying upper 16 bits or lower 16 bits of integer data elements via a first multiplier and a second multiplier, wherein the upper 16 bits of the integer data elements include the 16 most significant bits of the integer data elements, and the lower 16 bits of the integer data elements include the 16 least significant bits of the integer data elements.

13. The method of claim 12, wherein generating the first 32-bit sum comprises: loading a first operand and a second operand into a functional unit of an integer pipeline; In the first operating cycle: multiplying, via a first multiplier, lower 16 bits of an integer data element of a first operand by lower 16 bits of a second operand to generate a first intermediate result, the lower 16 bits of the integer data element comprising the 16 least significant bits of the integer data element; multiplying, via a first multiplier, upper 16 bits of a first operand by lower 16 bits of a second operand to generate a second intermediate result, the upper 16 bits of the integer data element comprising the 16 most significant bits of the integer data element; multiplying lower 16 bits of the first operand by upper 16 bits of the second operand via a second multiplier to generate a third intermediate result, and shifting the third intermediate result left by 16 bits; summing the first, second, and third intermediate results with the third operand; Save bit [33:32] as a carry bit; and Bits [31:0] of the sum are output as the first 32-bit sum.

14. The method according to claim 13, wherein: Generating the second 32-bit sum is included in the second operation cycle: multiplying the upper 16 bits of the first operand by the lower 16 bits of the second operand via a second multiplier while masking the lower 16 bits to generate a fourth intermediate result; multiplying lower 16 bits of the first operand by upper 16 bits of the second operand via the first multiplier to generate a fifth intermediate result; multiplying the upper 16 bits of the first operand by the upper 16 bits of the second operand via the first multiplier to generate a sixth intermediate result; summing the fourth, fifth, and sixth intermediate results with the carry bit; and The upper 32 bits of the sum are output as the second 32-bit sum.

15. The method of claim 14, wherein outputting the upper 32 bits of the sum as a second 32-bit sum comprises outputting bits [63:32] of a 64-bit adder.

16. The method of claim 14, wherein outputting upper 32 bits of the sum as a second 32-bit sum comprises outputting bits [47:16] of a 48-bit adder.

17. An apparatus comprising means for performing the method according to any one of claims 12 to 16.

Images