Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel has a vertically oriented side for mounting a driver IC. The display panel has a display area and a frame area surrounding the display area. The frame area has a first side for proximity to the driver IC. The display panel includes a pixel driving circuit, a reset connection line, and two first reset signal lines. An eighth transistor is connected to the pixel driving circuit. The reset connection line is located on the first side and connected to the driver IC. At least two first reset signal lines are positioned corresponding to the display area. The two first reset signal lines are arranged in a crisscross pattern and electrically connected at the intersection. Of the two first reset signal lines, the horizontally arranged first reset signal line is electrically connected to the drain of the eighth transistor in the pixel driving circuit, and one end of the vertically arranged first reset signal line extends to the first side and overlaps with the reset connection line.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] Currently, the mainstream driver circuits on the market are 7T2C and 8T1C. Due to layout space or wiring layout limitations, many products only connect the VI signals horizontally to a whole row of pixels in the actual layout. The source of the VI signal is from the source end (signal sending end) at the bottom of the panel to the panel pixels. When only horizontal connection is made, the VI traces have to go around the perimeter of the panel to connect with the horizontal VI signals of each row. During the upward transmission, the interference caused by the metal trace impedance has to be overcome, which increases the delay.

[0003] Application content

[0004] This application provides a display panel and a display device, which can achieve [the desired result].

[0005] In a first aspect, embodiments of this application provide a display panel, wherein a driver IC is disposed on one side of the display panel in the vertical direction, and a display area and a border area surrounding the display area are formed on the display panel, wherein the border area has a first side for approaching the driver IC;

[0006] The display panel includes:

[0007] A pixel driving circuit, wherein an eighth transistor is connected to the pixel driving circuit;

[0008] A reset connection line is located on the first side and connected to the driver IC; and,

[0009] At least two first reset signal lines are provided corresponding to the display area. The two first reset signal lines are arranged in a cross pattern and electrically connected at the intersection. Among the two first reset signal lines, the horizontally arranged first reset signal line is electrically connected to the drain of the eighth transistor of the pixel driving circuit, and one end of the vertically arranged first reset signal line extends to the first side and overlaps with the reset connection line.

[0010] In one embodiment, the display panel further includes:

[0011] A first power connection line is disposed in the frame area and extends circumferentially along the frame area. The first power connection line is used to electrically connect the pixel driving circuit and the driving IC; and...

[0012] Two power signal lines are arranged in a crisscross pattern and electrically connected at the intersection. The end of each power signal line passes through the display area and extends to the frame area to connect with the power connection line on the corresponding side.

[0013] In one embodiment, a first wiring layer and a second wiring layer are formed on the display panel;

[0014] The power signal lines arranged horizontally are laid on the first wiring layer, and the power signal lines arranged vertically are laid on the second wiring layer. The intersection of the two power signal lines is electrically connected through a first via.

[0015] In one embodiment, a third wiring layer and a fourth wiring layer are formed on the display panel;

[0016] The first reset signal line in the horizontal direction is laid on the third routing layer, and the first reset signal line in the vertical direction is laid on the fourth routing layer. The intersection of the two first reset signal lines is electrically connected through a second via.

[0017] In one embodiment, three reset connection lines are provided, which are arranged side by side at intervals in the longitudinal direction to be respectively connected to the driver IC;

[0018] The display panel also includes:

[0019] Two second reset signal lines are arranged in a crisscross pattern and electrically connected at the intersection. The second reset signal line arranged in the horizontal direction is electrically connected to the drain of the fourth transistor of the pixel driving circuit, and one end of the second reset signal line arranged in the vertical direction extends to the first side; and...

[0020] Two third reset signal lines are arranged in a cross pattern and electrically connected at the intersection. The third reset signal line arranged in the horizontal direction is electrically connected to the drain of the seventh transistor of the pixel driving circuit, and one end of the third reset signal line arranged in the vertical direction extends to the first side.

[0021] The ends of the first reset signal line, the second reset signal line, and the third reset signal line are respectively connected to the three reset connection lines.

[0022] In one embodiment, the display panel includes a first signal line group and a second signal line group arranged in a crisscross pattern. Both the first signal line group and the second signal line group include a first reset signal line, a second reset signal line, and a third reset signal line arranged side by side at intervals.

[0023] In one embodiment, the first signal line group is arranged longitudinally;

[0024] Multiple first signal line groups are provided, and the multiple first signal line groups are arranged side by side at intervals in the horizontal direction.

[0025] In one embodiment, the display panel further includes a second power connection line, which is disposed on the first side and is used to electrically connect the pixel driving circuit and the driving IC.

[0026] In one embodiment, the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the third transistor and the fourth transistor are N-type oxide transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type oxide transistors.

[0027] Secondly, this application provides a display device, which includes the display panel described above.

[0028] Beneficial Effects: The display panel provided in this application has a driver IC arranged on one side in the vertical direction. The display panel has a display area and a bezel area, with one side of the bezel area closest to the driver IC designated as a first side. The display panel has a pixel driving circuit, and a reset connection line is arranged on the first side. The reset connection line is connected to the driver IC. At least two crisscrossing first reset signal lines are arranged in the display area. The horizontally arranged first reset signal line is electrically connected to the drain of the eighth transistor of the pixel driving circuit, and one end of the vertically arranged first reset signal line extends to the first side and overlaps with the reset connection line. It should be noted that the pixel driving circuit involved in this application… The circuit is configured as an 8T1C driving circuit, which has eight transistors and one capacitor connected to it. At the same time, the two first reset signal lines are arranged in a crisscross pattern. The reset connection line is set on the first side. The signal from the driving IC is transmitted to the vertically arranged first reset signal line through the reset connection line, and then transmitted to the horizontally arranged first reset signal line through the intersection of the two first reset signal lines. In this way, it is no longer necessary to extend the reset connection line along the circumference of the frame area, thereby shortening the signal transmission distance, reducing the transmission delay, and enabling more sufficient reset of the source and drain of the driving TFT during the potential maintenance stage, thus improving the effect on low frequency or low grayscale display. Attached Figure Description

[0029] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0030] Figure 1The circuit connection diagram for the existing 8T1C driver circuit;

[0031] Figure 2 A schematic diagram of the wiring layout for the display panel (first embodiment) provided in this application;

[0032] Figure 3 This is a schematic diagram of the wiring layout of the display panel (second embodiment) provided in this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0034] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0036] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0037] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0038] This application provides a display panel 100 and a display device, wherein the display device can be a smartphone, tablet computer, display screen, or other similar device. This application provides a display panel 100; please refer to [link to relevant documentation]. Figure 1 and Figure 2 The display panel 100 has a vertical side for mounting a driver IC 200. The display panel 100 has a display area a and a border area b surrounding the display area a. The border area b has a first side for proximity to the driver IC 200. The display panel 100 includes a pixel driving circuit 1, a reset connection line 2, and at least two first reset signal lines 3. The reset connection line 2 is located on the first side and connected to the driver IC 200. The two first reset signal lines 3 are positioned corresponding to the display area a, and are arranged in a crisscross pattern and electrically connected at the intersection. Of the two first reset signal lines 3, the horizontally arranged first reset signal line 3 is electrically connected to the drain of the eighth transistor 18 of the pixel driving circuit 1, and one end of the vertically arranged first reset signal line 3 extends to the first side and overlaps with the reset connection line 2.

[0039] It should be noted that further reference is required. Figure 1The pixel driving circuit 1 involved in this application is configured as an 8T1C driving circuit. The 8T1C driving circuit has eight transistors and one capacitor connected to it. That is, based on the mainstream 7T2C driving circuit, by setting the first reset signal line 3, the newly added eighth transistor 18 is connected to the source of the first transistor 11 (forming an 8T1C driving circuit), thereby increasing the process of resetting the source and drain of the first transistor 11. This alleviates problems such as potential deviation caused by leakage after signal writing of the first transistor 11, and significantly improves low-frequency flicker and crosstalk. Simultaneously, based on the existing 8T1C driving circuit, the reset connection line 2 is set on the first side of the bezel area b near the driving IC 200, and two first reset signal lines 3 are set in a crisscrossing pattern. It is understood that the reset connection line 2 can be the VI_3 (reset signal connected to the drain of the eighth transistor 18 switching) connection line, and the first reset signal line 3 can be the VI_3 signal line. When the reset signal given by the driver IC 200 is transmitted to the vertically arranged VI_3 signal line via the VI_3 connection line, it is then transmitted to the horizontally arranged VI_3 signal line via the intersection of the two intersecting VI_3 signal lines, and finally transmitted to the drain of the eighth transistor 18 via the horizontally arranged VI_3 signal line. In this way, it is no longer necessary to extend the VI_3 connection line along the circumference of the frame area b, thereby shortening the signal transmission distance, reducing the transmission delay, and thus enabling a more sufficient reset of the driving TFT source and drain during the potential maintenance stage, improving the effect on low-frequency or low grayscale display.

[0040] Furthermore, in the existing display panel 100, each pixel in the display area a is provided with a VDD signal line, but no VSS signal line (the power signal connected to the source of the field-effect transistor) is provided. Therefore, the VSS signal line needs to be arranged around the perimeter of the border area b to ensure that the VSS signal is transmitted to each pixel in the display area a. This increases the transmission distance of the VSS signal, and the longer the transmission distance, the more severe the signal distortion, which not only reduces the uniformity of the panel display, but also generates greater power consumption.

[0041] In some embodiments of this application, the display panel 100 further includes a first power connection line 4 and two power signal lines 5; the first power connection line 4 is disposed in the frame area b and extends circumferentially along the frame area b, and is used to electrically connect the pixel driving circuit 1 and the driving IC 200; the two power signal lines 5 are arranged in a crisscross pattern and electrically connected at the intersection, and the end of each power signal line 5 passes through the display area a and extends to the frame area b, for connecting with the power connection line on the corresponding side; it can be understood that the first power connection line 4 and the power signal lines 5 are both VSS signal lines, and In other words, VSS signal lines are laid out around the perimeter of the frame area b and connected to the driver IC 200. Two VSS signal lines are laid out in the display area a in a crisscross pattern. The two VSS signal lines in the display area a extend to the frame area b and overlap with the VSS signal lines on the frame area b, thereby forming a VSS signal transmission network on the display panel 100. This shortens the power signal transmission distance, reduces transmission delay, and at the same time reduces transmission loss, so that the VSS potential is maintained as much as possible to avoid excessive distortion caused by transmission. It also reduces the panel EL power consumption (the energy loss generated by the panel itself due to the power signal input to the light-emitting pixels).

[0042] This application does not limit the specific arrangement of the two intersecting power signal lines 5. The two power signal lines 5 can be arranged on the same wiring layer or on different wiring layers. In one embodiment, the display panel 100 has a first wiring layer and a second wiring layer stacked on top of each other. The horizontally arranged power signal lines 5 are arranged on the first wiring layer, and the vertically arranged power signal lines 5 are arranged on the second wiring layer. The intersection of the two power signal lines 5 is electrically connected through a first via. By arranging the two power signal lines 5 in layers, the internal wiring layout of the display panel 100 is made more reasonable.

[0043] Similarly, this application does not limit the specific arrangement of the two intersecting first reset signal lines 3. The two first reset signal lines 3 can be arranged on the same wiring layer or on different wiring layers. In one embodiment, a third wiring layer and a fourth wiring layer are formed on the display panel 100. The first reset signal line 3 in the horizontal direction is arranged on the third wiring layer, and the first reset signal line 3 in the vertical direction is arranged on the fourth wiring layer. The intersection of the two first reset signal lines 3 is electrically connected through a second via. By routing the two first reset signal lines 3 in layers, the internal wiring layout of the display panel 100 is made more reasonable.

[0044] In one embodiment, three reset connection lines 2 are provided, arranged side-by-side at intervals in the vertical direction, for connecting to the driver IC 200 respectively; the display panel 100 also includes two second reset signal lines 6 and two third reset signal lines 7; the two second reset signal lines 6 are arranged in a crisscross pattern and electrically connected at the intersection, the second reset signal line 6 arranged in the horizontal direction is electrically connected to the drain of the fourth transistor 14 of the pixel driving circuit 1, and one end of the second reset signal line 6 arranged in the vertical direction extends to the first side; the two third reset signal lines 7 are arranged in a crisscross pattern and electrically connected at the intersection, the third reset signal line 7 arranged in the horizontal direction is electrically connected to the drain of the seventh transistor 17 of the pixel driving circuit 1, and one end of the third reset signal line 7 arranged in the vertical direction extends to the first side; wherein, the first reset signal line 3, the second reset signal line 6, the second reset signal line 7, the third ... The ends of signal line 6 and the third reset signal line 7 are respectively connected to the three reset connection lines 2. It can be understood that in the corresponding 8T1C driving circuit, the three reset connection lines 2 correspond to the VI_3 connection line, the VI_Gate (reset signal connected to the drain of the fourth transistor 14 switching switch) connection line, and the VI_ANO (reset signal connected to the drain of the seventh transistor 17 switching switch) connection line, respectively. The first reset signal line 3 is the VI_3 signal line, the second reset signal line 6 is the VI_Gate signal line, and the third reset signal line 7 is the VI_ANO signal line. In the display area a, the two VI_3 signal lines are arranged in a cross configuration, the two VI_Gate signal lines are arranged in a cross configuration, and the two VI_ANO signal lines are arranged in a cross configuration, thereby forming a reset signal transmission network in the display area a, thereby shortening the transmission distance of the reset signal and reducing the transmission delay.

[0045] It should be noted that the display panel 100 includes a first signal line group and a second signal line group arranged in a crisscross pattern. Both the first signal line group and the second signal line group include a first reset signal line 3, a second reset signal line 6, and a third reset signal line 7 arranged side by side at intervals. That is, in the horizontal direction, the first reset signal line 3, the second reset signal line 6, and the third reset signal line 7 are arranged side by side in sequence; in the vertical direction, the first reset signal line 3, the second reset signal line 6, and the third reset signal line 7 are arranged side by side in sequence.

[0046] Furthermore, in one embodiment, please refer to Figure 3The display panel 100 also includes two power signal lines 5, which are arranged in a crisscross pattern and electrically connected at the intersection. The end of each power signal line 5 passes through the display area a and extends to the frame area b, so as to connect with the power connection line on the corresponding side. In the horizontal direction, the VI_3 signal line, VI_Gate signal line, VI_ANO signal line and power signal line 5 are arranged side by side in sequence. In the vertical direction, the VI_3 signal line, VI_Gate signal line, VI_ANO signal line and power signal line 5 are arranged side by side in sequence. In this way, four alternating lines are formed in the display area a. This not only shortens the transmission distance of the reset signal and reduces the transmission delay, but also shortens the transmission distance of the power signal and reduces the transmission delay.

[0047] In one embodiment, please refer to further details. Figure 2 The first signal line group is arranged longitudinally; there are multiple first signal line groups, and the multiple first signal line groups are arranged side by side at intervals in the horizontal direction.

[0048] In some embodiments of this application, the display panel 100 further includes a second power connection line 8, which is disposed on the first side and is used to electrically connect the pixel driving circuit 1 and the driving IC 200. It can be understood that the second power connection line 8 is a VDD signal line. In the corresponding 8T1C driving circuit, VDD signal lines are evenly distributed in each pixel in the display area a. Therefore, it is only necessary to set a VDD signal line on the first side to connect the driving IC 200 and each pixel to realize signal transmission.

[0049] It is known that the pixel driving circuit 1 is configured as an 8T1C driving circuit, which includes a first transistor 11, a second transistor 12, a third transistor 13, a fourth transistor 14, a fifth transistor 15, a sixth transistor 16, a seventh transistor 17, and an eighth transistor 18; the third transistor 13 and the fourth transistor 14 are N-type oxide transistors, and the first transistor 11, the second transistor 12, the fifth transistor 15, the sixth transistor 16, the seventh transistor 17, and the eighth transistor 18 are all P-type oxide transistors.

[0050] Secondly, this application also provides a display device, which includes a display panel 100. It should be noted that the display panel 100 is configured as described above. That is to say, the display device has all the technical features of the above-mentioned display panel 100 embodiments, and thus has all the beneficial effects brought about by all the above-mentioned technical features, which will not be elaborated here.

[0051] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0052] The above provides a detailed description of a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel has a vertical side for mounting a driver IC. The display panel has a display area and a border area surrounding the display area. The border area has a first side for approaching the driver IC. The display panel includes: Pixel driving circuit; A reset connection line is provided on the first side and connected to the driver IC; three reset connection lines are provided, which are arranged side by side at intervals in the vertical direction, and are respectively connected to the driver IC. At least two first reset signal lines are provided corresponding to the display area. The two first reset signal lines are arranged in a cross pattern and electrically connected at the intersection. Among the two first reset signal lines, the horizontally arranged first reset signal line is electrically connected to the drain of the eighth transistor of the pixel driving circuit, and one end of the vertically arranged first reset signal line extends to the first side. Two second reset signal lines are arranged in a crisscross pattern and electrically connected at the intersection. The second reset signal line arranged in the horizontal direction is electrically connected to the drain of the fourth transistor of the pixel driving circuit, and one end of the second reset signal line arranged in the vertical direction extends to the first side; and... Two third reset signal lines are arranged in a cross pattern and electrically connected at the intersection. The third reset signal line arranged in the horizontal direction is electrically connected to the drain of the seventh transistor of the pixel driving circuit, and one end of the third reset signal line arranged in the vertical direction extends to the first side. The ends of the first reset signal line, the second reset signal line, and the third reset signal line are respectively connected to the three reset connection lines.

2. The display panel as described in claim 1, characterized in that, The display panel also includes: A first power connection line is disposed in the frame area and extends circumferentially along the frame area. The first power connection line is used to electrically connect the pixel driving circuit and the driving IC; and... Two power signal lines are arranged in a crisscross pattern and electrically connected at the intersection. The end of each power signal line passes through the display area and extends to the frame area to connect with the power connection line on the corresponding side.

3. The display panel as described in claim 2, characterized in that, The display panel has a first wiring layer and a second wiring layer stacked on top of each other. The power signal lines arranged horizontally are laid on the first wiring layer, and the power signal lines arranged vertically are laid on the second wiring layer. The intersection of the two power signal lines is electrically connected through a first via.

4. The display panel as described in claim 1, characterized in that, The display panel has a third wiring layer and a fourth wiring layer stacked on top of each other; The first reset signal line in the horizontal direction is laid on the third routing layer, and the first reset signal line in the vertical direction is laid on the fourth routing layer. The intersection of the two first reset signal lines is electrically connected through a second via.

5. The display panel as described in claim 1, characterized in that, The display panel includes a first signal line group and a second signal line group arranged in a crisscross pattern. Both the first signal line group and the second signal line group include a first reset signal line, a second reset signal line, and a third reset signal line arranged side by side at intervals.

6. The display panel as described in claim 5, characterized in that, The first signal line group is arranged longitudinally; Multiple first signal line groups are provided, and the multiple first signal line groups are arranged side by side at intervals in the horizontal direction.

7. The display panel as described in claim 1, characterized in that, The display panel also includes a second power connection line, which is located on the first side and is used to electrically connect the pixel driving circuit and the driving IC.

8. The display panel as described in claim 1, characterized in that, The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The third transistor and the fourth transistor are N-type oxide transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type oxide transistors.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

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