Semiconductor memory device

Abstract

The invention provides a semiconductor memory device capable of realizing high speed of data reading. The semiconductor memory device includes: a sense amplifier unit including a first latch circuit and a second latch circuit; and a third latch circuit electrically connected to the sense amplifier unit. A first read-out action is performed according to the first set of instructions, and a second read-out action is performed according to the second set of instructions. When the second set of instructions is input at the first timing, the first data transfer action is performed. When a second instruction set is input at a second timing prior to the first timing, a second data transfer operation is performed. The first data transmission action transmits data of the first latch circuit to the second latch circuit according to the first read-out action, and transmits data of the second latch circuit to the third latch circuit. The second data transmission action transmits data of the first latch circuit to the third latch circuit according to the first read-out action.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Art

[0002] A semiconductor memory device is known that includes a memory string and a plurality of first wirings electrically connected to the memory string. The memory string includes a plurality of memory transistors connected in series, and gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2023-12706

[0006] [Patent Document 2] Japanese Patent Application Publication No. 2022-174874 Summary of the invention

[0007] Provided is a semiconductor memory device capable of realizing high-speed data reading.

[0008] A semiconductor memory device according to one embodiment includes: a memory string having a plurality of memory transistors connected in series; a bit line connected to the memory string; a sense amplifier unit connected to the bit line and having a first latch circuit and a second latch circuit; and a third latch circuit electrically connected to the sense amplifier unit. A first read operation is performed according to a first instruction set, and a second read operation is performed continuously after the first read operation according to a second instruction set. When the second instruction set is input at a first timing, a first data transfer operation is performed. When the second instruction set is input at a second timing earlier than the first timing, a second data transfer operation is performed. The first data transfer operation transfers the data stored in the first latch circuit to the second latch circuit according to the first read operation, and transfers the data stored in the second latch circuit to the third latch circuit. The second data transfer operation transfers the data stored in the first latch circuit to the third latch circuit according to the first read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic block diagram showing the structure of the storage system 10 according to the first embodiment.

[0010] Figure 2 It is a schematic side view showing a configuration example of the storage system 10 .

[0011] Figure 3 It is a schematic plan view showing a configuration example of the storage system 10 .

[0012] Figure 4It is a schematic block diagram showing the structure of the memory chip MD according to the first embodiment.

[0013] Figure 5 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0014] Figure 6 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0015] Figure 7 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0016] Figure 8 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0017] Fig. 9 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0018] Fig.10 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0019] Fig.11 It is a schematic circuit diagram showing a part of the structure of the memory die MD.

[0020] Fig.12 It is a schematic exploded perspective view showing a structural example of the semiconductor memory device according to the present embodiment.

[0021] Fig.13 It means chip C M A schematic bottom view of a structural example of .

[0022] Fig.14 It is a schematic cross-sectional view showing a partial structure of the memory die MD.

[0023] Fig.15 It is a schematic cross-sectional view showing a partial structure of the memory die MD.

[0024] Fig.16 It means chip C M A schematic bottom view of a portion of the structure.

[0025] Fig.17 It means chip C M A schematic cross-sectional view of a portion of the structure.

[0026] Fig.18 It is a schematic diagram for explaining data recorded in the memory cell MC.

[0027] Fig.19It is a timing chart for explaining the read operation of the normal read and the first cache read.

[0028] Fig. 20 is a timing diagram for explaining the read action of normal read and second cache read;

[0029] Fig.21 This is a timing diagram for explaining the operation when the instruction set CS is received.

[0030] Fig. 22 It is a schematic cross-sectional view for explaining the read voltage supply operation.

[0031] Fig.23 It is a waveform diagram for explaining the read operation of the first cache read.

[0032] Fig.24 It is a waveform diagram for explaining the read operation of the second cache read.

[0033] Fig.25 is a flow chart for explaining the data transmission action;

[0034] Fig.26 It is a timing chart for explaining the read operation of the cache read in the comparative example and the second cache read in the first embodiment.

[0035] Fig. 27 It is a timing chart for explaining the read operation of the cache read in the comparative example and the first cache read in the first embodiment.

[0036] Fig.28 This is a waveform diagram for explaining the read operation of the second cache read in the second embodiment.

[0037] Fig.29 It is a timing chart for explaining the read operation of the cache read in the comparative example and the second cache read in the second embodiment.

[0038] Fig.30 It is a timing chart for explaining the read operation of the cache read in the comparative example and the first cache read in the second embodiment.

[0039] Fig.31 This is a waveform diagram for explaining the readout operation of the continuous read in the third embodiment.

[0040] Fig.32 It is a diagram showing a part of waveforms in the readout operation of continuous reading in the third embodiment.

[0041] Fig.33 This is a flowchart for explaining the read operation of the continuous reading in the third embodiment.

[0042] Fig.34 It is a waveform diagram for explaining the read operation of the continuous reading in the fourth embodiment.

[0043] Fig.35 This is a waveform diagram for explaining a modified example of the readout operation of the continuous reading in the fourth embodiment.

[0044] Fig.36 It is a waveform diagram for explaining the read operation of the sequential read in the fifth embodiment.

[0045] Fig.37 Yes means Fig.24 Waveform diagram of a modified example.

[0046] Fig.38 Yes means Fig.31 Waveform diagram of a modified example. DETAILED DESCRIPTION

[0047] Next, the semiconductor memory device of the embodiment is described in detail with reference to the accompanying drawings. In addition, the following embodiment is only an example and is not intended to limit the present invention. In addition, the following drawings are schematic, and for the sake of convenience of description, a part of the structure is sometimes omitted. In addition, the same figure mark is marked on the parts common to multiple embodiments, and the description is sometimes omitted.

[0048] In addition, when the term "semiconductor storage device" is used in this specification, it may mean a memory die, or a storage system including a controller die such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may also mean a structure including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0049] In addition, when referred to as a "control circuit" in this specification, it sometimes means a peripheral circuit such as a sequencer provided in a memory die, sometimes means a controller die or controller chip connected to the memory die, and sometimes means a structure including both of them.

[0050] In addition, in this specification, when it is said that a first structure is "electrically connected" to a second structure, the first structure may be directly connected to the second structure, or the first structure may be connected to the second structure via wiring, a semiconductor component, or a transistor. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the off state.

[0051] In addition, in this specification, when the first structure and the second structure and the third structure are referred to as “indirectly connected”, the first structure, the second structure, and the third structure may be connected in series, and the second structure may be connected to the third structure via the first structure.

[0052] In this specification, when a circuit or the like is referred to as bringing two wirings into "conduction", for example, the circuit or the like may include a transistor or the like which is provided in a current path between the two wirings and is in an on state.

[0053] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0054] In addition, in this specification, a direction along a predetermined plane is sometimes referred to as a first direction, a direction along the predetermined plane that intersects the first direction is sometimes referred to as a second direction, and a direction that intersects the predetermined plane is sometimes referred to as a third direction. These first direction, second direction, and third direction may correspond to any of the X direction, the Y direction, and the Z direction, or may not correspond to any of them.

[0055] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the above-mentioned Z direction is called upper, and the direction close to the substrate along the Z direction is called lower. In addition, when a structure is referred to as a lower surface or lower end, it means the surface or end on the substrate side of the structure, and when it is referred to as an upper surface or upper end, it means the surface or end on the opposite side of the substrate of the structure. In addition, the surface intersecting the X direction or the Y direction is called a side surface, etc.

[0056] [First embodiment]

[0057] [Storage system 10]

[0058] Figure 1 It is a schematic block diagram showing the structure of the storage system 10 according to the first embodiment.

[0059] The storage system 10 reads, writes, and erases user data according to signals sent from the host computer 20. The storage system 10 is, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The storage system 10 includes a plurality of memory chips MD and a controller chip CD.

[0060] The memory die MD stores user data. The memory die MD includes a plurality of memory blocks BLK. The memory block BLK includes a plurality of pages PG. The memory block BLK may also be an execution unit of an erase operation. The page PG may also be an execution unit of a read operation and a write operation.

[0061] like Figure 1 As shown, the controller die CD is connected to a plurality of memory die MD and a host 20. The controller die CD includes a logical-physical conversion table 21, a file allocation table (FAT: File Allocation Table) 22, an erase count storage unit 23, an ECC circuit 24, and a microprocessor unit (MPU: Micro Processor Unit) 25, for example.

[0062] The logical-physical conversion table 21 stores the logical addresses received from the host computer 20 and the physical addresses assigned to the pages PG in the memory die MD in association with each other. The logical-physical conversion table 21 is implemented by, for example, a RAM (Random Access Memory) not shown.

[0063] FAT22 stores FAT information indicating the status of each page PG. As such FAT information, there is information indicating "valid", "invalid", and "erased". For example, a "valid" page PG stores valid data read out according to a command from the host 20. In addition, an "invalid" page PG stores invalid data that is not read out according to a command from the host 20. In addition, in an "erased" page PG, no data is stored after the erasure process is performed. FAT22 is implemented, for example, by a RAM, etc., not shown in the figure.

[0064] The erase count storage unit 23 stores the physical address corresponding to the memory block BLK and the number of erase operations performed on the memory block BLK in association with each other. The erase count storage unit 23 is implemented by, for example, a RAM (not shown).

[0065] The ECC circuit 24 detects errors in data read from the memory chip MD and corrects the data when possible.

[0066] The MPU 25 refers to the logical-physical conversion table 21 , FAT 22 , the erase count storage unit 23 , and the ECC circuit 24 , and performs processing such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), and wear leveling.

[0067] Figure 2 It is a schematic side view showing a configuration example of the storage system 10 according to the present embodiment. Figure 3 FIG. 1 is a schematic top view showing the structural example. Figure 2 and Figure 3 Some structures are omitted.

[0068] like Figure 2As shown, the storage system 10 of the present embodiment includes a mounting substrate MSB, a plurality of memory bare chips MD, and a controller bare chip CD. A pad electrode Px is provided in a region at an end in the Y direction of the upper surface of the mounting substrate MSB. The region other than the end in the Y direction of the upper surface of the mounting substrate MSB is bonded to the lower surface of the memory bare chip MD via an adhesive or the like. A plurality of memory bare chips MD are stacked on the mounting substrate MSB. A pad electrode Px is provided in a region at an end in the Y direction of the upper surface of the memory bare chip MD. The region other than the end in the Y direction of the upper surface of the memory bare chip MD is bonded to the lower surface of another memory bare chip MD or the controller bare chip CD via an adhesive or the like. The controller bare chip CD is stacked on the memory bare chip MD. A pad electrode Px is provided in a region at an end in the Y direction of the upper surface of the controller bare chip CD.

[0069] like Figure 3 As shown, the mounting substrate MSB, the plurality of memory chips MD, and the controller chip CD each include a plurality of pad electrodes Px arranged in the X direction. The mounting substrate MSB, the plurality of memory chips MD, and the plurality of pad electrodes Px provided on the controller chip CD are connected to each other via bonding wires B.

[0070] in addition, Figure 2 and Figure 3 The structure shown is only an example, and the specific structure can be adjusted appropriately. Figure 2 and Figure 3 In the example shown, the controller die CD is stacked on the plurality of memory dies MD. In addition, the memory die MD and the controller die CD are connected by bonding wires B. In addition, the plurality of memory dies MD and the controller die CD are contained in one package. However, the controller die CD may also be contained in a package different from the memory die MD. In addition, the plurality of memory dies MD and the controller die CD may also be connected to each other via through electrodes, etc., instead of bonding wires B.

[0071] [Circuit structure of memory die MD]

[0072] Figure 4 It is a schematic block diagram showing the structure of the memory chip MD according to the first embodiment. Figure 5 to Figure 11 It is a schematic circuit diagram showing the structure of a part of the memory die MD.

[0073] In addition, Figure 4In the figure, multiple control terminals are shown. These multiple control terminals are sometimes shown as control terminals corresponding to high-level valid signals (positive logic signals). In addition, multiple control terminals are sometimes shown as control terminals corresponding to low-level valid signals (negative logic signals). In addition, multiple control terminals are sometimes shown as control terminals corresponding to both high-level valid signals and low-level valid signals. Figure 4 In the specification, the reference numerals of the control terminals corresponding to the low-level active signals include an overline (upper line). In the specification, the reference numerals of the control terminals corresponding to the low-level active signals include a slash (" / "). In addition, Figure 4 The description is an example, and the specific method can be adjusted appropriately. For example, part or all of the high-level active signals can be set to low-level active signals, or part or all of the low-level active signals can be set to high-level active signals.

[0074] like Figure 4 As shown, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. In addition, the peripheral circuit PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR.

[0075] [Circuit structure of memory cell array MCA]

[0076] The memory cell array MCA is Figure 5 As shown, it has the above-mentioned multiple storage blocks BLK. These multiple storage blocks BLK respectively have multiple string units SU. These multiple string units SU respectively have multiple storage strings MS. One end of these multiple storage strings MS is connected to the peripheral circuit PC via the bit line BL. In addition, the other ends of these multiple storage strings MS are connected to the peripheral circuit PC via a common source line SL.

[0077] The memory string MS includes a drain side selection transistor STD, a plurality of memory cells MC (memory transistors), a source side selection transistor STS, and a source side selection transistor STSb. The drain side selection transistor STD, the plurality of memory cells MC, the source side selection transistor STS, and the source side selection transistor STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb are sometimes referred to as selection transistors (STD, STS, STSb).

[0078] The memory cell MC is a field effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1 bit or multiple bits of data. In addition, word lines WL are respectively connected to the gate electrodes of multiple memory cells MC corresponding to one memory string MS. These word lines WL are respectively connected to all memory strings MS in one memory block BLK.

[0079] The selection transistors (STD, STS, STSb) are field effect transistors. The selection transistors (STD, STS, STSb) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors (STD, STS, STSb) are respectively connected to selection gate lines (SGD, SGS, SGSb). One drain-side selection gate line SGD is commonly connected to all storage strings MS in one string unit SU. One source-side selection gate line SGS is commonly connected to all storage strings MS in one storage block BLK. One source-side selection gate line SGSb is commonly connected to all storage strings MS in one storage block BLK.

[0080] [Circuit Configuration of Voltage Generating Circuit VG]

[0081] Voltage generating circuit VG( Figure 4 ) For example Figure 6 As shown, a plurality of voltage generating units vg1 to vg3 are provided. The voltage generating units vg1 to vg3 generate voltages of predetermined magnitudes in the read operation, the write operation, and the erase operation, and supply the voltages to the voltages through the voltage supply lines L. VG (L VG1 ~L VG3 ) output. For example, the voltage generating unit vg1 outputs a programming voltage used in a write operation. In addition, the voltage generating unit vg2 outputs a read channel voltage V described later in a read operation. READ In addition, the voltage generating unit vg2 outputs a write channel voltage used in the write operation. In addition, the voltage generating unit vg3 outputs a read voltage described later in the read operation. In addition, the voltage generating unit vg3 outputs a verification voltage described later in the write operation. The voltage generating units vg1 to vg3 can be, for example, a boost circuit such as a charge pump circuit, or a step-down circuit such as a regulator. These step-down circuits and boost circuits are respectively connected to the voltage supply line L P Connect the voltage supply line L P In the CC or ground voltage V SS ( Figure 4 ). These voltage supply lines LP For example, with reference Figure 2 , Figure 3 The pad electrode Px described above is connected to the operating voltage output from the voltage generating circuit VG according to the control signal from the sequencer SQC.

[0082] The charge pump circuit 32 ( Figure 7 ) includes a voltage output circuit 32a, a voltage dividing circuit 32b and a comparator 32c. The voltage output circuit 32a supplies a voltage to a voltage supply line L VG Output voltage V OUT The voltage divider circuit 32b and the voltage supply line L VG The comparator 32c generates a voltage V output from the voltage divider circuit 32b. OUT ' and the reference voltage V REF The feedback signal FB is output to the voltage output circuit 32a according to the magnitude relationship of .

[0083] like Figure 8 As shown in FIG. 1 , the voltage output circuit 32a includes a plurality of transistors 32a2a and 32a2b. The plurality of transistors 32a2a and 32a2b are connected to the voltage supply line L VG and voltage supply line L P The voltage supply line L shown in the figure is connected alternately. P Supply voltage V CC . The gate electrodes of the plurality of transistors 32a2a and 32a2b connected in series are connected to their respective drain electrodes and the capacitor 32a3. In addition, the voltage output circuit 32a includes an AND circuit 32a4, a level shifter 32a5a, and a level shifter 32a5b. The AND circuit 32a4 outputs the logical sum of the clock signal CLK and the feedback signal FB. The level shifter 32a5a boosts and outputs the output signal of the AND circuit 32a4. The output terminal of the level shifter 32a5a is connected to the gate electrode of the transistor 32a2a via the capacitor 32a3. The level shifter 32a5b boosts and outputs the inverted signal of the output signal of the AND circuit 32a4. The output terminal of the level shifter 32a5b is connected to the gate electrode of the transistor 32a2b via the capacitor 32a3.

[0084] When the feedback signal FB is in the "H" state, the clock signal CLK is output from the AND circuit 32a4. VG To the voltage supply line L P Transfer electrons, voltage supply line L VG On the other hand, when the feedback signal FB is in the "L" state, the clock signal CLK is not output from the AND circuit 32a4. VG The voltage does not increase.

[0085] like Figure 7 As shown in FIG. 1 , the voltage divider circuit 32 b includes a resistor element 32 b 2 and a variable resistor element 32 b 4 . The resistor element 32 b 2 is connected to the voltage supply line L VG The variable resistance element 32b4 is connected in series between the voltage dividing terminal 32b1 and the voltage supply line L. P The voltage is supplied to the line L P Supply ground voltage V SS The resistance value of the variable resistor 32b4 can be adjusted according to the operating voltage control signal V CTRL Therefore, the voltage V at the voltage dividing terminal 32b1 is OUT The size of ' can be controlled according to the action voltage control signal V CTRL Make adjustments.

[0086] like Fig. 9 As shown in FIG. 1 , the variable resistance element 32b4 includes a plurality of current paths 32b5. The plurality of current paths 32b5 are connected in parallel between the voltage dividing terminal 32b1 and the voltage supply line L P The plurality of current paths 32b5 each include a resistor 32b6 and a transistor 32b7 connected in series. The resistance values ​​of the resistor 32b6 provided in each current path 32b5 may be different from each other. The gate electrode of the transistor 32b7 is input with an operating voltage control signal V CTRL In addition, the variable resistance element 32b may have a current path 32b8 that does not include the transistor 32b7.

[0087] like Figure 7 As shown, the comparator 32c outputs a feedback signal FB. The feedback signal FB is, for example, a voltage V OUT ' is greater than the reference voltage V REF In addition, the feedback signal FB is in the "L" state when the voltage V OUT 'Compared to reference voltage V REF When the value is small, it becomes the "H" state.

[0088] [Circuit Structure of Row Decoder RD]

[0089] For example Figure 6 As shown, the row decoder RD includes a block decoder BLKD, a word line decoder WLD, a drive circuit DRV, and an address decoder (not shown).

[0090] The block decoder BLKD includes a plurality of block decoding units blkd. The plurality of block decoding units blkd correspond to the plurality of memory blocks BLK in the memory cell array MCA. The block decoding unit blkd includes a plurality of transistors T BLK. Multiple transistors T BLK Corresponding to a plurality of word lines WL in the memory block BLK. Transistor T BLK For example, it is a field effect type NMOS transistor. BLK The drain electrode of transistor T is connected to the word line WL. BLK The source electrode of transistor T is connected to wiring CG. Wiring CG is connected to all block decoding units blkd in block decoder BLKD. BLK The gate electrode of is connected to the signal line BLKSEL. A plurality of signal lines BLKSEL are provided corresponding to all the block decoding units blkd. In addition, the signal line BLKSEL is connected to all the transistors T in the block decoding unit blkd. BLK .

[0091] In a read operation, a write operation, etc., for example, with the address register ADR ( Figure 4 ) is set to the "H" state for a signal line BLKSEL corresponding to the block address in the block address, and the voltage of the other signal lines BLKSEL is set to the "L" state. For example, a predetermined driving voltage with a positive magnitude is supplied to one signal line BLKSEL, and a ground voltage V is supplied to the other signal lines BLKSEL. SS As a result, all word lines WL in one memory block BLK corresponding to the block address are conducted to all wirings CG. In addition, all word lines WL in other memory blocks BLK are in a floating state.

[0092] The word line decoder WLD includes a plurality of word line decoding units wld. The plurality of word line decoding units wld correspond to the plurality of memory cells MC in the memory string MS. In the example shown in the figure, the word line decoding unit wld includes two transistors T WLS , T WLU . Transistor T WLS , T WLU For example, it is a field effect type NMOS transistor. WLS , T WLU The drain electrode of transistor T is connected to wiring CG. WLS The source electrode and wiring CG S Connection. Transistor T WLU The source electrode and wiring CG U Connection. Transistor T WLS The gate electrode and signal line WLSEL S Connection. Transistor T WLU The gate electrode and signal line WLSEL U Connected to a transistor T included in all word line decoding units wld WLS A plurality of signal lines WLSEL are provided accordingly S. Another transistor T included in all word line decoding units wld WLU A plurality of signal lines WLSEL are provided accordingly U .

[0093] In a read operation, a write operation, etc., for example, with the address register ADR ( Figure 4 ) corresponds to a signal line WLSEL corresponding to a word line decoding unit wld S The voltage of the WLSEL U The voltage of the word line decoder wld is turned into the "L" state. S The voltage of becomes "L" state, and the corresponding WLSEL U The voltage of the wiring CG becomes "H". S Supply and select word line WL S In addition, the wiring CG U Supply and unselect word line WL U Thus, a voltage corresponding to the page address is supplied to the word line WL corresponding to the page address and the selected word line WL S In addition, the voltage corresponding to the non-selected word line WL is supplied to the other word lines WL. U The corresponding voltage.

[0094] The driver circuit DRV includes, for example, six transistors T DRV1 ~T DRV6 . Transistor T DRV1 ~T DRV6 For example, it is a field effect type NMOS transistor. DRV1 ~T DRV4 The drain electrode and wiring CG S Connection. Transistor T DRV5 , T DRV6 The drain electrode and wiring CG U Connection. Transistor T DRV1 The source electrode is supplied with a voltage via a voltage line L VG1 The transistor T is connected to the output terminal of the voltage generating unit vg1. DRV2 , T DRV5 The source electrode is supplied with a voltage via a voltage line L VG2 The transistor T is connected to the output terminal of the voltage generating unit vg2. DRV3 The source electrode is supplied with a voltage via a voltage line L VG3 The transistor T is connected to the output terminal of the voltage generating unit vg3. DRV4 , T DRV6 The source electrode is supplied with a voltage via a voltage line L P With reference Figure 2 , Figure 3 The pad electrode Px is connected to the transistor T DRV1 ~T DRV6 The gate electrodes are respectively connected to signal lines VSEL1 to VSEL6.

[0095] In a read operation, a write operation, etc., for example, the wiring CG S One of the corresponding signal lines VSEL1 to VSEL4 becomes "H" and the other becomes "L". U The voltage of one of the two corresponding signal lines VSEL5 and VSEL6 becomes the "H" state, and the voltage of the other becomes the "L" state.

[0096] The address decoder (not shown) is configured to receive the address from the sequencer SQC ( Figure 4 ) control signals refer to the address register ADR ( Figure 4 ) of the row address RA. The row address RA includes the block address and the page address. The address decoder transmits the signal lines BLKSEL and WLSEL S 、WLSEL U The voltage is controlled to be "H" state or "L" state.

[0097] In addition, Figure 6 In the example of FIG. 1 , one block decoding unit blkd is provided for each storage block BLK in the row decoder RD. However, this structure can be changed as appropriate. For example, one block decoding unit blkd can be provided for each of two or more storage blocks BLK.

[0098] [Circuit structure of sense amplifier module SAM]

[0099] Sense Amplifier Module SAM( Figure 4 ) For example Fig.10 As shown, a plurality of sense amplifier units SAU are provided. The plurality of sense amplifier units SAU correspond to the plurality of bit lines BL. The sense amplifier units SAU each include a sense amplifier SA, a wiring LBUS, and latch circuits SDL, ADL, BDL, and CDL. A charging transistor 55 ( Fig.11 ). The wiring LBUS is connected to the wiring DBUS via the switching transistor DSW.

[0100] like Fig.11 As shown in FIG. 1 , the sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charge in the wiring LBUS according to the current flowing in the bit line BL. The source electrode of the sense transistor 41 is connected to a ground voltage V SSThe drain electrode is connected to the wiring LBUS via the switch transistor 42. The gate electrode is connected to the bit line BL via the read node SEN, the discharge transistor 43, the node COM, the clamp transistor 44 and the withstand voltage transistor 45. In addition, the read node SEN is connected to the internal control signal line CLKSA via the capacitor 48.

[0101] In addition, the sense amplifier SA includes a voltage transmission circuit. The voltage transmission circuit selectively connects the node COM and the sense node SEN to the supplied voltage V according to the data latched in the latch circuit SDL. DD The voltage supply line or the voltage V SRC The voltage supply line is turned on. The voltage transmission circuit includes a node N1, a charging transistor 46, a charging transistor 49, a charging transistor 47 and a discharging transistor 50. The charging transistor 46 is connected between the node N1 and the readout node SEN. The charging transistor 49 is connected between the node N1 and the node COM. The charging transistor 47 is connected between the node N1 and the voltage V DD The discharge transistor 50 is connected between the node N1 and the voltage supply line V SRC In addition, the gate electrodes of the charging transistor 47 and the discharging transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

[0102] The read transistor 41, the switch transistor 42, the discharge transistor 43, the clamp transistor 44, the charge transistor 46, the charge transistor 49 and the discharge transistor 50 are, for example, enhancement-mode NMOS transistors. The withstand voltage transistor 45 is, for example, a depletion-mode NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0103] In addition, the gate electrode of the switching transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamp transistor 44 is connected to the signal line BLC. The gate electrode of the withstand voltage transistor 45 is connected to the signal line BLS. The gate electrode of the charging transistor 46 is connected to the signal line HLL. The gate electrode of the charging transistor 49 is connected to the signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC.

[0104] The latch circuit SDL includes nodes LAT_S, INV_S, an inverter 51, an inverter 52, a switch transistor 53, and a switch transistor 54. The inverter 51 includes an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S. The inverter 52 includes an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S. The switch transistor 53 is provided in a current path between the node LAT_S and the wiring LBUS. The switch transistor 54 is provided in a current path between the node INV_S and the wiring LBUS. The switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switch transistor 53 is connected to the sequencer SQC via the signal line STL. The gate electrode of the switch transistor 54 is connected to the sequencer SQC via the signal line STI.

[0105] The latch circuits ADL, BDL, and CDL are configured substantially similarly to the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is conductively connected to the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. The latch circuits ADL, BDL, and CDL are different from the latch circuit SDL in this respect.

[0106] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via the signal line DBS.

[0107] In addition, if Fig.10 As shown in the example, the signal lines STB, HLL, XXL, BLX, BLC, and BLS are connected in common between all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line and the supplied voltage V SRC The voltage supply lines are connected in common between all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the signal lines STI and the signal lines STL of the latch circuit SDL are connected in common between all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines ATI, ATL, BTI, BTL, CTI, and CTL corresponding to the signal lines STI and STL in the latch circuits ADL, BDL, and CDL are connected in common between all the sense amplifier units SAU included in the sense amplifier module SAM. On the other hand, the above-mentioned signal lines DBS are provided in plurality corresponding to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0108] [Circuit Structure of Cache Memory CM]

[0109] like Fig.10 As shown, the cache memory CM ( Figure 4 ) includes a plurality of latch circuits XDL. The plurality of latch circuits XDL are connected to the latch circuits in the sense amplifier module SAM via wiring DBUS.

[0110] The data DAT contained in these multiple latch circuits XDL are sequentially transferred to the latch circuits in the sense amplifier module SAM during the write operation. In addition, the data DAT contained in the latch circuits in the sense amplifier module SAM are sequentially transferred to the latch circuits XDL during the read operation. Generally speaking, when data transmission using the wiring DBUS is performed, the power supply voltage V is supplied to the wiring DBUS for charging and discharging. CC The operating current I flowing through the pad electrode Px CC In addition, the data DAT contained in the latch circuit XDL is sequentially transmitted to the input / output control circuit I / O via the bidirectional bus YIO when performing a data output operation.

[0111] In addition, the cache memory CM is connected to a decoding circuit and a switch circuit (not shown). The decoding circuit decodes the column address CA stored in the address register ADR. The switch circuit switches the latch circuit corresponding to the column address CA to the bidirectional bus YIO ( Figure 4 ) is turned on.

[0112] [Circuit structure of sequencer SQC]

[0113] Sequencer SQC( Figure 4 ) According to the instruction data D stored in the instruction register CMR CMD , outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC appropriately outputs the state data D indicating its own state. ST Output to status register STR.

[0114] In addition, the sequencer SQC generates a ready / busy signal RB and outputs it to the terminal RBn. The ready / busy signal RB is a signal that notifies the controller die CD whether it is in a ready state where instructions from the controller die CD can be accepted or in a busy state where instructions cannot be accepted. During the period when the voltage at the terminal RBn is in the "L" state (busy period), access to the memory die MD is basically prohibited. In addition, during the period when the voltage at the terminal RBn is in the "H" state (ready period), access to the memory die MD is permitted. In addition, the terminal RBn is controlled by, for example, referring to Figure 2 , Figure 3 This is achieved by the pad electrode Px described above.

[0115] [Circuit structure of input / output control circuit I / O]

[0116] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, trigger signal input / output terminals DQS and / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are respectively connected to the power supply voltage V CC and ground voltage V SS terminal connections.

[0117] The data signal input / output terminals DQ0 to DQ7, the trigger signal input / output terminals DQS and / DQS, and the power supply voltage V CC The terminals are such as by referring to Figure 2 , Figure 3 The data inputted through the data signal input / output terminals DQ0 to DQ7 are outputted from the buffer circuit to the cache memory CM, the address register ADR or the instruction register CMR according to the internal control signal from the logic circuit CTR. In addition, the data outputted through the data signal input / output terminals DQ0 to DQ7 are inputted from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0118] The plurality of input circuits include, for example, a comparator connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the trigger signal input / output terminals DQS and / DQS. The plurality of output circuits include, for example, an OCD (Off Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or any one of the trigger signal input / output terminals DQS and / DQS.

[0119] [Circuit structure of logic circuit CTR]

[0120] Logic circuit CTR( Figure 4 ) receives an external control signal from the controller bare chip CD via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and accordingly outputs an internal control signal to the input / output control circuit I / O. In addition, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are, for example, Figure 2 , Figure 3 This is achieved by the pad electrode Px described above.

[0121] [Structure of memory die MD]

[0122] Fig.121 is a schematic exploded perspective view showing an example of the structure of a semiconductor memory device according to this embodiment. Fig.12 As shown, the memory die MD has a chip C on the side of the memory cell array MCA. M And peripheral circuit PC side chip C P .

[0123] In Chip C M A plurality of pad electrodes Px that can be connected to bonding wires (not shown) are provided on the upper surface of the chip C. M The lower surface is provided with a plurality of bonding electrodes P I1 In addition, in chip C P The upper surface is provided with a plurality of bonding electrodes P I2 . Below, about chip C M , a plurality of bonding electrodes P are provided I1 The surface of the chip C is called the front surface, and the surface on which the plurality of pad electrodes Px are provided is called the back surface. P , a plurality of bonding electrodes P are provided I2 The surface on the opposite side of the surface is called the front surface, and the surface on the opposite side of the surface is called the back surface. P The surface is set at the ratio chip C P At the top of the back, chip C M The back side is set at the ratio chip C M The surface is located above.

[0124] Chip C M and Chip C P Chip C M The surface of the chip C P The plurality of electrodes P are arranged so that the surfaces thereof face each other. I1 With a plurality of bonding electrodes P I2 Correspondingly, it is arranged to be able to be bonded with multiple electrodes P I2 Bonding position. Bonding electrode P I1 and bonding electrode P I2 As a chip C M and Chip C P The bonded electrodes that are bonded and electrically connected function.

[0125] In addition, Fig.12 In the example, chip C M The corners a1, a2, a3, and a4 of the chip C are P The corners b1, b2, b3, and b4 correspond to each other.

[0126] Fig.13 It means chip C M A schematic bottom view of a structural example of. Fig.13In the figure, the bonding electrode P is omitted. I1 etc. Fig.14 and Fig.15 It is a schematic cross-sectional view showing a partial structure of the memory die MD. Fig.16 It means chip C M A schematic bottom view of a portion of the structure. Fig.17 It means chip C M A schematic cross-sectional view of a portion of the structure. Fig.17 The YZ cross section is shown, but when observing a cross section other than the YZ cross section (for example, the XZ cross section) along the central axis of the semiconductor layer 120, the same Fig.17 Same structure.

[0127] [Chip C M Structure of

[0128] exist Fig.13 In the example, chip C M The four memory planes MPL0, MPL1, MPL2, and MPL3 are arranged in the X direction. The four memory planes MPL0 to MPL3 correspond to the memory cell array MCA ( Figure 5 ). In addition, each of the four memory planes MPL0 to MPL3 includes a plurality of memory blocks BLK arranged in the Y direction. Fig.13 In the example, the plurality of memory blocks BLK each include a connection region R provided at both ends in the X direction. HU , and a storage hole region R disposed therebetween MH In addition, chip C M A peripheral region R is provided on one end side of the four memory planes MPL0 to MPL3 in the Y direction. P .

[0129] In the example shown in the figure, the connection area R HU Set in the memory cell array area R MCA However, such a structure is only an example, and the specific structure can be adjusted appropriately. For example, the connection area R HU It is also possible not to set it in the memory cell array area R MCA The connection area R HU It can also be set in the memory cell array area R MCA The center position or the vicinity of the center in the X direction.

[0130] Chip C M For example Fig.14 As shown, it has a base layer L SB , set in the base layer LSB The memory cell array layer L below MCA , and disposed in the memory cell array layer L MCA Multiple wiring layers CH, M0, M1, MB below.

[0131] [Chip C M The base layer L SB Structure of

[0132] For example Fig.14 As shown, the base layer L SB It has: a conductive layer 100, which is disposed on the memory cell array layer L MCA insulating layer 101, disposed on the upper surface of the conductive layer 100; a back wiring layer MA, disposed on the upper surface of the insulating layer 101; and an insulating layer 102, disposed on the upper surface of the back wiring layer MA.

[0133] Conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), a metal such as tungsten (W), or a silicide such as tungsten silicide (WSi).

[0134] The conductive layer 100 serves as the source line SL ( Figure 5 ) part of the function. With the four memory planes MPL0~MPL3 ( Fig.13 ) are provided corresponding to four conductive layers 100. Regions VZ not including the conductive layers 100 are provided at the ends of the memory planes MPL0 to MPL3 in the X direction and the Y direction.

[0135] The insulating layer 101 includes, for example, silicon oxide (SiO 2 ) or the like.

[0136] The backside wiring layer MA includes a plurality of wirings ma. These plurality of wirings ma may include, for example, aluminum (Al) or the like.

[0137] Some of the plurality of wirings ma serve as source lines SL ( Figure 5 ) part. This wiring ma is connected to the four memory planes MPL0~MPL3 ( Fig.13 ) are provided correspondingly. The wirings ma are electrically connected to the conductive layer 100 respectively.

[0138] In addition, some of the plurality of wirings ma function as pad electrodes Px. The wirings ma are provided in the peripheral region R P The wiring ma is connected to the memory cell array layer L in the region VZ that does not include the conductive layer 100. MCA In addition, a part of the wiring ma is exposed to the outside of the memory chip MD through an opening TV provided in the insulating layer 102 .

[0139] The insulating layer 102 is, for example, a passivation layer made of an insulating material such as polyimide.

[0140] [Chip C M The memory cell array layer L MCA Storage hole area R MH Structure in

[0141] As reference Fig.13 As described above, in the memory cell array layer L MCA In the embodiment, a plurality of storage blocks BLK are arranged in the Y direction. Fig.14 As shown, an inter-block insulating layer ST made of silicon oxide (SiO 2 ) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction.

[0142] The storage block BLK is, for example, Fig.14 As shown in FIG. 1 , the semiconductor device includes a plurality of conductive layers 110 arranged in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction. Fig.17 As shown, gate insulating films 130 are respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120 .

[0143] The conductive layer 110 has a substantially plate-like shape extending in the X direction. The conductive layer 110 may also include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0144] One or more conductive layers 110 located at the uppermost layer among the plurality of conductive layers 110 serve as source side selection transistors STS ( Figure 5 ) and the source side selection gate line SGS function (refer to Fig.14 ). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0145] In addition, a plurality of conductive layers 110 located below the conductive layers 110 serve as memory cells MC ( Figure 5 ) functions as a gate electrode and a word line WL. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0146] In addition, one or more conductive layers 110 located below the drain side select transistor STD function as a gate electrode and a drain side select gate line SGD. Fig.16 As shown, the width Y of the Y direction of these multiple conductive layers 110 is SGDsmaller than the width Y in the Y direction of the conductive layer 110 functioning as the word line WL. WL In addition, an insulating layer SHE such as silicon oxide (SiO 2 ) is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0147] The semiconductor layer 120 is, for example, Fig.16 As shown in FIG. 1 , the semiconductor layer 120 is arranged in a predetermined pattern in the X direction and the Y direction. Fig.12 ) and the channel region of the selection transistors (STD, STS). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the center. The outer peripheral surface of the semiconductor layer 120 is surrounded by a plurality of conductive layers 110, and faces these plurality of conductive layers 110.

[0148] In addition, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. The impurity region is connected to the conductive layer 100 (see Fig.14 ). The impurity region includes, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0149] In addition, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. The impurity region is connected to the bit line BL via the via contact electrode ch and the via contact electrode Vy. The impurity region contains, for example, N-type impurities such as phosphorus (P).

[0150] The gate insulating film 130 is, for example, Fig.16 As shown in FIG. 1 , the gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. Fig.17 As shown, a tunnel insulating film 131, a charge storage film 132 and a blocking insulating film 133 are stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the blocking insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132 and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0151] Fig.17 The gate insulating film 130 is shown as an example including the charge storage film 132 made of silicon nitride, for example. However, the gate insulating film 130 may include a floating gate made of polysilicon containing N-type or P-type impurities, for example.

[0152] [Chip C M The memory cell array layer L MCAThe connection area R HU Structure in

[0153] like Fig.15 As shown, in the connection area R HU A plurality of through-hole contact electrodes CC are provided in the conductive layer 110. The plurality of through-hole contact electrodes CC extend in the Z direction and are connected to the conductive layer 110 at their upper ends.

[0154] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in

[0155] In the surrounding area R P For example, Fig.14 As shown in FIG. 1 , a plurality of through-hole contact electrodes CC are provided corresponding to the pad electrodes Px. The plurality of through-hole contact electrodes CC are connected to the pad electrodes Px at their upper ends.

[0156] [Chip C M The structure of the wiring layers CH, M0, M1, MB]

[0157] The wiring layers CH, M0, M1, and MB include a plurality of wirings, for example, connected to the memory cell array layer L. MCA Structure and chip C P At least one of the structures in is electrically connected.

[0158] The wiring layer CH includes a plurality of through-hole contact electrodes ch as a plurality of wirings. These plurality of through-hole contact electrodes ch may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The through-hole contact electrodes ch are provided corresponding to the plurality of semiconductor layers 120 and connected to the lower ends of the plurality of semiconductor layers 120.

[0159] The wiring layer M0 includes a plurality of wirings m0. These plurality of wirings m0 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). In addition, some of the plurality of wirings m0 function as bit lines BL. The bit lines BL are, for example, Fig.16 As shown, they are arranged along the X direction and extend along the Y direction.

[0160] The wiring layer M1 is, for example, Fig.14 As shown, the plurality of wirings m1 are included. The plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0161] The wiring layer MB includes a plurality of bonding electrodes P I1 These multiple bonded electrodes P I1For example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu) may be included.

[0162] [Chip C P Structure of

[0163] Chip C P For example Fig.14 As shown, the semiconductor substrate 200, an electrode layer GC provided on the semiconductor substrate 200, and wiring layers D0, D1, D2, D3, D4, and DB provided on the electrode layer GC are provided.

[0164] [Chip C P Structure of the semiconductor substrate 200]

[0165] The semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, for example, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S where the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region 200I are provided. The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S function as a part of a plurality of transistors Tr and a plurality of capacitors constituting the peripheral circuit PC, respectively.

[0166] [Chip C P The structure of the electrode layer GC]

[0167] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to the through-hole contact electrodes CSb.

[0168] The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S of the semiconductor substrate 200 function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC, one electrode of a plurality of capacitors, and the like.

[0169] The plurality of electrodes gc included in the electrode layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, other electrodes of the plurality of capacitors, and the like.

[0170] The through hole contact electrode CSb extends in the Z direction and is connected to the semiconductor substrate 200 or the upper surface of the electrode gc at the lower end. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the through hole contact electrode CSb and the semiconductor substrate 200. The through hole contact electrode CSb may also include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0171] [Chip C P The structure of the wiring layers D0, D1, D2, D3, D4 and DB]

[0172] For example, Fig.14 As shown, multiple wirings included in D0, D1, D2, D3, D4, and DB are connected to the memory cell array layer L MCA Structure and chip C P At least one of the structures in is electrically connected.

[0173] The wiring layers D0, D1, and D2 include a plurality of wirings d0, d1, and d2, respectively. These plurality of wirings d0, d1, and d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0174] The wiring layers D3 and D4 include a plurality of wirings d3 and d4, respectively. These plurality of wirings d3 and d4 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0175] The wiring layer DB includes a plurality of bonding electrodes P I2 These multiple bonded electrodes P I2 For example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu) may be included.

[0176] [Threshold voltage of memory cell MC]

[0177] Next, refer to Fig.18 , the threshold voltage of the memory cell MC is described. Fig.18 (a) is a schematic histogram for explaining the threshold voltage of the memory cell MC. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Fig.18 (b) is an example of the threshold voltage of the memory cell MC and the data recorded in the memory cell MC.

[0178] As described above, the memory cell array MCA includes a plurality of memory cells MC. When a write operation is performed on the plurality of memory cells MC, the threshold voltages of the memory cells MC are controlled to be in a plurality of states. Fig.18(a) shows the distribution of the threshold voltages of the memory cells MC controlled to the eight states. For example, the threshold voltage ratio of the memory cell MC controlled to the A state is Fig.18 (a) The read voltage V CGAR Larger than the read voltage V CGBR In addition, the threshold voltage of all memory cells MC is smaller than Fig.18 (a) The read channel voltage V READ Small.

[0179] In the present embodiment, the memory cell MC is adjusted to eight states, and thus 3-bit data is recorded in each memory cell MC.

[0180] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erased state). For example, data "111" is allocated to the memory cell MC corresponding to the Er state.

[0181] The A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data "110" is allocated to the memory cell MC corresponding to the A state.

[0182] The B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above-mentioned A state. For example, data "100" is allocated to the memory cell MC corresponding to the B state.

[0183] Similarly, states C to G in the figure correspond to threshold voltages higher than threshold voltages corresponding to states B to F. Data "000", "010", "011", "001", and "101" are assigned to memory cells MC corresponding to these distributions, for example.

[0184] In addition, Fig.18 In the case of the allocation as shown in (b), the data of the lower bits (lower page: LP: Lower Page) can be read by two read voltages V CGAR 、V CGER To determine, the data of the middle bit (middle page: MP: MiddlePage) can be read through three voltages V CGBR 、V CGDR 、V CGFR To determine, the upper bit (upper page: UP: UpperPage) data can be read through two voltages V CGCR 、V CGGR This data allocation is sometimes called 2-3-2 code. The method of performing a read operation on each of the lower page, the middle page, and the upper page is called page read.

[0185] Furthermore, the number of bits of data recorded in the memory cell MC, the number of states, the allocation of data to each state, and the like can be changed as appropriate.

[0186] [Type of reading action mode]

[0187] Next, the types of read operation modes of this embodiment are described. As the types of read operation modes of this embodiment, there are a normal read mode and a cache read mode. In addition, as the types of cache read, there are a first cache read and a second cache read.

[0188] Fig.19 It is a timing chart for explaining the read operation of the normal read and the first cache read. Fig. 20 It is a timing chart for explaining the read operation of the normal read and the second cache read.

[0189] exist Fig.19 and Fig. 20 In the instruction set, "Read(N)" indicates the read operation of page N, "Read(N+1)" indicates the read operation of page N+1, and "Read(N+2)" indicates the read operation of page N+2. In addition, N is an integer greater than 1. In addition, "Dout(N)" indicates the data output operation of page N, "Dout(N+1)" indicates the data output operation of page N+1, and "Dout(N+2)" indicates the data output operation of page N+2. In addition, "ADD(N)" in the instruction set indicates that the address data D that specifies page N is included. ADD "ADD(N+1)" indicates that the address data D of the determined page N+1 is included. ADD "ADD(N+2)" indicates that the address data D of the determined page N+2 is included. ADD .

[0190] [Normal read mode]

[0191] The normal read mode is a mode for performing a normal read operation. Fig.19 and Fig. 20 As shown, in normal reading, when the ready / busy signal RB is controlled to the "H" state (ready state), if the slave controller die CD receives an instruction set indicating normal reading ( Fig.19 and Fig. 20 If “00h-ADD(N)-30h” is received, the read operation (Read(N)) of page N is started, and the ready / busy signal RB is controlled to the “L” state (busy state).

[0192] By performing a normal read operation (Read(N)) in the memory cell array MCA, the read data (the read data of page N) is stored in the latch circuit SDL in the sense amplifier module SAM. The read data stored in the latch circuit SDL in the sense amplifier module SAM is transferred to the latch circuit XDL in the cache memory CM before the read operation is completed.

[0193] When the read operation (Read(N)) of normal reading in the memory cell array MCA is completed, the ready / busy signal RB is controlled from the "L" state (busy state) to the "H" state (ready state), and becomes a state capable of accepting a command set instructing normal reading or cache reading. In the normal reading mode, the state of the ready / busy signal RB is consistent with "True busy". "True busy" indicates that access to the sense amplifier module SAM is prohibited, or a write operation, a read operation, an erase operation, etc. is being performed on the memory cell array MCA.

[0194] [Cache read mode]

[0195] The cache read mode is a mode in which a cache read operation is performed. There are first cache reads in which a data transfer operation is performed after the cache read operation is completed and second cache reads in which a data transfer operation is included in the cache read operation.

[0196] [First Cache Read]

[0197] like Fig.19 As shown, in the first cache read, when the ready / busy signal RB is controlled to the "H" state (ready state), if the instruction set indicating the cache read is accepted ( Fig.19 When "00h-ADD(N+1)-31h", hereinafter sometimes referred to as cache read instruction), the read action (Read(N+1)) of page N+1 is started, and the ready / busy signal RB is temporarily controlled from the "H" state (ready state) to the "L" state (busy state), and immediately controlled from the "L" state (busy state) to the "H" state (ready state). In this way, the ready / busy signal RB changes in the order of "H" state, "L" state, and "H" state. Since the read data (the read data of page N) is stored in the latch circuit XDL, there is no need for data transfer action, and the ready / busy signal RB changes in a short time.

[0198] If the ready / busy signal RB is controlled to the "H" state (ready state), the instruction set indicating data output from the controller bare chip CD is accepted ( Fig.19The "05h-ADD(N)-E0h" of the latch circuit XDL is sometimes referred to as the data output instruction below. By accepting this instruction set, the data output action Dout(N) of the read data (the read data of page N) stored in the latch circuit XDL is started. In the cache read, the read action (read (N+1)) and the data transfer action Dout(N) are executed in parallel. When the data output action Dout(N) is completed, it becomes possible to accept the next cache read instruction ( Fig.19 The status of "00h-ADD(N+2)-31h").

[0199] In this way, when the ready / busy signal RB is controlled to the "H" state (ready state), even if the cache read operation (Read(N+1)) is not completed, the cache read instruction can be accepted as the next read operation (Read(N+2)).

[0200] If the slave controller die CD receives a cache read command ( Fig.19 "00h-ADD(N+2)-31h"), the ready / busy signal RB is controlled to the "L" state (busy state). The timing of receiving the cache read instruction is later than the specific timing TA. When the read action (Read(N+1)) of page N+1 is completed, the read data of page N+1 is transferred to the latch circuit XDL. After the read data of page N+1 is transferred to the latch circuit XDL, the read action (Read(N+2)) of page N+2 is started, and the ready / busy signal RB is controlled to the "H" state (ready state).

[0201] Specifically, by performing the read operation (Read(N+1)) of page N+1, the read data (the read data of page N+1) is stored in the latch circuit SDL in the sense amplifier module SAM. The read data stored in the latch circuit SDL in the sense amplifier module SAM is temporarily stored in the latch circuit ADL in the sense amplifier module SAM before the read operation is completed. The read data stored in the latch circuit ADL is transferred to the latch circuit XDL in the cache memory CM at the timing when the read operation of page N+1 is completed and the cache read instruction ("00h-ADD(N+2)-31h") is executed.

[0202] When the read operation (Read(N+2)) of the N+2 page starts, the ready / busy signal RB returns to the "H" state (ready state). In the cache read mode, the state of the ready / busy signal RB is not consistent with "True busy".

[0203] After that, by receiving the data output command from the controller bare chip CD ( Fig.19The data output operation Dout(N+1) of the read data (the read data of page N+1) stored in the latch circuit XDL is performed. Then, the read operation (Read(N+2)) and the data transmission operation Dout(N+1) are performed in parallel. When the data output operation Dout(N+1) is completed, the instruction indicating the end of the cache read is received ( Fig.19 The "3Fh" status.

[0204] When the controller die CD receives the instruction indicating the end of the cache read ( Fig.19 When the ready / busy signal RB is controlled to the "L" state (busy state), the timing of receiving the instruction indicating the end of the cache read is after the specific timing TA. After the read action (Read(N+2)) of page N+2 is completed, the read data of page N+2 is transferred to the latch circuit XDL.

[0205] After that, by receiving the data output command from the controller bare chip CD ( Fig.19 The data output action Dout(N+2) of the read data (the read data of page N+2) stored in the latch circuit XDL is performed.

[0206] [Second Cache Read]

[0207] like Fig. 20 As shown, the read operation (Read(N+1)) of page N+1 and the data output operation (Dout(N)) of page N in the second cache read are the same as the read operation (Read(N+1)) of page N+1 and the data output operation (Dout(N)) of page N in the first cache read. Therefore, repeated descriptions are omitted.

[0208] If the slave controller die CD receives a cache read command ( Fig. 20 The ready / busy signal RB is controlled to the "L" state (busy state) when the cache read instruction is received before the specific timing TA. If the read action (Read(N+1)) of page N+1 is completed, the read action (Read(N+2)) of page N+2 is started immediately, and the ready / busy signal RB is controlled to the "H" state (ready state). The second cache read receives the cache read instruction before the specific timing TA, and before the read action (Read(N+1)) of page N+1 is completed, and the read data of page N+1 is transmitted to the latch circuit XDL.

[0209] Specifically, by performing the read operation (Read(N+1)) of page N+1, the read data (the read data of page N+1) is stored in the latch circuit SDL in the sense amplifier module SAM. The read data stored in the latch circuit SDL in the sense amplifier module SAM is transferred to the latch circuit XDL in the cache memory CM before the read operation is completed. In this way, in the second cache read, the read data stored in the latch circuit SDL is transferred to the latch circuit XDL in the cache memory CM without passing through the latch circuit ADL.

[0210] When the read operation (Read(N+2)) of page N+2 starts, the ready / busy signal RB returns to the "H" state (ready state). Fig. 20 As shown, the read operation (Read(N+1)) of the N+1 page and the read operation (Read(N+2)) of the N+2 page are continuously executed without any interval.

[0211] After that, by receiving the data output command from the controller bare chip CD ( Fig. 20 The data output operation Dout(N+1) of the read data (the read data of page N+1) stored in the latch circuit XDL is performed. Then, the read operation (Read(N+2)) and the data transmission operation Dout(N+1) are performed in parallel. When the data output operation Dout(N+1) is completed, it becomes possible to receive the instruction indicating the end of the next cache read ( Fig. 20 The "3Fh" status.

[0212] When the controller die CD receives the instruction indicating the end of the cache read ( Fig. 20 When the ready / busy signal RB is controlled to the "L" state (busy state), the timing of receiving the instruction indicating the end of the cache read is before the specific timing TA. Before the read action of page N+2 is completed, the read data of page N+2 is transferred to the latch circuit XDL.

[0213] After that, by receiving the data output command from the controller bare chip CD ( Fig. 20 The data output action Dout(N+2) of the read data (the read data of page N+2) stored in the latch circuit XDL is performed.

[0214] Thus, the data transmission speed of the interface between the controller die CD and the memory die MD is increased, and the time of the data output operation Dout is shortened. Therefore, the possibility that the instruction indicating the end of the cache read instruction and the cache read is received before the specific timing TA increases. In this case, if Fig. 20 As shown in FIG. 1 , before the cache read operation is completed, the read data is transferred from the latch circuit SDL to the latch circuit XDL. As a result, the total time of the cache read operation that is executed continuously can be shortened.

[0215] [Reading action command set]

[0216] Next, the operation when the command set for the read operation is received will be described. Fig.21 This is a timing diagram for explaining the operation when the instruction set CS is received.

[0217] In the following description, 8-bit data input to the 8 data signal input / output terminals DQ0 to DQ7 may be represented using a 2-digit hexadecimal number. For example, when "0, 0, 0, 0, 0, 0, 0" is input to the 8 data signal input / output terminals DQ0 to DQ7, the data may be represented as data 00h or the like. Also, when "1, 1, 1, 1, 1, 1, 1" is input, the data may be represented as data FFh or the like.

[0218] exist Fig.21 , an instruction set CS input to the memory chip MD during the read operation of the cache read is exemplified. The instruction set CS is the cache read instruction described above.

[0219] The instruction set CS includes data 00h, A101, A102, A103, A104, A105, and 31h. The data A101, A102, A103, A104, and A105 included in the instruction set CS are sometimes referred to as data D ADD The data D ADD It is the data input to the address register ADR.

[0220] At timing t1, the controller die CD inputs data 00h as the command data D to the memory die MD. CMD ( Figure 4 ). That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of the data 00h, "H" is input to the external control terminal CLE, and "L" is input to the external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". The data 00h is the instruction input at the start of the read operation.

[0221] At timing t2, the controller die CD inputs data A101 as address data D to the memory die MD. ADD ( Figure 4 ). That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of the data A101, "L" is input to the external control terminal CLE, and "H" is input to the external control terminal ALE. In this state, the external control terminal / WE is raised from "L" to "H". The data A101 is part of the column address CA.

[0222] At timing t3, the controller die CD inputs data A102 as address data D to the memory die MD. ADD ( Figure 4 ). Data A102 is a part of column address CA.

[0223] At timing t4, the controller die CD inputs data A103 as address data D to the memory die MD. ADD ( Figure 4 ). Data A103 is a part of the row address RA. Data A103 includes, for example, a block address and a page address. The block address is data for specifying a storage block BLK. The page address is data for specifying a string unit SU and a word line WL.

[0224] At timing t5, the controller die CD inputs data A104 as address data D to the memory die MD. ADD ( Figure 4 ). Data A104 is a part of row address RA. Data A104 includes, for example, a block address and a page address.

[0225] At timing t6, the controller die CD inputs data A105 as address data D to the memory die MD. ADD ( Figure 4 ). Data A105 includes a chip address and a plane address. The chip address is data for specifying one memory die MD from among a plurality of memory die MD controlled by the controller die CD. The plane address is data for specifying one memory plane from among a plurality of memory planes MPL0 to MPL3 controlled by the controller die CD.

[0226] At timing t7, the controller die CD inputs data 31h as command data D to the memory die MD. CMD ( Figure 4 ). Data 31h is a command indicating that the input of the command set CS related to the read operation has been completed.

[0227] At timing t8, the voltage of the terminal RBn (ready / busy signal RB) changes from the "H" state to the "L" state, and access to the memory die MD is prohibited. In addition, a read operation is performed in the memory die MD.

[0228] In addition, Fig.21 In the example, the data D in the instruction set CS ADD The data are A101, A102, A103, A104, and A105. However, the data D ADD It does not mean the same address, it can also be a different address.

[0229] [Read voltage supply operation]

[0230] Next, the read voltage supply operation in normal reading and cache reading will be described.

[0231] Fig. 22 2 is a schematic cross-sectional view for explaining the read voltage supply operation. The read voltage supply operation explained below is common to both normal reading and cache reading.

[0232] In the following description, the word line WL to be operated may be referred to as a selected word line WL. S The other word lines WL are called non-selected word lines WL U In the following description, the memory cells MC included in the string unit SU to be operated and connected to the selected word line WL are described. S The following description will be given of an example in which a connected memory cell MC (hereinafter sometimes referred to as a "selected memory cell MC") performs a read voltage supply operation. In addition, in the following description, a configuration including such a plurality of selected memory cells MC may be referred to as a selected page PG.

[0233] In the read voltage supply operation, for example, a voltage V is supplied to the bit line BL. DD For example, in Fig.11 The latch circuit SDL latches "H" and sets the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". As a result, the voltage V is supplied to the bit line BL and the read node SEN. DD In addition, the source line SL is supplied with a voltage V SRC Voltage V SRC Can be greater than the ground voltage V SS , or it can be equal to the ground voltage V SS Voltage V DD Greater than voltage V SRC .

[0234] In addition, in the read voltage supply operation, a voltage V is supplied to the drain side selection gate line SGD. SG Voltage V SG Greater than voltage V DD In addition, the voltage V SG With voltage V DD The voltage difference is greater than the threshold voltage of the drain side selection transistor STD. Therefore, a channel for electrons is formed in the channel region of the drain side selection transistor STD, and the transmission voltage V DD .

[0235] In addition, in the read voltage supply operation, the voltage V is supplied to the source side selection gate lines SGS and SGSb. SG Voltage V SG Greater than voltage V SRC In addition, the voltage V SG With voltage V SRC The voltage difference is greater than the threshold voltage of the source side selection transistors STS and STSb. Therefore, an electron channel is formed in the channel region of the source side selection transistors STS and STSb, and the transmission voltage V SRC .

[0236] In addition, in the read voltage supply operation, the non-selected word lines WL U Supply voltage V to the read channel READ . Read the channel voltage V READ Greater than voltage V DD 、V SRC In addition, the read channel voltage V READ With voltage V DD 、V SRC The voltage difference is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and the voltage V is transmitted to the selected memory cell MC. DD 、V SRC .

[0237] In addition, in the read voltage supply operation, the selected word line WL S Supply read voltage V CGR . Read the voltage V CGR Less than the read channel voltage V READ . Read voltage V CGR It is a reference Fig.18 The read voltage V CGAR ~V CGGR Any one of the following. Read voltage V CGR With voltage V SRCThe voltage difference is greater than the threshold voltage of the memory cell MC in which part of the data is recorded. Therefore, the memory cell MC in which part of the data is recorded becomes turned on. Therefore, current flows through the bit line BL connected to such memory cell MC. On the other hand, the read voltage V CGR With voltage V SRC The voltage difference is smaller than the threshold voltage of the memory cell MC in which part of the data is recorded. Therefore, the memory cell MC in which part of the data is recorded becomes an OFF state. Therefore, the current does not flow to the bit line BL connected to such a memory cell MC.

[0238] In addition, in the read voltage supply operation, the sense amplifier SA ( Fig.11 ) detects whether a current flows in the bit line BL, thereby detecting the on / off state of the memory cell MC. Hereinafter, such an operation is referred to as a "reading operation". In the reading operation, for example, a voltage V is supplied to the bit line BL. DD In the state of , the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, H, H, H, L, L". As a result, the sense amplifier SA ( Fig.11 ) is turned on the read node SEN and the bit line BL. In addition, after a certain period of time, the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, L". As a result, the sense amplifier SA ( Fig.11 ) is electrically disconnected from the bit line BL. After the read operation is performed, the state of the signal line STB is temporarily set to "H". As a result, the read transistor 41 is connected to the wiring LBUS ( Fig.11 ) is turned on, and the charge of the wiring LBUS is discharged or maintained. In addition, any latch circuit (for example, latch circuit SDL) in the sense amplifier unit SAU is turned on and the wiring LBUS, and the data of the wiring LBUS is latched by the latch circuit.

[0239] In the read voltage supply operation, as required, AND, OR, and other operations are performed on the data representing the state of the memory cell MC, thereby calculating the data recorded in the memory cell MC. Fig.11 ), the switching transistor DSW and the wiring DBUS are transmitted to the latch circuit XDL ( Fig.10 ).

[0240] [Reading operation of cache read]

[0241] Next, the read operation of the cache read according to the first embodiment will be described.

[0242] Fig.23It is a waveform diagram for explaining the read operation of the first cache read. Fig.24 It is a waveform diagram for explaining the read operation of the second cache read.

[0243] In addition, in the following description, Fig.18 The method described in (b) will now be described as an example in which data is allocated to each memory cell MC and data of a lower page (LP) and a middle page (MP) are read.

[0244] exist Fig.23 and Fig.24 In the above, “tR” refers to the period during which the read operation is performed. In addition, “R” refers to the period during which the word line WL is selected. S The voltage of is the first read voltage period. In addition, "RWL" refers to the selected word line WL S The voltage is set to the second (and third) read voltage period. In addition, "RR" refers to the period of performing the recovery action in the read action. Generally speaking, the period R is a period longer than the period RWL, and the period RR is a period shorter than the period R and the period RWL.

[0245] [Reading Operation of First Cache Read]

[0246] Reference Fig.23 , the read operation of the first cache read is described.

[0247] In addition, Fig.23 Among them, timing t101 to timing t105 and timing t111 to timing t114 are period R. Timing t105 to t107A, timing t114 to timing t116A, and timing t116A to timing t118 are period RWL. Timing t107A to timing t109A and timing t118 to timing t120 are period RR.

[0248] In addition, Fig.23 In the example, the plurality of actions executed at timing t103 to timing t107A and timing t112 to timing t118 are equivalent to the reference Fig. 22 The read voltage supply operation is described below.

[0249] When the cache read operation starts, the controller die CD outputs a command set CS(1) instructing the cache read operation to the memory die MD via the data signal input / output terminals DQ0 to DQ7. Fig. 20 As shown, instruction set CS(1) includes data 00h, ADD, and 31h. In order to distinguish between a plurality of instruction sets CS, instruction sets CS are denoted by numbers.

[0250] At timing t101, when command set CS(1) is input, the data 00h and 31h of command set CS(1) are used as command data D CMD The data D of instruction set CS(1) is stored in instruction register CMR. ADD As address data D ADD is stored in the address register ADR.

[0251] The sequencer SQC controls the terminal RBn (ready / busy signal RB) from the "H" state to the "L" state according to the input of the instruction set CS (1). In this way, access to the memory die MD is prohibited. In addition, a read operation is performed in the memory die MD. In addition, at the time when the read operation starts, the "True busy" state changes from the "H" state to the "L" state.

[0252] At timing t102, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state.

[0253] Furthermore, at timing t102, the unselected word lines WL included in the selected memory block BLK are switched to U The voltage from ground voltage V SS Read to read channel voltage V READ In addition, the drain side selection gate line SGD is supplied with a voltage V SG .

[0254] In addition, at timing t102, the controller die CD outputs the data output command to the memory die MD via the data signal input / output terminals DQ0 to DQ7. Fig.23 As shown, the data output instruction includes data 05h, ADD, E0h.

[0255] Data 05h is the instruction data D input to the instruction register CMR CMD The data 05h is input at the beginning of data output. ADD The data D of the cache read instruction ADD The same data. Data E0h is the instruction data D input to the instruction register CMR. CMD The data E0h is data indicating that the input of the data output command has been completed.

[0256] At timing t103, the selected word line WL included in the selected memory block BLK is S Supply read voltage V CGER Therefore, Fig.18 The memory cells MC corresponding to the Er state to the D state in (a) are in the on state, and the memory cells MC corresponding to the E state to the G state are in the off state.

[0257] In addition, although Fig.23 , but at timing t103, the voltage of the bit line BL included in the selected memory block BLK is increased from the ground voltage V SS Charge to voltage V DD In addition, at timing t103, a voltage V is supplied to the source line SL included in the selected memory block BLK. SRC .

[0258] At timing t104, a read operation is performed ( Fig.23 Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGER The corresponding read data (E) is stored in the latch circuit SDL.

[0259] At timing t105, the word line WL is selected. S Supply read voltage V CGAR Therefore, Fig.18 The memory cell MC corresponding to the Er state of (a) is in the on state, and the memory cell MC corresponding to the A state to the G state is in the off state.

[0260] At timing t106A, a read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGAR The corresponding read data (A). The sense amplifier SA performs a predetermined logic operation on the read data (E) and the read data (A). The latch circuit SDL stores the result of the logic operation (E&A). The result of the logic operation (E&A) is the read data [LP] of the lower bit (lower page).

[0261] At timing t107A to timing t109A, the recovery operation is performed. Timing t107A corresponds to reference Fig.19 Therefore, if the cache read instruction (00h-ADD-31h) is not input before the timing t107A, the read data (E&A) from the latch circuit SDL to the latch circuit XDL is not transferred at the timing t107A. In addition, in the recovery operation, the charge pump circuit 32 ( Figure 7 ), stop sending power to the selected word line WL S and non-selected word lines WL U The voltage is generated to select the word line WL S and non-selected word lines WL U For example, it converges to the ground voltage V SS .

[0262] exist Fig.23At timing t108A after timing t107A, a cache read instruction (00h-ADD-31h) is input as instruction set CS(2). Therefore, the read data (E&A) stored in latch circuit SDL is transferred to latch circuit ADL at timing t109A. Fig.23 In , the transfer of the read data (E&A) from the latch circuit SDL to the latch circuit ADL is expressed as "SDL2ADL". In addition, the read data (E&A) stored in the latch circuit ADL is transferred to the latch circuit XDL at timing t111. Fig.23 In FIG. 1 , the transfer of read data (E&A) from the latch circuit ADL to the latch circuit XDL is expressed as “ADA2XDL.” Note that the preparation of a power supply necessary for data transfer to the latch circuit XDL is performed at, for example, timing t109A.

[0263] In addition, the sequencer SQC controls the terminal RBn (ready / busy signal RB) from the "H" state to the "L" state according to the input of the instruction set CS (2) at the timing t108A. Accordingly, access to the memory die MD is prohibited. In addition, at the timing t108A, the non-selected word line WL included in the selected memory block BLK is turned on. U The voltages are respectively read from the channel voltage V READ Discharge to ground voltage V SS After the read operation is completed, the selected word line WL included in the selected memory block BLK is S Supply ground voltage V SS , a read operation is performed in the memory die MD.

[0264] At timing t111, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state. Also, at timing t111, the non-selected word line WL included in the selected memory block BLK is turned on. U The voltage from ground voltage V SS Read to read channel voltage V READ In addition, the drain side selection gate line SGD is supplied with a voltage V SG .

[0265] Furthermore, at timing t111, the memory chip MD inputs the data output command (05h-ADD-E0h) from the controller chip CD via the data signal input / output terminals DQ0 to DQ7.

[0266] At timing t112, the selected word line WL included in the selected memory block BLK is S Supply read voltage V CGFR Therefore, Fig.18The memory cells MC corresponding to the Er state to the E state in (a) are in the on state, and the memory cells MC corresponding to the F state to the G state are in the off state.

[0267] In addition, although Fig.23 , but at timing t112, the voltage of the bit line BL included in the selected memory block BLK is increased from the ground voltage V SS Charge to voltage V DD In addition, at timing t112, a voltage V is supplied to the source line SL included in the selected memory block BLK. SRC .

[0268] At timing t113, a read operation is performed. Thus, the sense amplifier SA obtains a voltage which is equal to the read voltage V CGFR The corresponding read data (F) is stored in the latch circuit SDL.

[0269] At timing t114, the word line WL is selected. S Supply read voltage V CGDR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the C state in (a) are in the on state, and the memory cells MC corresponding to the D state to the G state are in the off state.

[0270] At timing t115, a read operation is performed. Thus, the sense amplifier SA obtains a voltage which is equal to the read voltage V CGDR The sense amplifier SA performs a predetermined logic operation on the read data (F) and the read data (D). The latch circuit SDL stores the result of the logic operation (F&D).

[0271] At timing t116A, the word line WL is selected. S Supply read voltage V CGBR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the A state in (a) are in the on state, and the memory cells MC corresponding to the B state to the G state are in the off state.

[0272] At timing t117, a read operation is performed. Thus, the sense amplifier SA obtains a voltage which is equal to the read voltage V CGBR The corresponding read data (B). The read amplifier SA performs a predetermined logic operation on the read data (F), the read data (D), and the read data (B). The latch circuit SDL stores the result of the logic operation (F, D & B). The result of the logic operation (F, D & B) is the read data [MP] of the middle bit (middle page).

[0273] At timing t118 to timing t120, the recovery operation is performed. Timing t118 corresponds to reference Fig.19 Therefore, if the cache read instruction CS (3) is not input before the timing t118, the read data (F, D & B) is not transferred from the latch circuit SDL to the latch circuit XDL at the timing t120. In addition, in the recovery operation, the charge pump circuit 32 ( Figure 7 ), stop sending power to the selected word line WL S and non-selected word lines WL U The voltage output selects the word line WL S and non-selected word lines WL U For example, it converges to the ground voltage V SS .

[0274] exist Fig.23 In the example, at timing t119A after timing t118, a cache read instruction (00h-ADD-31h) is input. Therefore, the read data (F, D & B) stored in latch circuit SDL is transferred to latch circuit ADL at timing t120. In addition, the read data (F, D & B) stored in latch circuit ADL is transferred to latch circuit XDL at timing t121. Fig.23 As shown in FIG. 1 , the read data (F, D&B) stored in the latch circuit XDL is output to the controller bare chip CD based on the data output operation.

[0275] [Reading Operation of Second Cache Read]

[0276] Reference Fig.24 , the read operation of the second cache read is described.

[0277] exist Fig.24 The operations of timing t103 to timing t107A and timing t112 to timing t118 are equivalent to those of reference Fig. 22 The read voltage supply operation is described below.

[0278] Fig.24 Operation and reference of timing t101 to timing t105, timing t111 to timing t115, timing t116A to timing t118 Fig.23 The operations described are the same, so repeated descriptions are omitted.

[0279] exist Fig.24 In the example, at timing t106B before timing t107A, the cache read instruction CS(2) is input. Therefore, the read data (E&A) stored in the latch circuit SDL is transferred to the latch circuit XDL at timing t111. Fig.24In FIG. 1 , the transfer of read data (E&A) from the latch circuit SDL to the latch circuit XDL is expressed as “SDL2XDL.” Note that the preparation of power supply required for data transfer to the latch circuit XDL is performed at timing t101 , for example.

[0280] At timing t107A to timing t111, a recovery operation is performed. In the recovery operation, the charge pump circuit 32 ( Figure 7 ) is not reset, and the selected word line WL is maintained S and the non-selected word line WL U At timing t107A, for example, the voltage supply from the charge pump circuit 32 is stopped by a switch circuit between the charge pump circuit 32 and the wiring CG, and the selected word line WL is switched to the selected word line WL by an equalizer circuit (not shown) located downstream of the switch circuit. S and non-selected word lines WL U For example, it converges to the ground voltage V SS .

[0281] At timing t111, the equalization circuit is turned off, the switch circuit is turned on, and the charge pump circuit 32 ( Figure 7 ) to select word line WL S and non-selected word lines WL U The voltage supply. Fig.24 In the present embodiment, the charge pump circuit 32 is not reset during the recovery operation.

[0282] Fig.24 Operation and reference of timing t111 to timing t115 Fig.23 The operations described are the same, so repeated descriptions are omitted.

[0283] exist Fig.24 In the example, at timing t116B before timing t118, the cache read instruction CS(3) is input. Therefore, the read data (F, D, and B) stored in the latch circuit SDL is transferred to the latch circuit XDL at timing t120. Fig.24 In the example, the transfer of read data (F&D&B) from latch circuit SDL to latch circuit XDL is expressed as "SDL2XDL". Fig.24 As shown in FIG. 1 , the read data (F&D&B) stored in the latch circuit XDL is output to the controller bare chip CD based on the data output operation.

[0284] [Data transfer action]

[0285] Next, refer to Fig.25 The data transmission operation is described.

[0286] Fig.25 This is a flowchart for explaining the data transfer operation. Fig.25The actions of steps S101 to S106 correspond to Fig.23 The operations of timing t107A to timing t111 and timing t118 to timing t121, and Fig.24 The operations of timing t106B to timing t111 and timing t116B to timing t121. Fig.25 In the example, the actions of steps S102 to S106 are equivalent to data transmission actions.

[0287] For example, the read operation corresponding to the cache read command CS(1) is set as the read operation of page N, and the read operation corresponding to the cache read command CS(2) is set as the read operation of page N+1.

[0288] In step S101, if the memory die MD inputs a cache read instruction of page N+1 (refer to Fig.23 Timing t108A, Fig.24 If the timing of the cache read instruction of page N+1 is t106B), then in step S102, the memory die MD determines whether the read action of page N is being executed. If the read action of page N is being executed (yes in step S102), in step S103, the memory die MD determines whether the timing of the input of the cache read instruction of page N+1 is before the start of the recovery action of the read action of page N ( Fig.23 and Fig.24 before timing t107A).

[0289] When the read operation of page N is not being executed (No in step S102), or when the timing of inputting the cache read instruction of page N+1 is not before the start of the recovery operation of the read operation of page N (No in step S103), in step S104, the memory die MD transfers the read data stored in the latch circuit SDL to the latch circuit ADL (step S104). This operation corresponds to Fig.23 The action of timing t107A to timing t109A corresponds to Fig.23 In step S105, the read data stored in the latch circuit ADL is transferred to the latch circuit XDL. This operation corresponds to Fig.23 The action of timing t110A to timing t111.

[0290] When the timing of inputting the cache read instruction of page N+1 is before the start of the recovery operation in the read operation of page N (Yes in step S103), in step S106, the read data stored in the latch circuit SDL is transferred to the latch circuit XDL. This operation corresponds to Fig.24 The action of timing t107A to timing t111.

[0291] According to such a configuration, when the read operation of the cache read is continuously executed, the first cache read and the second cache read are automatically switched according to the timing when the next cache read command is input. Therefore, the data transfer operation is optimized according to the timing when the next cache read command is input. As a result, the interval between the read operations executed continuously can be shortened.

[0292] In addition, as the data transmission speed of the interface between the controller bare chip CD and the memory bare chip MD increases, the time of the data output action Dout is shortened. It is also possible that although the data transmission action Dout has been completed in advance, the data transmission action is still performed after the read action is completed. The structure of the first embodiment described above is effective in order to eliminate the above-mentioned problems. In addition, the structure according to the first embodiment can be implemented without using a special instruction set for optimizing the data transmission action.

[0293] For example, a comparison between the cache read in the comparative example and the cache read in the first embodiment will be described. Fig.26 It is a timing chart for explaining the read operation of the cache read in the comparative example and the second cache read in the first embodiment. Fig. 27 It is a timing chart for explaining the read operation of the cache read in the comparative example and the first cache read in the first embodiment.

[0294] In addition, if Fig.26 and Fig. 27 As shown, if a cache read instruction is input, the ready / busy signal RB is controlled from the "H" state to the "L" state, and if read data is transmitted to the latch circuit XDL, the ready / busy signal RB is controlled from the "L" state to the "H" state.

[0295] exist Fig.26 In the figure, the upper figure shows a case where the read operation of the cache read in the comparative example is continuously executed, and the lower figure shows a case where the read operation of the second cache read in the first embodiment is continuously executed.

[0296] like Fig.26 As shown in the above figure, in the cache read in the comparative example, even if the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is before the specific timing TA, the data transfer action from the latch circuit ADL to the latch circuit XDL is performed after the cache read action (Read(N+1)) is completed. In this case, after the data transfer action from the latch circuit ADL to the latch circuit XDL is performed, the next cache read action is started. On the other hand, as Fig.26As shown in the following figure, in the second cache read in the first embodiment, when the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is before the specific timing TA, the data transfer action from the latch circuit SDL to the latch circuit XDL is performed before the read action (Read(N+1)) of the cache read is completed. In this case, the read action of the next cache read is started immediately after the read action of the cache read is completed.

[0297] like Fig.26 As shown, the time from the time when the cache read instruction (00h-ADD(N+2)-31h) is input to the time when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the "L" state) is different from the cache read instruction ( Fig.26 Compared with the above figure), the second cache read in the first embodiment ( Fig.26 The following figure) is shorter.

[0298] exist Fig. 27 In the figure, the upper figure shows a case where the read operation of the cache read in the comparative example is continuously executed, and the lower figure shows a case where the read operation of the first cache read in the first embodiment is continuously executed.

[0299] like Fig. 27 As shown in the above figure, in the cache read in the comparative example, when the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is after the specific timing TA, after the read action (Read(N+1)) of the cache read is completed, the data transfer action from the latch circuit ADL to the latch circuit XDL is performed. In this case, after the data transfer action from the latch circuit ADL to the latch circuit XDL is performed, the next cache read read action is started. In addition, as Fig. 27 As shown in the following figure, the first cache read in the first embodiment is the same as the cache read in the comparative example. That is, when the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is after the specific timing TA, after the read action (Read(N+1)) of the cache read is completed, the data transfer action from the latch circuit ADL to the latch circuit XDL is performed.

[0300] Regarding the time from when the cache read instruction (00h-ADD(N+2)-31h) is input to when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the "L" state), the cache read ( Fig. 27 ) and the first cache read in the first embodiment ( Fig. 27The following figure) is the same time.

[0301] In addition, regarding the time from the time when the cache read instruction (00h-ADD(N+2)-31h) is input to the time when the data transfer operation to the latch circuit XDL is completed (the period during which the ready / busy signal RB is in the "L" state), the first cache read ( Fig. 27 ) is larger than the second cache read in the first embodiment ( Fig.26 That is, if the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is delayed, then in the first embodiment, the period during which the ready / busy signal RB is in the "L" state immediately after the cache read instruction (00h-ADD(N+2)-31h) is input becomes longer.

[0302] On the other hand, in the cache read in the comparative example, the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is early ( Fig.26 (above) is later than the timing of the input cache read instruction (00h-ADD(N+2)-31h) ( Fig. 27 That is, if the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is delayed, in the comparative example, the period during which the ready / busy signal RB is in the "L" state immediately after the cache read instruction (00h-ADD(N+2)-31h) is input becomes shorter.

[0303] [Second Embodiment]

[0304] Next, the read operation of the cache read according to the second embodiment will be described.

[0305] Fig.28 2 is a waveform diagram for explaining the read operation of the second cache read in the second embodiment. Fig.24 In the read operation of the second cache read described above, the read data stored in the latch circuit SDL is directly transferred to the latch circuit XDL during the recovery operation period RR (see Fig.24 In contrast, Fig.28 In the read operation of the second cache read shown in FIG. 1 , the read data stored in the latch circuit SDL is transferred to the latch circuit ADL (see FIG. 1 ) during the recovery operation period RR. Fig.28 At the beginning of period R in the subsequent read operation of the cache read, the read data stored in the latch circuit ADL is transferred to the latch circuit XDL (refer to Fig.28 Timing t209~timing t210 and timing t218~timing t219).

[0306] also, Fig.28 The structure other than the above in the read operation of the second cache read shown in FIG. Fig.24 The read operation of the second cache read is the same as described above. Fig.28 The timing t201 to timing t208 and the timing t210 to timing t217 are the same as Fig.24 The operations at timing t101 to timing t107A and timing t112 to timing t118 are the same. Therefore, the repeated description is omitted.

[0307] In addition, the first cache read in the second embodiment (the cache read when the cache read instruction is input after the specific timing TA) is shown in FIG. Fig.28 , similarly to the second cache read in the second embodiment (the cache read when the cache read instruction is input before the specific timing TA), during the recovery operation period RR, the read data stored in the latch circuit SDL is transferred to the latch circuit ADL, and at the beginning of the period R in the read operation of the next cache read, the read data stored in the latch circuit ADL is transferred to the latch circuit XDL. The details of the first cache read in the second embodiment will be described later (see Fig.30 ).

[0308] According to such a structure, even when the read operation of the cache read is executed continuously, the first cache read and the second cache read are automatically switched according to the timing when the next cache read command is input. Therefore, the data transfer operation is optimized according to the timing when the next cache read command is input. As a result, the interval between the read operations executed continuously can be shortened.

[0309] For example, a comparison is made between the cache read in the comparative example and the cache read in the second embodiment. Fig.29 It is a timing chart for explaining the read operation of the cache read in the comparative example and the second cache read in the second embodiment. Fig.30 It is a timing chart for explaining the read operation of the cache read in the comparative example and the first cache read in the second embodiment.

[0310] In addition, if Fig.29 and Fig.30As shown, if a cache read instruction is input, the ready / busy signal RB is controlled from the "H" state to the "L" state, and if read data is transmitted to the latch circuit XDL, the ready / busy signal RB is controlled from the "L" state to the "H" state.

[0311] exist Fig.29 In the figure, the upper figure shows a case where the read operation of the cache read in the comparative example is continuously executed, and the lower figure shows a case where the read operation of the second cache read in the second embodiment is continuously executed.

[0312] Fig.29 The comparison example shown in the figure above shows the cache read and Fig.26 The high-speed cache read is the same as the comparative example shown in the above figure. In this case, after the data transfer action from the latch circuit ADL to the latch circuit XDL is performed, the next high-speed cache read read action (Read (N+2)) is started. On the other hand, as Fig.29 As shown in the following figure, in the second cache read in the second embodiment, when the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is before the specific timing TA, the data transfer action from the latch circuit SDL to the latch circuit ADL is performed before the read action (Read(N+1)) of the cache read is completed, and the next cache read action (Read(N+2)) is immediately started after the read action (Read(N+1)) of the cache read is completed. During the execution of the read action (Read(N+2)) of the cache read, the data transfer action from the latch circuit ADL to the latch circuit XDL is performed.

[0313] like Fig.29 As shown, regarding the time from the time when the cache read instruction (00h-ADD(N+2)-31h) is input to the time when the data transfer operation to the latch circuit XDL is completed (the period when the ready / busy signal RB is in the "L" state), the cache read ( Fig.29 ) and the second cache read in the second embodiment ( Fig.29 The following figure) is the same time.

[0314] When the cache read operation (Read(N+2)) is started, the non-selected word lines WL U Charge the read channel voltage V READ , and data is transferred from latch circuit ADL to latch circuit XDL. Fig.29 As shown, the power supply voltage V CC The operating current I flowing in the pad electrode Px CC The operating current ICC The operating current I at the start of the read operation (Read(N+1)) of the cache read CC big.

[0315] exist Fig.30 In the figure, the upper figure shows a case where the read operation of the cache read in the comparative example is continuously executed, and the lower figure shows a case where the read operation of the first cache read in the second embodiment is continuously executed.

[0316] Fig.30 The comparison example shown in the figure above shows the cache read and Fig. 27 The high-speed cache read is the same as the comparative example shown in the above figure. In this case, after the data transfer action from the latch circuit ADL to the latch circuit XDL is performed, the next high-speed cache read read action (Read (N+2)) is started. On the other hand, as Fig.30 As shown in the following figure, in the first cache read in the second embodiment, when the timing of inputting the cache read instruction (00h-ADD(N+2)-31h) is after the specific timing TA, the data transfer action from the latch circuit SDL to the latch circuit ADL is performed before the read action (Read(N+1)) of the cache read is completed, and the next cache read action (Read(N+2)) is immediately started after the read action (Read(N+1)) of the cache read is completed. During the execution of the read action (Read(N+2)) of the cache read, the data transfer action from the latch circuit ADL to the latch circuit XDL is performed.

[0317] like Fig.30 As shown, regarding the time from the time when the cache read instruction (00h-ADD(N+2)-31h) is input to the time when the data transfer operation to the latch circuit XDL is completed (the period when the ready / busy signal RB is in the "L" state), the cache read ( Fig.30 ) and the first cache read in the second embodiment ( Fig.30 In the second embodiment, the first cache read ( Fig.30 The above period is longer than the second cache read ( Fig.29 The above period is shorter than that in the figure below.

[0318] When the cache read operation (Read(N+2)) is started, the non-selected word lines WL U Charge the read channel voltage V READ , and data is transferred from latch circuit ADL to latch circuit XDL. Fig.30 As shown, the power supply voltage VCC The operating current I flowing in the pad electrode Px CC The operating current I CC The operating current I at the start of the read operation (Read(N+1)) of the cache read CC big.

[0319] [Third Embodiment]

[0320] Next, the read operation of the continuous reading according to the third embodiment will be described.

[0321] Fig.31 This is a waveform diagram for explaining the readout operation of the continuous read in the third embodiment. Fig.32 1 is a diagram showing a part of waveforms in the continuous read operation in the third embodiment. Here, in the continuous read operation, when a specific condition is satisfied, the cache read operations of the previous and next pages are linked.

[0322] In addition, in the following description, Fig.31 Similarly, for the case described in Fig.18 The method described in (b) will be described as an example of allocating data to each memory cell MC and reading data of a lower page (LP), a middle page (MP), an upper page (UP), and a lower page (LP).

[0323] When the continuous read operation starts, the controller die CD outputs a command set instructing the normal read operation to the memory die MD via the data signal input / output terminals DQ0 to DQ7. Fig.31 As shown, the instruction set includes data 00h, ADD, 30h.

[0324] Data D ADD For example, it is data that determines the lower page (LP), memory block BLKx, word line WLm, and memory string MSa of the action target.

[0325] At timing t301, when a command set is input, the data 00h and 30h of the command set are used as the command data D CMD The data D of the instruction set is stored in the instruction register CMR. ADD As address data D ADD And saved in the address register ADR.

[0326] The sequencer SQC controls the terminal RBn (ready / busy signal RB) from the "H" state to the "L" state according to the input of the instruction set. Along with this, access to the memory die MD is prohibited. In addition, a read operation is performed in the memory die MD. In addition, at the moment when the read operation starts, the "True busy" state changes from the "H" state to the "L" state.

[0327] At timing t302, the unselected word lines WL included in the selected memory block BLKx are U The voltage from ground voltage V SS Charged to the read channel voltage V READ In addition, the drain side selection gate line SGD (MSa) is supplied with a voltage V SG .

[0328] Here, all the unselected word lines WL included in the selected memory block BLKx are U Charged to the read channel voltage V READ When the voltage generating unit vg2 ( Figure 6 ) to function, or to the voltage generating unit vg2 ( Figure 6 ) supply voltage to the charge pump circuit 32 to supply positive charge. Fig.31 As shown, the power supply voltage V CC The operating current I flowing in the pad electrode Px CC Increase.

[0329] At timing t303, the selected word line WL included in the selected memory block BLKx is S Supply read voltage V CGER Therefore, Fig.18 The memory cells MC corresponding to the Er state to the D state in (a) are in the on state, and the memory cells MC corresponding to the E state to the G state are in the off state.

[0330] In addition, Fig.31 Although not shown in the figure, at timing t303, the voltage of the bit line BL included in the selected memory block BLKx is increased from the ground voltage V SS Charge to voltage V DD In addition, at timing t303, the voltage V is supplied to the source line SL included in the selected memory block BLKx. SRC .

[0331] Next, perform the read operation ( Fig.31 Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGER The corresponding read data (E) is stored in the latch circuit SDL. When the read operation is performed, the amount of charge required to charge the read node SEN etc. increases. Fig.31 As shown, the power supply voltage V CC The operating current I flowing in the pad electrode Px CC Next, when the read operation is performed, the operating current I flowing through the pad electrode Px CC Increase.

[0332] At timing t304, the word line WL is selected. S Supply read voltage V CGAR Therefore, Fig.18 The memory cell MC corresponding to the Er state of (a) is in the on state, and the memory cell MC corresponding to the A state to the G state is in the off state.

[0333] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGAR The corresponding read data (A). The sense amplifier SA performs a predetermined logic operation on the read data (E) and the read data (A). The latch circuit SDL stores the result of the logic operation (E&A). The result of the logic operation (E&A) is the read data [LP] of the lower bit (lower page).

[0334] At timing t305 , the sequencer SQC controls the terminal RBn from the “L” state to the “H” state.

[0335] At timing t306, when the instruction set CS(1) instructing cache read is input, the data 00h and 31h of the instruction set CS(1) are used as the instruction data D CMD The data D of instruction set CS(1) is stored in instruction register CMR. ADD As address data D ADD is stored in the address register ADR.

[0336] Data D ADD For example, it is data that determines the mid-page (MP), memory block BLKx, word line WLm, and memory string MSa of the action target.

[0337] The sequencer SQC controls the terminal RBn (ready / busy signal RB) from the "H" state to the "L" state according to the input of the instruction set CS(1). Accordingly, access to the memory die MD is prohibited. In addition, a read operation is performed in the memory die MD.

[0338] At timing t307, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state.

[0339] In addition, at timing t307, the unselected word lines WL included in the selected memory block BLKx are switched to U The voltage from ground voltage V SS Charged to the read channel voltage V READ In addition, the drain side selection gate line SGD (MSa) is supplied with a voltage V SG Therefore, if Fig.31 As shown, the power supply voltage V CCThe operating current I flowing in the pad electrode Px CC Increase.

[0340] In addition, at timing t307, the controller die CD outputs the data output command to the memory die MD via the data signal input / output terminals DQ0 to DQ7. Fig.31 As shown, the data output instruction includes data 05h, ADD, E0h.

[0341] Data 05h is the instruction data D input to the instruction register CMR CMD The data 05h is input at the beginning of data output. ADD The data D is the same as the instruction set (00h-ADD-30h) indicating a normal read. ADD The same data. Data E0h is the instruction data D input to the instruction register CMR. CMD The data E0h indicates that the input of the data output command has been completed. The data output command is input through the memory die MD, and the data transfer operation Dout (LP) is started. Fig.32 Dout(N-1) in.

[0342] In addition, at timing t307, the selected word line WL included in the selected memory block BLKx is S Supply read voltage V CGFR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the E state in (a) are in the on state, and the memory cells MC corresponding to the F state to the G state are in the off state.

[0343] like Fig.32 As shown, at timing t307, the voltage of the bit line BL included in the selected memory block BLKx is increased from the ground voltage V SS Charge to voltage V DD In addition, at timing t307, the voltage V is supplied to the source line SL included in the selected memory block BLKx. SRC .

[0344] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGFR The corresponding read data (F) is stored in the latch circuit SDL.

[0345] At timing t308, the word line WL is selected. S Supply read voltage V CGDR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the C state in (a) are in the on state, and the memory cells MC corresponding to the D state to the G state are in the off state.

[0346] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGDR The sense amplifier SA performs a predetermined logic operation on the read data (F) and the read data (D). The latch circuit SDL stores the result of the logic operation (F&D).

[0347] At timing t309, the word line WL is selected. S Supply read voltage V CGBR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the A state in (a) are in the on state, and the memory cells MC corresponding to the B state to the G state are in the off state.

[0348] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGBR The corresponding read data (B). The read amplifier SA performs a predetermined logic operation on the read data (F), the read data (D), and the read data (B). The latch circuit SDL stores the result of the logic operation (F&D&B). The result of the logic operation (F&D&B) is the read data [MP] of the middle bit (middle page).

[0349] In addition, if Fig.31 and Fig.32 As shown, if the data output action ( Fig.31 Dout(LP), Fig.32 Dout(N-1)) is completed, and it becomes able to accept the next cache read instruction ( Fig.31 and Fig.32 When the cache read instruction CS(2) is input, the sequencer SQC controls the terminal RBn from the "H" state to the "L" state.

[0350] The data D contained in the cache read instruction CS(2) ADD For example, it is data that specifies an upper page (UP), a memory block BLKx, a word line WLm, and a memory string MSa of an action target.

[0351] In this case, on the median page ( Fig.32 Page N) and the upper page ( Fig.32 In page N+1), the memory block BLKx, word line WLm and memory string MSa are common. In this case, Fig.31 and Fig.32 As shown, the median page ( Fig.32 The read operation of the page N) is the same as that of the upper page ( Fig.32 The read action of page N+1) is linked.

[0352] Specifically, if Fig.32 As shown, the median page ( Fig.32 The period RR of the recovery action of the page N) is deleted, and the last period RWL of the middle page is connected to the period R at the beginning of the upper page. In addition, by connecting the period R at the beginning of the upper page with the period RWL of the middle page, the period R becomes the period RWL. In this way, by connecting the middle page and the upper page, the time of the read action is shortened. In addition, by connecting the middle page and the upper page, the word line WL supplied to the non-selected word line WL U The read channel voltage V READ , the voltage V supplied to the drain side selection gate line SGD (MSa) SG , the voltage V supplied to the source line SL SRC , and the voltage V supplied to the bit line BL DD Will not drop to ground voltage V SS Therefore, it is not necessary to discharge and charge these wirings, and the supply voltage V CC The operating current I flowing through the pad electrode Px CC .

[0353] Furthermore, at the timing when the cache read instruction CS(2) is input, at the specific timing TA( Fig.31 as well as Fig.32 In the case of timing t310 in the above example, the middle page ( Fig.32 The read operation of the page N) is the same as that of the upper page ( Fig.32 In this case, at timing t310, a recovery operation (period RR) is performed, and a data transfer operation from latch circuit SDL to latch circuit ADL is performed during the recovery operation (period RR). In addition, in the upper page ( Fig.32 After the read operation of the page N+1 of the cache is completed, the data transfer operation from the latch circuit ADL to the latch circuit XDL is performed. The timing of inputting the cache read instructions CS(3) and CS(4) is at a specific timing TA( Fig.31 and Fig.32 The same applies to the situation after timing t312, t314).

[0354] At timing t310, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state. Fig.31 and Fig.32Although not shown, at timing t310, the read data (F&D&B) stored in the latch circuit SDL is transferred to the latch circuit ADL. Furthermore, the read data (F&D&B) stored in the latch circuit ADL is transferred to the latch circuit XDL. In addition, at timing t310, the read data (F&D&B) stored in the latch circuit SDL may be directly transferred to the latch circuit XDL.

[0355] In addition, at timing t310, the selected word line WL included in the selected memory block BLKx is S Supply read voltage V CGGR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the F state in (a) are in the on state, and the memory cells MC corresponding to the G state are in the off state.

[0356] In addition, in response to the input of a data output command by the memory chip MD, a data transfer operation Dout(MP) is started ( Fig.32 Dout(N) in.

[0357] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGGR The corresponding read data (G) is stored in the latch circuit SDL.

[0358] At timing t311, the word line WL is selected. S Supply read voltage V CGCR Therefore, Fig.18 The memory cells MC corresponding to the Er state to the B state in (a) are in the on state, and the memory cells MC corresponding to the C state to the G state are in the off state.

[0359] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGCR The corresponding read data (C). The read amplifier SA performs a predetermined logic operation on the read data (G) and the read data (C). The latch circuit SDL stores the result of the logic operation (G&C). The result of the logic operation (G&C) is the read data [UP] of the upper bit (upper page).

[0360] In addition, if Fig.31 and Fig.32 As shown, if the data output action ( Fig.31 Dout(MP), Fig.32 Dout(N)) ends, it becomes ready to accept the next cache read instruction ( Fig.31 and Fig.32When the cache read instruction CS(3) is input, the sequencer SQC controls the terminal RBn from the "H" state to the "L" state.

[0361] The data D contained in the cache read instruction CS(3) ADD For example, it is data that determines the lower page (LP), memory block BLKx, word line WLm, and memory string MSb of the action target.

[0362] In this case, on the upper page ( Fig.32 Page N+1) and the lower page ( Fig.32 On the other hand, the memory string MSb of the lower page is different from the memory string MSa of the upper page. In this case, Fig.31 and Fig.32 As shown, the median page ( Fig.32 The read operation of page N+1) is the same as that of the upper page ( Fig.32 The read action of page N+2) is linked.

[0363] Specifically, if Fig.32 As shown, the upper page ( Fig.32 The period RR of the recovery action of the page N+1) is deleted, and the last period RWL of the upper page is connected to the period R at the beginning of the lower page. In addition, the period R at the beginning of the lower page is connected to the period RWL of the upper page, so that the period R becomes the period RWL. In this way, by connecting the upper page and the lower page, the time of the read action is shortened. In addition, there is no need to perform the non-selection of the word line WL U , the discharge and charge of the source line SL and the bit line BL are suppressed when the power supply voltage V CC The operating current I flowing in the pad electrode Px CC .

[0364] As described above, the memory string MSa of the upper page is different from the memory string MSb of the lower page, so the memory string MS is switched. At timing t312, the voltage V SG is discharged to the ground voltage V SS After that, the drain side selection gate line SGD(MSb) corresponding to the address of the memory string MSb is increased from the ground voltage V SS Charge to voltage V SG .

[0365] In addition, at timing t312, the sequencer SQC controls the terminal RBn from the "L" state to the "H" state. Fig.31 and Fig.32Although not shown, at timing t312, the read data (G&C) stored in the latch circuit SDL is transferred to the latch circuit ADL. Furthermore, the read data (G&C) stored in the latch circuit ADL is transferred to the latch circuit XDL. In addition, at timing t312, the read data (G&C) stored in the latch circuit SDL may be directly transferred to the latch circuit XDL.

[0366] In addition, at timing t312, the selected word line WL included in the selected memory block BLKx is S Supply read voltage V CGER Therefore, Fig.18 The memory cells MC corresponding to the Er state to the D state in (a) are in the on state, and the memory cells MC corresponding to the E state are in the off state.

[0367] In response to the memory die MD inputting a data output command, the data transmission operation Dout(UP) is started ( Fig.32 Dout(N+1) in.

[0368] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGER The corresponding read data (E) is stored in the latch circuit SDL.

[0369] At timing t313, the word line WL is selected. S Supply read voltage V CGAR Therefore, Fig.18 The memory cell MC corresponding to the Er state of (a) is in the on state, and the memory cell MC corresponding to the A state to the G state is in the off state.

[0370] Next, the read operation is performed. Thus, the sense amplifier SA obtains the same voltage as the read voltage V CGAR The corresponding read data (A). The sense amplifier SA performs a predetermined logic operation on the read data (E) and the read data (A). The latch circuit SDL stores the result of the logic operation (E&A). The result of the logic operation (E&A) is the read data [LP] of the lower bit (lower page).

[0371] In addition, if Fig.31 and Fig.32 As shown, if the data output action ( Fig.31 Dout(UP), Fig.32 Dout(N+1)) is completed, and it becomes able to accept the next cache read instruction ( Fig.31 and Fig.32When the cache read instruction CS (4) is input, the sequencer SQC controls the terminal RBn from the "H" state to the "L" state.

[0372] The data D contained in the cache read instruction CS(4) ADD For example, it is data that determines the mid-page (MP), memory block BLKy, word line WLm, and memory string MSb of the action object.

[0373] When the data D contained in the above cache read instruction CS(3) ADD and the data D contained in the next cache read instruction CS(4) ADD If the address of the memory block BLKx or the word line WLm is different, the read operation of the page N+2 and the read operation of the next page are not linked. In this case, at timing t314, the non-selected word line WL U The read channel voltage V READ , the voltage V of the drain side selection gate line SGD (MSb) SG , the voltage V of the source line SL SRC , and the voltage V of the bit line BL DD are discharged separately.

[0374] Even when the addresses of the memory block BLKx and the word line WLm are the same, the read operation of the normal read and the read operation of the cache read are not linked.

[0375] Fig.33 This is a flowchart for explaining the read operation of the continuous reading in the third embodiment.

[0376] In step S201, the memory die MD inputs a cache read instruction of page N (see Fig.31 In step S202, the memory die MD inputs the cache read instruction of page N+1 (see Fig.31 In step S203A, the memory die MD determines whether the read operation of page N is being executed. If the read operation of page N is being executed (yes in step S203A), in step S203B, the memory die MD determines whether the timing of inputting the cache read instruction of page N+1 is before the start of the recovery operation of the read operation of page N ( Fig.31 and Fig.32 before timing t310).

[0377] When the timing of inputting the cache read instruction of page N+1 is before the start of the recovery action in the read action of page N (yes in step S203B), in step S204, the memory die MD determines whether the addresses of the storage blocks BLK of page N and page N+1 are the same.

[0378] When the addresses of the memory blocks BLK of page N and page N+1 are the same (Yes in step S204), in step S205, the memory die MD determines whether the addresses of the word lines WL of page N and page N+1 are the same. When the addresses of the word lines WL of page N and page N+1 are the same (Yes in step S205), in step S206, the memory die MD determines whether the addresses of the memory strings MS of page N and page N+1 are the same.

[0379] When the addresses of the memory strings MS of page N and page N+1 are the same (Yes in step S206), in step S207, the memory die MD does not select the word line WL S Other wiring (non-selected word line WL U On the other hand, if the addresses of the memory strings MS of page N and page N+1 are different (No in step S206), in step S208, the memory die MD does not select the word line WL. S and wiring other than the drain side selection gate line SGD (non-selection word line WL U , source side selection gate line SGS, source line SL, bit line BL) voltage discharge, maintain the voltage of these wirings. In addition, the word line WL is selected S , the recovery action (period RR) is not performed and the read voltage supply action is continued.

[0380] When the read operation of page N is not being executed (No in step S203A), when the timing of inputting the cache read instruction of page N+1 is not before the start of the recovery operation in the read operation of page N (No in step S203B), when the addresses of the memory blocks BLK of page N and page N+1 are different (No in step S204), or when the addresses of the word lines WL of page N and page N+1 are different (No in step S205), in step S209, the memory die MD includes the selected word line WL. S and all wiring of the drain side selection gate line SGD (selection word line WL S , non-selected word line WL U, drain side selection gate line SGD, source side selection gate line SGS, source line SL, bit line BL) are discharged, and then the voltage of all wirings is charged.

[0381] According to such a structure, when the read operation of the cache read is continuously executed, if a specific condition (steps S203 to S206) is satisfied, the read operation of the previous and next pages is linked. Therefore, the period of executing the read operation of the cache read can be shortened. In addition, it is unnecessary to discharge and charge the predetermined wiring, and the supply voltage V CC The operating current I flowing through the pad electrode Px CC .

[0382] [Fourth Embodiment]

[0383] Fig.34 It is a waveform diagram for explaining the read operation of the continuous reading in the fourth embodiment.

[0384] In the continuous reading operation of the third embodiment, as Fig.32 As shown, the word line WL is selected S Supply read voltage V CGFR 、V CGDR 、V CGBR 、V CGGR 、V CGCR 、V CGER 、V CGAR In contrast, in the continuous reading operation of the fourth embodiment, as shown in FIG. Fig.34 As shown, the word line WL is selected S Supply read voltage V CGFR 、V CGDR 、V CGBR 、V CGCR 、V CGGR 、V CGER 、V CGAR . Other structures and references Fig.32 The contents of the description are the same, so repeated descriptions are omitted.

[0385] According to such a structure, since the selected word line WL in the continuous reading S The amount of transition of the read voltage level is reduced, so the period of the read operation of the cache read can be shortened. In addition, the discharge and charge of the predetermined wiring are not required, and the supply voltage V is suppressed. CC The operating current I flowing through the pad electrode Px CC In addition, the level of the read voltage can be switched smoothly.

[0386] In addition, Fig.34In the reverse read operation, the read voltage is changed from high to low (V CGFR , V CGDR , V CGBR ), performs a forward read by changing the read voltage from low to high (V CGCR , V CGGR ), then perform a reverse read (V CGER , V CGAR However, it is also possible to perform a forward read (V CGBR , V CGDR , V CGFR ), perform reverse read (V CGGR , V CGCR ), then, perform a forward read (V CGAR , V CGER ).

[0387] Fig.35 2 is a waveform diagram for explaining a modified example of the readout operation of the continuous reading in the fourth embodiment. Fig.35 , a forward read (V CGBR , V CGDR , V CGFR ), perform reverse read (V CGGR , V CGCR ), and then perform a forward read (V CGAR , V CGER That is, in a modified example of the continuous reading operation of the fourth embodiment, as Fig.35 As shown, the word line WL is selected S Supply read voltage V CGBR 、V CGDR 、V CGFR 、V CGGR 、V CGCR 、V CGAR 、V CGER . Other structures and references Fig.32 and Fig.34 The contents of the description are the same, so repeated descriptions are omitted.

[0388] Even with this structure, the selected word line WL in the continuous reading S The transition amount of the read voltage level is also reduced, so the period of the read operation of the cache read can be shortened. In addition, the discharge and charge of the specified wiring are not required, and the supply voltage V is suppressed. CC The operating current I flowing through the pad electrode Px CC In addition, the level of the read voltage can be switched smoothly.

[0389] In addition, in the case of QLC (Quad Level Cell: recording 16-value data (4 bits) in a storage cell), for example, reverse reading may be performed, forward reading may be performed, reverse reading may be performed, and then forward reading may be performed. Alternatively, in the case of QLC, for example, forward reading may be performed, reverse reading may be performed, forward reading may be performed, and then reverse reading may be performed.

[0390] In addition, in the case of PLC (abbreviation of Penta Level Cell: data of 32 values ​​(5 bits) is recorded in a storage unit), for example, reverse reading may be performed, forward reading may be performed, reverse reading may be performed, forward reading may be performed, and then reverse reading may be performed. Alternatively, in the case of PLC, for example, forward reading may be performed, reverse reading may be performed, forward reading may be performed, reverse reading may be performed, and then forward reading may be performed.

[0391] The case where reverse reading and forward reading are performed alternately has been described. However, if the word line WL is selected S If the amount of transition of the level of the read voltage is reduced, the reverse read and the forward read may not be performed alternately.

[0392] [Fifth Embodiment]

[0393] Next, refer to Fig.36 Next, the sequential read operation in the fifth embodiment is described. A method of collectively performing read operations on the lower page, the middle page, and the upper page is called sequential read.

[0394] Fig.36 1 is a waveform diagram for explaining the readout operation of the sequential readout in the fifth embodiment. The sequential readout reads out data from a plurality of pages at once. Fig.36 As shown, for example, according to V CGAR 、V CGBR 、V CGCR 、V CGDR 、V CGER 、V CGFR 、V CGGR The sequence of switching supply to the selected word line WL in stages S The latch circuit XDL of the cache memory CM stores the read data of the lower page, the middle page, and the upper page in sequence. Then, data output is performed every time the read data is stored.

[0395] exist Fig.36 In the example of FIG. 1 , it is assumed that the memory block BLKx and the word line WLm are common in the first sequential read and the second sequential read. On the other hand, the memory string MSa of the first sequential read is different from the memory string MSb of the second sequential read. In this case, Fig.36As shown, the read operation of the first sequential read and the read operation of the second sequential read can be connected. In this case, the non-selected word line WL U The read channel voltage V READ On the other hand, the voltage V of the drain side selection gate line SGD is SG Discharge and charge are performed.

[0396] According to such a structure, the period of the sequential read operation can be shortened, and the discharge and charge of the predetermined wiring are not required, thereby suppressing the supply voltage V CC The operating current I flowing through the pad electrode Px CC .

[0397] In the sequential read of the fifth embodiment, a command set dedicated to sequential read (eg, 50h-00h-ADD-31h) is used to instruct execution of sequential read. In the command set dedicated to sequential read, a prefix such as "50h" is added to the command.

[0398] Although not shown in the figure, by receiving a data output command ( Fig.19 The data output action Dout(N+1) of the read data stored in the latch circuit XDL is performed. In sequential reading, the data output action is performed in the order of the lower page (LP), the middle page (MP), and the upper page (UP).

[0399] Next, refer to Fig.37 Modifications of the first to second embodiments will be described.

[0400] Fig.37 Yes means Fig.24 Waveform diagram of a modified example. Fig.37 The structure is basically the same as Fig.24 Therefore, repeated descriptions of the same structures are omitted.

[0401] From timing t102 to timing t103, the selected word line WL included in the selected memory block BLK is S The voltage from ground voltage V SS Charged to the read channel voltage V READ In addition, from timing t102 to timing t103, the unselected word lines WL included in the selected memory block BLK are switched on. U The voltage from ground voltage V SS Charged to the read channel voltage V READ .

[0402] During the period from timing t107A to timing t111, the selected word line WLS Supply voltage V to the read channel READ After that, the ground voltage V SS The period from timing t107A to timing t111 is a period RR for performing a recovery operation. This period is also called a channel clean period (Channel Clean). In addition, during the period from timing t107A to timing t111, the non-selected word lines WL included in the selected memory block BLK are U The voltage from the read channel voltage V READ Discharge to ground voltage V SS . Select word line WL S and non-selected word lines WL U The timing of the discharge can also be simultaneous.

[0403] At timing t112A to timing t112, the selected word line WL included in the selected memory block BLK is S The voltage from ground voltage V SS Charge to the read channel voltage V READ In addition, from timing t112A to timing t112, the non-selected word lines WL included in the selected memory block BLK are turned on. U The voltage from ground voltage V SS Charged to the read channel voltage V READ .

[0404] During the period from timing t118 to timing t120, the word line WL is selected. S Supply voltage V to the read channel READ After that, the ground voltage V SS The period from timing t118 to timing t120 is a channel cleaning period (Channel Clean). In addition, during the period from timing t118 to timing t120, the non-selected word line WL U The voltage from the read channel voltage V READ Discharge to ground voltage V SS .

[0405] The word line WL can also be selected S and non-selected word lines WL U supply Fig.37 The voltage has the waveform shown. Fig.23 and Fig.28 The selected word line WL S and non-selected word lines WL U The same is true.

[0406] Next, refer to Fig.38 Modifications of the third to fourth embodiments will be described.

[0407] Fig.38 Yes means Fig.31 Waveform diagram of a modified example. Fig.38 The structure is basically the same as Fig.31 Therefore, repeated descriptions of the same structures are omitted.

[0408] From timing t302 to timing t303, the selected word line WL included in the selected memory block BLK is S The voltage from ground voltage V SS Charged to the read channel voltage V READ In addition, from timing t302 to timing t303, the unselected word lines WL included in the selected memory block BLK are turned on. U The voltage from ground voltage V SS Charged to the read channel voltage V READ .

[0409] During the period from timing t305A to timing t305, the word line WL is selected. S Supply voltage V to the read channel READ After that, the ground voltage V SS The period from timing t305A to timing t305 is a period RR for performing a recovery operation. This period is also called a channel clean period (Channel Clean). In addition, during the period from timing t305A to timing t305, the non-selected word line WL included in the selected memory block BLK is U The voltage from the read channel voltage V READ Discharge to ground voltage V SS . Select word line WL S and non-selected word lines WL U The timing of the discharge can also be simultaneous.

[0410] During the period from timing t306 to timing t307, the period from timing t310A to timing t310, and the period from timing t312A to timing t312, the selected word line WL included in the selected memory block BLK is switched on. S The voltage from ground voltage V SS Charged to the read channel voltage V READ In addition, during the period from timing t306 to timing t307, the unselected word lines WL included in the selected memory block BLK are turned on. U The voltage from ground voltage V SS Charged to the read channel voltage V READ .

[0411] During the period from timing t314A to timing t314, the word line WL is selected. S Supply voltage V to the read channelREAD After that, the ground voltage V SS The period from timing t314A to timing t314 is a channel cleaning period (Channel Clean). In addition, during the period from timing t314A to timing t314, the non-selected word line WL U The voltage from the read channel voltage V READ Discharge to ground voltage V SS .

[0412] The word line WL can also be selected S and non-selected word lines WL U supply Fig.38 The voltage has the waveform shown. Fig.31 , Fig.32 and Fig.34 The selected word line WL S and non-selected word lines WL U The same is true.

[0413] [Other embodiments]

[0414] The semiconductor memory devices according to the first to fifth embodiments have been described above. However, the semiconductor memory devices described above are merely examples, and the operation, structure, etc. can be adjusted as appropriate.

[0415] For example, in the semiconductor memory devices of the first to fifth embodiments, as shown in FIG. Fig.18 As described above, each memory cell MC records 3 bits of data, but the data recorded in the memory cell MC may be 1 bit, 2 bits, 4 bits, or 5 bits or more.

[0416] In the third to fifth embodiments, whether to execute linked read is determined based on whether the timing of inputting the cache read command CS is before the specific timing TA. However, a configuration may be adopted in which the user can select whether to execute linked read.

[0417] In this case, it is also possible to configure the SET FEATURE action to be able to set whether to execute the linked read. For example, in a certain mode (enable mode), whether to execute the linked read is determined based on the timing of the input cache read command CS. In another mode (disable mode), the linked read is not executed regardless of the timing of the input cache read command CS.

[0418] In addition, it is also possible to configure so that a prefix instruction can be used to specify whether to perform a linked read. A prefix instruction is an instruction attached to the beginning of a normal instruction set. For example, in the instruction set (xxh-00h-ADD-31h), the prefix instruction is "xxh". In a certain mode (enable base mode), when a prefix instruction is attached, a linked read is not implemented, and when a prefix instruction is not attached, a linked read can be implemented. In another mode (disable base mode), when a prefix instruction is attached, a linked read can be implemented, and when a prefix instruction is not attached, a linked read is not implemented. The selection of the mode is set, for example, using the SETFEATURE action.

[0419] In addition, in the first embodiment, the following structure is disclosed. According to the first instruction set, a first read action is performed, and according to the second instruction set, a second read action is performed continuously after the first read action. When the second instruction set is input at a first timing, a first data transfer action is performed, and when the second instruction set is input at a second timing before the first timing, a second data transfer action is performed. The first data transfer action transfers the data stored in the first latch circuit (e.g., latch circuit SDL) to the second latch circuit (e.g., latch circuit ADL) according to the first read action, and transfers the data stored in the second latch circuit (e.g., latch circuit ADL) to the third latch circuit (e.g., latch circuit XDL). The second data transfer action transfers the data stored in the first latch circuit (e.g., latch circuit SDL) to the third latch circuit (e.g., latch circuit XDL) according to the first read action.

[0420] Here, the first instruction set corresponds to, for example, Fig.23 and Fig.24 The second instruction set corresponds to, for example, the instruction set CS(1) input at timing t101. Fig.23 The timing t108A or Fig.24 The first read operation corresponds to, for example, the instruction set CS(2) input at timing t106B. Fig.23 Timing t102 to timing t109A or Fig.24 The second read operation corresponds to, for example, Fig.23 and Fig.24 The first timing corresponds to, for example, the read operation performed at the timing t111 to the timing t120. Fig.23 The second timing corresponds to, for example, Fig.24 The timing t106B. Fig.23 and Fig.24 As shown, the second timing is the timing before the first timing. The first data transmission action corresponds to Fig.23 The second data transmission action corresponds to the data transmission action performed at the timing t107A to the timing t111. Fig.24 The data transmission operation is performed at the timing t107A to the timing t111. Fig.23 and Fig.24 As shown, the action period of the second data transmission action is shorter than that of the first data transmission action.

[0421] [other]

[0422] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0423] [Explanation of Reference Numerals]

[0424] 110 ...conductive layer, 120 ...semiconductor layer, 130 ...gate insulating film, WL ...word line, WL S ...select word line (conductive layer, select conductive layer), WL U …non-select word line (non-select conductive layer), SGD…drain side selection gate line (second conductive layer), MC…storage cell, MS…storage string, SU…string unit, BLK…storage block, MCA…storage cell array.

Claims

1. A semiconductor storage device comprising: A memory string having a plurality of memory transistors connected in series; A bit line connected to the memory string; A sense amplifier unit connected to the bit line and having a first latch circuit and a second latch circuit; as well as a third latch circuit electrically connected to the sense amplifier unit, According to the first instruction set, a first read operation is performed, According to a second instruction set, a second readout action is continuously performed after the first readout action. When the second instruction set is input at the first timing, a first data transmission operation is executed. When the second instruction set is input at a second timing before the first timing, a second data transmission action is executed, The first data transfer operation transfers the data stored in the first latch circuit to the second latch circuit and transfers the data stored in the second latch circuit to the third latch circuit according to the first read operation. The second data transfer operation transfers the data stored in the first latch circuit to the third latch circuit according to the first read operation.

2. The semiconductor memory device according to claim 1, wherein: According to a third instruction set, a third reading action is performed before the first reading action, According to a fourth instruction set, executing a data output action related to the third reading action, The data output operation outputs data from the third latch circuit to the outside. After the data output action, the second instruction set is accepted.

3. The semiconductor memory device according to claim 2, wherein: The second data transfer operation is executed while the first read operation is being executed, and the second read operation is started immediately after the first read operation is completed.

4. The semiconductor memory device according to claim 1, wherein: is configured to output a ready / busy signal indicating whether the instruction set can be accepted, The second instruction set is input when the ready / busy signal is capable of accepting the instruction set and is in a ready state.

5. The semiconductor memory device according to claim 4, wherein: When the data is transferred to the third latch circuit, the ready / busy signal becomes the ready state.

6. The semiconductor memory device according to claim 1, wherein: A plurality of conductive layers connected to the gate electrodes of the plurality of storage transistors are provided, In the first readout operation and the second readout operation, a readout voltage is supplied to a selected conductive layer which is one of the plurality of conductive layers, and a readout channel voltage greater than the readout voltage is supplied to a non-selected conductive layer different from the selected conductive layer. The first timing is a timing after the third timing at which the readout channel voltage starts to drop, The second timing is a timing before the third timing.

7. The semiconductor memory device according to claim 1, wherein: A plurality of conductive layers connected to the gate electrodes of the plurality of storage transistors are provided, In the first readout operation and the second readout operation, after supplying a readout voltage to a selected conductive layer that is one of the plurality of conductive layers, a readout channel voltage greater than the readout voltage is supplied. The first timing is a timing after a fourth timing at which the voltage of the selection conductive layer starts to rise toward the readout channel voltage. The second timing is a timing before the fourth timing.

8. A semiconductor storage device comprising: A memory string having a plurality of memory transistors connected in series; A bit line connected to the memory string; A sense amplifier unit connected to the bit line and having a first latch circuit and a second latch circuit; as well as a third latch circuit electrically connected to the sense amplifier unit, According to the first instruction set, a first read operation is performed, According to a second instruction set, a second readout action is continuously performed after the first readout action. transferring the data stored in the first latch circuit to the second latch circuit according to the first read operation, and transferring the data stored in the second latch circuit to the third latch circuit during the execution of the second read operation, The second reading operation starts immediately after the first reading operation is completed.

9. A semiconductor storage device comprising: A memory string having a plurality of memory transistors connected in series; a plurality of conductive layers connected to the gate electrodes of the plurality of storage transistors; and Multiple storage blocks, According to the first instruction set, a first read operation is performed, According to a second instruction set, a second readout action is continuously performed after the first readout action. The first readout operation and the second readout operation each include a readout voltage supply operation of supplying a readout voltage to a selected conductive layer that is one of the plurality of conductive layers. When the addresses of the storage block and the selection conductive layer as the action targets of the first read action are the same as the addresses of the storage block and the selection conductive layer as the action targets of the second read action, the read voltage supply action of the first read action is connected with the read voltage supply action of the second read action.

10. The semiconductor memory device according to claim 9, wherein: The read channel voltage supplied to the non-selected conductive layer different from the selected conductive layer among the plurality of conductive layers is maintained during the execution of the first read operation and the second read operation.

11. The semiconductor memory device according to claim 9, wherein: The memory string has a select gate transistor connected in series with the plurality of memory transistors, The semiconductor memory device includes a second conductive layer connected to the gate electrode of the select gate transistor. When the address of the second conductive layer as the target of the first read operation is the same as the address of the second conductive layer as the target of the second read operation, the voltage supplied to the second conductive layer is maintained while the first read operation and the second read operation are performed.

12. The semiconductor memory device according to claim 9, wherein: A source line connected to the other end of the memory string is provided, The voltage supplied to the source line is maintained while the first readout operation and the second readout operation are performed.

13. The semiconductor memory device according to claim 9, wherein: A bit line connected to one end of the memory string is provided, The voltage supplied to the bit line is maintained while the first read operation and the second read operation are performed.

14. The semiconductor memory device according to claim 9, wherein: In the first read operation, the read voltage changes from a high level to a low level. In the second read operation, the read voltage changes from a low level to a high level.

15. The semiconductor memory device according to claim 9, wherein: In the first read operation, the read voltage changes from a low level to a high level. In the second read operation, the read voltage changes from a high level to a low level.

16. The semiconductor memory device according to claim 10, wherein: The second command set is input at a timing during a period in which the read voltage is supplied to the selection conductive layer.

17. The semiconductor memory device according to claim 9, wherein: In the first readout operation and the second readout operation, after the readout voltage is supplied to the selection conductive layer, a readout channel voltage is supplied. The second command set is input at a time before the read channel voltage is reached.

18. The semiconductor memory device according to claim 9, wherein: The first instruction set and the second instruction set are related to page reading.

19. The semiconductor memory device according to claim 9, wherein: The first instruction set and the second instruction set are related to sequential reading.

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