Random access memory and testing apparatus

Abstract

The application discloses a random memory and a testing device. The random memory comprises a clock transmission link and a second duty cycle detection circuit. The clock transmission link comprises a duty cycle adjustment circuit and a first duty cycle detection circuit. The duty cycle adjustment circuit is used for duty cycle adjustment on an input first clock signal to obtain a second clock signal. The first duty cycle detection circuit is used for first duty cycle detection on the second clock signal and feedback of a detection result to the duty cycle adjustment circuit. The second duty cycle detection circuit is coupled to an output end of the clock transmission link, used for second duty cycle detection on the second clock signal and output of a detection flag signal. The detection precision of the second duty cycle detection circuit is higher than that of the first duty cycle detection circuit. In this way, the detection problem of the frequency performance of the random memory is solved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a random access memory and a testing device. Background Art

[0002] With the miniaturization of electronic systems, multi-die stacking technology has been widely used in production to reduce chip packaging volume. Multi-die stacking technology encapsulates different types of unpackaged chips that meet product performance requirements into the same package, achieving space compression.

[0003] Since the development of random access memory, it is usually necessary to perform corresponding performance tests on random access memory, such as the high-frequency performance of random access memory. After the chip particles are packaged into chips, high-speed machines can be used to complete the high-frequency testing of the chips and the screening after the test; however, if they are shipped in the form of chip particles rather than chips, high-frequency testing is required during the wafer-level testing stage (also known as chip probe testing, CP testing) of chip particle manufacturing to screen out chip particles that meet the high-frequency performance. The chip particles screened out in the CP testing stage are called KGD (Know Good Die). However, CP testing is limited by the requirements of the test equipment. The operating frequency of a single probe is generally only at the 100MHz level, which cannot meet the conditions for high-frequency testing. Therefore, how to detect the frequency performance of random access memory at high frequencies is a problem that needs to be solved. In addition, the duty cycle adjustment and calibration in random access memory is usually completed by external devices, but at high frequencies, external devices cannot meet this requirement. Summary of the Invention

[0004] The present application provides a random access memory and a testing device to solve the problem of detecting the frequency performance of the random access memory and the problem of duty cycle self-calibration.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a random access memory, which includes: a clock transmission link, the clock transmission link includes a duty cycle adjustment circuit and a first duty cycle detection circuit; wherein the duty cycle adjustment circuit is used to adjust the duty cycle of the input first clock signal to obtain a second clock signal; the first duty cycle detection circuit is used to perform a first duty cycle detection on the second clock signal, and feed back the detection result to the duty cycle adjustment circuit; the second duty cycle detection circuit is coupled to the output end of the clock transmission link, performs a second duty cycle detection on the second clock signal, and outputs a detection flag signal, wherein the detection accuracy of the second duty cycle detection circuit is higher than the detection accuracy of the first duty cycle detection circuit, and the detection flag signal indicates whether the duty cycle of the second clock signal is detected when the first clock signal is used as the input clock of the duty cycle adjustment circuit, and obtains the first duty cycle adjustment code of the first duty cycle detection circuit when the detection is passed.

[0006] Before performing a second duty cycle detection on the second clock signal, the second duty cycle detection circuit first adjusts and detects the duty cycle of the first clock signal, and saves the second duty cycle adjustment code of the second duty cycle detection circuit when the detection passes to complete the self-calibration of the second duty cycle detection circuit.

[0007] The first duty cycle adjustment code of the first duty cycle detection circuit is burned into the electronic fuse of the random access memory to complete the frequency performance detection of the random access memory, or serves as the initial value of the duty cycle adjustment when the duty cycle adjustment circuit is working normally to complete the duty cycle self-calibration of the duty cycle adjustment circuit.

[0008] Among them, the random access memory further includes: a clock generating unit; a first selection circuit, a first input end of the first selection circuit is coupled to the external clock input end, a second input end of the first selection circuit is coupled to the clock generating unit, and an output end of the first selection circuit is coupled to the input end of the clock transmission link; a logic control circuit, coupled to the control end of the first selection circuit, responding to a first control instruction, controlling the output end of the first selection circuit to output the external clock signal as the first clock signal; or responding to a second control instruction, controlling the output end of the first selection circuit to output the first internal clock signal generated by the clock generating unit as the first clock signal.

[0009] In which, the random access memory further includes: a second selection circuit, a first input end of the second selection circuit is coupled to the output end of the clock transmission link, a second input end of the second selection circuit is coupled to the clock generation unit, and an output end of the second selection circuit is coupled to a second duty cycle detection circuit; a logic control circuit is coupled to the control end of the second selection circuit, and in response to a third control instruction, controls the output end of the second selection circuit to output the second clock signal; or in response to a fourth control instruction, controls the output end of the second selection circuit to output the first internal clock signal, so that the second duty cycle detection circuit self-calibrates.

[0010] Among them, the second duty cycle detection circuit includes: a first adjustment unit, a second adjustment unit and a detection unit; wherein, the first adjustment unit is used to perform a second duty cycle adjustment on the first internal clock signal to obtain a second internal clock signal; the second adjustment unit is used to perform a third duty cycle adjustment on the second internal clock signal to obtain a third internal clock signal; wherein, the adjustment step of the second duty cycle adjustment is greater than the adjustment step of the third duty cycle adjustment; the detection unit is used to start the third duty cycle adjustment when it is detected that the third internal clock signal meets the first preset requirement, and when it is detected that the third internal clock signal meets the second preset requirement, save the current adjustment codes of the first adjustment unit and the second adjustment unit as the second duty cycle adjustment code.

[0011] The starting duty cycle adjustment code of the second adjustment unit is determined according to the duty cycle adjustment code of the first adjustment unit when the third internal clock signal meets the first preset requirement.

[0012] Among them, in response to the third control instruction, the logic control circuit loads the second duty cycle adjustment code into the second duty cycle detection circuit; in response to the fifth control instruction, the logic control circuit controls the second duty cycle detection circuit to perform a second duty cycle detection on the second clock signal and records the detection flag signal; in response to the sixth control instruction, the logic control circuit controls the step adjustment of the first duty cycle adjustment code; in response to the seventh control instruction, the logic control circuit controls the second duty cycle detection circuit to perform a second duty cycle detection on the second clock signal again and records the detection flag signal. If the detection flag signal is flipped, the first duty cycle adjustment code at this time is obtained and burned into the electronic fuse of the random access memory to complete the frequency performance test of the random access memory, or used as the initial value of the duty cycle adjustment circuit to complete the duty cycle self-calibration of the duty cycle adjustment circuit.

[0013] The adjustment step size of the step-by-step adjustment of the first duty cycle adjustment code is greater than the adjustment step size of the second duty cycle detection circuit.

[0014] When the random access memory is subjected to frequency performance testing, the first to seventh control instructions are sent by a test device coupled to the random access memory; or when the duty cycle adjustment circuit is subjected to duty cycle self-calibration, the first to seventh control instructions are sent by a logic control circuit.

[0015] Among them, the clock transmission link further includes: a delay circuit, coupled to the duty cycle adjustment circuit, for delaying the second clock signal and outputting it; a phase detection circuit, coupled to the duty cycle adjustment circuit and the delay circuit, for comparing the first clock signal with the delayed second clock signal; a controller, the controller is respectively coupled to the duty cycle adjustment circuit, the delay circuit, the phase detection circuit and the first duty cycle detection circuit, for adjusting the first duty cycle adjustment code of the first duty cycle detection circuit and the delay of the delay circuit according to the detection result of the first duty cycle detection circuit and the detection result of the phase detection circuit.

[0016] The clock transmission link further includes a clock buffer circuit coupled to the delay circuit and outputting the delayed second clock signal to the first duty cycle detection circuit.

[0017] The clock transmission link further includes an output buffer coupled to the clock buffer circuit, buffering the delayed second clock signal input from the clock buffer circuit, and outputting the buffered delayed second clock signal to the second duty cycle detection circuit.

[0018] To solve the above technical problems, another technical solution adopted in this application is: to provide a testing device, including a random access memory and a testing device coupled to the random access memory as provided in the above technical solution; wherein, the testing device sends a detection instruction to the random access memory so that the random access memory outputs a corresponding detection flag signal.

[0019] The beneficial effects of the embodiments of the present application are: different from the prior art, the present application provides a random access memory, which includes: a clock transmission link, the clock transmission link includes a duty cycle adjustment circuit and a first duty cycle detection circuit; wherein the duty cycle adjustment circuit is used to adjust the duty cycle of the input first clock signal to obtain a second clock signal; the first duty cycle detection circuit is used to perform a first duty cycle detection on the second clock signal, and feed back the detection result to the duty cycle adjustment circuit; the second duty cycle detection circuit is coupled to the output end of the clock transmission link, performs a second duty cycle detection on the second clock signal, and outputs a detection flag signal, wherein the detection accuracy of the second duty cycle detection circuit is higher than the detection accuracy of the first duty cycle detection circuit, and the detection flag signal indicates whether the duty cycle of the second clock signal is detected when the first clock signal is used as the input clock of the duty cycle adjustment circuit, and obtains the first duty cycle adjustment code of the first duty cycle detection circuit when the detection is passed. Through the above-described method, the two duty cycle detection circuits within the RAM are utilized to complete duty cycle calibration detection of the RAM's clock transmission link, thereby resolving the RAM's frequency performance detection problem and / or the RAM's duty cycle self-calibration problem. Furthermore, the high-frequency clock signal provided by the clock unit can be used to detect the RAM's high-frequency performance, resolving the problem of the test device's probe hardware being unable to provide a high-frequency clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] in:

[0022] Figure 1 1 is a schematic structural diagram of a first embodiment of a random access memory provided by the present application;

[0023] Figure 2 1 is a schematic structural diagram of a second embodiment of a random access memory provided by the present application;

[0024] Figure 3 1 is a schematic structural diagram of a third embodiment of a random access memory provided by the present application;

[0025] Figure 4 This is a flowchart of an application scenario of a random access memory provided by this application;

[0026] Figure 5 is a structural diagram of an embodiment of a second duty cycle detection circuit provided by the present application;

[0027] Figure 6 This is a schematic diagram of the process of duty cycle calibration of a random access memory provided by the present application;

[0028] Figure 7 This is a schematic structural diagram of an embodiment of a clock transmission link provided by the present application;

[0029] Figure 8 This is a structural diagram of another embodiment of the clock transmission link provided by the present application;

[0030] Figure 9 This is a schematic structural diagram of an embodiment of a testing device provided by the present application;

[0031] Figure 10 This is a schematic diagram of a scenario in which the test device provided in this application detects random access memory. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] The inventors of this application have found through long-term research that, as random access memory has developed to date, it is usually necessary to perform corresponding tests on the random access memory before the random access memory chip is shipped (such as wafer-level CP test or chip-level FT test). If the high-frequency performance of the random access memory is tested under a high-frequency clock, a test device is required to input a high-frequency clock from the outside of the random access memory, which may not be possible with the current test device. Therefore, how to detect the frequency performance of the random access memory is a problem that needs to be solved. Based on this, the present application proposes any of the following technical solutions to solve any of the above problems. It is worth noting that the following embodiments of the present invention can be applied to realize the frequency performance detection of the random access memory, and can also be applied to the normal operation of the random access memory to realize the duty cycle self-calibration in the random access memory.

[0035] See Figure 1 , Figure 1 FIG1 is a schematic diagram of the structure of a first embodiment of a random access memory provided by the present application. The random access memory 100 includes: a clock transmission link 10 and a second duty cycle detection circuit 20.

[0036] The clock transmission link 10 includes a duty cycle adjustment circuit 11 and a first duty cycle detection circuit 12. The duty cycle adjustment circuit 11 is used to adjust the duty cycle of the input first clock signal CLK1 to generate a second clock signal CLK2. It will be understood that a clock signal is periodically composed of logic high and logic low levels. Therefore, the proportion of time a logic high or logic low level is present within a time period is the duty cycle. For example, the duty cycle corresponding to a logic high level is 70%, 60%, 40%, or 35%. Therefore, to meet different performance requirements, the duty cycle of the clock signal can be adjusted. For example, the duty cycle can be adjusted from 70% to 50%, from 70% to 60%, from 60% to 50%, or from 40% to 50%. In other words, the duty cycle can be adjusted to the target duty cycle based on actual conditions, so that the corresponding function can be achieved using a clock signal with the target duty cycle. In a further embodiment, if the second clock signal CLK2 is used as the operating clock of the internal circuit of the random access memory, the target duty cycle is generally 50%.

[0037] The first duty cycle detection circuit 12 is configured to perform a first duty cycle detection on the second clock signal CLK2 and feed back the detection result to the duty cycle adjustment circuit 11 .

[0038] In a further embodiment, the first duty cycle detection circuit 12 can perform a first duty cycle detection on the second clock signal CLK2. If the detection passes, the clock transmission link 10 outputs the second clock signal CLK2. If the detection fails, the duty cycle adjustment circuit 11 continues to adjust the corresponding duty cycle adjustment code and uses the adjusted duty cycle adjustment code to adjust the duty cycle of the first clock signal CLK1 to generate the second clock signal CLK2. Furthermore, the condition for passing the detection can be that the first duty cycle detection circuit 12 detects that the duty cycle of CLK2 reaches a target duty cycle (e.g., 50%), or the number of times the target duty cycle crosses back and forth reaches a certain threshold.

[0039] The second duty cycle detection circuit 20 is coupled to the output end of the clock transmission link 10, performs a second duty cycle detection on the second clock signal CLK2, and outputs a detection flag signal F. The detection accuracy of the second duty cycle detection circuit 20 is greater than the detection accuracy of the first duty cycle detection circuit 12. The detection flag signal F indicates whether the duty cycle of the second clock signal CLK2 passes detection (for example, whether it reaches the target duty cycle) when the first clock signal CLK1 serves as the input clock of the duty cycle adjustment circuit 11. If the detection passes, the first duty cycle adjustment code (DCD trim code) of the first duty cycle detection circuit 12 is obtained. Furthermore, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is obtained, and in an embodiment of frequency performance testing of the random access memory 100, the first duty cycle adjustment code is burned into the electronic fuse of the random access memory 100 (for example, as a duty cycle adjustment code corresponding to the frequency value of the first clock signal CLK1); in an embodiment of duty cycle self-calibration of the duty cycle adjustment circuit 11, the first duty cycle adjustment code is used as the initial value of the duty cycle adjustment when the first duty cycle detection circuit 12 is operating normally. It is worth noting that the embodiment of frequency performance testing of the random access memory 100 requires a test device external to the random access memory 100 to send instructions for control, so as to screen out the random access memory 100 that passes the frequency performance test during the test phase and record the first duty cycle adjustment code when the test passes. The frequency test can correspond to different frequency values ​​of the first clock signal CLK1, for example, a high frequency of up to 1600 MHz. The embodiment of realizing self-calibration of the duty cycle of the duty cycle adjustment circuit 11 requires the built-in logic control circuit of the random access memory 100 to send instructions for control, the purpose of which is to perform self-calibration of the duty cycle of the duty cycle adjustment circuit 11 each time the random access memory 100 is powered on when the normal operation is performed, and the obtained first duty cycle adjustment code is used as the initial value of the duty cycle adjustment during its normal operation. This embodiment can obtain the corresponding initial value of the duty cycle adjustment code according to the first clock signal CLK1 of different frequencies in real time, thereby realizing real-time self-calibration of the duty cycle of the duty cycle adjustment circuit 11.

[0040] Among them, the detection accuracy of the second duty cycle detection circuit 20 is higher than the detection accuracy of the first duty cycle detection circuit 12. Furthermore, the duty cycle adjustment step of the second duty cycle detection circuit 20 is smaller than the duty cycle adjustment step of the duty cycle adjustment circuit 11. The second duty cycle detection circuit 20 with higher detection accuracy can be used to perform duty cycle detection and adjustment on the clock transmission link 10 again, thereby improving the detection accuracy and / or the accuracy of the duty cycle adjustment.

[0041] In some embodiments, the second duty cycle detection circuit 20 performs a second duty cycle detection on the second clock signal CLK2 and outputs a detection flag signal F. The detection flag signal F can be represented by 0 or 1. When the detection flag signal F is 0, indicating that the duty cycle detection of the second clock signal CLK2 has failed, the clock transmission link 10 can adjust the corresponding duty cycle adjustment code again based on the detection flag signal F, and use the adjusted duty cycle adjustment code to continue adjusting the first clock signal CLK1.

[0042] When the detection flag signal F is 1, it indicates that the duty cycle detection of the second clock signal CLK2 has passed.

[0043] In one application scenario, a random access memory 100 is coupled to a test device. The test device inputs a first clock signal CLK1 into the random access memory 100. The duty cycle adjustment circuit 11 within the clock transmission link 10 adjusts the duty cycle of the input first clock signal CLK1 to obtain a second clock signal CLK2. The first duty cycle detection circuit 12 within the clock transmission link 10 performs a first duty cycle detection on the second clock signal CLK2 and feeds the detection result back to the duty cycle adjustment circuit 11. The second duty cycle detection circuit 20 is coupled to the output end of the clock transmission link 10, performs a second duty cycle detection on the second clock signal CLK2, and outputs a detection flag signal F. The detection flag signal F can be output to the test device so that the test device determines, based on the detection flag signal F, whether the duty cycle of the second clock signal CLK2 passes detection when the first clock signal CLK1 serves as the input clock of the duty cycle adjustment circuit 11. If the detection passes, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is obtained.

[0044] In one application scenario, a random access memory 100 is coupled to a test device. The test device inputs a first clock signal CLK1 to the random access memory 100. The duty cycle adjustment circuit 11 within the clock transmission link 10 adjusts the duty cycle of the input first clock signal CLK1 to obtain a second clock signal CLK2. The first duty cycle detection circuit 12 within the clock transmission link 10 performs a first duty cycle detection on the second clock signal CLK2 and feeds the detection result back to the duty cycle adjustment circuit 11. The second duty cycle detection circuit 20 is coupled to the output end of the clock transmission link 10, performs a second duty cycle detection on the second clock signal CLK2, and outputs a detection flag signal F. The detection flag signal F is output to the random access memory 100 so that the random access memory 100 determines whether the duty cycle of the second clock signal CLK2 passes detection based on the detection flag signal F when the first clock signal CLK1 serves as the input clock of the duty cycle adjustment circuit 11. If the detection passes, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is obtained.

[0045] Therefore, after the preset time, the test device sends a corresponding instruction to the random access memory 100 to obtain the detection flag signal F. The random access memory 100 can adjust the duty cycle within the preset time to obtain the final detection flag signal F.

[0046] In one application scenario, after the random access memory 100 is powered on, a first clock signal CLK1 is generated within the random access memory 100. The duty cycle adjustment circuit 11 within the clock transmission link 10 adjusts the duty cycle of the first clock signal CLK1 input to the random access memory 100 to generate a second clock signal CLK2. The first duty cycle detection circuit 12 within the clock transmission link 10 performs a first duty cycle detection on the second clock signal CLK2 and feeds the detection result back to the duty cycle adjustment circuit 11. The second duty cycle detection circuit 20 is coupled to the output end of the clock transmission link 10, performs a second duty cycle detection on the second clock signal CLK2, and outputs a detection flag signal F. The detection flag signal F is output to the random access memory 100 so that the random access memory 100 determines whether the duty cycle of the second clock signal CLK2 passes detection based on the detection flag signal F when the first clock signal CLK1 serves as the input clock of the duty cycle adjustment circuit 11. If the detection passes, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is obtained. Specifically, a corresponding state machine may be provided inside the random access memory 100 , and corresponding instruction control may be performed inside the random access memory 100 through the state machine.

[0047] In this way, after a preset time, the test device is coupled to the random access memory 100 and sends a corresponding instruction to the random access memory 100 to obtain a detection flag signal F. The random access memory 100 can adjust the duty cycle within the preset time to obtain a final detection flag signal F. When the detection device performs performance testing of a large number of random access memories 100, it can send a corresponding control instruction to each random access memory 100 so that the random access memory 100 completes the duty cycle adjustment internally within the preset time. The detection device can uniformly send a corresponding acquisition instruction to the random access memory 100 after a preset time to obtain the detection flag signal F fed back by the random access memory 100, thereby determining the frequency performance of each random access memory 100.

[0048] In a further embodiment, before performing a second duty cycle detection on the second clock signal CLK2, the second duty cycle detection circuit 20 first adjusts and detects the duty cycle of the first clock signal CLK1, and saves the second duty cycle adjustment code of the second duty cycle detection circuit 20 when the detection passes to complete the self-calibration of the second duty cycle detection circuit 20.

[0049] It will be appreciated that before utilizing the second duty cycle detection circuit 20 to detect the duty cycles of the remaining clock signals, the detection accuracy of the second duty cycle detection circuit 20 itself must be ensured. Therefore, the second duty cycle detection circuit 20 first adjusts and detects the duty cycle of the first clock signal CLK1. If the detection passes, the second duty cycle adjustment code of the second duty cycle detection circuit 20 is stored to complete self-calibration of the second duty cycle detection circuit 20. The specific self-calibration method of the second duty cycle detection circuit 20 will be described in detail in the following embodiments and will not be elaborated upon here.

[0050] In a further embodiment, after obtaining the first duty cycle adjustment code of the first duty cycle detection circuit 12 when the detection passes, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is burned into the electronic fuse of the random access memory 100 to complete the frequency performance detection of the random access memory 100.

[0051] In a further embodiment, after obtaining the first duty cycle adjustment code of the first duty cycle detection circuit 12 when the detection passes, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is used as the initial value for duty cycle adjustment when the duty cycle adjustment circuit 11 is operating normally, thereby completing the duty cycle self-calibration of the duty cycle adjustment circuit 11. The specific self-calibration method of the second duty cycle detection circuit 20 will be described in the following embodiment and will not be described in detail here.

[0052] In this embodiment, two duty cycle detection circuits in the random access memory 100 are used to complete the duty cycle calibration detection of the clock transmission link 10 in the random access memory 100, thereby solving the problem of detecting the frequency performance of the random access memory 100 and / or the problem of self-calibration of the duty cycle of the random access memory 100.

[0053] See Figure 2 , Figure 2 FIG2 is a schematic diagram of the structure of a second embodiment of a random access memory provided by the present application. The random access memory 100 includes: a clock transmission link 10, a second duty cycle detection circuit 20, a clock generation unit 40, a first selection circuit 30 and a logic control circuit 50.

[0054] Among them, the first input end of the first selection circuit 30 is coupled to the external clock input end, and can receive the clock signal PAD_CLK; the second input end of the first selection circuit 30 is coupled to the clock generation unit 40, and can receive the clock signal CLK0; the output end of the first selection circuit 30 is coupled to the input end of the clock transmission link 10.

[0055] The logic control circuit 50 is coupled to the control terminal of the first selection circuit 30 .

[0056] In one application scenario, the logic control circuit 50 controls the output end of the first selection circuit 30 to output the external clock signal as the first clock signal CLK1 in response to the first control instruction.

[0057] In one application scenario, the logic control circuit 50 controls the output end of the first selection circuit 30 to output the first internal clock signal generated by the clock generation unit 40 as the first clock signal CLK1 in response to the second control instruction.

[0058] The clock generating unit 40 can generate a high-frequency clock signal, such as a high-frequency clock signal of 3200 MHz, 3300 MHz, 3400 MHz or 3500 MHz.

[0059] In this embodiment, considering the hardware limitations of the test device, the operating frequency of a single probe of the test device is generally at the 100 MHz level, which cannot meet the high-frequency clock frequency requirements. Therefore, a clock generation unit 40 is set in the random access memory 100 to generate a high-frequency clock signal to complete the detection of the high-frequency performance of the random access memory 100.

[0060] Based on this, when performing low-frequency performance detection, the logic control circuit 50 responds to the first control instruction and controls the output end of the first selection circuit 30 to output the external clock signal as the first clock signal CLK1.

[0061] When performing high-frequency performance testing, the logic control circuit 50 responds to the second control instruction and controls the output end of the first selection circuit 30 to output the first internal clock signal generated by the clock generation unit 40 as the first clock signal CLK1 .

[0062] Based on this, the duty cycle adjustment circuit 11 in the clock transmission link 10 adjusts the duty cycle of the input first clock signal CLK1 to generate a second clock signal CLK2. The first duty cycle detection circuit 12 in the clock transmission link 10 performs a first duty cycle detection on the second clock signal CLK2 and feeds the detection result back to the duty cycle adjustment circuit 11. The second duty cycle detection circuit 20 is coupled to the output end of the clock transmission link 10 and performs a second duty cycle detection on the second clock signal CLK2, outputting a detection flag signal F. The detection accuracy of the second duty cycle detection circuit 20 is higher than that of the first duty cycle detection circuit 12. The detection flag signal indicates whether the duty cycle of the second clock signal CLK2 has passed detection when the first clock signal CLK1 serves as the input clock of the duty cycle adjustment circuit 11. If the detection passes, the first duty cycle adjustment code of the first duty cycle detection circuit 12 is obtained.

[0063] In this embodiment, two duty cycle detection circuits within the random access memory 100 are used to perform duty cycle calibration and detection of the clock transmission link 10 within the random access memory 100, thereby solving the problem of detecting the frequency performance of the random access memory 100 and / or the problem of self-calibration of the duty cycle of the random access memory 100. Furthermore, the clock unit is used to provide a high-frequency clock signal, thereby detecting the high-frequency performance of the random access memory 100, thereby solving the problem of the probe hardware limitations of the test device that cannot provide a high-frequency clock signal.

[0064] See Figure 3 , Figure 3 FIG3 is a schematic diagram of the structure of the third embodiment of the random access memory provided by the present application. The random access memory 100 includes: a clock transmission link 10, a second duty cycle detection circuit 20, a clock generation unit 40, a first selection circuit 30, a logic control circuit 50, and a second selection circuit 60.

[0065] Among them, the first input end of the second selection circuit 60 is coupled to the output end of the clock transmission link 10, the second input end of the second selection circuit 60 is coupled to the clock generation unit 40, and the output end of the second selection circuit 60 is coupled to the second duty cycle detection circuit 20; the logic control circuit 50 is coupled to the control end of the second selection circuit 60.

[0066] Since the second selection circuit 60 is provided, the second selection circuit 60 can be used to select different input terminals to input corresponding clock signals and output them to the second duty cycle detection circuit 20 to achieve corresponding functions.

[0067] In one application scenario, the logic control circuit 50 responds to the third control instruction and controls the output end of the second selection circuit 60 to output the second clock signal CLK2 to the second duty cycle detection circuit 20. The second duty cycle detection circuit 20 can then perform a second duty cycle detection on the second clock signal CLK2 and output a detection flag signal F. The detection flag signal indicates whether the duty cycle of the second clock signal CLK2 passes the detection when the first clock signal CLK1 is used as the input clock of the duty cycle adjustment circuit 11, and obtains the first duty cycle adjustment code of the first duty cycle detection circuit 12 when the detection passes. At the same time, the detection flag signal F can be used to determine whether the clock transmission link 10 adjusts the duty cycle of the second clock signal CLK2 to the target duty cycle.

[0068] In one application scenario, the logic control circuit 50 controls the output terminal of the second selection circuit 60 to output the first internal clock signal in response to the fourth control instruction, so as to self-calibrate the second duty cycle detection circuit 20. It is understood that before the second duty cycle detection circuit 20 performs detection, it is necessary to self-calibrate the second duty cycle detection circuit 20 to ensure the accuracy of subsequent detection.

[0069] In one application scenario, combined with Figure 4 To explain:

[0070] Step 102 : In response to the third control instruction, the logic control circuit loads a second duty cycle adjustment code into the second duty cycle detection circuit.

[0071] When the logic control circuit 50 receives the third control instruction, it indicates that the second duty cycle detection circuit 20 needs to perform a second duty cycle detection on the second clock signal CLK2. Therefore, the logic control circuit 50 loads the second duty cycle adjustment code into the second duty cycle detection circuit 20, so that the second duty cycle detection circuit 20 subsequently performs a second duty cycle detection on the second clock signal CLK2 using the second duty cycle adjustment code.

[0072] Step 103: In response to the fifth control instruction, the logic control circuit controls the second duty cycle detection circuit to perform a second duty cycle detection on the second clock signal and record a detection flag signal.

[0073] After the logic control circuit 50 loads the second duty cycle adjustment code into the second duty cycle detection circuit 20 , in response to the fifth control instruction, the logic control circuit 50 controls the second duty cycle detection circuit 20 to perform a second duty cycle detection on the second clock signal CLK2 and record the detection flag signal F.

[0074] Step 104 : In response to the sixth control instruction, the logic control circuit controls the step adjustment of the first duty cycle adjustment code.

[0075] In some embodiments, when the duty cycle adjustment circuit 11 adjusts the duty cycle of the input first clock signal CLK1, it is not always adjusted directly to the correct position. Therefore, the logic control circuit 50 controls the step-by-step adjustment of the first duty cycle adjustment code accordingly, so that the duty cycle adjustment circuit 11 uses the adjusted first duty cycle adjustment code to adjust the duty cycle of the input first clock signal CLK1.

[0076] For example, the duty cycle adjustment circuit 11 uses the first duty cycle adjustment code to adjust the duty cycle of the input first clock signal CLK1 to generate the second clock signal CLK2. The logic control circuit 50 controls the second duty cycle detection circuit 20 to perform a second duty cycle detection on the second clock signal CLK2 and record the detection flag signal F. If the detection flag signal F does not flip, the first duty cycle adjustment code needs to be adjusted. Therefore, step 104 is executed at this time.

[0077] Step 105: In response to the seventh control instruction, the logic control circuit controls the second duty cycle detection circuit to perform a second duty cycle detection on the second clock signal again, and records a detection flag signal.

[0078] After executing step 104, the first duty cycle adjustment code is adjusted, and the duty cycle adjustment circuit 11 uses the stepped-adjusted first duty cycle adjustment code to adjust the duty cycle of the input first clock signal CLK1 to obtain the second clock signal CLK2. At this time, step 105 is executed again, so that the logic control circuit 50 controls the second duty cycle detection circuit 20 to perform a second duty cycle detection on the second clock signal CLK2 again and record the detection flag signal F.

[0079] Step 106: If the detection flag signal is flipped, the first duty cycle adjustment code at this time is obtained and burned into the electronic fuse of the random access memory to complete the frequency performance detection of the random access memory, or used as the initial value of the first duty cycle detection circuit to complete the duty cycle self-calibration of the duty cycle adjustment circuit.

[0080] If the detection flag signal flips, it indicates that the duty cycle of the second clock signal CLK2 adjusted by the duty cycle adjustment circuit 11 using the first duty cycle adjustment code at that time satisfies the frequency performance test or that the duty cycle self-calibration of the duty cycle adjustment circuit 11 is completed. Therefore, the first duty cycle adjustment code at that time can be obtained and burned into the electronic fuse of the random access memory 100, or the first duty cycle adjustment code at that time can be used as the initial value of the first duty cycle detection circuit 12.

[0081] If the detection flag signal does not flip, step 104 is executed.

[0082] The adjustment step of the first duty cycle adjustment code is greater than the adjustment step of the second duty cycle detection circuit 20. It can be understood that the larger the adjustment step, the worse the accuracy of the duty cycle adjustment code.

[0083] In some embodiments, when performing frequency performance testing on the random access memory 100 , the first to seventh control instructions are sent by a testing device coupled to the random access memory 100 .

[0084] In some embodiments, when the duty cycle self-calibration is performed on the duty cycle adjustment circuit 11 , the first to seventh control instructions are sent by the logic control circuit 50 .

[0085] For further information, see Figure 5 , Figure 5 FIG2 is a schematic diagram of a second duty cycle detection circuit according to an embodiment of the present invention. The second duty cycle detection circuit 20 includes a first adjustment unit 21 , a second adjustment unit 22 and a detection unit 23 .

[0086] The first adjustment unit 21 is configured to adjust the first internal clock signal CLK0 to a second duty cycle to obtain a second internal clock signal CLK0 ′.

[0087] The detection unit 23 is configured to control the first adjustment unit 21 to output the second internal clock signal CLK0 ′ to the second adjustment unit 22 when detecting that the second internal clock signal CLK0 ′ meets a preset requirement.

[0088] The second adjustment unit 22 is used for adjusting the second internal clock signal CLK0 ′ to a third duty cycle to obtain a third internal clock signal CLK0 ″.

[0089] The adjustment step size of the second duty cycle adjustment is greater than the adjustment step size of the third duty cycle adjustment. The detection unit 23 is configured to initiate the third duty cycle adjustment upon detecting that the third internal clock signal CLK0″ meets a first preset requirement, and to save the current adjustment codes of the first adjustment unit 21 and the second adjustment unit 22 as the second duty cycle adjustment code upon detecting that the third internal clock signal CLK0″ meets a second preset requirement. In some embodiments, the frequency of the first internal clock signal CLK0 may be greater than or equal to the first clock signal CLK1 described above.

[0090] Among them, the starting duty cycle adjustment code of the second adjustment unit 22 is determined according to the duty cycle adjustment code of the first adjustment unit 21 when the third internal clock signal CLK0" meets the first preset requirement. When the detection unit 23 detects that the third internal clock signal CLK0" meets the first preset requirement, it starts the third duty cycle adjustment and uses the previous duty cycle adjustment code corresponding to the current duty cycle adjustment code of the first adjustment unit 21 as the starting duty cycle adjustment code of the second adjustment unit 22. Because the adjustment step of the second duty cycle adjustment is greater than the adjustment step of the third duty cycle adjustment, when the third internal clock signal CLK0" meets the first preset requirement, it has crossed from not meeting the preset requirement to meeting the preset requirement. Therefore, the duty cycle adjustment code corresponding to the optimal duty cycle should be within the range between the current duty cycle adjustment code and the previous duty cycle adjustment code. Therefore, the previous duty cycle adjustment code corresponding to the current duty cycle adjustment code of the first adjustment unit 21 can be further used as the starting duty cycle adjustment code of the second adjustment unit 22.

[0091] Combine Figure 6 To explain:

[0092] Step 51: Clock generation is enabled.

[0093] Step 52: Initialize the duty cycle adjustment code.

[0094] In some embodiments, the duty cycle adjustment code is initialized to ensure that the initial state of the detection flag signal F output by the detection unit 23 for the first time is 0. When the second duty cycle detection circuit 20 is self-calibrating, 0 indicates that the self-calibration is not completed, and 1 indicates that the self-calibration is completed.

[0095] Step 53: The detection unit outputs the first 0-to-1 transition.

[0096] The first adjustment unit 21 adjusts the duty cycle of the clock signal, and the detection unit 23 detects the adjusted clock signal and outputs a detection flag signal F. Typically, the detection flag signal F outputted several times is 0. When the output detection flag signal F is 1, it indicates that the first adjustment unit 21 has completed the preliminary calibration of the clock signal.

[0097] Therefore, it is necessary to determine in step 53 whether the detection unit 23 outputs 1 for the first time. If so, step 54 is executed; if not, step 55 is executed.

[0098] Step 54: The duty cycle adjustment code of the first adjustment unit is reduced to serve as the initial duty cycle adjustment code of the second adjustment unit.

[0099] It is understood that, because the adjustment steps of the first adjustment unit 21 and the second adjustment unit 22 are different, the adjustment step of the first adjustment unit 21 is larger than that of the second adjustment unit 22. For example, the first adjustment unit 21 only needs one adjustment to adjust the duty cycle of the clock signal from 45% to 55%, while the second adjustment unit 22 only needs ten adjustments to adjust the duty cycle of the clock signal from 45% to 55%. This is equivalent to the first adjustment unit 21 performing coarse adjustment and the second adjustment unit 22 performing fine adjustment.

[0100] After adjustment by the first adjustment unit 21, the detection flag signal F corresponding to the current duty cycle adjustment code is 1, indicating that the detection flag signal F corresponding to the previous duty cycle adjustment code was 0. Therefore, the current duty cycle adjustment code of the first adjustment unit 21 is reduced to determine the previous duty cycle adjustment code. The previous duty cycle adjustment code of the first adjustment unit 21 is used as the initial duty cycle adjustment code of the second adjustment unit 22. The specific increase or decrease amplitude is determined by the adjustment step size of the corresponding adjustment unit, such as increasing by 1 each time and decreasing by 1 each time.

[0101] Step 55: The duty cycle adjustment code of the first adjustment unit is increased.

[0102] If it is determined that the detection unit 23 does not output 1, the duty cycle adjustment code of the first adjustment unit continues to be adjusted, and the duty cycle of the clock signal is adjusted using the adjusted duty cycle adjustment code.

[0103] Step 56: The duty cycle adjustment code of the second adjustment unit is increased.

[0104] After the initial duty cycle adjustment code of the second adjustment unit 22 is determined, the initial duty cycle adjustment code is adjusted according to the adjustment step of the second adjustment unit 22 , and then the duty cycle of the clock signal is adjusted using the adjusted duty cycle adjustment code.

[0105] Step 57: The detection unit outputs the second 0-to-1 transition.

[0106] After the second adjustment unit 22 adjusts the duty cycle of the clock signal, the detection unit 23 detects the adjusted clock signal and outputs a detection flag signal F. Typically, the detection flag signal F outputted several times is 0. When the output detection flag signal F is 1, it indicates that the second adjustment unit 22 has finally completed the calibration of the clock signal.

[0107] Therefore, it is necessary to determine in step 57 whether the detection unit 23 outputs 1 for the second time. If so, execute step 59; if not, execute step 56 to continue adjusting the duty cycle adjustment code of the second adjustment unit 22 and adjust the duty cycle of the clock signal.

[0108] Step 58: Detection unit detection.

[0109] The detection unit 23 detects the clock signal after the duty cycle is adjusted, and makes corresponding judgments according to the output detection flag signal F.

[0110] For example, when the first adjustment unit 21 performs duty cycle adjustment, the detection unit 23 outputs the detection flag signal F and then executes step 53 ; when the second adjustment unit 22 performs duty cycle adjustment, the detection unit 23 outputs the detection flag signal F and then executes step 57 .

[0111] Step 59: Save the current duty cycle adjustment code.

[0112] When the detection unit 23 outputs the second output 1, it indicates that the second adjustment unit 22 has adjusted the duty cycle of the clock signal to the target state.

[0113] In one application scenario, the initialization duty cycle adjustment code is set to ensure that the initial output state of the detection unit 23 is 0. An output of 0 represents a duty cycle less than 50%, and an output of 1 represents a duty cycle greater than 50%.

[0114] Because second adjustment unit 22 is fine-tuning, when the clock signal adjusted by second adjustment unit 22 is detected by detection unit 23 and outputs 1, it indicates that the current duty cycle adjustment code is able to effectively identify a clock signal with a 50% duty cycle. If the duty cycle is 50%, then after adjustment by the current duty cycle adjustment code, detection unit 23 will inevitably output 1.

[0115] In some embodiments, when performing frequency performance testing on the random access memory 100 , the first to seventh control instructions are sent by a testing device coupled to the random access memory 100 .

[0116] In some embodiments, when the duty cycle self-calibration is performed on the duty cycle adjustment circuit 11 , the first to seventh control instructions are sent by the logic control circuit 50 .

[0117] See Figure 7 , Figure 7 FIG1 is a schematic diagram of a clock transmission link according to an embodiment of the present invention. The clock transmission link 10 includes a duty cycle adjustment circuit 11 , a delay circuit 13 , a phase detection circuit 14 , a controller 15 and a first duty cycle detection circuit 12 .

[0118] The duty cycle adjustment circuit 11 receives the first clock signal CLK1 and performs a first duty cycle adjustment on the first clock signal CLK1 to obtain the second clock signal CLK2 .

[0119] The delay circuit 13 is coupled to the duty cycle adjustment circuit 11 and is configured to delay the second clock signal CLK2 and then output the delayed signal.

[0120] The phase detector circuit 14 is coupled to the duty cycle adjustment circuit 11 and the delay circuit 13 for comparing the first clock signal CLK1 with the delayed second clock signal CLK2 ′.

[0121] The controller 15 is coupled to the duty cycle adjustment circuit 11, the delay circuit 13, the phase detector circuit 14, and the first duty cycle detection circuit 12, respectively, and is configured to adjust the first duty cycle adjustment code of the duty cycle adjustment circuit 11 and the delay of the delay circuit 13 according to the detection results of the first duty cycle detection circuit 12 and the detection results of the phase detector circuit 14. Specifically, the controller 15 receives external signals sent by the test device coupled to the random access memory 100 and decodes the instructions, thereby controlling the state switching of the circuits within the random access memory 100. Alternatively, the controller 15 receives internal signals sent by the state machine within the random access memory 100 and decodes the instructions, thereby controlling the state switching of the circuits within the random access memory 100.

[0122] The duty cycle adjustment circuit 11 , the delay circuit 13 , the phase detector circuit 14 , the controller 15 and the first duty cycle detection circuit 12 cooperate to adjust the duty cycle of the clock signal.

[0123] In some embodiments, when the RAM 100 performs duty cycle self-calibration, this is achieved by providing a state machine within the RAM 100. The state machine is coupled to the output of the second duty cycle detection circuit 20 and the controller 15. After the RAM 100 is powered on, the state machine sends a first duty cycle adjustment code to the controller 15, which serves as the initial value for duty cycle adjustment when the first duty cycle detection circuit 12 is operating normally. Furthermore, the state machine determines whether to send a corresponding control instruction to the controller 15 based on a detection flag signal F output from the output of the second duty cycle detection circuit 20. For example, if the initial detection flag signal F is 0, when the state machine receives a detection flag signal F of 0, the state machine sends a corresponding control instruction to the controller 15, causing the controller 15 to adjust the first duty cycle adjustment code and then perform duty cycle adjustment again using the adjusted first duty cycle adjustment code. When the state machine receives a detection flag signal F of 1, it indicates that the RAM 100 has completed duty cycle self-calibration. This duty cycle self-calibration may be the duty cycle self-calibration of the duty cycle adjustment circuit 11.

[0124] For further information, see Figure 8 , Figure 8 FIG1 is a schematic diagram of another embodiment of a clock transmission link provided by the present application. The clock transmission link 10 includes a duty cycle adjustment circuit 11, a delay circuit 13, a phase detection circuit 14, a controller 15, a first duty cycle detection circuit 12, a clock buffer circuit 16, and an output buffer 17.

[0125] The duty cycle adjustment circuit 11 receives the first clock signal CLK1 and performs a first duty cycle adjustment on the first clock signal CLK1 to obtain the second clock signal CLK2 .

[0126] The delay circuit 13 is used for delaying the second clock signal CLK2 and then outputting the delayed signal.

[0127] The phase detector circuit 14 is used to compare the first clock signal CLK1 with the delayed second clock signal CLK2 ′.

[0128] The clock buffer circuit 16 is coupled to the delay circuit 13 and outputs the delayed second clock signal CLK2 ′ to the first duty cycle detection circuit 12 .

[0129] The output buffer 17 is coupled to the clock buffer circuit 16, caches the delayed second clock signal CLK2′ input by the clock buffer circuit 16, and outputs the cached delayed second clock signal CLK2′ to the second duty cycle detection circuit 20. The second duty cycle detection circuit 20 is used to detect whether the clock transmission link 10 adjusts the clock signal to the target duty cycle.

[0130] The duty cycle adjustment circuit 11 , the delay circuit 13 , the phase detection circuit 14 , the controller 15 , the first duty cycle detection circuit 12 , the clock buffer circuit 16 and the output buffer 17 cooperate to complete the duty cycle adjustment of the clock signal.

[0131] See Figure 9 , Figure 9 1 is a schematic diagram of a test device according to an embodiment of the present invention. The test device 200 is coupled to a random access memory 100, which is the random access memory 100 provided by the above technical solution.

[0132] The test device 200 sends a control instruction to the random access memory 100 so that the random access memory 100 outputs a corresponding detection flag signal F. The test device 200 can determine whether the random access memory 100 meets the frequency performance requirement based on the detection flag signal F.

[0133] Combine Figure 10 To explain:

[0134] After the test device 200 is coupled to the random access memory 100, the corresponding PAD_CMD and PAD_AD instructions are first sent to perform self-calibration on the second duty cycle detection circuit 20. For details of the self-calibration, please refer to the corresponding embodiments above, which will not be described in detail here.

[0135] After the test device 200 detects that the self-calibration of the second duty cycle detection circuit 20 is completed, the input clock of the second duty cycle detection circuit 20 is switched to the clock signal (ie, DQS / DQS#) output by the output buffer 17 .

[0136] The input clock signal of the clock transmission link 10 is the clock signal generated by the clock generation unit 40. The first selection circuit 30 here switches according to the control instruction sent by the test device 200, and then selects the clock signal generated by the clock generation unit 40 to input into the clock transmission link 10.

[0137] The second duty cycle detection circuit 20 is enabled and the duty cycle adjustment code obtained by self-calibration of the second duty cycle detection circuit 20 is sent to the first duty cycle detection circuit 12 so that the first duty cycle detection circuit 12 performs duty cycle detection using the duty cycle adjustment code.

[0138] The testing device 200 sends a PAD_CMD instruction to enable the clock transmission link 10 .

[0139] After waiting for a preset time period, the output state of the second duty cycle detection circuit 20 is read through the pin PAD_DQ and the current state is recorded. The PAD_DQ signal output by the pin PAD_DQ can be used as the detection flag signal F mentioned above.

[0140] After resetting the clock transmission link 10, the test device 200 sends a new PAD_CMD command to change the duty cycle adjustment code of the first duty cycle detection circuit 12 in the clock transmission link 10. Assuming the initial state is 0, the duty cycle adjustment code of the first duty cycle detection circuit 12 is increased. If the initial state is 1, the duty cycle adjustment code of the first duty cycle detection circuit 12 is decreased. The duty cycle adjustment code is increased to widen the duty cycle in the clock transmission link 10. The initial state of 0 is merely an example. If the initial state is 1, the duty cycle adjustment code is decreased to narrow the duty cycle in the clock transmission link 10.

[0141] The testing device 200 sends a new PAD_CMD instruction to enable the clock transmission link 10 .

[0142] After waiting for a preset time period, the detection flag signal F output by the second duty cycle detection circuit 20 is read through the pin PAD_DQ to record the current state. The purpose of waiting for the preset time period is to allow the output of the clock transmission link 10 to stabilize.

[0143] For example, if the initial state is 0 and the current state is also 0, the above process is repeated to adjust the duty cycle adjustment code of the first duty cycle detection circuit 12. If the current state is 1, the current state is recorded as the final duty cycle adjustment result. When the current state is 1, it indicates that the duty cycle of the clock signal output by the pin DQS / DQS# has reached the target duty cycle, such as 50%.

[0144] For example, if the initial state is 1 and the current state is also 1, the above process is repeated to adjust the duty cycle adjustment code of the first duty cycle detection circuit 12. If the current state is 0, the current state is recorded as the final duty cycle adjustment result. When the current state is 0, it means that the duty cycle of the clock signal output by the pin DQS / DQS# has reached the target duty cycle, such as 50%.

[0145] The final duty cycle adjustment result, that is, the duty cycle adjustment code of the first duty cycle detection circuit 12 when the first clock signal CLK1 is adjusted to a clock signal with a duty cycle of 50%, is written into the electronic fuse efuse.

[0146] It can be understood that when the clock transmission link 10 is actually working, the frequency of the external input PAD_clk may be lower than 3233, but the duty cycle error is tolerable at low frequency.

[0147] If the final duty cycle adjustment result indicates that the random access memory 100 does not meet the frequency performance requirement, the random access memory 100 may be marked as being unable to implement the corresponding frequency function.

[0148] The above process may be performed when the random access memory 100 is still a wafer or a packaged wafer, such as a CP test or a FT test.

[0149] Furthermore, the clock transmission link 10 may be a series of links capable of performing clock adjustment, such as a DLL.

[0150] In combination with the beneficial effects of the above embodiments, the two duty cycle detection circuits within the random access memory 100 are utilized to perform duty cycle calibration detection of the clock transmission link 10 within the random access memory 100, thereby solving the problem of detecting the frequency performance of the random access memory 100 and / or the problem of self-calibration of the duty cycle in the random access memory 100. Furthermore, the clock unit is utilized to provide a high-frequency clock signal, thereby detecting the high-frequency performance of the random access memory 100, thereby solving the problem of the probe hardware limitations of the test device 200 that cannot provide a high-frequency clock signal.

[0151] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0152] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A random access memory, characterized in that: The random access memory comprises: A clock transmission link, the clock transmission link comprising a duty cycle adjustment circuit and a first duty cycle detection circuit; wherein the duty cycle adjustment circuit is used to adjust the duty cycle of an input first clock signal to obtain a second clock signal; and the first duty cycle detection circuit is used to perform a first duty cycle detection on the second clock signal and feed the detection result back to the duty cycle adjustment circuit; A second duty cycle detection circuit is coupled to the output end of the clock transmission link, performs a second duty cycle detection on the second clock signal, and outputs a detection flag signal, wherein the detection accuracy of the second duty cycle detection circuit is higher than the detection accuracy of the first duty cycle detection circuit, and the detection flag signal indicates whether the duty cycle of the second clock signal passes the detection when the first clock signal is used as the input clock of the duty cycle adjustment circuit, and obtains the first duty cycle adjustment code of the first duty cycle detection circuit when the detection passes.

2. The random access memory according to claim 1, wherein: Before performing the second duty cycle detection on the second clock signal, the second duty cycle detection circuit first adjusts and detects the duty cycle of the first clock signal, and saves the second duty cycle adjustment code of the second duty cycle detection circuit when the detection passes to complete the self-calibration of the second duty cycle detection circuit.

3. The random access memory according to claim 1, wherein: The first duty cycle adjustment code of the first duty cycle detection circuit is burned into the electronic fuse of the random access memory to complete the frequency performance detection of the random access memory, or serves as the initial value of the duty cycle adjustment when the duty cycle adjustment circuit is working normally to complete the duty cycle self-calibration of the duty cycle adjustment circuit.

4. The random access memory according to claim 1, wherein: The random access memory further includes: clock generation unit; a first selection circuit, wherein a first input terminal of the first selection circuit is coupled to an external clock input terminal, a second input terminal of the first selection circuit is coupled to the clock generation unit, and an output terminal of the first selection circuit is coupled to an input terminal of the clock transmission link; A logic control circuit is coupled to the control end of the first selection circuit, and controls the output end of the first selection circuit to output the external clock signal as the first clock signal in response to a first control instruction; or controls the output end of the first selection circuit to output the first internal clock signal generated by the clock generation unit as the first clock signal in response to a second control instruction.

5. The random access memory according to claim 4, wherein: The random access memory further includes: a second selection circuit, wherein a first input terminal of the second selection circuit is coupled to the output terminal of the clock transmission link, a second input terminal of the second selection circuit is coupled to the clock generation unit, and an output terminal of the second selection circuit is coupled to the second duty cycle detection circuit; The logic control circuit is coupled to the control end of the second selection circuit, and in response to a third control instruction, controls the output end of the second selection circuit to output the second clock signal; or in response to a fourth control instruction, controls the output end of the second selection circuit to output the first internal clock signal, so that the second duty cycle detection circuit self-calibrates.

6. The random access memory according to claim 5, wherein: The second duty cycle detection circuit includes: a first adjustment unit, a second adjustment unit and a detection unit; The first adjustment unit is used to adjust the second duty cycle of the first internal clock signal to obtain a second internal clock signal; The second adjustment unit is configured to perform a third duty cycle adjustment on the second internal clock signal to obtain a third internal clock signal; wherein an adjustment step length of the second duty cycle adjustment is greater than an adjustment step length of the third duty cycle adjustment; The detection unit is used to start the third duty cycle adjustment when it is detected that the third internal clock signal meets the first preset requirement, and to save the current adjustment codes of the first adjustment unit and the second adjustment unit as the second duty cycle adjustment code of the second duty cycle detection circuit when it is detected that the third internal clock signal meets the second preset requirement.

7. The random access memory according to claim 6, wherein: The starting duty cycle adjustment code of the second adjustment unit is determined according to the duty cycle adjustment code of the first adjustment unit when the third internal clock signal meets the first preset requirement.

8. The random access memory according to claim 5, wherein: In response to the third control instruction, the logic control circuit loads a second duty cycle adjustment code of the second duty cycle detection circuit into the second duty cycle detection circuit; In response to a fifth control instruction, the logic control circuit controls the second duty cycle detection circuit to perform the second duty cycle detection on the second clock signal and record the detection flag signal; in response to a sixth control instruction, the logic control circuit controls the step adjustment of the first duty cycle adjustment code; In response to the seventh control instruction, the logic control circuit controls the second duty cycle detection circuit to perform the second duty cycle detection on the second clock signal again, and records the detection flag signal. If the detection flag signal flips, the first duty cycle adjustment code at this time is obtained and burned into the electronic fuse of the random access memory to complete the frequency performance detection of the random access memory, or used as the initial value of the duty cycle adjustment circuit to complete the duty cycle self-calibration of the duty cycle adjustment circuit.

9. The random access memory according to claim 8, wherein: The adjustment step size of the step-by-step adjustment of the first duty cycle adjustment code is greater than the adjustment step size of the second duty cycle detection circuit.

10. The random access memory according to claim 8, wherein: When the frequency performance test is performed on the random access memory, the first control instruction to the seventh control instruction are sent by a test device coupled to the random access memory; or When the duty cycle self-calibration is performed on the duty cycle adjustment circuit, the first control instruction to the seventh control instruction are sent by the logic control circuit.

11. The random access memory according to claim 1, wherein: The clock transmission link further includes: a delay circuit, coupled to the duty cycle adjustment circuit, configured to delay the second clock signal and then output it; a phase detection circuit coupled to the duty cycle adjustment circuit and the delay circuit, and configured to compare the first clock signal with the delayed second clock signal; a controller, wherein the controller is respectively coupled to the duty cycle adjustment circuit, the delay circuit, the phase detection circuit and the first duty cycle detection circuit, and is used to adjust the first duty cycle adjustment code of the first duty cycle detection circuit and the delay of the delay circuit according to the detection result of the first duty cycle detection circuit and the detection result of the phase detection circuit.

12. The random access memory according to claim 11, wherein: The clock transmission link further includes: The clock buffer circuit is coupled to the delay circuit and outputs the delayed second clock signal to the first duty cycle detection circuit.

13. The random access memory according to claim 12, wherein: The clock transmission link further includes: An output buffer is coupled to the clock buffer circuit, buffers the delayed second clock signal input from the clock buffer circuit, and outputs the buffered delayed second clock signal to the second duty cycle detection circuit.

14. A testing device, characterized in that: A random access memory according to any one of claims 1 to 13 and a testing device coupled to the random access memory; The testing device sends a detection instruction to the random access memory so that the random access memory outputs a corresponding detection flag signal.

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