An embedded resistive thin film material with extremely low temperature coefficient of resistance and its preparation method

Abstract

This invention relates to an embedded resistive thin film material with an extremely low temperature coefficient of resistance. The material includes a substrate, an insertion layer, and a resistive layer. The embedded resistive thin film material with an extremely low temperature coefficient of resistance is deposited on the substrate by sputtering. By changing the annealing temperature, the embedded resistive material with an extremely low temperature coefficient of resistance can be obtained. The temperature coefficient of resistance can be increased by up to 38 times, thereby improving the thermal stability of the embedded resistive thin film material. This results in an embedded resistive thin film material with a wide range of applications, high repeatability, simple process, and easy-to-control preparation process.

Description

Technical Field

[0001] This invention relates to a thin-film resistor material, specifically to an embedded resistor thin-film material with an extremely low temperature coefficient of resistance, belonging to the field of electronic materials and electronic components technology. Background Technology

[0002] With the development of electronic technology, electronic products are trending towards miniaturization and portability. This places higher demands on the PCB (Printed Circuit Board) of electronic products, requiring higher integration density to improve the miniaturization of electronic components. The large number of passive components on the PCB surface is a major obstacle to PCB miniaturization. Furthermore, as the number of surface-mount electronic components increases, not only does the available PCB space become limited, but the traditional surface mount technology (SMT) inevitably leads to an increase in the number of solder joints, affecting the reliability of electronic component connections. Embedding passive components inside the PCB not only saves a significant amount of surface space, increases PCB integration, and promotes PCB miniaturization, but also reduces the number of solder joints, ensuring the reliability of electronic products. Therefore, to overcome the technical limitations of SMT and improve the integration of electronic components, embedded technology is constantly evolving.

[0003] The temperature coefficient of resistance (TCR) refers to the relative rate of change of resistance with temperature, usually expressed as the change in resistivity per degree Celsius (°C). It reflects the sensitivity of a material's resistance to temperature changes. A low TCR ensures circuit stability in environments with large temperature variations, reduces the risk of circuit failure, and extends the lifespan of equipment. In many electronic devices, changes in the resistance of resistive elements can affect the performance of the entire circuit. To maintain circuit accuracy and stability, it is necessary to control the characteristics of resistance changing with temperature, and the temperature coefficient of resistance can be controlled by altering the resistor's structure.

[0004] Embedded resistors require high stability in applications, and chromium-silicon-carbon (chromium-silicon-carbon) materials combine the properties of metals, semiconductors, and ceramics. They exhibit excellent oxidation and corrosion resistance at high temperatures, and through annealing, the temperature coefficient of resistance (TCR) of chromium-silicon-carbon gradually changes from negative to positive as the annealing temperature increases. Furthermore, chromium-silicon-carbon materials perform well in high-frequency applications, reducing electrical performance attenuation during signal transmission, making them suitable for RF and microwave communication systems. Nickel-phosphorus alloys possess corrosion resistance, high resistivity, and good stability, with a positive TCR after annealing. By layering chromium-silicon-carbon and nickel-phosphorus materials, the TCR values ​​are mutually compensated, and the values ​​are extremely low after annealing. Combining the advantages of both materials will result in a new type of resistor material with more stable resistive performance.

[0005] Currently, Japan and the United States are leading in PCB embedded capacitor and resistor raw materials, as well as product design and manufacturing technologies. Their main commercialized products include nickel-phosphorus resistor materials prepared by electroplating by Ohmega-ply in the United States, nickel-phosphorus resistor materials prepared by Mac Demid using the addition method, and nickel-chromium resistor materials prepared by Gould using the sputtering method. These resistor products each have their own advantages, while their performance still has room for improvement.

[0006] The development of embedded thin-film resistors in China is still in its early stages. Currently, the main research method for the resistance value and electrical performance of embedded resistors is to change the doping ratio of the resistive material. However, this method is difficult to precisely control the resistance value and is hard to repeat in production. Furthermore, copper is commonly used in the production and development of electronic components, and interdiffusion between copper and the resistive material can affect the electrical performance of the device. However, by changing the thickness ratio of the resistive material, the resistance value can be precisely controlled, and the repeatability in production is high. The introduction of nickel-phosphorus alloys can effectively block the diffusion between copper and the resistive material. Therefore, to address the above problems in the development of embedded resistor products, it is crucial to develop a bilayer film resistive material and an industrial production method that is based on thickness ratio and annealing temperature control, prevents interdiffusion between the resistive material and copper, has a wide range of adjustable resistance values, and provides stable electrical performance. Summary of the Invention

[0007] This invention addresses the existing technical problems in the field of embedded resistors by proposing a method for fabricating a double-layer film resistor structure and a high-temperature annealing process. This method broadens the resistance value range of the resistor and improves the stability of its electrical performance.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows: an embedded resistor thin film material with an extremely low temperature coefficient of resistance, the material comprising a substrate, a resistive layer, and an insertion layer, wherein the insertion layer is disposed between the substrate and the resistive layer, i.e., substrate (Al2O3) - insertion layer (nickel phosphide) - resistive layer (chromium silicon carbide). The material composition and structure of the embedded resistor are studied.

[0009] In terms of thickness, the total thickness of the film in the embedded resistor material with extremely low temperature coefficient of resistance is 60-180 nanometers, of which the thickness of the resistor layer is 30-150 nanometers and the thickness of the insertion layer is 2-30 nanometers.

[0010] The substrate is one or more of a ceramic substrate, a metal substrate, or a silicon substrate.

[0011] The resistive layer is made of a CrSiC alloy, with an atomic percentage of 25% chromium, 50% silicon, and 25% carbon. Under complex electromagnetic environments and varying temperature and humidity conditions, the CrSiC material maintains relatively stable resistance, ensuring the accuracy of instrument measurements. This CrSiC alloy, without annealing, has a negative temperature coefficient of -699.9 ppm / K, resulting in lower film stability. However, the addition of carbon interferes with electron movement within the crystal lattice, leading to a significant improvement in sheet resistance compared to CrSi alloy.

[0012] The insert layer is made of NiP alloy, with 70% nickel and 30% phosphorus by atomic percentage. This ratio of NiP alloy allows for precise fabrication of resistors with specific resistance values ​​via sputtering deposition. The NiP material at this ratio bonds well with the substrate, improving the stability of the embedded resistor in the circuit board and reducing the likelihood of delamination or peeling.

[0013] NiP alloy (7:3) and CrSiC alloy (1:2:1) possess different electrical properties. NiP alloy exhibits good conductivity and a relatively low temperature coefficient of resistance, while CrSiC alloy provides more stable resistance characteristics, especially under high temperature and high frequency environments. By inserting a nickel-phosphorus thin film under a chromium-silicon-carbon layer using magnetron sputtering, the resistance value of the embedded resistor can be precisely controlled over a wider range to meet the varying resistance requirements of various complex circuits. NiP alloy (7:3) has a low temperature coefficient of resistance, while CrSiC alloy (1:2:1) maintains stable resistance over a wide temperature range. When NiP (7:3) film is used as an insertion layer for CrSiC (1:2:1) film, a lower temperature coefficient can be achieved, ensuring accurate resistance values ​​even in more extreme temperature environments.

[0014] This embedded resistive thin film with an extremely low temperature coefficient of resistance uses a chromium-silicon-carbon thin film as the main material and a nickel-phosphorus film as the intercalation layer. On the one hand, the nickel-phosphorus film, when used as the intercalation layer, can significantly improve the crystal structure of chromium-silicon-carbon and enhance the thermal stability of the film. On the other hand, the insertion of the nickel-phosphorus layer increases the probability of electrons being scattered at the interface, thereby causing a sharp increase in resistivity and sheet resistance of the nickel-phosphorus-chromium-silicon-carbon bilayer structure film of the same thickness. When the proportion of the nickel-phosphorus layer increases, the nickel-phosphorus layer becomes dominant, achieving ultra-low sheet resistance, thus enabling a wide range of sheet resistance adjustment.

[0015] A method for preparing an embedded resistive material with an extremely low temperature coefficient of resistance, the method comprising the following steps:

[0016] Step 1: Select chromium silicon carbon and nickel phosphorus as the basic materials for double-layer thin film resistors. Chromium silicon carbon has the characteristic of high sheet resistance. After high-temperature annealing, the temperature coefficient gradually increases and turns from negative to positive at 500℃. After annealing, the temperature coefficient of nickel phosphorus material quickly turns to positive. The double-layer structure thin film is achieved by inserting nickel phosphorus material at the bottom of the chromium silicon carbon thin film to adjust the film temperature coefficient.

[0017] Step 2: Substrate selection. Al2O3 was selected as the sputtering substrate. The substrate was ultrasonically cleaned for 10 minutes each in anhydrous acetone, anhydrous ethanol, and deionized water, and then dried with a nitrogen gun for later use.

[0018] Step 3: Sputtering deposition is performed on the substrate using magnetron sputtering to obtain the corresponding bilayer thin film material, wherein the atomic percentage of chromium silicon-carbon target is 1:2:1 and the atomic percentage of nickel-phosphorus target is 7:3; the purity of chromium silicon-carbon target is 99.9% and the purity of nickel-phosphorus target is 99.9%; the chromium silicon-carbon target and nickel-phosphorus target are placed on different cathode palladium positions, and the substrate is fixed on a rotating work stand in the main sputtering cavity;

[0019] Argon gas is introduced during sputtering, and the gas pressure in the main chamber is controlled at around 0.9 Pa through the flow valve and the vent valve. The rotation speed of the sample rotating worktable is set to 10 rpm. Before sputtering, chromium silicon carbide and nickel phosphorus targets are pre-sputtered for 5 minutes respectively to prevent oxidation or dust accumulation on the target surface from contaminating the thin film sample.

[0020] During the sputtering process, the substrate temperature is kept at room temperature;

[0021] During the sputtering process, the sputtering power for both the chromium-silicon-carbon target and the nickel-phosphorus target was 50W. By changing the sputtering time, the sputtering thickness of each thin film was adjusted, thereby changing the proportion of each component in the bilayer thin film.

[0022] High-vacuum annealing control. The temperature coefficient and electrical properties of the film are adjusted by annealing the film under high vacuum at 200℃~500℃ for 30 minutes.

[0023] After annealing, the sheet resistance of the chromium-silicon-carbon-nickel-phosphorus bilayer film changed significantly compared to when it was not inserted. At an annealing temperature of 200℃, the sheet resistance of the embedded resistor film changed from 485.25 Ω / sq to 31.38 Ω / sq after introducing the nickel-phosphorus insertion layer; at 300℃, the sheet resistance changed from 545.39 Ω / sq to 32.28 Ω / sq; at 400℃, the sheet resistance changed from 745.37 Ω / sq to 68.62 Ω / sq; and at 500℃, the sheet resistance changed from 1776.77 Ω / sq to 56.54 Ω / sq. This demonstrates that inserting the nickel-phosphorus layer broadens the resistance range of the embedded resistor.

[0024] This embedded resistive thin film with an extremely low temperature coefficient of resistance uses a chromium-silicon-carbon thin film as the main material and a nickel-phosphorus film as the intercalation layer. On the one hand, the nickel-phosphorus film, when used as the intercalation layer, can significantly improve the crystal structure of chromium-silicon-carbon and enhance the thermal stability of the film. On the other hand, the insertion of the nickel-phosphorus layer increases the probability of electrons being scattered at the interface, thereby causing a sharp increase in resistivity and sheet resistance of the nickel-phosphorus-chromium-silicon-carbon bilayer structure film of the same thickness. When the proportion of the nickel-phosphorus layer increases, the nickel-phosphorus layer becomes dominant, achieving ultra-low sheet resistance, thus enabling a wide range of sheet resistance adjustment.

[0025] In nickel-phosphorus-chromium-silicon-carbon bilayer thin films, an incoherent interface is formed at the interface, resulting in decreased film crystallinity and smaller grains. This increases the surface area of ​​the grain boundaries, leading to a significant increase in the probability of electrons being scattered by the grain boundaries. This is one of the reasons why the resistivity of the nickel-phosphorus-chromium-silicon-carbon bilayer thin film increases sharply compared to the chromium-silicon-carbon monolayer thin film.

[0026] The nickel-phosphorus-chromium-silicon-carbon bilayer thin film initially exists in an amorphous state with loosely arranged atoms. After annealing at 200℃, impurities and defects within the film decrease, and the electron scattering mechanism shifts to phonon scattering dominance, causing the temperature coefficient of the film to change from negative to positive. When the annealing temperature is between 200℃ and 300℃, electron and phonon scattering within the film reaches a certain equilibrium, and the film's resistance and temperature coefficient remain almost unchanged. During annealing at 300℃ to 400℃, a chromium-silicon-carbon-nickel-phosphorus alloy layer forms at the resistivity interface of the nickel-phosphorus-chromium-silicon-carbon bilayer thin film. Furthermore, this chromium-silicon-carbon-nickel-phosphorus alloy exhibits improved resistance and temperature coefficient under annealing conditions ranging from 0℃ to 500℃. Since the temperature coefficient is negative, the thin-film resistor annealed at 400℃ is equivalent to a resistor with a negative temperature coefficient (chromium silicon carbon nickel phosphorus layer) connected in parallel with a resistor with a positive temperature coefficient (chromium silicon carbon layer, nickel phosphorus layer), achieving temperature coefficient compensation. Therefore, the overall temperature coefficient of resistance of the thin-film resistor suddenly drops from the positive value at 300℃ annealing to the negative value at 400℃ annealing. When annealing at 400℃ to 500℃, atomic diffusion at the interface tends to saturate, the thickness of the chromium silicon carbon nickel phosphorus alloy layer is stable, and the overall temperature coefficient of resistance of the thin film further changes towards a positive value as the crystals in the chromium silicon carbon and nickel phosphorus thin films grow.

[0027] Compared to existing technologies, the ultra-low temperature coefficient thin-film resistive material of this invention has a wider resistance range. The insertion of the nickel-phosphorus layer compensates for the lack of resistance value of chromium-silicon-carbon material in the low resistance range, and significantly improves its temperature coefficient. After annealing at 500℃, the original sample achieved a change from a negative to a positive temperature coefficient in the temperature range of -55 to 125℃. When the thickness ratio of chromium-silicon-carbon to nickel-phosphorus is 30nm:30nm, the sample with the best TCR is obtained after annealing at 500℃, with a TCR value of -4.87ppm / K.

[0028] Magnetron sputtering deposition enables precise control of film thickness and yields extremely thin, uniform films. By reducing the thickness of the nickel-phosphorus intercalation layer, the sheet resistance of the bilayer film increases. With a chromium-silicon-carbon to nickel-phosphorus thickness ratio of 5 nm:30 nm, after annealing at 500 °C, the sheet resistance increases from 64.5 Ω / sq when the chromium-silicon-carbon to nickel-phosphorus thickness ratio is 30 nm:30 nm to 269.6 Ω / sq, and the TCR value changes from -4.87 ppm / K to -4.97 ppm / K. This indicates that the method can effectively achieve wide-range control of sheet resistance and has an extremely low film temperature coefficient, thus addressing the shortcomings of embedded resistors in temperature stability. Attached Figure Description

[0029] Figure 1 This is a simplified structural diagram of the magnetron sputtering instrument used in this invention.

[0030] Figure 2 Diagram of an embedded resistor with an extremely low temperature coefficient of resistance.

[0031] Figure 3 This is a structural diagram of the buried resistor device used in the four-terminal method test according to the present invention.

[0032] Figure 4 The temperature coefficients and resistivity of monolayer chromium-silicon-carbon thin films and monolayer nickel-phosphorus thin films of different thicknesses, as well as the temperature coefficient changes at room temperature after insertion, are investigated.

[0033] Figure 5 The graph shows the relationship between the temperature coefficients of 30nm+30nm nickel-phosphorus-chromium-silicon-carbon bilayer films, single-layer 30nm chromium-silicon-carbon films, single-layer 30nm nickel-phosphorus films, and single-layer chromium-silicon-carbon nickel-phosphorus films as a function of annealing temperature. Detailed Implementation

[0034] To enhance understanding of the present invention, a detailed description of the invention will be provided below with reference to the accompanying drawings.

[0035] Example: See Figure 1 (Sputtering diagram inside the sputtering chamber), chromium-silicon-carbon and nickel-phosphorus ultra-low temperature coefficient thin films. The bilayer thin film resistor adjusts the ratio of the two materials by changing the thickness of the chromium-silicon-carbon material. The bilayer thin film resistor also includes a substrate, on which the resistive thin film is deposited. The substrate is selected as Al2O3.

[0036] Experiments have shown that the aforementioned chromium-silicon-carbon-nickel-phosphorus bilayer thin-film resistor exhibits a wide range of sheet resistance variation and good electrical stability within a temperature range of -55 to 125°C after annealing. It has high application value and a wide range of applications.

[0037] The method for preparing an embedded thin-film resistor with an extremely low temperature coefficient in a chromium-silicon-carbon-nickel-phosphorus bilayer structure includes the following steps:

[0038] Step S110: Provide a substrate. The substrate is selected as Al2O3. The substrate is ultrasonically cleaned once in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes, and then dried with a nitrogen gun for later use.

[0039] Step S120: Sputtering deposition is performed on the substrate using magnetron sputtering to obtain the corresponding bilayer thin film material, wherein the atomic percentage of chromium silicon-carbon target is 1:2:1 and the atomic percentage of nickel-phosphorus target is 7:3; wherein the purity of chromium silicon-carbon target is 99.9% and the purity of nickel-phosphorus target is 99.9%; the chromium silicon-carbon target and the nickel-phosphorus target are placed on different cathode palladium positions, and the substrate is fixed on a rotating work stand in the main sputtering cavity;

[0040] Argon gas is introduced during sputtering, and the gas pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the vent valve. The rotation speed of the sample rotating worktable is set to 10 rpm. Before sputtering, chromium silicon carbide target and nickel phosphorus target are pre-sputtered for 5 minutes respectively to prevent oxidation or dust accumulation on the target surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering.

[0041] During the sputtering process, the substrate temperature is kept at room temperature;

[0042] During the sputtering process, the sputtering power for both the chromium-silicon-carbon target and the nickel-phosphorus target was 50W. By changing the sputtering time, the sputtering thickness of each thin film was adjusted, thereby changing the proportion of each component in the bilayer thin film.

[0043] After sputtering, the thin film is annealed under high vacuum. The annealing temperature range is 200-500℃ and the annealing time is 30 minutes. After cooling, the annealed ultra-low temperature coefficient thin film resistive material is taken out.

[0044] The above describes a simple and highly repeatable method for preparing embedded resistor materials with extremely low temperature coefficients, which is conducive to industrial application. The resulting thin films have good uniformity, precise thickness, and easy-to-adjust resistance values.

[0045] Example 1:

[0046] Fabrication of embedded thin film resistors

[0047] (1) The Al2O3 substrate with a size of 1cm×1cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol and deionized water for 10 minutes in sequence, and then dried with a nitrogen gun for later use.

[0048] (2) Argon gas is introduced during sputtering, and the gas pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the vent valve. The rotation speed of the sample rotating worktable is set to 10 rpm. Before sputtering, the chromium silicon carbide target and the nickel phosphorus target are pre-sputtered for 5 minutes respectively to prevent oxidation or dust accumulation on the target surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After pre-sputtering, the substrate baffle is opened for thin film sputtering deposition. First, a nickel phosphorus thin film is sputtered and deposited on the substrate with a sputtering power of 50 W and a sputtering time of 7 minutes and 30 seconds. Then, a chromium silicon carbide thin film is sputtered and deposited on the nickel phosphorus thin film with a sputtering power of 50 W and a sputtering time of 7 to 36 minutes. A nickel phosphorus-chromium silicon carbide bilayer film structure thin film resistor is formed, and the substrate temperature is kept at room temperature.

[0049] (3) After sputtering, the nickel-phosphorus-chromium-silicon-carbon double-layer film resistor is subjected to a high-temperature annealing process, that is, the film is annealed for 30 minutes at 200℃, 300℃, 400℃ and 500℃ in a high vacuum state.

[0050] Target material selection. The resistive layer material is selected as CrSiC alloy, with 25% chromium, 50% silicon, and 25% carbon by atomic percentage. The insertion layer material is NiP alloy, with 70% nickel and 30% phosphorus by atomic percentage.

[0051] Substrate cleaning. Select a ceramic substrate as the substrate, place the substrate in a sieve, and use acetone, alcohol, and deionized water to ultrasonically clean for 10 minutes in sequence, with an ultrasonic frequency of 40Hz;

[0052] Photolithography. Using AZ5510 photoresist and a reverse photoresist process, a resistance pattern with a size of 300nm × 600nm is fabricated on the substrate.

[0053] Sample transfer. The substrate with the resistance pattern after photolithography is sent into the sputtering cavity, maintaining a vacuum state during the transfer process;

[0054] Sample sputtering growth. Argon gas was introduced, and the gas flow meter and gas valve were adjusted to maintain the chamber pressure at about 0.9 Pa. The sample was rotated at 10 rpm. The sputtering power of NiP target was 50 W and the sputtering time was 7 minutes and 30 seconds. The sputtering power of CrSiC target was 50 W and the sputtering time ranged from 7 to 37 minutes. Sputtering deposition was carried out sequentially.

[0055] The sputtered sample was placed in a flower bed and ultrasonically removed using NMP (N-methylpyrrolidone, 1-Methyl-2-pyrrolidinone) at a frequency of 80 Hz for 20 minutes. This yielded electronic devices with extremely low temperature coefficients of resistance, such as… Figure 2 As shown.

[0056] Comparative Example 1:

[0057] (1) The Al2O3 substrate with a size of 1cm×1cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol and deionized water for 10 minutes in sequence, and then dried with a nitrogen gun for later use.

[0058] (2) Argon gas is introduced during sputtering, and the gas pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the vent valve. The rotation speed of the sample rotating worktable is set to 10 rpm. Before sputtering, the chromium silicon-carbon target is pre-sputtered for 5 minutes to prevent oxidation or dust accumulation on the target surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After pre-sputtering, the substrate baffle is opened for thin film sputtering deposition. Chromium silicon-carbon thin films are deposited on the substrate. The sputtering power is selected as 50 W, and the sputtering time is 7 to 36 minutes to form chromium silicon-carbon monolayer thin films of different thicknesses.

[0059] (3) After sputtering, the chromium-silicon-carbon monolayer thin film structure resistor is subjected to a high-temperature annealing process, that is, the thin film is annealed for 30 minutes at 200℃, 300℃, 400℃ and 500℃ respectively in a high vacuum state.

[0060] Comparative Example 2:

[0061] (1) The Al2O3 substrate with a size of 1cm×1cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol and deionized water for 10 minutes in sequence, and then dried with a nitrogen gun for later use.

[0062] (2) Argon gas is introduced during sputtering, and the gas pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the vent valve. The rotation speed of the sample rotating worktable is set to 10 rpm. Before sputtering, the nickel-phosphorus target is pre-sputtered for 5 minutes to prevent oxidation or dust accumulation on the target surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After pre-sputtering, the substrate baffle is opened for thin film sputtering deposition. A nickel-phosphorus thin film is deposited on the substrate. The sputtering power is selected as 50 W, and the sputtering time is 7 minutes and 30 seconds to form a 30 nm monolayer film.

[0063] (3) After sputtering, the chromium-silicon-carbon monolayer thin film structure resistor is subjected to a high-temperature annealing process, that is, the thin film is annealed for 30 minutes at 200℃, 300℃, 400℃ and 500℃ respectively in a high vacuum state.

[0064] Comparative Example 3:

[0065] (1) The Al2O3 substrate with a size of 1cm×1cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol and deionized water for 10 minutes in sequence, and then dried with a nitrogen gun for later use.

[0066] (2) Argon gas is introduced during sputtering, and the gas pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the vent valve. The rotation speed of the sample rotating worktable is set to 10 rpm. Before sputtering, the chromium silicon carbide target and the nickel phosphorus target are pre-sputtered for 5 minutes respectively to prevent oxidation or dust accumulation on the target surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After pre-sputtering, the substrate baffle is opened for thin film sputtering deposition. Chromium silicon carbide and nickel phosphorus targets are sputtered simultaneously on the substrate. The sputtering power of the targets is 50 W for each target, forming a chromium silicon carbide-nickel phosphorus co-sputtered thin film structure.

[0067] (3) After sputtering, the chromium-silicon-carbon-nickel-phosphorus co-sputtered thin film resistive structure is subjected to a high-temperature annealing process, namely, the thin film is annealed at 200℃, 300℃, 400℃ and 500℃ respectively in a high vacuum state.

[0068] Anneal for 30 minutes.

[0069] The double-layer thin film in Example 1 and the thin film in Comparative Example 1 were subjected to photolithography to obtain the embedded resistor device required for the four-terminal testing method, such as... Figure 3 As shown.

[0070] The obtained thin-film resistive device was tested using a high and low temperature vacuum testing station (KT-Z160T-RL), with temperature variations performed at vacuum levels below 100 Pa. Figure 2 As shown, four probes are connected to the four terminals of the resistor under test. Ports 1 and 2 are connected to a Keithley 2450 digital source meter, with a constant current I flowing between them. The Keithley 2450 digital source meter records the voltage change U between ports 34 (or 35, 56, 46) during the temperature change process. By comparing the measured voltage value with the current value flowing through ports 1 and 2, the resistance value of the corresponding resistor can be obtained. Given that the effective length of the resistive device is L, the width is W, and the film thickness is t, according to the formula... The sheet resistance value R of the corresponding embedded resistor device is calculated. sq The resistance measurement temperature range is -55℃ to 125℃, with a node set every 25℃. Each node is held for 6 minutes to ensure the sample reaches the target temperature, according to the temperature coefficient formula. The temperature coefficient of resistance of the material at each temperature point with respect to room temperature T0 (T0 = 25℃) was obtained. The relationship between the temperature coefficient and sheet resistance of Example 1 as a function of film thickness is shown below. Figure 4 As shown.

[0071] Plot the sheet resistance curves of Example 1 and Comparative Example 1 as a function of annealing temperature; plot the temperature coefficient curves of Example 1 and Comparative Example 1 as a function of annealing temperature, as follows: Figure 4 As shown.

[0072] At room temperature, four-probe tests were performed on nickel-phosphorus-chromium-silicon-carbon bilayer thin film embedded resistor samples with different chromium-silicon-carbon thicknesses from Example 1. Curves showing the relationship between the thin film resistivity and annealing temperature, and the relationship between the thin film temperature coefficient and annealing temperature for the relevant structures were plotted. Figure 5 As shown.

[0073] Plot the temperature coefficient graphs of Example 1 and Comparative Examples 1-2 before annealing, as follows: Figure 4 As shown.

[0074] Figure 4 In Example 1, the overall temperature coefficient of the thin film's resistance remains essentially unchanged. The temperature coefficient range for chromium-silicon-carbon monolayer thin films of different thicknesses is -699.9 to -652.5 ppm / K. Thin films without an inserted nickel-phosphorus layer exhibit poor thermal stability.

[0075] Figure 4As can be seen, after sputtering insertion into the nickel-phosphorus layer, the temperature coefficient range changes from -699.9 to -652.5 ppm / K to -188.85 to -148.8 ppm / K, with the lowest reaching -148.8 ppm / K. This indicates a significant improvement in the thermal stability of the film.

[0076] Figure 5 The results show that when the annealing temperature is 200℃, the temperature coefficient of the buried resist film increases from -329.84 ppm / K to 521.41 ppm / K after introducing the nickel-phosphorus intercalation layer; when the annealing temperature is 300℃, the temperature coefficient of the buried resist film increases from -423.56 ppm / K to 512.41 ppm / K; when the annealing temperature is 400℃, the temperature coefficient of the buried resist film increases from -263.15 ppm / K to -96.94 ppm / K; and when the annealing temperature is 500℃, the temperature coefficient of the buried resist film decreases from 94.66 ppm / K to -4.87 ppm / K. This demonstrates that introducing the intercalation layer significantly improves the thermal stability of the monolayer buried resist film, and the TCR is lowest at a nickel-phosphorus-chromium-silicon-carbon thickness ratio of 1:1, reaching -4.87 ppm / K.

[0077] When the film thickness ratio is 30:30 (nm), the temperature coefficient changes from -188.41ppm / K before annealing to -4.87ppm / K after annealing at 500℃, which is 38 times lower and the thermal stability is significantly improved. When the film thickness ratio of chromium silicon carbon and nickel phosphorus is 1:1, after annealing at 500℃, a new alloy layer is generated at the interface of the double-layer resistor, and the internal grain growth changes, so that its TCR can reach the optimal state.

[0078] The above experimental data fully demonstrate that adding appropriate materials to the lower layer of chromium-silicon-carbon resistive layer material helps to promote the stability of the electrical performance of embedded thin film resistive material, maintains stable electrical performance in a wide temperature range (-55~125℃), and has a wide range of applications.

[0079] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A buried resistive thin film material with an extremely low temperature coefficient of resistance, characterized in that, The material comprises a substrate, a resistive layer, and an insertion layer, wherein the insertion layer is disposed between the substrate and the resistive layer; The resistive layer is made of CrSiC alloy, which, by atomic percentage, consists of 25% chromium, 50% silicon, and 25% carbon. The material of the insertion layer is a NiP alloy, which, by atomic percentage, consists of 70% nickel and 30% phosphorus.

2. The embedded resistive thin film material with extremely low temperature coefficient of resistance according to claim 1, characterized in that, in, The substrate was set as Al2O3.

3. The embedded resistive thin film material with extremely low temperature coefficient of resistance according to claim 1, characterized in that, In terms of thickness, the total film thickness of the embedded resistor material with extremely low temperature coefficient of resistance is 60~180 nanometers, of which the thickness of the resistor layer is 30~150 nanometers and the thickness of the insertion layer is 2~30 nanometers.

4. The embedded resistive thin film material with extremely low temperature coefficient of resistance according to claim 1, characterized in that, The substrate is one or more of a ceramic substrate, a metal substrate, or a silicon substrate.

5. A method for preparing an embedded resistive thin film material with an extremely low temperature coefficient of resistance as described in any one of claims 1-4, characterized in that, The method includes the following steps: Step 1: Select and install the sputtering target corresponding to the resistive layer material and the insertion layer material. Step 2: Select a substrate. Step 3: Using photolithography, a resistor pattern is fabricated on the substrate. Step 4: The substrate with the resistance pattern is fed into the sputtering chamber while maintaining a vacuum in the chamber. The sputtering operation is performed at a pressure on the order of 10⁻⁵ Pa. Step 5: Introduce argon gas and adjust the gas flow meter and the vent valve to maintain the cavity pressure at approximately 0.9 Pa. Step 6: Begin film deposition. Sputtering is performed using a target corresponding to the intercalation layer material to deposit the film on the selected substrate. Sputtering is also performed using a target corresponding to the resistive layer material to deposit the film on the intercalation layer. The thickness of each deposited layer in the film is adjusted by sputtering time or sputtering power. The sputtering power for chromium silicon carbon is 10~50W, and the sputtering time is 7~36 minutes. The sputtering power for nickel phosphorus is 10~50W, and the sputtering time is 7 minutes and 30 seconds. The chromium silicon carbon-nickel phosphorus bilayer structure film consists of a 2~30 nm nickel phosphorus film as the intercalation layer film and a 30~150 nm chromium silicon carbon film as the top layer film.

6. The method for preparing an embedded resistive thin film material with an extremely low temperature coefficient of resistance according to claim 5, characterized in that, When performing sputtering deposition steps on resistive layer materials and insert layer materials using sputtering, the sputtering power of the target material corresponding to the resistive layer is 50W, and the sputtering power of the target material corresponding to the insert layer is 50W.

7. The method for preparing an embedded resistive thin film material with an extremely low temperature coefficient of resistance according to claim 6, characterized in that, After forming a resistive layer-intercalation layer structure thin film on the substrate by sputtering, the obtained thin film needs to be subjected to high-temperature annealing. The high-temperature annealing process is carried out in a high vacuum environment or a protective gas atmosphere, specifically at a temperature of 200℃~500℃ for 30 minutes; the protective gas is argon, nitrogen or helium.

8. The method for preparing an embedded resistive thin film material with an extremely low temperature coefficient of resistance according to claim 7, characterized in that, In the step of forming a resistive layer-intercalation layer structure thin film on a substrate by sputtering, the substrate is kept at room temperature during the sputtering process.

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