Capacitor element, circuit board comprising capacitor element and manufacturing method of capacitor element
Through the intermediate electrodes with a sparse structure in the internal buried capacitance element, the problem of insufficient electricity capacity of the existing capacitance component is solved, and the capacitance value is improved and the line sheet is thin, which meets the high density and highization and high level Demand of functional circuit.
Patent Information
- Application Number
- CN202310921633.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-26
- Publication Date
- 2025-01-28
AI Technical Summary
The capacitance of existing embedded capacitor components is not high enough, making it difficult to meet the requirements of high-functional and high-density circuits in a limited space.
A capacitor element containing the intermediate electrode is designed. The intermediate electrode is composed of the tablet and the protruding part. The prominent part extends from the sides of the tablet to form a sparse structure to increase the capacitance value. Reduce the distance between the electrodes, and the thin line carrier.
By increasing the capacitor value of the intermediate electrode, the total electrical capacity of the line load is increased, while reducing the distance between the electrodes, the thinning of the line carrier board, and meeting the high -density and high -function circuit demand.
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Figure CN119381164A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a circuit carrier structure, and in particular to a circuit carrier structure with capacitors. Background Art
[0002] As the demand for electronic products moves towards high functionality, high-speed signal transmission, and high-density circuit components, the functions of integrated circuit chips are becoming more powerful, and the number of passive components used in consumer electronic products is also increasing rapidly. Embedded capacitor components are one of the important components that cannot be missing in circuit board design. In response to the development of high-density circuit components, how to manufacture embedded capacitor components with higher capacitance in a limited space is a problem that needs to be solved in this technical field. Summary of the invention
[0003] In view of the above problems, the present invention provides a circuit board including a capacitor element, which helps to solve the problem that the capacitance of the existing embedded capacitor element is not high enough. The present invention also provides a method for manufacturing the capacitor element of the circuit board.
[0004] The circuit board disclosed in the present invention comprises at least one circuit layer and a capacitor element. The capacitor element is arranged in at least one dielectric layer of the circuit layer. The capacitor element comprises a lower electrode, an intermediate electrode and an upper electrode. The intermediate electrode is between the lower electrode and the upper electrode. The intermediate electrode comprises a flat plate portion, at least one first protrusion portion and at least one second protrusion portion. The first protrusion portion and the second protrusion portion extend from opposite sides of the flat plate portion respectively.
[0005] In the circuit board, the lower electrode may include a flat plate portion and at least one protrusion. The protrusion of the lower electrode extends from the flat plate portion toward the flat plate portion of the middle electrode, and the protrusion of the lower electrode is arranged parallel to the first protrusion of the middle electrode.
[0006] In the aforementioned circuit carrier, in the length direction of the circuit carrier, the protrusion of the lower electrode may overlap with the first protrusion of the middle electrode.
[0007] In the circuit board, the upper electrode may include a flat plate portion and at least one protrusion. The protrusion of the upper electrode extends from the flat plate portion toward the flat plate portion of the middle electrode, and the protrusion of the upper electrode is arranged parallel to the second protrusion of the middle electrode.
[0008] In the aforementioned circuit carrier, in the length direction of the circuit carrier, the protrusion of the upper electrode may overlap with the second protrusion of the middle electrode.
[0009] In the aforementioned circuit carrier, the first protrusion and the second protrusion of the middle electrode may be symmetrical with respect to the plate portion thereof.
[0010] In the aforementioned circuit carrier, in the thickness direction of the circuit carrier, the first protrusion and the second protrusion of the intermediate electrode may completely overlap.
[0011] In the circuit board, the capacitor element may further include a first dielectric interlayer and a second dielectric interlayer. The first dielectric interlayer is between the lower electrode and the middle electrode, and the second dielectric interlayer is between the middle electrode and the upper electrode. The materials of the first dielectric interlayer and the second dielectric interlayer are different from the material of the dielectric layer.
[0012] In the aforementioned circuit carrier, the lower electrode, the middle electrode and the upper electrode may all be comb-shaped electrodes.
[0013] The present invention also discloses a capacitor element of a circuit board including a lower electrode, a middle electrode and an upper electrode. The middle electrode is between the lower electrode and the upper electrode. The middle electrode includes a flat plate portion, at least one first protrusion portion and at least one second protrusion portion, and the first protrusion portion and the second protrusion portion extend from opposite sides of the flat plate portion, respectively. The first protrusion portion and the second protrusion portion are symmetrical with respect to the flat plate portion of the middle electrode.
[0014] The present invention further discloses a method for manufacturing a circuit carrier, which includes the following steps: forming a lower electrode and a first dielectric interlayer on a core board, wherein the lower electrode is located below the first dielectric interlayer; forming a first dielectric layer on the core board, wherein the first dielectric layer exposes the first dielectric interlayer; forming an intermediate electrode on the first dielectric interlayer, wherein the intermediate electrode includes a flat plate portion, at least one first protrusion portion and at least one second protrusion portion, and the first protrusion portion and the second protrusion portion extend from opposite sides of the flat plate portion respectively; forming a second dielectric interlayer on the intermediate electrode; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer exposes the second dielectric interlayer; and forming an upper electrode on the second dielectric interlayer.
[0015] In the aforementioned manufacturing method, forming the lower electrode and the first dielectric interlayer on the core substrate may include the following steps: forming a metal layer on the core substrate; forming the first dielectric interlayer on the metal layer; and removing part of the metal layer to form the lower electrode.
[0016] In the aforementioned manufacturing method, forming a metal layer on the core substrate may include processing the metal layer by photolithography and plating.
[0017] In the aforementioned manufacturing method, a metal layer is formed in the circuit area and the capacitor area of the circuit carrier, and forming a first dielectric interlayer on the metal layer may include the following steps: forming a dielectric material layer on the metal layer, the dielectric material layer spreads over the circuit area and the capacitor area; completely removing the dielectric material layer in the circuit area; and patterning the dielectric material layer in the capacitor area to form a first dielectric interlayer.
[0018] In the aforementioned manufacturing method, forming the middle electrode on the first dielectric interlayer may include the following steps: forming a metal layer on the first dielectric interlayer; reducing the thickness of the metal layer to form a flat plate portion and a first protrusion of the middle electrode; and forming a second protrusion of the middle electrode on the flat plate portion.
[0019] In the aforementioned manufacturing method, the circuit carrier has a circuit area and a capacitor area, and forming a second dielectric interlayer on the middle electrode may include the following steps: forming a dielectric material layer on the first dielectric layer to cover the middle electrode, and the dielectric material layer spreads throughout the circuit area and the capacitor area; completely removing the dielectric material layer in the circuit area; and patterning the dielectric material layer in the capacitor area to form a second dielectric interlayer.
[0020] In the aforementioned manufacturing method, forming the upper electrode on the second dielectric interlayer may include the following steps: forming a metal layer on the second dielectric interlayer; and reducing the thickness of the metal layer to form the upper electrode.
[0021] According to the capacitor element, circuit board and manufacturing method thereof disclosed in the present invention, the capacitor element includes a lower electrode, an intermediate electrode and an upper electrode, and the intermediate electrode includes a first protrusion extending from a flat plate portion toward the lower electrode and a second protrusion extending toward the upper electrode. Thus, the intermediate electrode with a sparse structure helps to increase the capacitance between the intermediate electrode and the lower electrode and the upper electrode at the same time. In addition, the intermediate electrode with a protrusion can allow the distance between the intermediate electrode and the lower / upper electrode to be reduced while providing the required capacitance value, thereby facilitating the thinning of the circuit board.
[0022] In some embodiments, the first protrusion and the second protrusion of the middle electrode are symmetrical with respect to the flat plate portion, which is beneficial for providing a better capacitance enhancement effect and reducing the process cost.
[0023] The above description of the content of the present invention and the following description of the embodiments are used to demonstrate and explain the principles of the present invention and to provide further explanation of the claims of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 FIG. 4 is a schematic diagram of a circuit carrier according to an embodiment of the present invention.
[0025] Figures 2 to 5 To form Figure 1 Schematic diagram of the first circuit, the lower electrode and the first dielectric interlayer of the circuit carrier.
[0026] Figure 6 and Figure 7 To form Figure 1 Schematic diagram of the first dielectric layer of a circuit carrier.
[0027] Figures 8 to 10 To form Figure 1 Schematic diagram of a first conductive blind hole, a second circuit and a middle electrode of a circuit carrier.
[0028] Fig.11 and Fig.12 To form Figure 1 Schematic diagram of the second dielectric interlayer of the circuit carrier.
[0029] Fig.13 To form Figure 1 Schematic diagram of the second dielectric layer of the circuit carrier.
[0030] Fig.14 and Fig.15 To form Figure 1 Schematic diagram of the upper electrode of the circuit carrier.
[0031] Fig.16 FIG. 4 is a schematic diagram of a circuit carrier according to another embodiment of the present invention. DETAILED DESCRIPTION
[0032] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient for those skilled in the art to understand the technical content of the present invention and implement it accordingly. According to the contents disclosed in this specification, the claims and the drawings, any person skilled in the art can easily understand the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any viewpoint.
[0033] Please refer to Figure 1 , is a schematic diagram of a circuit board according to an embodiment of the present invention. In this embodiment, the circuit board 1A includes a core board 10, a circuit layer 20, a circuit layer 20' and a capacitor element 30. The core board 10 can be, for example, an electrically insulating substrate made of glass fiber and epoxy resin. Figure 1 Two circuit layers 20, 20" stacked in sequence are shown as an example, but the number of circuit layers is not intended to limit the present invention.
[0034] The circuit layer 20 may include a first dielectric layer 210, a first circuit 220, and a first conductive blind via 230. The circuit layer 20" may include a second dielectric layer 210", a second circuit 220" and a second conductive blind via 230". The first dielectric layer 210 and the second dielectric layer 210" may each be a dielectric layer made of a composite material of bakelite, glass fiber, epoxy resin, polyimide or other organic polymer materials and filler materials.
[0035] The circuit layers 20 and 20 ″ provided in this embodiment are merely examples, and thus the present invention is not limited to the specific structures of the circuit layers 20 and 20 ″. In some other embodiments, the circuit layer may include a conductive through hole and an additional circuit layer connected thereto.
[0036] The capacitor element 30 is disposed in the first dielectric layer 210 and the second dielectric layer 210″. The capacitor element 30 can be, for example, an embedded capacitor element, which includes a lower electrode 310, an intermediate electrode 320 and an upper electrode 330, and the intermediate electrode 320 is between the lower electrode 310 and the upper electrode 330. The lower electrode 310 can include a connected flat portion 311 and a plurality of protrusions 312, and the number of the protrusions 312 is not intended to limit the present invention.
[0037] The middle electrode 320 includes a flat plate portion 321, a plurality of first protrusions 322, and a plurality of second protrusions 323, and the number of the first protrusions 322 and the second protrusions 323 is not intended to limit the present invention. The first protrusions 322 and the second protrusions 323 extend from opposite sides of the flat plate portion 321, respectively, and the protrusions 312 of the lower electrode 310 extend toward the flat plate portion 321 of the middle electrode 320.
[0038] The upper electrode 330 may include a connected flat portion 331 and a plurality of protrusions 332, and the number of the protrusions 332 is not intended to limit the present invention. The protrusions 332 of the upper electrode 330 extend toward the flat portion 321 of the middle electrode 320. In addition, the first protrusion 322 of the middle electrode 320 extends from the flat portion 321 toward the flat portion 311 of the lower electrode 310, and the second protrusion 323 extends from the flat portion 321 toward the flat portion of the upper electrode 330.
[0039] In the present embodiment, the protrusion 312 of the lower electrode 310 is arranged in parallel with the first protrusion 322 of the middle electrode 320. More specifically, in the length direction D1 of the circuit board 1A, the protrusion 312 of the lower electrode 310 overlaps with the first protrusion 322 of the middle electrode 320. In addition, the protrusion 332 of the upper electrode 330 is arranged in parallel with the second protrusion 323 of the middle electrode 320. More specifically, in the length direction D1 of the circuit board 1A, the protrusion 332 of the upper electrode 330 overlaps with the second protrusion 323 of the middle electrode 320. The length direction D1 of the circuit board 1A is relatively orthogonal to the build-up direction D0 in which the lower electrode 310, the middle electrode 320 and the upper electrode 330 are sequentially arranged.
[0040] In this embodiment, the lower electrode 310, the middle electrode 320 and the upper electrode 330 may all be comb-shaped electrodes. The protrusion 312 of the lower electrode 310 and the first protrusion 322 of the middle electrode 320 are spaced apart from each other at a fixed interval and arranged interlaced, so the lower electrode 310 and the middle electrode 320 can be equivalent to a flat plate capacitor. The protrusion 332 of the upper electrode 330 and the second protrusion 323 of the middle electrode 320 are spaced apart from each other at a fixed interval and arranged interlaced, so the upper electrode 330 and the middle electrode 320 can be equivalent to another flat plate capacitor. The two flat plate capacitors can be connected in parallel to obtain a higher equivalent capacitance.
[0041] In this embodiment, the first protrusion 322 and the second protrusion 323 of the middle electrode 320 are symmetrical with respect to the plate portion 321. More specifically, in the thickness direction (ie, build-up direction D0) of the circuit board 1A, the first protrusion 322 and the second protrusion 323 of the middle electrode 320 completely overlap.
[0042] In this embodiment, the capacitor element 30 may further include a first dielectric interlayer 340 and a second dielectric interlayer 350. The first dielectric interlayer 340 is disposed between the lower electrode 310 and the middle electrode 320, and the second dielectric interlayer 350 is disposed between the middle electrode 320 and the upper electrode 330. The materials of the first dielectric interlayer 340 and the second dielectric interlayer 350 may be different from the materials of the first dielectric layer 210 and the second dielectric layer 210". For example, the first dielectric interlayer 340 and the second dielectric interlayer 350 may be made of an epoxy-ceramic composite material having a high dielectric constant to increase the capacitance.
[0043] An exemplary method of manufacturing the circuit carrier 1A is described below. Figures 2 to 5 To form Figure 1 Schematic diagram of the first circuit, the lower electrode and the first dielectric interlayer of the circuit carrier. Figure 2 As shown, a core board 10 is provided, and a metal layer 40 is formed on the core board 10. Specifically, the metal layer 40 can be formed by photolithography and plating processes, so that the shape of the metal layer 40 meets the shape of the subsequent Figure 5 The shapes of the first circuit 220 and the lower electrode 310 are shown. The plating process may be a chemical plating process or an electroplating process.
[0044] Then, if Figure 3 and Figure 4 As shown, a first dielectric interlayer 340 is formed on the metal layer 40. Specifically, the circuit substrate 1A can be defined into a circuit region R1 and a capacitor region R2 that do not overlap each other, and the metal layer 40 is formed in the circuit region R1 and the capacitor region R2. Figure 1The circuit layer 20 in the circuit area R1 will be subsequently formed in the circuit area R1, and the capacitor element 30 will be subsequently formed in the capacitor area R2. A dielectric material layer 50 is formed on the metal layer 40 to cover the circuit area R1 and the capacitor area R2. In the circuit area R1, the dielectric material layer 50 is completely removed so that the metal layer 40 in the circuit area R1 is completely exposed. In the capacitor area R2, the dielectric material layer 50 is patterned to form a first dielectric interlayer 340. The formation of the dielectric material layer 50 can be implemented, for example, by physical vapor deposition (PVD) or inkjet printing (Ink-jet Printing) or vacuum lamination (Vacuum Lamination). The removal or patterning of the dielectric material layer 50 can be implemented, for example, by a photolithography process and / or a dry etching process.
[0045] Then, if Figure 5 As shown, a portion of the metal layer 40 is removed to form the first circuit 220 and the lower electrode 310, and the lower electrode 310 in the capacitor region R2 is located below the first dielectric interlayer 340. The removal of the metal layer 40 can be performed by dry etching and / or wet etching, for example.
[0046] Figure 6 and Figure 7 To form Figure 1 Schematic diagram of the first dielectric layer of the circuit carrier of the present invention. The first dielectric layer 210 of the circuit layer 20 is formed on the core board 10, and the first dielectric layer 210 exposes the first dielectric interlayer 340 and at least a portion of the first circuit 220. In detail, the first dielectric layer 210 is first formed on the core board 10, which covers the first circuit 220, the lower electrode 310 and the first dielectric interlayer 340. In the circuit area R1, part of the first dielectric layer 210 is removed to expose a portion of the upper surface of the first circuit 220. In the capacitor area R2, part of the first dielectric layer 210 is removed to expose the entire upper surface of the first dielectric interlayer 340. The formation of the first dielectric layer 210 can be implemented, for example, by physical vapor deposition. The removal of the first dielectric layer 210 can be implemented, for example, by a photolithography process and / or a dry etching process.
[0047] Figures 8 to 10 To form Figure 1 Schematic diagram of the first conductive blind hole, the second circuit and the middle electrode of the circuit carrier. Figure 8 As shown, a metal layer 60 is formed on the first circuit 220, the first dielectric layer 210 and the first dielectric interlayer 340. The metal layer 60 may be formed by, for example, a chemical plating process or an electroplating process.
[0048] Then, if Fig. 9As shown, the thickness of the metal layer 60 is reduced to form the first conductive blind via 230 of the circuit layer 20 and the flat plate portion 321 and the first protrusion 322 of the intermediate electrode 320. The first conductive blind via 230 is connected to the first circuit 220. The thickness reduction of the metal layer 60 can be implemented, for example, by chemical mechanical polishing (CMP).
[0049] Then, if Fig.10 As shown, in the circuit area R1, a second circuit 220" is formed on the first conductive blind hole 230 and the first dielectric layer 210. In the capacitor area R2, a second protrusion 323 of the intermediate electrode 320 is formed on the flat plate portion 321. The second circuit 220" and the second protrusion 323 can be formed by photolithography and plating processes. The plating process can be a chemical plating process or an electroplating process.
[0050] Fig.11 and Fig.12 To form Figure 1 Schematic diagram of the second dielectric interlayer of the circuit carrier. A dielectric material layer 70 is formed on the first dielectric layer 210 to cover the second circuit 220" and the intermediate electrode 320. In the circuit area R1, the dielectric material layer 70 is completely removed so that the second circuit 220" is completely exposed. In the capacitor area R2, the dielectric material layer 70 is patterned to form a second dielectric interlayer 350. The formation of the dielectric material layer 70 can be implemented, for example, by physical vapor deposition (PVD) or inkjet printing (Ink-jet Printing) or vacuum lamination (Vacuum Lamination). Removal or patterning of the dielectric material layer 70 can be implemented, for example, by a photolithography process and / or a dry etching process.
[0051] Fig.13 To form Figure 1 Schematic diagram of the second dielectric layer of the circuit carrier. A second dielectric layer 210" of the circuit layer 20" is formed on the first dielectric layer 210, and the second dielectric layer 210" exposes the second dielectric interlayer 350 and at least a portion of the second circuit 220". In detail, the second dielectric layer 210" is first formed on the first dielectric layer 210 to cover the second circuit 220" and the second dielectric interlayer 350. In the circuit region R1, part of the second dielectric layer 210" is removed to expose a portion of the upper surface of the second circuit 220". In the capacitor region R2, part of the second dielectric layer 210" is removed to expose the entire upper surface of the second dielectric interlayer 350. The formation of the second dielectric layer 210" can be implemented, for example, by physical vapor deposition. The removal of the second dielectric layer 210" can be implemented, for example, by a photolithography process and / or a dry etching process.
[0052] Fig.14 and Fig.15 To form Figure 1 Schematic diagram of the upper electrode of the circuit board. Fig.14 As shown, a metal layer 80 is formed on the second circuit 220 ″, the second dielectric layer 210 ″ and the second dielectric interlayer 350. The metal layer 80 can be formed by, for example, a chemical plating process or an electroplating process. Fig.15 As shown, the thickness of the metal layer 80 is reduced to form a second conductive blind via 230" and an upper electrode 330 of the circuit layer 20". The second conductive blind via 230" is connected to the second circuit 220". The thickness reduction of the metal layer 80 can be implemented, for example, by chemical mechanical polishing. A signal transmission circuit (not shown separately) can be additionally formed on the second conductive blind via 230".
[0053] The capacitor element of the present invention is not limited to the structure of three-layer electrodes. Fig.16 FIG. 1 is a schematic diagram of a circuit board according to another embodiment of the present invention. Figure 1 The circuit carrier 1A is similar to the circuit carrier 1B, with the main difference being that the capacitor element 30 of the circuit carrier 1B includes a plurality of middle electrodes 320.
[0054] In summary, according to the capacitor element, circuit board and manufacturing method thereof disclosed in the present invention, the capacitor element includes a lower electrode, an intermediate electrode and an upper electrode, and the intermediate electrode includes a first protrusion extending from a flat plate portion toward the lower electrode and a second protrusion extending toward the upper electrode. Thus, the intermediate electrode with a sparse structure helps to increase the capacitance between the intermediate electrode and the lower electrode and the upper electrode at the same time. In addition, the intermediate electrode with a protrusion can allow the distance between the intermediate electrode and the lower / upper electrode to be reduced while providing the required capacitance value, thereby facilitating the thinning of the circuit board.
[0055] In some embodiments, the first protrusion and the second protrusion of the middle electrode are symmetrical with respect to the flat plate portion, which is beneficial for providing a better capacitance enhancement effect and reducing the process cost.
[0056]
Explanation of symbols
[0057] 1A, 1B: Circuit board
[0058] 10: Core board
[0059] 20, 20”: Circuit layer
[0060] 210: First dielectric layer
[0061] 220: First Line
[0062] 230: First conductive blind hole
[0063] 210”: Second dielectric layer
[0064] 220”: Second Line
[0065] 230”: Second conductive blind via
[0066] 30: Capacitor element
[0067] 310: Lower electrode
[0068] 311: Flat panel
[0069] 312: Protrusion
[0070] 320: Intermediate electrode
[0071] 321: Flat Panel
[0072] 322: First protrusion
[0073] 323: Second protrusion
[0074] 330: Upper electrode
[0075] 331: Flat panel
[0076] 332: Protrusion
[0077] 340: First dielectric interlayer
[0078] 350: Second dielectric interlayer
[0079] 40: Metal layer
[0080] 50, 70: Dielectric material layer
[0081] 60, 80: Metal layer
[0082] D0: Layer-adding direction
[0083] D1: Length direction
[0084] R1: Line area
[0085] R2: Capacitor area.
Claims
1. A circuit carrier, characterized in that: Include: at least one circuit layer; and A capacitor element is disposed in at least one dielectric layer of the at least one circuit layer; The capacitor element includes a lower electrode, an intermediate electrode and an upper electrode, wherein the intermediate electrode is located between the lower electrode and the upper electrode, and the intermediate electrode includes a flat plate portion, at least one first protrusion portion and at least one second protrusion portion, wherein the at least one first protrusion portion and the at least one second protrusion portion extend from opposite sides of the flat plate portion respectively.
2. The circuit carrier according to claim 1, wherein the lower electrode comprises a flat portion and at least one protrusion, the at least one protrusion of the lower electrode extends from the flat portion of the lower electrode toward the flat portion of the middle electrode, and the at least one protrusion of the lower electrode is arranged parallel to the at least one first protrusion of the middle electrode. 3 . The circuit carrier according to claim 2 , wherein in a length direction of the circuit carrier, the at least one protrusion of the lower electrode overlaps with the at least one first protrusion of the middle electrode.
4. The circuit carrier according to claim 1, wherein the upper electrode comprises a flat portion and at least one protrusion, the at least one protrusion of the upper electrode extends from the flat portion of the upper electrode toward the flat portion of the middle electrode, and the at least one protrusion of the upper electrode is arranged parallel to the at least one second protrusion of the middle electrode. 5 . The circuit carrier according to claim 4 , wherein in a length direction of the circuit carrier, the at least one protrusion of the upper electrode overlaps with the at least one second protrusion of the middle electrode. 6 . The circuit carrier according to claim 1 , wherein the at least one first protrusion and the at least one second protrusion of the middle electrode are symmetrical with respect to the flat plate portion of the middle electrode. 7 . The circuit carrier according to claim 1 , wherein in a thickness direction of the circuit carrier, the at least one first protrusion of the middle electrode completely overlaps with the at least one second protrusion.
8. The circuit carrier according to claim 1, wherein the capacitor element further comprises a first dielectric interlayer and a second dielectric interlayer, the first dielectric interlayer is between the lower electrode and the middle electrode, the second dielectric interlayer is between the middle electrode and the upper electrode, and the material of the first dielectric interlayer and the second dielectric interlayer is different from the material of the at least one dielectric layer. 9 . The circuit carrier according to claim 1 , wherein the lower electrode, the middle electrode and the upper electrode are all comb-shaped electrodes.
10. A capacitor element for a circuit board, characterized in that: Include: A lower electrode, an intermediate electrode and an upper electrode, wherein the intermediate electrode is disposed between the lower electrode and the upper electrode, the intermediate electrode comprises a flat plate portion, at least one first protrusion portion and at least one second protrusion portion, and the at least one first protrusion portion and the at least one second protrusion portion extend from opposite sides of the flat plate portion respectively; The at least one first protrusion and the at least one second protrusion are symmetrical to each other relative to the flat plate portion of the middle electrode.
11. A method for manufacturing a capacitor element of a circuit carrier, characterized in that: Include: forming a lower electrode and a first dielectric interlayer on the core plate, wherein the lower electrode is located below the first dielectric interlayer; forming a first dielectric layer on the core board, wherein the first dielectric layer exposes the first dielectric interlayer; forming an intermediate electrode on the first dielectric interlayer, wherein the intermediate electrode comprises a flat plate portion, at least one first protrusion portion and at least one second protrusion portion, wherein the at least one first protrusion portion and the at least one second protrusion portion extend from opposite sides of the flat plate portion respectively; forming a second dielectric interlayer on the middle electrode; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer exposes the second dielectric interlayer; and A top electrode is formed on the second dielectric interlayer.
12. The method for manufacturing a capacitor element of a circuit board according to claim 11, wherein forming the lower electrode and the first dielectric interlayer on the core board comprises: forming a metal layer on the core board; forming the first dielectric interlayer on the metal layer; and A portion of the metal layer is removed to form the bottom electrode. 13 . The method for manufacturing a capacitor element of a circuit carrier as claimed in claim 12 , wherein forming the metal layer on the core board comprises processing the metal layer by photolithography and plating.
14. The method for manufacturing a capacitor element of a circuit carrier according to claim 12, wherein the metal layer is formed in the circuit region and the capacitor region of the circuit carrier, and the forming of the first dielectric interlayer on the metal layer comprises: Forming a dielectric material layer on the metal layer, wherein the dielectric material layer covers the circuit area and the capacitor area; Completely removing the dielectric material layer in the circuit area; and The dielectric material layer in the capacitor region is patterned to form the first dielectric interlayer.
15. The method for manufacturing a capacitor element of a circuit board according to claim 11, wherein forming the middle electrode on the first dielectric interlayer comprises: forming a metal layer on the first dielectric interlayer; reducing the thickness of the metal layer to form the plate portion and the at least one first protrusion of the intermediate electrode; and The at least one second protrusion of the intermediate electrode is formed on the flat plate portion.
16. The method for manufacturing a capacitor element of a circuit carrier according to claim 11, wherein the circuit carrier has a circuit region and a capacitor region, and the forming of the second dielectric interlayer on the middle electrode comprises: Forming a dielectric material layer on the first dielectric layer to cover the middle electrode, wherein the dielectric material layer is spread over the circuit area and the capacitor area; Completely removing the dielectric material layer in the circuit area; and The dielectric material layer in the capacitor region is patterned to form the second dielectric interlayer.
17. The method for manufacturing a capacitor element of a circuit board according to claim 11, wherein forming the upper electrode on the second dielectric interlayer comprises: forming a metal layer on the second dielectric interlayer; and The thickness of the metal layer is reduced to form the upper electrode.