Compensation structure, semiconductor structure and preparation method thereof

Abstract

The invention provides a compensation structure, a semiconductor structure and a preparation method thereof, and the method comprises the steps: a first gate region of a metal gate fills a gap of a pattern dense region of a gate oxide layer, a second gate region is located at one side, away from the pattern dense region, of an isolation region, and a third gate region covers the upper surfaces of the gate oxide layer, the first gate region and the second gate region; photoresist is arranged on the metal gate for exposure, development and etching, a graphical compensation region is formed in the position, corresponding to the isolation region and the second gate region, of the third gate region, the compensation region is filled with a filling layer, and the metal gate is ground to expose the gate oxide layer. According to the invention, the compensation area is arranged on the metal gate, so that a load effect and a dish-shaped recess caused by grinding are avoided; meanwhile, over-etching is avoided by controlling the time of etching the metal gate, and the structural yield is guaranteed; in addition, the hard mask layer is arranged on the metal gate, so that the over-etching of the metal gate is avoided, the process steps for controlling the etching time are reduced, and the process efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a compensation structure, a semiconductor structure and a preparation method thereof. Background Art

[0002] In semiconductor technology, chemical reaction and mechanical grinding are combined to planarize the surface of thin films.

[0003] However, during the flattening process, the grinding rate for areas with high pattern density is slower, while the grinding rate for the entire area without patterns is faster. This phenomenon is called the Loading Effect, which will cause the overall plane obtained after grinding to have uneven grinding surface height in areas with different pattern densities. In addition, in the entire area without patterns, the grinding rate at the edge position will be slower than that at the center position, so after grinding, a Dishing (dish-shaped depression) with a thin middle and thick edges will be produced.

[0004] In the prior art, the metal gate is generally planarized only by CMP (Chemical Mechanical Polishing), and the process stops when the metal gate is planarized to a preset height. The metal gate includes a patterned area and a whole non-patterned area. Due to the influence of Loading Effect and Dishing, the height of the non-patterned area may be lower than the preset height, and the center area may be lower than the edge area. In severe cases, the metal gate in the center area may be polished to expose the active area below, which may affect areas such as I / O (input / output port), large sensor areas or gate resistance areas, resulting in too low yield. At the same time, since the metal gate is usually made of aluminum, which is relatively soft, the Loading Effect and Dishing are more serious, especially in large-sized metal gates.

[0005] In the prior art, the influence of dishing is solved by using a test piece. However, it is impossible to set a test piece in a location such as an I / O (input / output port) area, a sensor large area or a gate resistor area to solve this problem.

[0006] Therefore, a process method that can achieve uniform surface grinding is urgently needed for grinding areas such as I / O (input / output) areas, sensor areas, or gate resistor areas where test pieces cannot be set.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0008] In view of the above shortcomings of the prior art, an object of the present invention is to provide a compensating structure, a semiconductor structure and a preparation method thereof, which are used to solve the problems of load effect and dishing caused by planarizing the metal gate in the I / O area, sensor area or gate resistance area in the prior art.

[0009] To achieve the above object, the present invention provides a method for preparing a semiconductor structure, the method comprising:

[0010] A semiconductor structure is provided, the semiconductor structure comprising an active area, a gate oxide layer and a metal gate, the gate oxide layer being arranged on the active area; the gate oxide layer comprising a pattern-intensive area and an isolation area, the pattern-intensive area being a densely patterned gate oxide material, the isolation area being a whole block of gate oxide material for isolation; the metal gate comprising a first gate area, a second gate area and a third gate area, the first gate area filling a gap in the pattern-intensive area, the second gate area being adjacent to a side of the isolation area away from the pattern-intensive area, and the third gate area covering the upper surfaces of the gate oxide layer, the first gate area and the second gate area;

[0011] Disposing a photoresist on the metal gate, and disposing a photolithography mask on the photoresist for exposure, wherein the photolithography mask is provided with a patterned structure at a position corresponding to the isolation area and above the second gate area to allow exposure light to pass through;

[0012] Developing the photoresist so that the exposed positions of the photoresist corresponding to the isolation region and the second gate region are removed, thereby exposing a portion of the metal gate;

[0013] Etching the exposed metal gate so that the third gate region of the metal gate corresponding to the isolation region and the second gate region forms a patterned compensation region corresponding to the pattern-intensive region, and removing the photoresist;

[0014] Filling a filling layer in the patterned compensation area in the metal gate;

[0015] The metal gate is ground until the gate oxide layer is exposed.

[0016] Optionally, when etching the exposed metal gate, the time for etching the metal gate is set to a preset time, so that the bottom of the formed compensation area is not lower than the top of the gate oxide layer.

[0017] The present invention also provides a method for preparing a semiconductor structure, the method comprising:

[0018] A semiconductor structure is provided, the semiconductor structure comprising an active area, a gate oxide layer and a metal gate, the gate oxide layer being arranged on the active area; the gate oxide layer comprising a pattern-intensive area and an isolation area, the pattern-intensive area being a densely patterned gate oxide material, the isolation area being a whole block of gate oxide material for isolation; the metal gate comprising a first gate area, a second gate area and a third gate area, the first gate area filling a gap in the pattern-intensive area, the second gate area being adjacent to a side of the isolation area away from the pattern-intensive area, and the third gate area covering the upper surfaces of the gate oxide layer, the first gate area and the second gate area;

[0019] A hard mask layer is arranged on the metal gate, a photoresist is arranged on the hard mask layer, a photolithography mask is arranged on the photoresist for exposure, and the photolithography mask is provided with a patterned structure at a position corresponding to the isolation area and above the second gate area to allow exposure light to pass through;

[0020] Developing the photoresist so that the positions of the photoresist corresponding to the isolation region and the exposure above the second gate region are removed, exposing a portion of the hard mask layer;

[0021] Etching the exposed hard mask layer to form a patterned compensation area corresponding to the pattern-intensive area in the hard mask layer in the area corresponding to the isolation area and the second gate area, and removing the photoresist;

[0022] Filling a filling layer in the patterned compensation area in the hard mask layer;

[0023] The hard mask layer and the metal gate are ground until the gate oxide layer is exposed.

[0024] Optionally, a length of the compensation region in a direction perpendicular to the surface of the active region is equal to a length of the gate oxide layer in a direction perpendicular to the surface of the active region.

[0025] Optionally, the metal grid is made of aluminum.

[0026] Optionally, the length of the metal gate in the first direction and the second direction are both greater than 0.25 micrometers, the first direction and the second direction are both parallel to the surface of the active area, and the first direction is perpendicular to the second direction.

[0027] Optionally, an etching selectivity ratio between the material of the hard mask layer and the material of the metal gate is not equal to 1.

[0028] The present invention also provides a compensation structure, which is used to carry out any of the preparation methods described above, wherein the compensation structure includes a patterned compensation area, and the area to be ground includes a patterned area and a non-patterned area, and the compensation area of ​​the compensation structure is arranged above the non-patterned area of ​​the area to be ground, so that the semiconductor structure provided with the compensation structure obtains a uniform ground surface after grinding.

[0029] The present invention further provides a semiconductor structure, wherein the semiconductor structure is prepared by using any one of the above-mentioned preparation methods, or the semiconductor structure is prepared by using the above-mentioned compensation structure.

[0030] As described above, the compensation structure, semiconductor structure and preparation method thereof of the present invention have the following beneficial effects:

[0031] The present invention sets a compensation area on the metal grid to avoid the etching load effect caused by grinding due to different pattern densities and the dish-shaped depression caused by different grinding rates at the edge and center of a large area without patterns.

[0032] The present invention avoids over-etching by controlling the time of etching the metal gate, thereby ensuring the structural yield;

[0033] The present invention arranges a hard mask layer on the metal gate to avoid over-etching of the metal gate, reduce the process steps of controlling the etching time, and improve the process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of the semiconductor structure provided in step 1 in the first embodiment of the present invention.

[0035] Figure 2 It shows a schematic diagram of the structure presented by setting the photoresist exposure in step 2 in the first embodiment of the present invention.

[0036] Figure 3 It is a schematic diagram of the structure presented by the development and removal of the photoresist in step 3 in the first embodiment of the present invention.

[0037] Figure 4 It is a schematic diagram of the structure presented by forming the compensation area in step 4 in the first embodiment of the present invention.

[0038] Figure 5 It is a schematic diagram of the structure presented by filling the filling layer in step 5 in the first embodiment of the present invention.

[0039] Figure 6 It is a schematic diagram showing the structure of the metal grid polished in step 6 in the first embodiment of the present invention.

[0040] Figure 7The schematic diagram of a semiconductor structure showing a dish-shaped depression after the entire area is ground in the prior art.

[0041] Figure 8 It is a schematic structural diagram of the semiconductor structure provided in step 1 of the second embodiment of the present invention.

[0042] Fig. 9 It is a schematic diagram of the structure presented by setting the hard mask layer and photoresist exposure in step 2 in the second embodiment of the present invention.

[0043] Fig.10 It is a schematic diagram of the structure presented by the developed photoresist in step 3 in the second embodiment of the present invention.

[0044] Fig.11 It is a schematic diagram of the structure presented by forming the compensation area in step 4 in the second embodiment of the present invention.

[0045] Fig.12 It is a schematic diagram of the structure presented by filling the filling layer in step 5 in the second embodiment of the present invention.

[0046] Fig.13 It is a schematic diagram of the structure presented by grinding the hard mask layer and the metal gate in step 6 in the second embodiment of the present invention.

[0047] Fig.14 It is a schematic diagram of the compensation structure in the third embodiment of the present invention.

[0048] Component number description

[0049] 11. active area; 12. gate oxide layer; 121. pattern-intensive area; 122. isolation area; 13. metal gate; 131. first gate area;

[0050] 132, second grid area; 133, third grid area;

[0051] 21. Photoresist; 22. Photolithography mask; 23. Exposure light; 24. Filling layer; 25. Hard mask layer; 26. Compensation structure;

[0052] 261. Make up area;

[0053] 30. Disc-shaped depression. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0056] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0057] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0058] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0059] Embodiment 1:

[0060] like Figure 1-Figure 6 As shown, the present invention provides a method for preparing a semiconductor structure, the preparation method comprising:

[0061] Step 1: providing a semiconductor structure, the semiconductor structure comprising an active area 11, a gate oxide layer 12 and a metal gate 13, the gate oxide layer 12 being arranged on the active area 11; the gate oxide layer 12 comprising a pattern-intensive area 121 and an isolation area 122, the pattern-intensive area 121 being a densely patterned gate oxide material, the isolation area 122 being a whole block of gate oxide material for isolation; the metal gate 13 comprising a first gate area 131, a second gate area 132 and a third gate area 133, the first gate area 131 filling a gap in the pattern-intensive area 121, the second gate area 132 being adjacent to a side of the isolation area 122 away from the pattern-intensive area 121, and the third gate area 133 covering the upper surfaces of the gate oxide layer 12, the first gate area 131 and the second gate area 132;

[0062] Step 2: a photoresist 21 is disposed on the metal gate 13, and a photolithography mask 22 is disposed on the photoresist 21 for exposure, wherein the photolithography mask 22 is provided with a patterned structure at a position corresponding to the isolation region 122 and above the second gate region 132 to allow exposure light 23 to pass through;

[0063] Step 3: developing the photoresist 21 to remove the exposed positions of the photoresist 21 corresponding to the isolation region 122 and the second gate region 132 , thereby exposing a portion of the metal gate 13 ;

[0064] Step 4: etching the exposed metal gate 13 so that the third gate region 133 of the metal gate 13 corresponding to the isolation region 122 and the second gate region 132 forms a patterned compensation region 261 corresponding to the pattern-intensive region 121, and removing the photoresist 21;

[0065] Step 5: Filling the patterned compensation area 261 in the metal gate 13 with a filling layer 24;

[0066] Step 6: Grinding the metal gate 13 until the gate oxide layer 12 is exposed.

[0067] The method for preparing the semiconductor structure of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0068] First, if Figure 1 As shown, step 1 is performed to provide a semiconductor structure, wherein the semiconductor structure includes an active area 11, a gate oxide layer 12 and a metal gate 13, wherein the gate oxide layer 12 is disposed on the active area 11; the gate oxide layer 12 includes a pattern-intensive area 121 and an isolation area 122, wherein the pattern-intensive area 121 is a densely patterned gate oxide material, and the isolation area 122 is a whole block of gate oxide material used for isolation; the metal gate 13 includes a first gate area 131, a second gate area 132 and a third gate area 133, wherein the first gate area 131 fills the gap in the pattern-intensive area 121, the second gate area 132 is adjacent to a side of the isolation area 122 away from the pattern-intensive area 121, and the third gate area 133 covers the upper surfaces of the gate oxide layer 12, the first gate area 131 and the second gate area 132.

[0069] In one embodiment, the metal grid 13 is made of aluminum.

[0070] In one embodiment, the lengths of the metal gate 13 in the first direction and the second direction are both greater than 0.25 micrometers, the first direction and the second direction are both parallel to the surface of the active region 11 , and the first direction is perpendicular to the second direction.

[0071] Specifically, Figure 1 As shown, the first direction is the x-axis direction in the figure, the y-axis direction is the direction perpendicular to the surface of the active area 11, and the second direction is the direction perpendicular to the paper surface. Since it is a two-dimensional figure, the second direction is not shown in the figure.

[0072] Specifically, the isolation area 122 is a gate oxide material that has not been patterned, and the pattern-dense area 121 is a gate oxide material that has been patterned. Since the patterning density in the pattern-dense area 121 is higher than the patterning density of the isolation area 122 that has not been patterned, there is a problem that the grinding speed of the pattern-dense area 121 with a high patterning density in the gate oxide layer 12 is lower than the grinding speed of the isolation area 122 with a low patterning density. The method improvement of the present invention is a solution designed to this problem.

[0073] Then, if Figure 2 As shown, step 2 is performed, a photoresist 21 is set on the metal gate 13, and a photolithography mask 22 is set on the photoresist 21 for exposure. The photolithography mask 22 is provided with a graphical structure at a position corresponding to the isolation area 122 and above the second gate area 132 to allow the exposure light 23 to pass through.

[0074] Then, if Figure 3 As shown, step 3 is performed to develop the photoresist 21 so that the exposed positions of the photoresist 21 corresponding to the isolation region 122 and the second gate region 132 are removed, thereby exposing a portion of the metal gate 13 .

[0075] Then, if Figure 4 As shown, step 4 is performed to etch the exposed metal gate 13 so that the third gate region 133 of the metal gate 13 corresponding to the isolation region 122 and the second gate region 132 forms a patterned compensation area 261 corresponding to the pattern-intensive region 121, and the photoresist 21 is removed.

[0076] In one embodiment, in step 4, when etching the exposed metal gate 13 , the etching time of the metal gate 13 is set to a preset time, so that the bottom of the formed compensation area 261 is not lower than the top of the gate oxide layer 12 .

[0077] The present invention sets the etching time for the metal gate 13 to avoid over-etching the second gate region 132 during the process of forming the compensation region 261 to affect the original structure of the semiconductor structure, thereby ensuring the yield of the semiconductor structure.

[0078] In one embodiment, the pattern density of the patterned compensation area 261 is equal to the pattern density of the pattern-dense area 121 .

[0079] Specifically, the graphic dense area 121 is a gate oxide material arranged at intervals, and the number of gate oxide materials contained in a unit area of ​​the graphic dense area 121 is the graphic density of the graphic dense area 121; the compensation area 261 is a groove arranged at intervals, and the number of grooves contained in a unit area is the graphic density of the compensation area 261.

[0080] In one embodiment, the length of the compensation region 261 in the direction perpendicular to the surface of the active region 11 is equal to the length of the gate oxide layer 12 in the direction perpendicular to the surface of the active region 11 .

[0081] Then, if Figure 5 As shown, step 5 is performed to fill the patterned compensation area 261 in the metal gate 13 with a filling layer 24 .

[0082] In one embodiment, the material of the filling layer 24 is the same as that of the gate oxide layer 12 .

[0083] In the present invention, by setting the material of the filling layer 24 to be the same as the material of the gate oxide layer 12 , the polished surface obtained after polishing can be made more uniform.

[0084] Finally, if Figure 6 As shown, step 6 is performed to grind the metal gate 13 until the gate oxide layer 12 is exposed.

[0085] In the prior art, the polishing rate of semiconductor structures is lower in areas with higher pattern density, and higher in areas with lower pattern density or areas that are not patterned. This phenomenon is called loading effect, which is more obvious in large-scale structures. Figure 7As shown, in the whole area that has not been patterned, the grinding rate at the center position will be faster than that at the edge position, thereby forming a dishing (dish-shaped depression 30). In the process of flattening the metal gate 13, generally only chemical mechanical polishing is used, and the polishing is stopped when the gate height of the metal gate 13 is polished to a preset height. However, due to the above-mentioned loading effect and dishing, an uneven polishing surface will be produced in the whole area of ​​the metal gate 13 that has not been patterned. In addition, the material of the metal gate 13 is generally aluminum, which is softer, and part of the center area may be polished, which will have an impact on special circuit structures such as the I / O area, the sensor area or the gate resistor area, and even cause a lower yield rate. However, due to the large size of the special circuits such as the I / O area, the sensor area or the gate resistor area, the difference in the polishing surface cannot be eliminated by the commonly used dummy (control piece).

[0086] The present invention provides a compensation area 261 complementary to the patterned area of ​​the metal grid 13 before grinding, thereby adjusting the overall grinding rate and achieving a uniform grinding surface.

[0087] Embodiment 2:

[0088] like Figure 8-Figure 13 As shown, the present invention provides a method for preparing a semiconductor structure, the preparation method comprising:

[0089] Step 1: providing a semiconductor structure, the semiconductor structure comprising an active area 11, a gate oxide layer 12 and a metal gate 13, the gate oxide layer 12 being arranged on the active area 11; the gate oxide layer 12 comprising a pattern-intensive area 121 and an isolation area 122, the pattern-intensive area 121 being a densely patterned gate oxide material, the isolation area 122 being a whole block of gate oxide material for isolation; the metal gate 13 comprising a first gate area 131, a second gate area 132 and a third gate area 133, the first gate area 131 filling a gap in the pattern-intensive area 121, the second gate area 132 being adjacent to a side of the isolation area 122 away from the pattern-intensive area 121, and the third gate area 133 covering the upper surfaces of the gate oxide layer 12, the first gate area 131 and the second gate area 132;

[0090] Step 2: a hard mask layer 25 is disposed on the metal gate 13, a photoresist 21 is disposed on the hard mask layer 25, a photolithography mask 22 is disposed on the photoresist 21 for exposure, and the photolithography mask 22 is provided with a patterned structure at a position corresponding to the isolation region 122 and above the second gate region 132 to allow exposure light 23 to pass through;

[0091] Step 3: developing the photoresist 21 to remove the exposed positions of the photoresist 21 corresponding to the isolation region 122 and the second gate region 132 , thereby exposing a portion of the hard mask layer 25 ;

[0092] Step 4: etching the exposed hard mask layer 25 to form a patterned compensation area 261 corresponding to the pattern-intensive area 121 in the area corresponding to the isolation area 122 and the second gate area 132, and removing the photoresist 21;

[0093] Step 5: Filling the patterned compensation area 261 in the hard mask layer 25 with a filling layer 24;

[0094] Step 6: Grind the hard mask layer 25 and the metal gate 13 until the gate oxide layer 12 is exposed.

[0095] The method for preparing the semiconductor structure of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0096] First, if Figure 8 As shown, step 1 is performed to provide a semiconductor structure, wherein the semiconductor structure includes an active area 11, a gate oxide layer 12 and a metal gate 13, wherein the gate oxide layer 12 is disposed on the active area 11; the gate oxide layer 12 includes a pattern-intensive area 121 and an isolation area 122, wherein the pattern-intensive area 121 is a densely patterned gate oxide material, and the isolation area 122 is a whole block of gate oxide material used for isolation; the metal gate 13 includes a first gate area 131, a second gate area 132 and a third gate area 133, wherein the first gate area 131 fills the gap in the pattern-intensive area 121, the second gate area 132 is adjacent to a side of the isolation area 122 away from the pattern-intensive area 121, and the third gate area 133 covers the upper surfaces of the gate oxide layer 12, the first gate area 131 and the second gate area 132.

[0097] In one embodiment, the metal grid 13 is made of aluminum.

[0098] In one embodiment, the lengths of the metal gate 13 in the first direction and the second direction are both greater than 0.25 micrometers, the first direction and the second direction are both parallel to the surface of the active region 11 , and the first direction is perpendicular to the second direction.

[0099] Specifically, Figure 8As shown, the first direction is the x-axis direction in the figure, the y-axis direction is the direction perpendicular to the surface of the active area 11, and the second direction is the direction perpendicular to the paper surface. Since it is a two-dimensional figure, the second direction is not shown in the figure.

[0100] Then, if Fig. 9 As shown, step 2 is performed, a hard mask layer 25 is set on the metal gate 13, a photoresist 21 is set on the hard mask layer 25, and a photolithography mask 22 is set on the photoresist 21 for exposure. The photolithography mask 22 is provided with a patterned structure at a position corresponding to the isolation area 122 and above the second gate area 132 to allow the exposure light 23 to pass through.

[0101] Then, if Fig.10 As shown, step 3 is performed to develop the photoresist 21 so that the exposed positions of the photoresist 21 corresponding to the isolation region 122 and the second gate region 132 are removed, thereby exposing a portion of the hard mask layer 25 .

[0102] Then, if Fig.11 As shown, step 4 is performed to etch the exposed hard mask layer 25 so that the hard mask layer 25 forms a patterned compensation area 261 corresponding to the pattern dense area 121 in the corresponding area above the isolation area 122 and the second gate area 132, and the photoresist 21 is removed.

[0103] In one embodiment, the pattern density of the patterned compensation area 261 is equal to the pattern density of the pattern-dense area 121 .

[0104] In one embodiment, the length of the compensation region 261 in the direction perpendicular to the surface of the active region 11 is equal to the length of the gate oxide layer 12 in the direction perpendicular to the surface of the active region 11 .

[0105] In one embodiment, an etching selectivity ratio between the material of the hard mask layer 25 and the material of the metal gate 13 is not equal to 1.

[0106] Then, if Fig.12 As shown, step 5 is performed to fill the filling layer 24 in the patterned compensation area 261 in the hard mask layer 25 .

[0107] In one embodiment, the etching selectivity ratio between the material of the filling layer 24 and the material of the metal gate 13 is not equal to 1.

[0108] Finally, if Fig.13 As shown, step 6 is performed to grind the hard mask layer 25 and the metal gate 13 until the gate oxide layer 12 is exposed.

[0109] The present invention sets a compensation area 261 on the hard mask layer 25 and utilizes the etching selectivity ratio between the etching material and the metal gate 13, so that the etching material stops etching after etching the hard mask layer 25, thereby avoiding over-etching to the second gate area 132 during the process of etching the hard mask layer 25 to form the compensation area 261, thereby ensuring the yield of the semiconductor structure and eliminating the step of monitoring the etching time in the first embodiment, thereby further improving the process efficiency.

[0110] Embodiment three:

[0111] like Fig.14 As shown, the present invention provides a compensation structure 26, and the compensation structure 26 is used to carry out the preparation method described in any one of Example 1 or Example 2, the compensation structure 26 includes a patterned compensation area 261, and the area to be ground includes a patterned area and a non-patterned area. The compensation area 261 of the compensation structure 26 is arranged above the non-patterned area of ​​the area to be ground, so that the semiconductor structure provided with the compensation structure 26 can obtain a uniform grinding surface after grinding.

[0112] In one embodiment, as in the first embodiment, the material of the compensation structure 26 is the material of the metal gate 13 , and the compensation region 261 is disposed in the third gate region 133 of the metal gate 13 .

[0113] In one embodiment, the material of the compensation structure 26 in the second embodiment is the material of the hard mask layer 25 , and the compensation region 261 is obtained by separately disposing a hard mask layer 25 on the metal gate 13 .

[0114] Specifically, practitioners may set the material and structural position of the compensation area 261 according to specific application requirements and conditions to obtain the compensation structure 26 .

[0115] In one embodiment, the compensation area 261 of the compensation structure 26 is filled with a filling layer 24, and the material of the filling layer 24 is set according to the material filling the gaps in the graphic dense area 121 which is complementary to the compensation area 261, so that the grinding rate of the compensation area 261 is further close to the grinding rate of the graphic dense area 121, thereby improving the uniformity of the grinding surface.

[0116] The present invention achieves a uniform grinding surface in areas with different densities or large unpatterned areas by setting a compensation structure 26 including a compensation area 261 as a grinding compensation for the pattern-dense area 121, so that circuit structures such as I / O areas, sensor areas or gate resistor areas that cannot achieve uniform grinding surfaces through dummy can also achieve highly uniform grinding surfaces.

[0117] Embodiment 4:

[0118] The present invention further provides a semiconductor structure, which is prepared by using the preparation method described in any one of the first embodiment or the second embodiment, or the semiconductor structure is prepared by using the compensation structure 26 in the third embodiment.

[0119] In one embodiment, the semiconductor structure includes one or any combination of input or output interactive devices, sensors, or gate resistors.

[0120] In summary, the compensation structure, semiconductor structure and preparation method of the present invention can avoid the etching load effect caused by grinding due to different pattern densities and the dish-shaped depression caused by different grinding rates at the edge and center of a large area without a pattern by setting a compensation area on the metal gate; at the same time, over-etching can be avoided by controlling the etching time of the metal gate to ensure the structural yield; in addition, a hard mask layer is set on the metal gate to avoid over-etching of the metal gate, reduce the process steps of controlling the etching time, and improve the process efficiency.

[0121] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: A semiconductor structure is provided, the semiconductor structure comprising an active area, a gate oxide layer and a metal gate, the gate oxide layer being arranged on the active area; the gate oxide layer comprising a pattern-intensive area and an isolation area, the pattern-intensive area being a densely patterned gate oxide material, the isolation area being a whole block of gate oxide material for isolation; the metal gate comprising a first gate area, a second gate area and a third gate area, the first gate area filling a gap in the pattern-intensive area, the second gate area being adjacent to a side of the isolation area away from the pattern-intensive area, and the third gate area covering the upper surfaces of the gate oxide layer, the first gate area and the second gate area; Disposing a photoresist on the metal grid, and disposing a photolithography mask on the photoresist for exposure, wherein the photolithography mask is provided with a patterned structure at a position corresponding to the isolation region and above the second grid region to allow exposure light to pass through; Developing the photoresist so that the exposed positions of the photoresist corresponding to the isolation region and the second gate region are removed, thereby exposing a portion of the metal gate; Etching the exposed metal gate so that the third gate region of the metal gate corresponding to the isolation region and the second gate region forms a patterned compensation region corresponding to the pattern-intensive region, and removing the photoresist; Filling a filling layer in the patterned compensation area in the metal gate; The metal gate is ground until the gate oxide layer is exposed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: When etching the exposed metal gate, the time for etching the metal gate is set to a preset time, so that the bottom of the formed compensation area is not lower than the top of the gate oxide layer.

3. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: A semiconductor structure is provided, the semiconductor structure comprising an active area, a gate oxide layer and a metal gate, the gate oxide layer being arranged on the active area; the gate oxide layer comprising a pattern-intensive area and an isolation area, the pattern-intensive area being a densely patterned gate oxide material, the isolation area being a whole block of gate oxide material for isolation; the metal gate comprising a first gate area, a second gate area and a third gate area, the first gate area filling a gap in the pattern-intensive area, the second gate area being adjacent to a side of the isolation area away from the pattern-intensive area, and the third gate area covering the upper surfaces of the gate oxide layer, the first gate area and the second gate area; A hard mask layer is arranged on the metal gate, a photoresist is arranged on the hard mask layer, a photolithography mask is arranged on the photoresist for exposure, and the photolithography mask is provided with a patterned structure at a position corresponding to the isolation area and above the second gate area to allow exposure light to pass through; Developing the photoresist so that the positions of the photoresist corresponding to the isolation region and the exposure above the second gate region are removed, exposing a portion of the hard mask layer; Etching the exposed hard mask layer to form a patterned compensation area corresponding to the pattern-intensive area in the hard mask layer in the area corresponding to the isolation area and the second gate area, and removing the photoresist; Filling a filling layer in the patterned compensation area in the hard mask layer; The hard mask layer and the metal gate are ground until the gate oxide layer is exposed.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The pattern density of the patterned compensation area is equal to the pattern density of the pattern-intensive area.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The length of the compensation region in a direction perpendicular to the surface of the active region is equal to the length of the gate oxide layer in a direction perpendicular to the surface of the active region.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the metal grid is aluminum.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The lengths of the metal gate in the first direction and the second direction are both greater than 0.25 micrometers, the first direction and the second direction are both parallel to the surface of the active area, and the first direction is perpendicular to the second direction.

8. The method for preparing a semiconductor structure according to claim 3, characterized in that: An etching selectivity ratio between the material of the hard mask layer and the material of the metal gate is not equal to 1.

9. A compensating structure, characterized in that: The compensating structure is used to carry out the preparation method described in any one of claims 1 to 8, the compensating structure includes a patterned compensating area, the area to be ground includes a patterned area and a non-patterned area, the compensating area of ​​the compensating structure is arranged above the non-patterned area of ​​the area to be ground, so that the semiconductor structure provided with the compensating structure can obtain a uniform ground surface after grinding.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the preparation method described in any one of claims 1 to 8, or the semiconductor structure is prepared by the compensation structure described in claim 9.

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