Semiconductor device and manufacturing method thereof
By forming a different semiconductor layer on the SOI substrate, the material or crystal surface of the upper semi -semiconductor layer of the SOI substrate can be solved. Improve the performance of the device.
Patent Information
- Application Number
- CN202411524388.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-01-28
AI Technical Summary
On the SOI substrate, semiconductor layers with the same material or the same crystal plane orientation cannot meet the requirements of different devices, making it difficult to form semiconductor layers with different materials or the same crystal plane orientation in the SOI substrate according to actual needs.
By forming the first and second base lining, and keep the first half and the second semiconductor layer from the side of the first base, far from the key on the insulation layer to remove the first base to form a Soi substrate to achieve Make different device areas on the same SOI substrate.
A semiconductor layer with different crystal orientations or materials is made on the same SOI substrate to meet the requirements of different devices, thereby improving the performance of the device.
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Figure CN119381338A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] SOI (Semiconductor-On-Insulator) substrate includes a lower substrate, an insulating buried layer and a semiconductor layer, and the lower substrate and the semiconductor layer are separated by the insulating buried layer. SOI substrate is widely used in the manufacture of semiconductor devices. The integrated circuit formed by this substrate has considerable advantages over similar circuits formed on a conventional substrate formed only of single crystal silicon. These advantages include faster switching speed, stronger noise resistance, smaller loss current, reduced parasitic capacitance, stronger radiation resistance, etc.
[0003] The semiconductor layers in the SOI substrate usually have the same material or the same crystal plane orientation. When different devices are prepared on the SOI substrate, the semiconductor layers with the same material or the same crystal plane orientation cannot meet the requirements of different devices.
[0004] Therefore, how to form semiconductor layers of different materials or different crystal plane orientations in an SOI substrate according to actual needs is a problem that needs to be solved urgently. Summary of the invention
[0005] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so that different device regions can be manufactured on the same SOI substrate.
[0006] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0007] forming a first substrate, the first substrate comprising a first base and a first semiconductor layer and a second semiconductor layer formed on the first base;
[0008] forming a second substrate, the second substrate comprising a second base and an insulating layer formed on the second base;
[0009] Bonding a surface of the first semiconductor layer and the second semiconductor layer away from the first substrate to a surface of the insulating layer away from the second substrate;
[0010] The first substrate is removed to form an SOI substrate, wherein the SOI substrate includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the SOI substrate includes a first device region and a second device region, the second substrate serves as the lower substrate, the insulating layer serves as the insulating buried layer, the first semiconductor layer serves as the semiconductor layer of the first device region, and the second semiconductor layer serves as the semiconductor layer of the second device region.
[0011] Optionally, the step of forming the first substrate includes:
[0012] Providing a first substrate, and forming a first semiconductor layer on the first substrate;
[0013] Etching the first semiconductor layer to form a first groove exposing a surface of the first substrate portion;
[0014] forming a second semiconductor layer in the first trench; or,
[0015] providing a substrate;
[0016] Etching the substrate to form a first trench in the substrate;
[0017] forming a second semiconductor layer in the first trench, wherein the area of the substrate flush with the top surface and the bottom surface of the second semiconductor layer is the first semiconductor layer, and the substrate below the first semiconductor layer and the second semiconductor layer is the first substrate;
[0018] The first substrate, the first semiconductor layer and the second semiconductor layer have the same crystal plane orientation, and the first semiconductor layer and the second semiconductor layer are made of different materials.
[0019] Optionally, the step of forming the first substrate includes:
[0020] Providing a sacrificial SOI substrate, the sacrificial SOI substrate comprising, from bottom to top, a sacrificial lower substrate, a sacrificial insulating buried layer and a first semiconductor layer;
[0021] Etching the first semiconductor layer and the sacrificial insulating buried layer to form a second trench exposing the sacrificial lower substrate;
[0022] A semiconductor material layer is formed in the second trench, the semiconductor material layer within the height range of the first semiconductor layer serves as the second semiconductor layer, and the sacrificial lower substrate, the sacrificial insulating buried layer outside the second trench, and the semiconductor material layer within the height range of the sacrificial insulating buried layer serve as the first base.
[0023] Optionally, the semiconductor material layer and the sacrificial lower substrate have the same crystal plane orientation, the sacrificial lower substrate and the first semiconductor layer have different crystal plane orientations, and / or the semiconductor material layer and the first semiconductor layer are made of different materials.
[0024] Optionally, the semiconductor layer in the first device region and the semiconductor layer in the second device region have different crystal plane orientations and / or materials.
[0025] Optionally, top surfaces of the first semiconductor layer and the second semiconductor layer are flush.
[0026] Optionally, the first semiconductor layer and the second semiconductor layer are single crystal.
[0027] The present invention also provides a semiconductor device, including an SOI substrate, wherein the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate includes a first device region and a second device region, and the semiconductor layer in the first device region has a different crystal plane orientation and / or material from the semiconductor layer in the second device region.
[0028] Optionally, a top surface of the semiconductor layer in the first device region is flush with a top surface of the semiconductor layer in the second device region.
[0029] Optionally, the semiconductor layer in the first device region and the semiconductor layer in the second device region are single crystal.
[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0031] 1. A method for manufacturing a semiconductor device of the present invention comprises: forming a first substrate, the first substrate comprising a first base and a first semiconductor layer and a second semiconductor layer formed on the first substrate; forming a second substrate, the second substrate comprising a second base and an insulating layer formed on the second base; bonding the first semiconductor layer and the second semiconductor layer on a side away from the first base with a side of the insulating layer away from the second base; removing the first base to form an SOI substrate, the SOI substrate comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprising a first device region and a second device region, the second base serving as the lower substrate, the insulating layer serving as the insulating buried layer, the first semiconductor layer serving as the semiconductor layer of the first device region, and the second semiconductor layer serving as the semiconductor layer of the second device region, so that different device regions can be manufactured on the same SOI substrate.
[0032] 2. The semiconductor device of the present invention comprises: an SOI substrate, wherein the SOI substrate comprises, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate comprises a first device region and a second device region, and the semiconductor layer in the first device region has a different crystal plane orientation and / or material from the semiconductor layer in the second device region, so that different device regions can be manufactured on the same SOI substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0034] Figure 2a to Figure 2e yes Figure 1 A schematic diagram of a semiconductor device manufacturing method shown;
[0035] Figure 3a to Figure 3b It is a schematic structural diagram of a first substrate according to an embodiment of the present invention.
[0036] Among them, Figure 1 to Figure 3b The reference numerals are described as follows:
[0037] 101 - sacrificial lower substrate; 102 - sacrificial insulating buried layer; 103 - semiconductor material layer; 104 - second trench; 11 - first semiconductor layer; 12 - second semiconductor layer; 13 - first base; 14 - base; 21 - second base; 22 - insulating layer. DETAILED DESCRIPTION
[0038] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0039] MOSFET devices are divided into NMOS devices and PMOS devices. For various reasons, it is usually desirable to integrate NMOS and PMOS into the same circuit. The applicant has found that NMOS and PMOS have different requirements for the crystal plane orientation or material of the semiconductor layer. For example, the (110) silicon surface is more suitable for making PMOS due to its good hole mobility, and the (100) silicon surface is more suitable for making NMOS due to its good electron mobility. In addition, in order to improve the performance of PMOS, PMOS will use a germanium silicon channel, while NMOS uses a silicon channel.
[0040] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:
[0041] Step S1, forming a first substrate, wherein the first substrate comprises a first base and a first semiconductor layer and a second semiconductor layer formed on the first base;
[0042] Step S2, forming a second substrate, wherein the second substrate includes a second base and an insulating layer formed on the second base;
[0043] Step S3, bonding the first semiconductor layer and the second semiconductor layer at a side away from the first substrate to the insulating layer at a side away from the second substrate;
[0044] Step S4, removing the first substrate to form an SOI substrate, the SOI substrate including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate including a first device region and a second device region, the second substrate serving as the lower substrate, the insulating layer serving as the insulating buried layer, the first semiconductor layer serving as the semiconductor layer of the first device region, and the second semiconductor layer serving as the semiconductor layer of the second device region.
[0045] Reference below Figure 2a to Figure 2e , Figure 3a to Figure 3b The method for manufacturing the semiconductor device provided in this embodiment is described in more detail. Figure 2a to Figure 2e , Figure 3a to Figure 3b It is a schematic diagram of a longitudinal cross-section of a semiconductor device.
[0046] According to step S1, a first substrate is formed, the first substrate comprising a first base and a first semiconductor layer and a second semiconductor layer formed on the first base, that is, the first semiconductor layer is formed on a portion of the surface of the first base, and the second semiconductor layer is formed on another portion of the surface of the first base.
[0047] In one embodiment, the steps of forming the first substrate include: first, providing a first base 13, and forming a first semiconductor layer 11 on the first base 13 by using an epitaxial process; then, etching the first semiconductor layer 11 to form a first groove (not shown) exposing a portion of the surface of the first base 13; then, forming a second semiconductor layer 12 in the first groove by using an epitaxial process. Figure 3a Alternatively, in another embodiment, the step of forming the first substrate includes: providing a base 14; etching the base 14 to form a first groove (not shown) in the base 14; forming a second semiconductor layer 12 in the first groove by using an epitaxial process, then the area of the base 14 flush with the top surface and the bottom surface of the second semiconductor layer 12 is the first semiconductor layer 11, and the base 14 below the first semiconductor layer 11 and the second semiconductor layer 12 is the first base, see Figure 3b The first substrate, the first semiconductor layer and the second semiconductor layer have the same crystal plane orientation, the first semiconductor layer and the second semiconductor layer are made of different materials, and the materials of the first semiconductor layer and the second semiconductor layer may be the same as or different from the material of the first substrate.
[0048] Or, in another embodiment, see Figure 2a to Figure 2c The steps of forming the first substrate include: first, Figure 2aAs shown, a sacrificial SOI substrate is provided, wherein the sacrificial SOI substrate comprises a sacrificial lower substrate 101, a sacrificial insulating buried layer 102 and a first semiconductor layer 11 from bottom to top; then, as shown in FIG. Figure 2b As shown, the first semiconductor layer 11 and the sacrificial insulating buried layer 102 are etched to form a second trench 104 (the mask layer is not shown) exposing the sacrificial lower substrate 101; then, as shown Figure 2c As shown, an epitaxial process is used to form a semiconductor material layer 103 in the second groove 104, and then chemical mechanical polishing is performed to make the surface of the semiconductor material layer 103 flush with the surface of the first semiconductor layer 11, and the semiconductor material layer 103 within the height range of the first semiconductor layer 11 serves as the second semiconductor layer, and the sacrificial underlying substrate 101, the sacrificial insulating buried layer 102 outside the second groove 104, and the semiconductor material layer 103 within the height range of the sacrificial insulating buried layer 102 serve as the first base.
[0049] Among them, Figure 2a to Figure 2c In the embodiment shown, the crystal plane orientation of the semiconductor material layer 103 is the same as that of the sacrificial lower substrate 101, and the crystal plane orientation of the sacrificial lower substrate 101 is different from that of the first semiconductor layer 11. In one embodiment, the crystal plane orientation of the sacrificial lower substrate 101 is (100) or (110), and the crystal plane orientation of the formed semiconductor material layer 103 is correspondingly (100) or (110), and the crystal plane orientation of the first semiconductor layer 11 is correspondingly (110) or (100).
[0050] At this time, the material of the semiconductor material layer 103 and the first semiconductor layer 11 may be the same or different, and the material of the semiconductor material layer 103 and the sacrificial lower substrate 101 may be the same or different. Alternatively, the material of the semiconductor material layer 103 and the first semiconductor layer 11 are different, and at this time, the material of the semiconductor material layer 103 and the sacrificial lower substrate 101 may be the same or different, and the material of the first semiconductor layer 11 and the sacrificial lower substrate 101 may be the same or different, and the crystal plane orientation of the semiconductor material layer 103 and the sacrificial lower substrate 101 is the same, and the crystal plane orientation of the semiconductor material layer 103 and the first semiconductor layer 11 may be the same or different.
[0051] The top surfaces of the first semiconductor layer and the second semiconductor layer are flush, so that devices can be subsequently manufactured based on planes at the same height.
[0052] The first semiconductor layer and the second semiconductor layer are single crystal.
[0053] According to step S2, Figure 2dAs shown, a second substrate is formed, and the second substrate includes a second base 21 and an insulating layer 22 formed on the second base 21 .
[0054] According to step S3, a surface of the first semiconductor layer and the second semiconductor layer away from the first substrate is bonded to a surface of the insulating layer away from the second substrate.
[0055] exist Figure 2d In the illustrated embodiment, a surface of the first semiconductor layer 11 and the second semiconductor layer away from the sacrificial lower substrate 101 is bonded to a surface of the insulating layer 22 away from the second base 21 .
[0056] According to step S4, the first substrate is removed to form a SOI (Semiconductor-On-Insulator) substrate, wherein the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, wherein the SOI substrate includes a first device region and a second device region, the second substrate serves as the lower substrate, the insulating layer serves as the insulating buried layer, the first semiconductor layer serves as the semiconductor layer of the first device region, and the second semiconductor layer serves as the semiconductor layer of the second device region.
[0057] exist Figure 2d to Figure 2e In the illustrated embodiment, the step of removing the first substrate includes: first, thinning the sacrificial lower substrate 101 to a certain thickness by rapid grinding; then, removing the remaining sacrificial lower substrate 101, the sacrificial insulating buried layer 102, and the semiconductor material layer 103 within the height range of the sacrificial insulating buried layer 102 by a chemical mechanical grinding process, the top surface of the first semiconductor layer 11 after grinding is flush with the top surface of the remaining semiconductor material layer 103, and the remaining semiconductor material layer 103 serves as the second semiconductor layer 12. By adopting the above method to remove the first substrate, the first substrate can be quickly removed while avoiding damage to the surfaces of the first semiconductor layer 11 and the second semiconductor layer 12.
[0058] like Figure 2e As shown, the SOI substrate includes a first device area A1 and a second device area A2, the second base 21 serves as the lower substrate, the insulating layer 22 serves as the insulating buried layer, the first semiconductor layer 11 serves as the semiconductor layer of the first device area A1, and the second semiconductor layer 12 serves as the semiconductor layer of the second device area A2.
[0059] The first semiconductor layer and the second semiconductor layer have different crystal plane orientations and / or materials.
[0060] Wherein, when the crystal plane orientations of the first semiconductor layer and the second semiconductor layer are different, if the crystal plane orientation of the first semiconductor layer is (100) and the crystal plane orientation of the second semiconductor layer is (110), the first device region is an NMOS device region and the second device region is a PMOS device region; if the crystal plane orientation of the first semiconductor layer is (110) and the crystal plane orientation of the second semiconductor layer is (100), the first device region is a PMOS device region and the second device region is an NMOS device region. At this time, the material types of the first semiconductor layer and the second semiconductor layer are not limited, and can be semiconductor materials such as single crystal silicon, single crystal silicon germanium or single crystal silicon carbide.
[0061] When the materials of the first semiconductor layer and the second semiconductor layer are different, if the material of the first semiconductor layer is single crystal silicon or single crystal silicon carbide, etc., and the material of the second semiconductor layer is single crystal silicon germanium, etc., then the first device area is an NMOS device area, and the second device area is a PMOS device area; if the material of the first semiconductor layer is single crystal silicon germanium, etc., and the material of the second semiconductor layer is single crystal silicon or single crystal silicon carbide, etc., then the first device area is a PMOS device area, and the second device area is an NMOS device area. At this time, the crystal plane orientations of the first semiconductor layer and the second semiconductor layer are not limited.
[0062] When the first semiconductor layer or the second semiconductor layer is formed by an epitaxial process, if the material of the first semiconductor layer or the second semiconductor layer is single crystal silicon, gases such as silane may be introduced into the reaction chamber; if the material of the first semiconductor layer or the second semiconductor layer is single crystal silicon germanium, gases such as silane and germane may be introduced into the reaction chamber; if the material of the first semiconductor layer or the second semiconductor layer is single crystal silicon carbide, gases such as silane, propane and methane may be introduced into the reaction chamber. In addition, gases of desired doping ions may be introduced into the reaction chamber according to the doping type of the first semiconductor layer or the second semiconductor layer.
[0063] The buried insulating layer is, for example, a silicon oxide layer.
[0064] The method for manufacturing the semiconductor device further includes: forming an NMOS device (not shown) and forming a PMOS device (not shown).
[0065] Taking the example that the NMOS device is formed in the first device region and the PMOS device is formed in the second device region, the NMOS device includes a first gate structure formed on the first semiconductor layer and a first source region and a first drain region formed in the first semiconductor layer on both sides of the first gate structure, and the region below the first gate structure and between the first source region and the first drain region is a first channel region; the PMOS device includes a second gate structure formed on the second semiconductor layer and a second source region and a second drain region formed in the second semiconductor layer on both sides of the second gate structure, and the region below the second gate structure and between the second source region and the second drain region is a second channel region.
[0066] A shallow trench isolation structure (not shown) may also be formed between the first device region and the second device region to isolate the NMOS device from the PMOS device. The shallow trench isolation structure may penetrate the first semiconductor layer and / or the second semiconductor layer to contact the insulating layer, or the shallow trench isolation structure may penetrate the first semiconductor layer and / or the second semiconductor layer, the insulating layer and enter the second substrate.
[0067] As can be seen from the above content, by bonding the first semiconductor layer and the second semiconductor layer in the first substrate away from the first base with the surface of the insulating layer in the second substrate away from the second base, and forming an SOI substrate after removing the first base, the SOI substrate can include a first device region and a second device region, the second base serves as the lower substrate, the insulating layer serves as the insulating buried layer, the first semiconductor layer serves as the semiconductor layer in the first device region, and the second semiconductor layer serves as the semiconductor layer in the second device region, so that different crystal plane orientations of the lattice have different effects on the mobility of carriers in the channel region of different types of devices, and a semiconductor layer with a crystal plane orientation of (100) and a semiconductor layer with a crystal plane orientation of (110) can be integrated into the same SOI substrate. On the basis, that is, different device areas can be manufactured on the same SOI substrate, and NMOS devices can be manufactured in the device area where the semiconductor layer with a crystal plane orientation of (100) is located, and PMOS devices can be manufactured in the device area where the semiconductor layer with a crystal plane orientation of (110) is located, so that the electron mobility of the NMOS device and the hole mobility of the PMOS device can be improved at the same time, thereby improving the performance of the NMOS device and the PMOS device at the same time; and / or, according to different materials, the performance of the channel region of different types of devices has different effects, and semiconductor layers of different materials can be integrated on the same SOI substrate, that is, different device areas can be manufactured on the same SOI substrate, and NMOS devices and PMOS devices can be manufactured in different device areas, thereby improving the performance of NMOS devices and PMOS devices.
[0068] In one embodiment, if the material of the semiconductor layer in the device area where the NMOS device is located is single crystal silicon or single crystal silicon carbide, and the material of the semiconductor layer in the device area where the PMOS device is located is single crystal silicon germanium, since the atomic radius of germanium is larger than the atomic radius of silicon, compressive stress can be generated in the channel area of the PMOS device, thereby improving the performance of the PMOS device.
[0069] In summary, the method for manufacturing a semiconductor device provided by the present invention includes: forming a first substrate, the first substrate including a first base and a first semiconductor layer and a second semiconductor layer formed on the first substrate; forming a second substrate, the second substrate including a second base and an insulating layer formed on the second base; bonding the first semiconductor layer and the second semiconductor layer away from the first base with the side of the insulating layer away from the second base; removing the first base to form an SOI substrate, the SOI substrate including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate including a first device region and a second device region, the second substrate serving as the lower substrate, the insulating layer serving as the insulating buried layer, the first semiconductor layer serving as the semiconductor layer of the first device region, and the second semiconductor layer serving as the semiconductor layer of the second device region. The method for manufacturing a semiconductor device of the present invention enables different device regions to be fabricated on the same SOI substrate.
[0070] An embodiment of the present invention provides a semiconductor device, which includes an SOI substrate, wherein the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate includes a first device region and a second device region, and the semiconductor layer in the first device region has a different crystal plane orientation and / or material from the semiconductor layer in the second device region.
[0071] The semiconductor device provided by this embodiment is described in more detail below.
[0072] The SOI (Semiconductor-On-Insulator) substrate includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the SOI substrate includes a first device area and a second device area. The semiconductor layer in the first device area and the semiconductor layer in the second device area have different crystal plane orientations or materials, or both crystal plane orientations and materials are different.
[0073] Wherein, when the crystal plane orientation of the semiconductor layer in the first device region is different from that of the semiconductor layer in the second device region, if the crystal plane orientation of the semiconductor layer in the first device region is (100) and the crystal plane orientation of the semiconductor layer in the second device region is (110), then the first device region is an NMOS device region and the second device region is a PMOS device region; if the crystal plane orientation of the semiconductor layer in the first device region is (110) and the crystal plane orientation of the semiconductor layer in the second device region is (100), then the first device region is a PMOS device region and the second device region is an NMOS device region. At this time, the materials of the semiconductor layer in the first device region and the semiconductor layer in the second device region can be the same or different, and the materials of the semiconductor layer in the first device region and the semiconductor layer in the second device region are not limited, and can be semiconductor materials such as single crystal silicon, single crystal silicon germanium or single crystal silicon carbide.
[0074] When the semiconductor layer in the first device region and the semiconductor layer in the second device region are made of different materials, if the semiconductor layer in the first device region is made of single crystal silicon or single crystal silicon carbide, etc., and the semiconductor layer in the second device region is made of single crystal silicon germanium, etc., then the first device region is an NMOS device region, and the second device region is a PMOS device region; if the semiconductor layer in the first device region is made of single crystal silicon germanium, etc., and the semiconductor layer in the second device region is made of single crystal silicon or single crystal silicon carbide, etc., then the first device region is a PMOS device region, and the second device region is an NMOS device region. At this time, the crystal plane orientations of the semiconductor layer in the first device region and the semiconductor layer in the second device region may be the same or different, and the crystal plane orientations of the semiconductor layer in the first device region and the semiconductor layer in the second device region are not limited.
[0075] The semiconductor layer in the first device region and the semiconductor layer in the second device region are single crystal.
[0076] The top surface of the semiconductor layer in the first device region is flush with the top surface of the semiconductor layer in the second device region, so that devices can be subsequently manufactured based on planes at the same height.
[0077] The crystal plane orientation of the semiconductor layer in the first device area may be the same as or different from the crystal plane orientation of the underlying substrate, and the crystal plane orientation of the semiconductor layer in the second device area may be the same as or different from the crystal plane orientation of the underlying substrate; the material of the semiconductor layer in the first device area may be the same as or different from the material of the underlying substrate, and the material of the semiconductor layer in the second device area may be the same as or different from the material of the underlying substrate.
[0078] The material of the lower substrate may be a semiconductor material such as single crystal silicon, single crystal silicon germanium or single crystal silicon carbide, and the buried insulating layer may be, for example, a silicon oxide layer.
[0079] The semiconductor device further comprises an NMOS device and a PMOS device.
[0080] Taking the example that the NMOS device is formed in the first device area and the PMOS device is formed in the second device area, the NMOS device includes a first gate structure formed on the semiconductor layer in the first device area and a first source region and a first drain region formed in the semiconductor layer on both sides of the first gate structure, and the area below the first gate structure and between the first source region and the first drain region is a first channel region; the PMOS device includes a second gate structure formed on the semiconductor layer in the second device area and a second source region and a second drain region formed in the semiconductor layer on both sides of the second gate structure, and the area below the second gate structure and between the second source region and the second drain region is a second channel region.
[0081] A shallow trench isolation structure may be formed between the first device region and the second device region to isolate the NMOS device from the PMOS device. The shallow trench isolation structure may penetrate the semiconductor layer to contact the buried insulating layer, or the shallow trench isolation structure may penetrate the semiconductor layer, the buried insulating layer and enter the lower substrate.
[0082] From the above content, it can be seen that since the crystal plane orientation and / or material of the semiconductor layer in the first device area and the semiconductor layer in the second device area are different, the different crystal plane orientations of the lattice have different effects on the mobility of carriers in the channel region of different types of devices, and the semiconductor layer with a crystal plane orientation of (100) and the semiconductor layer with a crystal plane orientation of (110) can be integrated into the same SOI substrate, that is, different device areas can be made on the same SOI substrate, and the NMOS device can be made in the device area where the semiconductor layer with a crystal plane orientation of (100) is located, and the PMOS device can be made in the device area where the semiconductor layer with a crystal plane orientation of (110) is located. The device region where the semiconductor layer with an orientation of (110) is located can simultaneously improve the electron mobility of the NMOS device and the hole mobility of the PMOS device, thereby simultaneously improving the performance of the NMOS device and the PMOS device; and / or, different materials have different effects on the performance of the channel region of different types of devices, and semiconductor layers of different materials can be integrated on the same SOI substrate, that is, different device regions can be made on the same SOI substrate, and NMOS devices and PMOS devices can be made in different device regions, thereby improving the performance of NMOS devices and PMOS devices.
[0083] In one embodiment, if the material of the semiconductor layer in the device area where the NMOS device is located is single crystal silicon or single crystal silicon carbide, and the material of the semiconductor layer in the device area where the PMOS device is located is single crystal silicon germanium, since the atomic radius of germanium is larger than the atomic radius of silicon, compressive stress can be generated in the channel area of the PMOS device, thereby improving the performance of the PMOS device.
[0084] In summary, the semiconductor device provided by the present invention comprises an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, wherein the SOI substrate comprises a first device region and a second device region, wherein the semiconductor layer in the first device region and the semiconductor layer in the second device region have different crystal plane orientations and / or materials. The semiconductor device of the present invention enables different device regions to be fabricated on the same SOI substrate.
[0085] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: forming a first substrate, the first substrate comprising a first base and a first semiconductor layer and a second semiconductor layer formed on the first base; forming a second substrate, the second substrate comprising a second base and an insulating layer formed on the second base; Bonding a surface of the first semiconductor layer and the second semiconductor layer away from the first substrate to a surface of the insulating layer away from the second substrate; The first substrate is removed to form an SOI substrate, wherein the SOI substrate includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the SOI substrate includes a first device region and a second device region, the second substrate serves as the lower substrate, the insulating layer serves as the insulating buried layer, the first semiconductor layer serves as the semiconductor layer of the first device region, and the second semiconductor layer serves as the semiconductor layer of the second device region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the first substrate comprises: Providing a first substrate, and forming a first semiconductor layer on the first substrate; Etching the first semiconductor layer to form a first groove exposing a surface of the first substrate portion; forming a second semiconductor layer in the first trench; or, providing a substrate; Etching the substrate to form a first trench in the substrate; forming a second semiconductor layer in the first trench, wherein the area of the substrate flush with the top surface and the bottom surface of the second semiconductor layer is the first semiconductor layer, and the substrate below the first semiconductor layer and the second semiconductor layer is the first substrate; The first substrate, the first semiconductor layer and the second semiconductor layer have the same crystal plane orientation, and the first semiconductor layer and the second semiconductor layer are made of different materials.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the first substrate comprises: Providing a sacrificial SOI substrate, the sacrificial SOI substrate comprising, from bottom to top, a sacrificial lower substrate, a sacrificial insulating buried layer and a first semiconductor layer; Etching the first semiconductor layer and the sacrificial insulating buried layer to form a second trench exposing the sacrificial lower substrate; A semiconductor material layer is formed in the second trench, the semiconductor material layer within the height range of the first semiconductor layer serves as the second semiconductor layer, and the sacrificial lower substrate, the sacrificial insulating buried layer outside the second trench, and the semiconductor material layer within the height range of the sacrificial insulating buried layer serve as the first base.
4. The method for manufacturing a semiconductor device according to claim 3, wherein: The semiconductor material layer and the sacrificial lower substrate have the same crystal plane orientation, the sacrificial lower substrate and the first semiconductor layer have different crystal plane orientations, and / or the semiconductor material layer and the first semiconductor layer are made of different materials.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor layer in the first device region and the semiconductor layer in the second device region have different crystal plane orientations and / or materials.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The top surfaces of the first semiconductor layer and the second semiconductor layer are flush.
7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that: The first semiconductor layer and the second semiconductor layer are single crystal.
8. A semiconductor device, characterized in that: It includes an SOI substrate, which includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top. The SOI substrate includes a first device area and a second device area. The semiconductor layer in the first device area and the semiconductor layer in the second device area have different crystal plane orientations and / or materials.
9. The semiconductor device according to claim 8, characterized in that A top surface of the semiconductor layer in the first device region is flush with a top surface of the semiconductor layer in the second device region.
10. The semiconductor device according to claim 8 or 9, characterized in that The semiconductor layer in the first device region and the semiconductor layer in the second device region are single crystal.