Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor structure, a bonding layer is formed on the semiconductor structure, and the bonding layer comprises an insulating layer and a first metal layer formed in the insulating layer; the alloy protection layer is formed on the first metal layer, the alloy protection layer is an alloy of the first metal layer and a second metal layer, and the reduction potential of the second metal layer is smaller than that of the first metal layer. According to the technical scheme of the invention, the surface of the metal layer in the bonding layer can be prevented from being oxidized into a metal oxide, and the electrical connection performance between the metal layers on the two bonded semiconductor structures can be prevented from being reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the hybrid bonding process, taking the metal layer in the bonding layer as Cu as an example, in order to prevent the Cu surface from being oxidized into CuO with strong chemical stability, which will increase the contact resistance between the metal layers after bonding and then cause the connection failure between the two wafers after bonding, Cu2O produced by the chemical mechanical polishing process is currently used to protect Cu, and the surface activation process is used to reduce Cu2O to Cu before bonding. However, Cu2O is unstable, which limits the waiting time (Q time) before bonding to only 8 hours. If the waiting time exceeds 8 hours, Cu2O will be oxidized to CuO that cannot be removed.

[0003] Therefore, how to prevent the surface of the metal layer in the bonding layer from being oxidized into metal oxide is a problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can prevent the surface of the metal layer in the bonding layer from being oxidized into metal oxide and can avoid reducing the electrical connection performance between the metal layers on the two semiconductor structures after bonding.

[0005] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor structure having a bonding layer formed thereon, the bonding layer comprising an insulating layer and a first metal layer formed in the insulating layer;

[0007] The alloy protective layer is formed on the first metal layer. The alloy protective layer is an alloy of the first metal layer and a second metal layer. The reduction potential of the second metal layer is lower than the reduction potential of the first metal layer.

[0008] Optionally, the resistivity of the second metal layer is in a range of plus or minus 10 times the resistivity of the first metal layer, and the atomic radius of the second metal layer is in a range of plus or minus 1.5 times the atomic radius of the first metal layer.

[0009] Optionally, the first metal layer includes at least one of Cu, Al and W, and the second metal layer includes at least one of Ni, Co and Ru.

[0010] Optionally, a top surface of the alloy protective layer is lower than a top surface of the insulating layer.

[0011] Optionally, the semiconductor device includes:

[0012] The two semiconductor structures are bonded together, the insulating layers on the two semiconductor structures are in contact with each other, and the alloy protection layers on the two semiconductor structures are in contact with each other.

[0013] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0014] Providing a semiconductor structure, on which a bonding layer is formed, the bonding layer comprising an insulating layer and a first metal layer formed in the insulating layer;

[0015] forming a second metal layer on the first metal layer, wherein the reduction potential of the second metal layer is lower than the reduction potential of the first metal layer;

[0016] An annealing process is performed to allow the second metal layer to react with a portion of the first metal layer to form an alloy protection layer.

[0017] Optionally, the resistivity of the second metal layer is in a range of plus or minus 10 times the resistivity of the first metal layer, and the atomic radius of the second metal layer is in a range of plus or minus 1.5 times the atomic radius of the first metal layer.

[0018] Optionally, the first metal layer includes at least one of Cu, Al and W, and the second metal layer includes at least one of Ni, Co and Ru.

[0019] Optionally, a top surface of the alloy protective layer is lower than a top surface of the insulating layer.

[0020] Optionally, the thickness of the second metal layer is

[0021] Optionally, the method for manufacturing the semiconductor device further includes:

[0022] The two semiconductor structures are bonded together, so that the insulating layers on the two semiconductor structures are in contact with each other, and the alloy protection layers on the two semiconductor structures are in contact with each other.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] 1. The semiconductor device of the present invention comprises: a semiconductor structure, on which a bonding layer is formed, the bonding layer comprising an insulating layer and a first metal layer formed in the insulating layer; an alloy protective layer formed on the first metal layer, the alloy protective layer is an alloy of the first metal layer and a second metal layer, the reduction potential of the second metal layer is lower than the reduction potential of the first metal layer, so that the surface of the metal layer in the bonding layer can be prevented from being oxidized to metal oxide, and the electrical connection performance between the metal layers on the two semiconductor structures after bonding can be prevented from being reduced.

[0025] 2. The manufacturing method of the semiconductor device of the present invention comprises: providing a semiconductor structure, on which a bonding layer is formed, the bonding layer comprising an insulating layer and a first metal layer formed in the insulating layer; forming a second metal layer on the first metal layer, the reduction potential of the second metal layer being less than the reduction potential of the first metal layer; performing an annealing process so that the second metal layer reacts with a portion of the first metal layer to form an alloy protective layer, so that the surface of the metal layer in the bonding layer can be prevented from being oxidized into metal oxide, and the electrical connection performance between the metal layers on the two semiconductor structures after bonding can be prevented from being reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0028] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] Figures 4 to 8 yes Figure 3 A device schematic diagram of a method for manufacturing a semiconductor device is shown.

[0030] Among them, Figures 1 to 8 The reference numerals are described as follows:

[0031] 10 - semiconductor structure; 101 - metal interconnect structure; 11 - insulating layer; 12 - first metal layer; 13 - second metal layer; 14 - alloy protection layer. DETAILED DESCRIPTION

[0032] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] An embodiment of the present invention provides a semiconductor device, which includes: a semiconductor structure, on which a bonding layer is formed, the bonding layer including an insulating layer and a first metal layer formed in the insulating layer; an alloy protective layer formed on the first metal layer, the alloy protective layer is an alloy of the first metal layer and a second metal layer, and the reduction potential of the second metal layer is lower than the reduction potential of the first metal layer.

[0034] See below Figure 1-2 The semiconductor device provided by this embodiment is described in more detail. Figure 1-2 It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0035] The semiconductor structure 10 may include a substrate and an insulating dielectric layer formed on the substrate, and a metal interconnect structure 101 may be formed in the insulating dielectric layer.

[0036] Device structures such as MOS transistors, resistors, and capacitors may also be formed in the semiconductor structure 10 , and the metal interconnect structure 101 is electrically connected to the device structures.

[0037] The semiconductor structure 10 may be a wafer or a chip, and the material or device function of the semiconductor structure 10 is not limited herein.

[0038] A bonding layer is formed on the semiconductor structure 10 , and the bonding layer includes an insulating layer 11 and a first metal layer 12 formed in the insulating layer 11 .

[0039] The material of the insulating layer 11 may include at least one of insulating materials such as nitrogen-doped silicon carbide, silicon oxide, and silicon oxynitride.

[0040] Preferably, Figure 1 and Figure 2 As shown, the first metal layer 12 extends into the semiconductor structure 10, so that the thickness of the first metal layer 12 is thick enough to improve the bonding strength when two subsequent semiconductor structures 10 are bonded. In other embodiments, the first metal layer 12 is only located in the insulating layer 11 and does not extend into the semiconductor structure 10.

[0041] In one embodiment, a plurality of spaced first metal layers 12 are formed in the insulating layer 11 , and bottom ends of at least some of the first metal layers 12 are electrically connected to the metal interconnection structure 101 .

[0042] The alloy protection layer 14 is formed on the first metal layer 12. The alloy protection layer 14 is formed on the first metal layer 12 and the second metal layer (i.e. Figure 5 The alloy of the second metal layer 13).

[0043] The reduction potential of the second metal layer 13 is lower than the reduction potential of the first metal layer 12, so that the property stability of the second metal layer 13 is higher than the property stability of the first metal layer 12, that is, compared with the first metal layer 12, the second metal layer 13 is less likely to be oxidized at room temperature, and the second metal layer 13 has stronger corrosion resistance, thereby improving the stability and corrosion resistance of the alloy protective layer 14, so that the alloy protective layer 14 can protect the surface of the first metal layer 12 from being oxidized, and the alloy protective layer 14 itself is not easily oxidized.

[0044] Preferably, the resistivity of the second metal layer 13 is in the range of plus or minus 10 times the resistivity of the first metal layer 12, that is, the resistivity of the second metal layer 13 is close to the resistivity of the first metal layer 12, so as to avoid the resistivity of the second metal layer 13 being too high, which may lead to the resistivity of the alloy protective layer 14 being too high, thereby avoiding the conductivity of the alloy protective layer 14 being reduced and affecting the electrical connection performance between the first metal layers 12 in the two semiconductor structures 10 after bonding; the atomic radius of the second metal layer 13 is in the range of plus or minus 1.5 times the atomic radius of the first metal layer 12, so that the lattice of the first metal layer 12 and the second metal layer 13 are adapted, so that the stress of the first metal layer 12 and the second metal layer 13 are adapted and the bonding is better when forming an alloy, so that the stability of the formed alloy protective layer 14 is better.

[0045] The first metal layer 12 may include at least one of Cu, Al, and W, and the second metal layer 13 may include at least one of Ni, Co, and Ru.

[0046] The top surface of the alloy protective layer 14 is lower than the top surface of the insulating layer 11. When the two semiconductor structures 10 are bonded, the lattice of the first metal layer 12 will be reorganized under the action of high temperature, so that the volume of the first metal layer 12 will expand and increase. By defining the top surface of the alloy protective layer 14 to be lower than the top surface of the insulating layer 11, space can be provided for the volume expansion of the first metal layer 12, thereby preventing the volume expansion of the first metal layer 12 from cracking the bonding interface.

[0047] like Figure 2 As shown, the semiconductor device includes: two bonded semiconductor structures 10, the insulating layers 11 on the two semiconductor structures 10 are in contact with each other, and the alloy protective layers 14 on the two semiconductor structures 10 are in contact with each other, so that the metal interconnection structures 101 in the two semiconductor structures 10 are electrically connected through the first metal layer 12 and the alloy protective layer 14.

[0048] The types of the two semiconductor structures 10 can be the same or different.

[0049] From the above content, it can be seen that since the alloy protective layer 14 is formed on the first metal layer 12 in the bonding layer, the alloy protective layer 14 is an alloy of the first metal layer 12 and the second metal layer 13, and the reduction potential of the second metal layer 13 is lower than the reduction potential of the first metal layer 12, so that the alloy protective layer 14 can protect the first metal layer 12, avoiding the surface of the first metal layer 12 from being oxidized to form metal oxide before the two semiconductor structures 10 are bonded, thereby increasing the waiting time (Q time) before bonding; and the alloy protective layer 14 itself has good conductivity, which can avoid reducing the electrical connection performance between the first metal layers 12 on the two semiconductor structures 10 after bonding.

[0050] Among them, when the first metal layer 12 is Cu, there is no need to form Cu2O on the surface of the first metal layer 12 by adopting a chemical mechanical polishing process to protect the first metal layer 12, and there is no need to use a surface activation process to reduce Cu2O to Cu before bonding, thereby avoiding production capacity loss.

[0051] In summary, the semiconductor device provided by the present invention comprises: a semiconductor structure, a bonding layer is formed on the semiconductor structure, the bonding layer comprises an insulating layer and a first metal layer formed in the insulating layer; an alloy protective layer is formed on the first metal layer, the alloy protective layer is an alloy of the first metal layer and the second metal layer, and the reduction potential of the second metal layer is lower than the reduction potential of the first metal layer. The semiconductor device of the present invention can prevent the surface of the metal layer in the bonding layer from being oxidized to metal oxide, and can avoid reducing the electrical connection performance between the metal layers on the two semiconductor structures after bonding.

[0052] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 3 , Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0053] Step S1, providing a semiconductor structure, on which a bonding layer is formed, wherein the bonding layer includes an insulating layer and a first metal layer formed in the insulating layer;

[0054] Step S2, forming a second metal layer on the first metal layer, wherein the reduction potential of the second metal layer is lower than the reduction potential of the first metal layer;

[0055] Step S3: performing an annealing process so that the second metal layer reacts with a portion of the first metal layer to form an alloy protection layer.

[0056] See below Figures 4 to 8 The method for manufacturing the semiconductor device provided in this embodiment is described in more detail. Figures 4 to 8 It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0057] According to step S1, Figure 4 As shown, a semiconductor structure 10 is provided. A bonding layer is formed on the semiconductor structure 10 . The bonding layer includes an insulating layer 11 and a first metal layer 12 formed in the insulating layer 11 .

[0058] The semiconductor structure 10 may include a substrate and an insulating dielectric layer formed on the substrate, and a metal interconnect structure 101 may be formed in the insulating dielectric layer.

[0059] Device structures such as MOS transistors, resistors, and capacitors may also be formed in the semiconductor structure 10 , and the metal interconnect structure 101 is electrically connected to the device structures.

[0060] The semiconductor structure 10 may be a wafer or a chip, and the material or device function of the semiconductor structure 10 is not limited herein.

[0061] The material of the insulating layer 11 may include at least one of insulating materials such as nitrogen-doped silicon carbide, silicon oxide, and silicon oxynitride.

[0062] Preferably, Figure 4 As shown, the first metal layer 12 extends into the semiconductor structure 10, so that the thickness of the first metal layer 12 is thick enough to improve the bonding strength when two subsequent semiconductor structures 10 are bonded. In other embodiments, the first metal layer 12 is only located in the insulating layer 11 and does not extend into the semiconductor structure 10.

[0063] In one embodiment, a plurality of spaced first metal layers 12 are formed in the insulating layer 11 , and bottom ends of at least some of the first metal layers 12 are electrically connected to the metal interconnection structure 101 .

[0064] The top surface of the first metal layer 12 is lower than the top surface of the insulating layer 11 , so that the top surface of the subsequently formed alloy protection layer 14 is lower than the top surface of the insulating layer 11 .

[0065] In one embodiment, when a chemical mechanical polishing process is used to planarize the surface of the bonding layer, since the corrosion rate of the polishing liquid used in the chemical mechanical polishing process on the first metal layer 12 is greater than the corrosion rate on the insulating layer 11, the top surface of the first metal layer 12 after polishing is lower than the top surface of the insulating layer 11.

[0066] According to step S2, Figure 5 As shown, a second metal layer 13 is formed on the first metal layer 12 , and a reduction potential of the second metal layer 13 is lower than a reduction potential of the first metal layer 12 .

[0067] The second metal layer 13 may be formed on the first metal layer 12 by a physical vapor deposition process, and the second metal layer 13 may also extend onto the insulating layer 11 .

[0068] In one embodiment, the thickness of the second metal layer 13 is

[0069] A top surface of the second metal layer 13 on the first metal layer 12 is lower than a top surface of the insulating layer 11 .

[0070] According to step S3, Figure 6 As shown, an annealing process is performed to allow the second metal layer 13 to react with a portion of the first metal layer 12 to form an alloy protection layer 14 .

[0071] The temperature of the annealing process may be 400°C to 800°C.

[0072] like Figure 7 As shown, after the second metal layer 13 reacts with a partial thickness of the first metal layer 12 to form the alloy protection layer 14, the unreacted second metal layer 13 on the surface of the insulating layer 11 is removed.

[0073] Among them, a highly selective etching solution can be used to etch and remove the unreacted second metal layer 13 on the surface of the insulating layer 11, so that the unreacted second metal layer 13 can be accurately removed without using a mask and the alloy protective layer 14 on the first metal layer 12 can be retained, achieving a self-alignment effect, and the alignment accuracy of the alloy protective layer 14 and the first metal layer 12 is high, and the alloy protective layer 14 can play a good protective role on the first metal layer 12.

[0074] Preferably, the etching selectivity ratio of the insulating layer 11 and the alloy protective layer 14 to the second metal layer 13 is 1:100 to 1:200, so that when etching away the unreacted second metal layer 13, the insulating layer 11 and the alloy protective layer 14 are avoided or only a small amount of etching is performed.

[0075] Since the reduction potential of the second metal layer 13 is lower than the reduction potential of the first metal layer 12, the property stability of the second metal layer 13 is higher than the property stability of the first metal layer 12, that is, compared with the first metal layer 12, the second metal layer 13 is less likely to be oxidized at room temperature, and the second metal layer 13 has stronger corrosion resistance, thereby improving the stability and corrosion resistance of the alloy protective layer 14, so that the alloy protective layer 14 can protect the surface of the first metal layer 12 from oxidation, and the alloy protective layer 14 itself is not easily oxidized.

[0076] Preferably, the resistivity of the second metal layer 13 is in the range of plus or minus 10 times the resistivity of the first metal layer 12, that is, the resistivity of the second metal layer 13 is close to the resistivity of the first metal layer 12, so as to avoid the resistivity of the second metal layer 13 being too high, which may lead to the resistivity of the alloy protective layer 14 being too high, thereby avoiding the conductivity of the alloy protective layer 14 being reduced and affecting the electrical connection performance between the first metal layers 12 in the two semiconductor structures 10 after subsequent bonding; the atomic radius of the second metal layer 13 is in the range of plus or minus 1.5 times the atomic radius of the first metal layer 12, so that the lattice of the first metal layer 12 and the second metal layer 13 are adapted, so that the stress of the first metal layer 12 and the second metal layer 13 are adapted and the bonding is better when forming an alloy, so that the stability of the formed alloy protective layer 14 is better.

[0077] The first metal layer 12 may include at least one of Cu, Al, and W, and the second metal layer 13 may include at least one of Ni, Co, and Ru.

[0078] The top surface of the alloy protective layer 14 is lower than the top surface of the insulating layer 11. When the two semiconductor structures 10 are subsequently bonded, the lattice of the first metal layer 12 will be reorganized under the action of high temperature, so that the volume of the first metal layer 12 will expand and increase. By defining the top surface of the alloy protective layer 14 to be lower than the top surface of the insulating layer 11, space can be provided for the volume expansion of the first metal layer 12, thereby preventing the volume expansion of the first metal layer 12 from cracking the bonding interface.

[0079] like Figure 8 As shown, the manufacturing method of the semiconductor device also includes: bonding two semiconductor structures 10, the insulating layers 11 on the two semiconductor structures 10 are in contact with each other, and the alloy protective layers 14 on the two semiconductor structures 10 are in contact with each other, so that the metal interconnection structures 101 in the two semiconductor structures 10 are electrically connected through the first metal layer 12 and the alloy protective layer 14.

[0080] The types of the two semiconductor structures 10 can be the same or different.

[0081] When bonding the two semiconductor structures 10 , the two semiconductor structures 10 are subjected to high temperature treatment, and the temperature may be 250° C. to 350° C.

[0082] From the above content, it can be known that by forming the second metal 13 on the first metal layer 12 in the bonding layer, the reduction potential of the second metal layer 13 is less than the reduction potential of the first metal layer 12, and the second metal layer 13 reacts with part of the first metal layer 12 to form the alloy protective layer 14, so that the alloy protective layer 14 can protect the first metal layer 12, avoiding the surface of the first metal layer 12 to be oxidized to form metal oxide before the two semiconductor structures 10 are bonded, thereby increasing the waiting time (Q time) before bonding; and the alloy protective layer 14 itself has good conductivity, which can avoid reducing the electrical connection performance between the first metal layers 12 on the two semiconductor structures 10 after bonding.

[0083] Among them, when the first metal layer 12 is Cu, there is no need to form Cu2O on the surface of the first metal layer 12 by adopting a chemical mechanical polishing process to protect the first metal layer 12, and there is no need to use a surface activation process to reduce Cu2O to Cu before bonding, thereby avoiding production capacity loss.

[0084] In summary, the method for manufacturing a semiconductor device provided by the present invention includes: providing a semiconductor structure, on which a bonding layer is formed, the bonding layer includes an insulating layer and a first metal layer formed in the insulating layer; forming a second metal layer on the first metal layer, the reduction potential of the second metal layer is less than the reduction potential of the first metal layer; performing an annealing process so that the second metal layer reacts with a portion of the first metal layer to form an alloy protective layer. The method for manufacturing a semiconductor device of the present invention can prevent the surface of the metal layer in the bonding layer from being oxidized into metal oxide, and can avoid reducing the electrical connection performance between the metal layers on the two semiconductor structures after bonding.

[0085] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor structure having a bonding layer formed thereon, the bonding layer comprising an insulating layer and a first metal layer formed in the insulating layer; The alloy protective layer is formed on the first metal layer. The alloy protective layer is an alloy of the first metal layer and a second metal layer. The reduction potential of the second metal layer is lower than the reduction potential of the first metal layer.

2. The semiconductor device according to claim 1, wherein The resistivity of the second metal layer is within a range of plus or minus 10 times the resistivity of the first metal layer, and the atomic radius of the second metal layer is within a range of plus or minus 1.5 times the atomic radius of the first metal layer.

3. The semiconductor device according to claim 2, wherein: The first metal layer includes at least one of Cu, Al and W, and the second metal layer includes at least one of Ni, Co and Ru.

4. The semiconductor device according to claim 1, wherein A top surface of the alloy protection layer is lower than a top surface of the insulating layer.

5. The semiconductor device according to claim 1, wherein The semiconductor device comprises: The two semiconductor structures are bonded together, the insulating layers on the two semiconductor structures are in contact with each other, and the alloy protection layers on the two semiconductor structures are in contact with each other.

6. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor structure, on which a bonding layer is formed, the bonding layer comprising an insulating layer and a first metal layer formed in the insulating layer; forming a second metal layer on the first metal layer, wherein the reduction potential of the second metal layer is lower than the reduction potential of the first metal layer; An annealing process is performed to allow the second metal layer to react with a portion of the first metal layer to form an alloy protection layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The resistivity of the second metal layer is within a range of plus or minus 10 times the resistivity of the first metal layer, and the atomic radius of the second metal layer is within a range of plus or minus 1.5 times the atomic radius of the first metal layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The first metal layer includes at least one of Cu, Al and W, and the second metal layer includes at least one of Ni, Co and Ru.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: A top surface of the alloy protection layer is lower than a top surface of the insulating layer.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The thickness of the second metal layer is 11. The method for manufacturing a semiconductor device according to claim 6, wherein: The method for manufacturing the semiconductor device further includes: The two semiconductor structures are bonded together, so that the insulating layers on the two semiconductor structures are in contact with each other, and the alloy protection layers on the two semiconductor structures are in contact with each other.

Images