FLASH chip three-dimensional stacked packaging structure and packaging method

Abstract

The invention discloses a FLASH chip three-dimensional stacked packaging structure and packaging method, and belongs to the technical field of semiconductor chip packaging. Through wafer rewiring of a FLASH chip, a multi-layer wiring substrate and a lead bonding technology, front electrodes of the FLASH chip are led out to the front surface of the chip and the back surface of the multi-layer substrate according to setting by utilizing the wafer rewiring technology, copper pillar bumps are formed for interconnection during stacking, the copper pillar bumps are interconnected with the multi-layer substrate through lead bonding, and the chip is packaged by utilizing a flip packaging technology. And the substrate BGA and the copper pillar bumps are interconnected to realize chip vertical stacking integration. The problems that in the prior art, chips are stacked in a staggered mode or vertically stacked on a multi-layer substrate, interconnection welding is difficult, electrode number layout is limited, thermal expansion coefficients of materials are not matched, and packaging cost is high are solved, and FLASH chip stacking packaging with high packaging density is achieved. The method is widely applied to the technical field of high-performance and low-cost microsystem SiP packaging.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor chip packaging technology, and further relates to the field of semiconductor chip three-dimensional packaging technology, and specifically, to a three-dimensional stacking packaging structure and packaging method of a FLASH chip. Background Art

[0002] Embedded FLASH memory simplifies the design and connection process by integrating storage chips, controllers and interfaces, providing convenient, compact and highly integrated storage solutions, and is widely used in embedded systems and mobile devices. In order to meet the demand for low-cost FLASH chip packaging with high integration and miniaturization, three-dimensional stacking packaging technology is one of the most important packaging technologies at present. The most widely used three-dimensional stacking packaging technology is to achieve chip stacking through rewiring, bumping and through silicon via technology, but this type of packaging technology is relatively expensive and is only suitable for HBM-type high-integration storage stacking packaging. For memory chips with medium and low packaging density (such as eMMC chips), the cost of stacking through rewiring, bumping and through silicon via technology is relatively high. Therefore, based on the low-cost advantages of traditional packaging and the flexibility advantages of rewiring and bumping, the realization of medium and low-density memory chip stacking packaging is a technical problem that needs to be broken through.

[0003] Original technical defects: Driven by the demand for high performance, miniaturization, and modularization of chips in electronic devices, the traditional multi-FLASH chip two-dimensional system integration method can no longer meet these demands. Figure 1As shown, although the current packaging process design has achieved multi-layer chip stacking, it is difficult to integrate memory chips with higher packaging density due to the number and layout of electrodes of the packaged chip. For example, the Chinese patent with application number CN117790483A discloses a computing and storage integrated chip stacking packaging structure, which realizes the integration of computing power chips and memory chips by stacking the chips on a carrier (multi-layer substrate) in a staggered manner, interconnecting the chip and the carrier through wire bonding, and interconnecting the back of the carrier through BGA. The Chinese patent with application number CN117612952A discloses an LGA packaging stacking method and structure, which mainly forms a stepped mold through soft glue, and then stacks the chip in a Z shape on the mold, and interconnects them through wire bonding. Both methods realize the stacking packaging of memory chips through staggered stacking. This type of staggered stacking packaging structure has great limitations and limited applications. A Chinese patent application numbered CN117878064A discloses a vertical stacking method, in which memory chip leads are bonded to a substrate, chip electrodes are distributed on the back of the substrate using rewiring technology, and an intermediate stacked chip-substrate structure with a vertical interconnection structure is produced in the same manner. This type of solution makes interconnection welding difficult during stacking, and the rewiring and interconnection structure production are performed after mounting on the substrate. Due to the mismatch in thermal expansion coefficients between different materials, the stacking structure has a high risk of misalignment.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The technical problem to be solved by the present invention is to solve the problems in the prior art of stacking chips in an offset manner or vertically stacking them on a carrier (multi-layer substrate), difficulty in interconnection welding, limited layout of the number of electrodes, mismatch in thermal expansion coefficients between materials, and high packaging costs.

[0006] The inventive concept of the present invention is: through wafer rewiring, multi-layer wiring substrate and wire bonding technology, the front electrode of the FLASH chip is divided into two, and is led out to the front side of the chip and the back side of the multi-layer substrate respectively, and the FLASH chip electrode is led out as a double electrode by using wafer rewiring technology, and interconnected by forming copper pillar bumps for stacking, and interconnected with the multi-layer substrate through wire bonding, and use flip-chip packaging technology to interconnect the substrate BGA and the copper pillar bumps to realize vertical stacking integration of chips.

[0007] To this end, the present invention provides a FLASH chip three-dimensional stacking packaging structure, such as Figure 2 As shown. Includes: FLASH chip 1, electrode 101 on chip, chip surface redistribution layer 2, chip surface redistribution passivation layer 3, chip surface redistribution interconnection copper pillar 4, multi-layer substrate 5, wiring circuit 501 in substrate, chip bonding layer 6, bonding wire 7, plastic encapsulation layer 8, substrate BGA9, interlayer filling layer 10.

[0008] The back side of the multi-layer substrate 5 is a substrate BGA9, and the front side is a chip bonding area and a wire bonding area. The substrate BGA9 is correspondingly connected to the chip bonding area and the wire bonding area through a wiring circuit 501 in the substrate.

[0009] The FLASH chip 1 is bonded to the chip bonding area via a chip bonding layer 6 .

[0010] The chip surface rewiring passivation layer 3 is located on the surface of the FLASH chip 1 .

[0011] The chip surface redistribution layer 2 is located on the surface of the chip surface redistribution passivation layer 3, and the wire bonding area on the surface of the chip surface redistribution layer 2 and the chip surface redistribution interconnection copper pillars 4 are correspondingly connected to the electrodes on the chip surface (electrodes 101 on the chip).

[0012] The wire bonding area on the surface of the chip surface redistribution layer 2 and the wire bonding area on the front surface of the multi-layer substrate 5 are bonded and connected through bonding wires 7 according to circuit connection regulations.

[0013] The plastic encapsulation layer 8 seals the bonded substrate and chip, with the chip surface rewiring interconnection copper pillars 4 exposed on the upper surface and the substrate BGA 9 exposed on the bottom surface, forming a FLASH chip packaging unit.

[0014] There are more than two FLASH chip packaging units, and an interlayer filling layer 10 is provided between two adjacent layers of FLASH chip packaging units, which are connected by welding through an upper substrate BGA9 and a redistribution interconnection copper pillar 4 on the surface of a lower chip.

[0015] The packaging method of the FLASH chip three-dimensional stacking packaging structure is as follows: Figure 3-4 As shown. The following steps are included: Step S1: multi-layer wiring substrate manufacturing and FLASH chip wafer preparation; Step S2: rewiring is performed on the surface of the FLASH wafer, and the electrodes on the FLASH chip are led out to the designed positions through rewiring; Step S3: copper pillars are fabricated on the middle layer and the bottom redistribution layer except the top layer; Step S4: Thinning and dicing the FLASH wafer after rewiring and copper pillar fabrication; Step S5: mounting the thinned FLASH chip onto the multi-layer substrate; Step S6: interconnecting the rewiring lead-out electrodes and the multi-layer substrate design electrodes through wire bonding; Step S7: Protect the wire bonding structure with a plastic layer to expose the top copper column and the back of the substrate; Step S8: performing metal BGA ball planting on the back of the substrate to form a FLASH chip packaging unit; Step S9: according to the setting, with the top FLASH chip packaging unit as the base and the BGA facing upward, the top of the set layer FLASH chip packaging unit is sequentially soldered to the corresponding position of the bottom BGA of the lower layer chip by flip-chip method; Step S10: filling an interlayer filling layer 10 between the FLASH chip packaging units and curing the interlayer filling layer 10 to obtain a FLASH chip with a three-dimensional stacked packaging structure.

[0016] Technical effects of the present invention: The FLASH chip electrodes are rearranged into a dual-electrode structure through wafer rewiring and bump technology, the bottom of the chip is interconnected using wire bonding technology, and the top of the chip is interconnected through flip-chip packaging technology, thereby realizing three-dimensional stacking of FLASH chips.

[0017] The traditional method of staggered stacking + wire bonding interconnection is changed to achieve low-cost three-dimensional vertical stacking and reduce the packaging area through mature and low-cost wafer rewiring process, flip chip process and wire bonding process.

[0018] It breaks through the limitations of the traditional FLASH chip staggered stacking packaging structure and avoids the use of expensive wafer-level 3D packaging technology.

[0019] While achieving high-density packaging, the packaging volume is also reduced.

[0020] It realizes high packaging density and low-cost FLASH chip stacking packaging. The stacking quantity is larger than the traditional offset wire bonding stacking, and the finished package volume is smaller. The stacking packaging cost is lower than the wafer-level 3D packaging, and the packaging process technology is less difficult.

[0021] It can be widely used in the field of high-performance, low-cost microsystem SiP packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the existing FLASH chip stacking packaging structure.

[0023] Figure 2 It is a schematic diagram of the three-dimensional stacking packaging structure of the FLASH chip of the present invention.

[0024] Figure 3 It is a schematic diagram of the flowchart of the three-dimensional stacking packaging process of FLASH chips of the present invention.

[0025] Figure 4 It is a schematic diagram of the structure of the 3D stacking packaging process of FLASH chips of the present invention.

[0026] Figure 5 It is a schematic diagram of the middle layer wiring structure of the single FLASH chip stacking package of the present invention.

[0027] Figure 6 It is a schematic diagram of the middle layer wiring structure of the dual FLASH chip stacking package of the present invention.

[0028] Figure 7 It is a schematic diagram of the intermediate layer bump array of the single FLASH chip stacking package of the present invention.

[0029] In the figure: 1 is a FLASH chip (referred to as chip), 101 is an electrode on the chip, 2 is a chip surface redistribution layer (referred to as redistribution layer), 3 is a chip surface redistribution passivation layer (referred to as passivation layer), 4 is a chip surface redistribution interconnection copper pillar (referred to as copper pillar bump or copper pillar), 401 is a copper pillar metal barrier layer (referred to as barrier layer), 5 is a multi-layer substrate (referred to as substrate), 501 is a wiring circuit in the substrate, 6 is a chip bonding layer, 7 is a bonding lead (referred to as lead or bonding wire), 8 is a plastic encapsulation layer, 9 is a substrate BGA (referred to as BGA), and 10 is an interlayer filling layer (referred to as filling layer). DETAILED DESCRIPTION

[0030] like Figure 2-7 As shown, the three-dimensional stacking packaging structure and packaging method of the FLASH chip are specifically implemented as follows: The FLASH chip is square and has a size of 3mm*3mm to 15mm*15mm.

[0031] The redistribution layer leads the chip electrodes to form interconnected dual electrodes, namely the first electrode and the second electrode. The first electrode is used for stacking to interconnect the corresponding electrodes of the multi-layer substrate by wire bonding, and the second electrode is used for stacking to interconnect the corresponding electrodes of the multi-layer substrate by flip-chip bonding. The electrode density is 10 pin / mm 2 ~200 pin / mm 2 The material of the redistribution is copper, and the electrode is formed on the surface of the redistribution by electrochemical copper plating, chemical nickel-palladium-gold plating, etc. The redistribution line width is 2μm~30μm, the redistribution line spacing is 2μm~30μm, and the redistribution thickness is 1μm~20μm.

[0032] The copper pillar bumps are cubic or cylindrical, with a width / diameter of 80 μm to 600 μm, a height higher than the height of the plastic package, a distribution range for the inside of the wire bonding electrode, and distribution types include annular distribution, array distribution, and the like.

[0033] The metal barrier layer is located on the top surface of the copper column bump, and the barrier layer is a nickel barrier layer with a thickness of 1 μm to 5 μm.

[0034] The multi-layer substrate includes a ceramic substrate with multi-layer wiring (multi-layer co-fired ceramic substrate), an organic substrate, etc. The multi-layer substrate is wired internally by copper metal. The upper electrode is higher than the substrate plane and is distributed in the edge area around the multi-layer substrate. The electrode size is 40μm *40μm~600μm *600μm, and the electrode material is copper, copper-nickel-gold and other structures.

[0035] The lead wire (bonding wire) is a copper wire, a gold wire, etc., and the wire diameter (wire diameter) is 10 μm to 30 μm.

[0036] The number of chips mounted on each layer of the multi-layer substrate is at least 1.

[0037] The BGA ball diameter is consistent with the copper column bump width or diameter, and the material of the BGA is tin-lead, tin-silver-copper, etc.

[0038] The single chip structure of each layer is as follows: The 12-inch wafer that has completed the FLASH chip manufacturing is rewired, and the electrodes on the chip are led out to the designed position through rewiring, and present a double electrode shape (first electrode, second electrode). The rewiring layer is made of copper, and the seed layer is deposited by magnetron sputtering, and then produced by electrochemical deposition. The line width / line spacing is 10μm / 10μm and the thickness is 5μm.

[0039] The first electrode is evenly distributed around the FLASH chip, with a size of 65μm*65μm, made of copper, and the electrode height is 10μm higher than the passivation layer; The second electrode is evenly distributed inside the first electrode of the FLASH chip. A cylindrical copper column is made on the second electrode, with a diameter of 90 μm and a height of 100 μm, and a metal nickel barrier layer with a thickness of 3 μm is covered on the copper column by electrochemical deposition.

[0040] The FLASH wafer that has completed rewiring and copper pillar production is thinned and diced to a thickness of 150μm. The chip size after dicing is 12mm*4.9mm; The substrate is a LTCC multi-layer co-fired ceramic substrate. The front electrodes are distributed around the substrate, and the back electrodes are distributed directly below the second electrode of the mounted FLASH chip. The electrode size is 80μm*80μm*20μm and the material is copper. The substrate size is 13.5mm*6.5mm*0.2mm; Then the diced chip is mounted on the LTCC multi-layer co-fired ceramic substrate, and the first electrode is interconnected with the front electrode of the multi-layer substrate through a copper wire with a wire diameter of 20μm, and epoxy molding compound (EMC) molding (abbreviated as EMC molding) is performed to protect the wire bonding structure. The copper column is higher than the overall molding height.

[0041] BGA ball planting is performed on the back electrode of the multi-layer substrate. The material is SAC305 and the ball diameter is 120μm to obtain a stacked chip structure layer.

[0042] The stacked chip structure layers are stacked and integrated by flip-chip welding according to the set structure, and finally the interlayer filling is performed to obtain a four-layer single FLASH chip stacking packaging structure.

[0043] The double chip structure of each layer is as follows: The 12-inch wafer that has completed the FLASH chip manufacturing is rewired, and the electrodes on the chip are led out to the designed position through rewiring, and present a double electrode shape (first electrode, second electrode). The rewiring layer is made of copper, and the seed layer is deposited by magnetron sputtering and then produced by electrochemical deposition. The line width / line spacing is 10μm / 10μm and the thickness is 5μm.

[0044] The first electrode is evenly distributed around the FLASH chip, with a size of 65μm*65μm, made of copper, and the electrode height is 10μm higher than the passivation layer; The second electrode is evenly distributed inside the first electrode of the FLASH chip. A cylindrical copper column is made on the second electrode, with a diameter of 90 μm and a height of 100 μm, and a metal nickel barrier layer with a thickness of 3 μm is covered on the copper column by electrochemical deposition.

[0045] The FLASH wafer that has completed rewiring and copper pillar production is thinned and diced to a thickness of 150μm. The chip size after dicing is 12mm*4.9mm; The substrate is a LTCC multi-layer co-fired ceramic substrate. The front electrodes are distributed around the substrate, and the back electrodes are distributed directly below the second electrode of the mounted FLASH chip. The electrode size is 80μm*80μm*20μm. The front electrode material of the substrate is copper-nickel-gold, and the back electrode material is copper. The substrate size is 13.5mm*13.5mm*0.2mm, and the chip spacing is 1mm.

[0046] Then the diced chip is mounted on the LTCC ceramic multilayer substrate, and the first electrode is interconnected with the front electrode of the multilayer substrate through gold wire bonding with a wire diameter of 18 μm, and EMC plastic sealing is performed to protect the wire bonding structure. The copper column is higher than the overall plastic sealing height.

[0047] BGA ball planting is performed on the back electrode of the multi-layer substrate. The material is SAC305 and the ball diameter is 120μm to obtain a stacked chip structure layer.

[0048] The stacked chip structure layers are stacked and integrated by flip-chip welding according to the set structure, and finally the interlayer filling is performed to obtain a four-layer dual FLASH chip stacking packaging structure.

[0049] The present invention can achieve an electrode density of 10 pin / mm 2 ~200pin / mm 2 The stacked FLASH chip packaging has a larger stacking quantity than the traditional staggered wire bonding stacking, and the finished package volume is smaller; the stacked packaging cost is lower than the wafer-level 3D packaging, and the packaging process technology is less difficult.

[0050] Finally, it should be noted that the above embodiments are merely examples for the purpose of clear explanation. The present invention includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods exhaustively. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. All implementation methods that meet the requirements of the present invention belong to the protection scope of the present invention.

Claims

1. A FLASH chip three-dimensional stacking packaging structure, characterized in that: Including FLASH chip, chip surface rewiring layer, chip surface rewiring passivation layer, chip surface rewiring interconnect copper pillars, multi-layer substrate, chip bonding layer, bonding wire, plastic sealing layer, substrate BGA, interlayer filling layer; The back of the multi-layer substrate is a substrate BGA, and the front is a chip bonding area and a lead bonding area. The substrate BGA is correspondingly connected to the chip bonding area and the lead bonding area through a wiring circuit in the substrate; The FLASH chip is bonded to the chip bonding area via a chip bonding layer; The chip surface rewiring passivation layer is located on the surface of the FLASH chip; The chip surface redistribution layer is located on the surface of the chip surface redistribution passivation layer, and the wire bonding area on the surface of the chip surface redistribution layer and the chip surface redistribution interconnection copper pillars are correspondingly connected to the chip electrodes on the chip surface; The wire bonding area on the surface of the chip surface redistribution layer is bonded to the wire bonding area on the front side of the multi-layer substrate through bonding wires according to circuit connection regulations; The plastic sealing layer seals the bonded substrate and chip, with the chip surface rewiring interconnection copper pillars exposed on the upper surface and the substrate BGA exposed on the bottom surface, forming a FLASH chip packaging unit; There are more than two FLASH chip packaging units, and an interlayer filling layer is provided between two adjacent layers of FLASH chip packaging units, which are welded and connected with the upper layer substrate BGA and the lower layer chip surface rewiring interconnection copper pillars.

2. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The FLASH chip is square and has a size of 3mm*3mm to 15mm*15mm.

3. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The redistribution layer leads the chip electrode to form an interconnected first electrode and a second electrode, and the electrode density of the redistribution layer is 10 pin / mm 2 ~200 pin / mm 2 The redistribution line width is 2μm~30μm, the redistribution line spacing is 2μm~30μm, and the redistribution thickness is 1μm~20μm.

4. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The wire material of the redistribution layer is copper, and the electrodes of the redistribution layer are formed on the surface of the redistribution layer by electrochemical copper plating or chemical nickel-palladium-gold plating.

5. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The copper pillar is located inside the wire bonding electrode, and the distribution type is annular distribution or array distribution; the copper pillar is cubic or cylindrical, with a width / diameter of 80 μm to 600 μm, and a height higher than the thickness of the plastic package.

6. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The top surface of the copper column is a metal barrier layer.

7. The FLASH chip three-dimensional stacking packaging structure according to claim 6, characterized in that: The barrier layer is a nickel barrier layer, and the thickness of the nickel layer is 1 μm to 5 μm.

8. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The multi-layer substrate is a multi-layer co-fired ceramic substrate or a multi-layer organic substrate. The multi-layer substrate is wired internally by copper metal. The upper electrode is higher than the substrate plane and is distributed in the edge area around the multi-layer substrate. The electrode size is 40μm*40μm~600μm*600μm, and the electrode material is copper or copper-nickel-gold.

9. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The lead wire is a copper wire or a gold wire, and the wire diameter is 10 μm to 30 μm.

10. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The number of chips mounted on each layer of the multi-layer substrate is at least 1.

11. The FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The ball diameter of the BGA is consistent with the width or diameter of the copper column, and the material of the BGA is tin-lead alloy or tin-silver-copper alloy.

12. The packaging method of a FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The following steps are involved: Step S1: multi-layer wiring substrate manufacturing and FLASH chip wafer preparation; Step S2: rewiring is performed on the surface of the FLASH wafer, and the electrodes on the FLASH chip are led out to the designed positions through rewiring; Step S3: fabricating copper pillars on the redistribution layer; Step S4: Thinning and dicing the FLASH wafer after rewiring and copper pillar fabrication; Step S5: mounting the thinned FLASH chip onto the multi-layer substrate; Step S6: interconnecting the rewiring lead-out electrodes and the multi-layer substrate design electrodes through wire bonding; Step S7: Protect the wire bonding structure with a plastic layer to expose the top copper column and the back of the substrate; Step S8: performing metal BGA ball planting on the back of the substrate to form a FLASH chip packaging unit; Step S9: according to the setting, with the top FLASH chip packaging unit as the base and the BGA facing upward, the top of the set layer FLASH chip packaging unit is sequentially soldered to the corresponding position of the bottom BGA of the lower layer chip by flip-chip method; Step S10: filling an interlayer filling layer 10 between the FLASH chip packaging units and curing the interlayer filling layer 10 to obtain a FLASH chip with a three-dimensional stacked packaging structure.

13. The packaging method of a FLASH chip three-dimensional stacking packaging structure according to claim 1, characterized in that: The redistribution layer is firstly produced by magnetron sputtering to deposit a seed layer and then by electrochemical deposition, with a line width / line spacing of 10 μm / 10 μm and a thickness of 5 μm.

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