Semiconductor structure, mask set and monitoring method of photoetching process

Abstract

The invention relates to a semiconductor structure, a mask set and a monitoring method of a photoetching process. The semiconductor structure comprises a pattern area and a cutting channel located on at least one side of the pattern area. The semiconductor structure further comprises a design pattern located in the pattern area and a monitoring pattern located in the cutting channel. Wherein the monitoring pattern comprises a spliced pattern formed by overlapping at least two patterns to be detected. According to the semiconductor structure, whether the exposure process or the etching process is normal can be judged by comparing the contour difference of the overlapping region and the non-overlapping region of the pattern to be detected. Therefore, the photoetching process can be monitored simply and efficiently, and the yield of chips can be ensured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a monitoring method for a semiconductor structure, a mask set, and a photolithography process. Background Art

[0002] In the chip lithography process, high aspect ratio lithography has always been a problem for the lithography process due to the limited penetration depth of the light source. High aspect ratio photoresists are prone to incomplete development. If it is not discovered and improved in time, it will inevitably affect the chip yield.

[0003] From the above, how to monitor the photolithography process simply and efficiently has become a difficult problem that needs to be solved urgently in related technologies. Summary of the invention

[0004] Based on this, the embodiments of the present disclosure provide a method for monitoring a semiconductor structure, a mask set, and a photolithography process, which can simply and efficiently monitor the photolithography process, thereby facilitating ensuring the yield of the chip.

[0005] Some embodiments of the present disclosure provide a semiconductor structure, including: a pattern area and a cutting path located on at least one side of the pattern area. The semiconductor structure also includes: a design pattern located in the pattern area, and a monitoring pattern located on the cutting path. The monitoring pattern includes: a spliced ​​pattern formed by overlapping at least two patterns to be tested.

[0006] In some embodiments of the present disclosure, different patterns to be tested within a same monitoring pattern are formed using different exposure processes or different etching processes.

[0007] In some embodiments of the present disclosure, the semiconductor structure further includes: at least two reference patterns located on the cutting path, wherein the reference patterns correspond to the patterns to be tested one by one, and the reference patterns and the corresponding patterns to be tested have the same shape and feature size.

[0008] In some embodiments of the present disclosure, the number of pattern areas is at least two. The monitoring pattern is located in the cutting path between adjacent pattern areas. Each pattern to be tested in the monitoring pattern has the same shape and characteristic size as the corresponding design pattern in the adjacent pattern area.

[0009] In some embodiments of the present disclosure, each pattern to be tested in the same monitoring pattern corresponds to an adjacent pattern area one by one. Each pattern to be tested in the same monitoring pattern overlaps in the same area.

[0010] In some embodiments of the present disclosure, the shapes and characteristic sizes of the patterns to be tested within the same monitoring pattern are the same.

[0011] In some embodiments of the present disclosure, the pattern to be tested includes a linear pattern or a hole-shaped pattern.

[0012] Some embodiments of the present disclosure also provide a mask set for preparing a semiconductor structure as described in any of the above embodiments, wherein the mask set includes at least two masks, each of which has a mask pattern corresponding to a design pattern and any pattern to be tested in a monitoring pattern.

[0013] In some embodiments of the present disclosure, different masks have mask patterns corresponding to the same design pattern.

[0014] Some embodiments of the present disclosure also provide a method for monitoring a photolithography process, comprising the following steps:

[0015] Providing a substrate, the substrate having a pattern area and a cutting path located on at least one side of the pattern area;

[0016] forming a photoresist layer on a substrate;

[0017] Expose and develop the photoresist layer in the pattern area to form a design pattern, and simultaneously expose and develop the photoresist layer in the cutting path to form a monitoring pattern; wherein the monitoring pattern includes: a spliced ​​pattern formed by overlapping at least two patterns to be tested, and different patterns to be tested are formed by at least using different exposure processes;

[0018] Observe the development contour of the overlapping area of ​​the pattern to be tested in the monitoring pattern;

[0019] Based on the observation results of the development profile, it is determined whether there is any abnormality in the exposure process of the design pattern in the pattern area.

[0020] In some embodiments of the present disclosure, the method for monitoring a photolithography process further includes:

[0021] While forming the monitoring pattern, exposing and developing in the photoresist layer of the cutting path to form at least two reference patterns;

[0022] The reference pattern and the pattern to be tested correspond one to one, and the reference pattern and the corresponding pattern to be tested have the same shape and characteristic size reference pattern;

[0023] While observing the development profile of the overlapping area of ​​the pattern to be tested in the monitoring pattern, the development profile of the reference pattern is observed.

[0024] Among them, determining whether there is an abnormality in the exposure process based on the observation results of the development profile also includes: using the observation results of the development profile of the reference pattern as a reference to determine whether there is an abnormality in the development profile of the overlapping area of ​​the to-be-tested pattern in the monitoring pattern, so as to determine the abnormality of the corresponding exposure process based on the abnormality of the development profile.

[0025] In some embodiments of the present disclosure, determining whether there is an abnormality in the exposure process includes: determining whether the exposure amount of the exposure process is sufficient.

[0026] The monitoring method further includes: determining whether the development of the photoresist layer is complete according to the observation result of the development profile.

[0027] In some embodiments of the present disclosure, the method for monitoring a photolithography process further includes:

[0028] When there is no abnormality in the exposure process, the design pattern is transferred to the substrate by an etching process to form a target pattern, and the monitoring pattern is transferred to the substrate to form a photolithography monitoring pattern;

[0029] Observe the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern;

[0030] Based on the observation results of the etching profile, determine whether there is any abnormality in the etching process.

[0031] In some embodiments of the present disclosure, the method for monitoring a photolithography process further includes:

[0032] Based on the observation results of the etching profile, the bottom morphology of the target pattern is determined.

[0033] In some embodiments of the present disclosure, observation results of the development profile of the overlapping area of ​​the pattern to be tested in the monitoring pattern and observation results of the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern are both obtained by scanning electron microscope observation.

[0034] The embodiments of the present disclosure may or at least have the following advantages:

[0035] The monitoring method of the semiconductor structure, mask set and photolithography process provided by the embodiment of the present disclosure is as above. In the embodiment of the present disclosure, a spliced ​​pattern formed by overlapping at least two patterns to be tested is arranged in the cutting path, wherein, since the cutting path is arranged between different pattern areas, the overlapping area of ​​the pattern to be tested in the cutting path can be exposed at least twice or etched at least twice. In this way, by comparing the contour difference between the overlapping area and the non-overlapping area of ​​the pattern to be tested, it can be clearly judged whether the exposure process or the etching process is normal. Thereby, the photolithography process can be monitored online simply and efficiently, which is conducive to ensuring the yield of the chip. In addition, a reference pattern corresponding to the pattern to be tested is also arranged in the cutting path. In this way, by comparing the contour difference between the pattern to be tested and the reference pattern, the influencing factors of the abnormal exposure process or etching process can be further analyzed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] FIG. 1( a ) is a schematic top view of a semiconductor structure provided in one embodiment;

[0038] FIG1( b ) is a schematic top view of another semiconductor structure provided in one embodiment;

[0039] Figure 2 is a schematic top view of another semiconductor structure provided in an embodiment;

[0040] Figure 3 is a schematic top view of another semiconductor structure provided in an embodiment;

[0041] Figure 4 is a schematic top view of another semiconductor structure provided in an embodiment;

[0042] Figure 5 is a schematic top view of another semiconductor structure provided in an embodiment;

[0043] Figure 6 is a schematic top view of another semiconductor structure provided in an embodiment;

[0044] Figure 7 is a schematic diagram of a top view of a mask set provided in an embodiment;

[0045] Figure 8 is a flow chart of a method for monitoring a photolithography process provided in an embodiment;

[0046] Fig. 9 is a flow chart of another method for monitoring a photolithography process provided in an embodiment;

[0047] Fig.10 A schematic diagram of a top view of a structure obtained in step S100 of a method for monitoring a photolithography process provided in an embodiment;

[0048] FIG. 11( a ) is a schematic diagram of a top view of a structure obtained in step S200 in a method for monitoring a photolithography process provided in one embodiment; FIG. 11( b ) is a schematic diagram of a cross-sectional structure of a structure obtained in step S200 in a method for monitoring a photolithography process provided in one embodiment;

[0049] Fig.12 Schematic diagram of a top view of a structure obtained in step S300 of a method for monitoring a photolithography process provided in an embodiment;

[0050] FIG13(a) is a scanning electron microscope image of a structure obtained in step S400 of a method for monitoring a photolithography process provided in one embodiment, viewed from above along the aa' direction; FIG13(b) is a schematic diagram of a cross-sectional structure of a structure obtained in step S400 of a method for monitoring a photolithography process provided in one embodiment, viewed from above along the bb' direction; FIG13(c) is a scanning electron microscope image of another structure obtained in step S400 of a method for monitoring a photolithography process provided in one embodiment, viewed from above along the aa' direction; FIG13(d) is a schematic diagram of a cross-sectional structure of another structure obtained in step S400 of a method for monitoring a photolithography process provided in one embodiment, viewed from above along the bb' direction;

[0051] Fig.14 FIG. 1 is a schematic diagram of a top view of a structure obtained in step S600 in a method for monitoring a photolithography process provided in an embodiment.

[0052] Description of reference numerals:

[0053] 1, 1a, 1b-design graphics; 11-first design graphics; 12-second design graphics; 13-third design graphics; 14-fourth design graphics;

[0054] 2, 2a, 2b, 2c, 2d, 2e-monitoring pattern; 21, 21a, 21b, 21c, 21d, 21e-first pattern to be tested; 22, 22a, 22b, 22c, 22d, 22e-second pattern to be tested; 23-third pattern to be tested; 200-photoresist layer; 300-oxide layer; (2e-monitoring pattern 21e-first pattern to be tested 22e-second pattern to be tested is not found in the figure)

[0055] 31, 31a, 31b, 31c, 31d, 31e-first reference pattern; 32, 32a, 32b, 32c, 32d, 32e-second reference pattern; 4-substrate;

[0056] P-pattern area; P1-first pattern area; P2-second pattern area;

[0057] S-cutting line; S1-first cutting line; S2-second cutting line; S3-third cutting line; S4-fourth cutting line;

[0058] Y1-first mask; Y2-second mask; O-overlapping area of ​​the pattern to be tested;

[0059] K11, K12, K21, K22, K31, K32-opening pattern;

[0060] M-target pattern; N1-lithography monitoring pattern; N21, N22-lithography reference patterns. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0063] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0064] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0065] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0066] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0067] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0068] In the chip lithography process, high aspect ratio lithography has always been a problem for the lithography process due to the limited penetration depth of the light source. When the aspect ratio is less than 3, the photoresist usually develops well and there is no photoresist residue. However, when the aspect ratio is greater than 3, the photoresist may not be fully developed. When the high aspect ratio photoresist is not fully developed, if it is not discovered and improved in time, it will inevitably affect the chip yield.

[0069] From the above, how to monitor the photolithography process simply and efficiently has become a difficult problem that needs to be solved urgently in related technologies.

[0070] Based on this, the embodiments of the present disclosure provide a method for monitoring a semiconductor structure, a mask set, and a photolithography process, which can simply and efficiently monitor the photolithography process, thereby facilitating ensuring the yield of the chip.

[0071] Referring to FIG. 1( a ), some embodiments of the present disclosure provide a semiconductor structure, including: a pattern area P and a cutting path S located on at least one side of the pattern area P. The semiconductor structure also includes: a design graphic 1 located in the pattern area P, and a monitoring graphic 2 located on the cutting path S. The monitoring graphic 2 includes: a spliced ​​graphic formed by overlapping at least two graphics to be tested. For example, the monitoring graphic 2 includes a spliced ​​graphic formed by overlapping a first graphic to be tested 21 and a second graphic to be tested 22.

[0072] For example, different patterns to be tested within the same monitoring pattern 2 are formed by using different exposure processes or different etching processes.

[0073] Here, it can be understood that in some examples, the monitoring pattern 2 is a photoresist pattern, and different patterns to be tested in the monitoring pattern 2 can be formed by different exposure processes. In other examples, the monitoring pattern 2 is an etching pattern, and different patterns to be tested in the monitoring pattern 2 can be formed by different etching processes. In this way, the abnormality of the corresponding process can be judged by the contour shape of the monitoring pattern 2.

[0074] In the disclosed embodiment, a spliced ​​pattern formed by overlapping at least two patterns to be tested is arranged in the cutting path S, wherein, since the cutting path S is arranged between different pattern areas P, the overlapping area of ​​the pattern to be tested in the cutting path S can be exposed at least twice or etched at least twice. In this way, by comparing the contour difference between the overlapping area and the non-overlapping area of ​​the pattern to be tested, it can be clearly judged whether the corresponding exposure process or etching process is normal. Thus, the photolithography process can be monitored online in a simple and efficient manner, which is conducive to ensuring the yield of the chip.

[0075] Here, it should be particularly noted that in the semiconductor structure shown in FIG. 1(a), the monitoring pattern 2 is illustrated as an example in which only two patterns to be tested overlap to form a spliced ​​pattern, but it does not mean that the monitoring pattern 2 can only overlap two patterns to be tested. For example, the monitoring pattern 2 can be formed by the overlap of 3 or 4 patterns to be tested. Please refer to FIG. 1(b), the monitoring pattern 2 can be formed by the overlap of a first pattern to be tested 21, a second pattern to be tested 22 and a third pattern to be tested 23, and the monitoring pattern 2 in the cutting path S includes the first pattern to be tested 21, the second pattern to be tested 22, the third pattern to be tested 23 and a spliced ​​pattern formed by the overlap of the three. The disclosed embodiment does not limit the number of monitoring patterns in the cutting path S and the number of patterns to be tested in the monitoring pattern 2.

[0076] For example, in the semiconductor structure shown in Figure 1(a), the cutting path S is only located on one side of the pattern area P, but it can be understood that multiple pattern areas P can be distributed in an array, and accordingly, the cutting path S is located between adjacent pattern areas P, for example, it can be located on the adjacent two sides or opposite sides of the corresponding pattern area P, or on the surrounding side of the pattern area P, etc.

[0077] For example, see Figure 2 , the first cutting lane S1, the second cutting lane S2, the third cutting lane S3, and the fourth cutting lane S4 are sequentially located around the pattern area P. At this time, the pattern area P includes the design graphic 1a and the design graphic 1b. The monitoring graphic 2a in the first cutting lane S1 includes the first graphic to be tested 21a, the second graphic to be tested 22a, and a splicing graphic formed by the overlap of the two. The monitoring graphic 2b in the second cutting lane S2 includes the first graphic to be tested 21b, the second graphic to be tested 22b, and a splicing graphic formed by the overlap of the two. The monitoring graphic 2c in the third cutting lane S3 includes the first graphic to be tested 21c, the second graphic to be tested 22c, and a splicing graphic formed by the overlap of the two. The monitoring graphic 2d in the fourth cutting lane S4 includes the first graphic to be tested 21d, the second graphic to be tested 22d, and a splicing graphic formed by the overlap of the two.

[0078] For example, the pattern area P is a rectangular area, and the monitoring pattern 2 can be set in the overlapping area of ​​the cutting area S at the center of four adjacent pattern areas P and formed by overlapping four patterns to be tested. In this way, the monitoring pattern 2 can be formed by four exposure processes or etching processes.

[0079] In some embodiments, the semiconductor structure further comprises: at least two reference patterns located on the cutting path, wherein the reference patterns correspond to the patterns to be tested one by one, and the reference patterns and the corresponding patterns to be tested have the same shape and feature size.

[0080] For example, see Figure 3 Taking the first cutting lane S1, the second cutting lane S2, the third cutting lane S3, and the fourth cutting lane S4 as an example, which are sequentially located on the peripheral side of the pattern area P, the semiconductor structure also includes: a first reference graphic 31a and a second reference graphic 32a located at the first cutting lane S1, a first reference graphic 31b and a second reference graphic 32b located at the second cutting lane S2, a first reference graphic 31c and a second reference graphic 32c located at the third cutting lane S3, and a first reference graphic 31d and a second reference graphic 32d located at the fourth cutting lane S4. Among them, the first reference figure 31a corresponds to the first figure to be tested 21a, the second reference figure 32a corresponds to the first figure to be tested 22a, the first reference figure 31b corresponds to the first figure to be tested 21b, the second reference figure 32b corresponds to the first figure to be tested 22b, the first reference figure 31c corresponds to the first figure to be tested 21c, the second reference figure 32c corresponds to the first figure to be tested 22c, the first reference figure 31d corresponds to the first figure to be tested 21d, the second reference figure 32d corresponds to the first figure to be tested 22d, and the above reference figures and the corresponding figures to be tested have the same shape and characteristic size.

[0081] Here, it should be added that the reference patterns and the patterns to be tested correspond to each other one by one, so the number of reference patterns in each cutting lane is consistent with the number of patterns to be tested.

[0082] In the disclosed embodiment, the reference pattern in the cutting path S is set in one-to-one correspondence with the pattern to be tested, and the reference pattern and the corresponding pattern to be tested have the same shape and characteristic size. In this way, by comparing the contour difference between the overlapping area of ​​the pattern to be tested and the reference pattern, it can be clearly determined whether the exposure process or etching process is normal.

[0083] Here, it can be understood that when there is an abnormality in the exposure process or the etching process in the overlapping area of ​​the test pattern, through the difference between the outline of the overlapping area and the outline of the corresponding reference pattern, if the outline of the overlapping area is consistent with the first reference pattern corresponding to the first test pattern, it can be further judged that the abnormality in the overlapping area originates from the abnormality of the first test pattern; if the outline of the overlapping area is consistent with the second reference pattern corresponding to the second test pattern, it can be further judged that the abnormality in the overlapping area originates from the abnormality of the second test pattern, which is beneficial to further improve the accuracy of online detection.

[0084] In some embodiments, see Figure 4 , the number of pattern areas P is at least two. The monitoring pattern is located in the cutting path S between adjacent pattern areas P. Each pattern to be tested in the monitoring pattern and the corresponding design pattern 1 in the adjacent pattern area P have the same shape and characteristic size.

[0085] For example, see Figure 5 , Figure 5 for Figure 4 The monitoring pattern 2 is located in the cutting path S between the adjacent first pattern area P1 and the second pattern area P2. The first pattern to be tested 21 in the monitoring pattern 2 has the same shape and feature size as the corresponding first design pattern 11, and the second pattern to be tested 22 has the same shape and feature size as the corresponding second design pattern 12.

[0086] For example, the first design graphic 11 and the second design graphic 12 are both linear graphics. The first graphic to be tested 21 and the corresponding first design graphic 11 have the same shape, and the characteristic dimensions (such as line width) of the two are also the same. The second graphic to be tested 22 and the corresponding second design graphic 12 have the same shape, and the characteristic dimensions (such as line width) of the two are also the same. However, it is not limited to this, and the first design graphic 11 and the second design graphic 12 can also be hole-shaped graphics or other graphics. The first design graphic 11 and the second design graphic 12 can be arranged in an array in the corresponding pattern area.

[0087] As a further example, the pattern areas are arranged in an array, and there are cutting paths between adjacent pattern areas. Figure 3The second cutting street S2, the third cutting street S3 and the fourth cutting street S4 shown in FIG. 1 all have a pattern area ( Figure 3 (not shown), the cutting road S5, the cutting road S6 and the cutting road S7 have a pattern area ( Figure 3 The design pattern corresponding to each pattern to be tested in the monitoring pattern in any cutting path can be understood with reference to the above example.

[0088] As a further example, the pattern areas are arranged in an array, so that the first pattern to be tested 21a and the second pattern to be tested 22a can have the same shape and characteristic size, so the first pattern to be tested 21a, the second pattern to be tested 22a, the design pattern 11 and the design pattern 13 can all have the same shape and characteristic size.

[0089] Here, it should be noted that Figure 1(a) to Figure 5 In the semiconductor structure shown, only one monitoring pattern is provided in each cutting lane as an example, but this does not mean that only one monitoring pattern can be provided in each cutting lane. The embodiment of the present disclosure does not limit the number of monitoring patterns in each cutting lane.

[0090] In some embodiments, each of the patterns to be tested in the same monitoring pattern corresponds to an adjacent pattern area one by one. Each of the patterns to be tested in the same monitoring pattern overlaps in the same area.

[0091] For example, please refer to Figure 5 , the first pattern to be tested 21 in the monitoring pattern 2 corresponds to the first design pattern 11 in the adjacent first pattern area P1; the second pattern to be tested 22 in the monitoring pattern 2 corresponds to the second design pattern 12 in the adjacent second pattern area P2. The correspondence between each pattern to be tested and the adjacent pattern area in any monitoring pattern can be understood with reference to the above examples.

[0092] Here, the design graph and the monitoring graph may be located on the same horizontal line or may not be located on the same horizontal line.

[0093] In some examples, the design graph and the monitoring graph are located on the same horizontal line to facilitate monitoring and searching.

[0094] In some embodiments, the shapes and characteristic sizes of the patterns to be tested within the same monitoring pattern 2 are the same.

[0095] In some embodiments, the pattern to be tested includes a linear pattern or a hole-shaped pattern.

[0096] For example, see Figure 6, the first pattern to be tested 21a and the second pattern to be tested 22a in the pattern to be tested 2a can be linear patterns, and the first pattern to be tested 21e and the second pattern to be tested 22e in the pattern to be tested 2e can be hole-shaped patterns. The first pattern to be tested 21e in the monitoring pattern 2e corresponds to the third design pattern 13 in the adjacent first pattern area P1; the second pattern to be tested 22e in the monitoring pattern 2e corresponds to the fourth design pattern 14 in the adjacent second pattern area P2. The first reference pattern 31e corresponds to the first pattern to be tested 21e, and the second reference pattern 32e corresponds to the first pattern to be tested 22e, and the above reference patterns and the corresponding patterns to be tested have the same shape and characteristic size.

[0097] In some embodiments, different patterns to be tested within the same monitoring pattern 2 are formed by using different exposure processes or different etching processes.

[0098] As a further example, the design patterns in different pattern areas are formed using different exposure processes or different etching processes; and different reference patterns are formed using different exposure processes or different etching processes. Figure 6 In the embodiment, the third design pattern 13 and the fourth design pattern 14 are formed by using different exposure processes or different etching processes, and the first reference pattern 31e and the second reference pattern 32e are formed by using different exposure processes or different etching processes.

[0099] Based on the same inventive concept, some embodiments of the present disclosure also provide a mask set for preparing a semiconductor structure as in any of the above embodiments. The mask set also possesses the technical advantages of the above semiconductor structure, which will not be described in detail here. The mask set includes: at least two masks, and each mask has a mask pattern corresponding to the design pattern and any pattern to be tested in the corresponding monitoring pattern.

[0100] For example, taking the monitoring pattern 2 formed by overlapping two patterns to be tested as an example, the mask set may include only two masks. If the monitoring pattern 2 includes more patterns to be tested, the mask set also includes more masks. The following embodiments are described by taking the mask set including two masks as an example, and the case where the mask set includes more masks can be expanded in the same way.

[0101] In some embodiments, see Figure 7 The mask set includes a first mask Y1 and a second mask Y2, wherein the structure of the first mask Y1 is as follows: Figure 7 As shown in Figure (a), the structure of the second mask Y2 is as follows: Figure 7As shown in (b) of FIG. 1 . The first mask Y1 has a mask pattern corresponding to the first design pattern 11 and any first pattern to be tested 21 in the corresponding monitoring pattern 2 (for example, opening patterns K11, K21 and K31, wherein the opening pattern K11 is used to form the first design pattern 11, the opening pattern K21 is used to form the first pattern to be tested 21 in the monitoring pattern 2, and the opening pattern K31 is used to form the first reference pattern 31). The second mask Y2 has a mask pattern corresponding to the second design pattern 12 and any second pattern to be tested 22 in the corresponding monitoring pattern 2 (for example, opening patterns K12, K22 and K32, wherein the opening pattern K12 is used to form the second design pattern 12, the opening pattern K22 is used to form the second pattern to be tested 22 in the monitoring pattern 2, and the opening pattern K32 is used to form the second reference pattern 32).

[0102] It can be understood that the opening pattern K21 in the first mask Y1 and the opening pattern K22 in the second mask Y2 are used to form the first test pattern and the second test pattern that can constitute a splicing pattern. Therefore, the first mask Y1 and the second mask Y2 can overlap for the same target area when used, and the target area is, for example, a cutting path area.

[0103] In some examples, the first mask Y1 and the second mask Y2 may have the same size specifications to facilitate alignment.

[0104] In other examples, the size specification of the first mask Y1 is slightly larger than the size of the corresponding first pattern area and the cutting path in the same direction, the size specification of the second mask Y2 is slightly larger than the size of the corresponding second pattern area and the cutting path in the same direction, and alignment marks are provided on the first mask Y1 and the second mask Y2 to ensure that after two exposures or etchings are performed using the opening pattern K21 in the first mask Y1 and the opening pattern K22 in the second mask Y2, respectively, a monitoring pattern formed by the overlap of the first pattern to be tested and the second pattern to be tested can be obtained.

[0105] From the above, in the embodiment of the present disclosure, the first mask Y1 and the second mask Y2 are respectively used to perform different exposure processes or different etching processes, so the overlapping area of ​​the imaging areas of the first mask Y1 and the second mask Y2 can undergo multiple exposures or multiple etches, so as to facilitate the subsequent online monitoring of the process by comparing the contour differences between the multiple exposure or double etching areas and the single exposure or single etching areas.

[0106] In some embodiments of the present disclosure, different masks have mask patterns corresponding to the same design pattern.

[0107] For example, the first test pattern 21 and the corresponding first design pattern 11 in the adjacent first pattern area P1 have the same shape and characteristic size, the second test pattern 22 and the corresponding second design pattern 12 in the adjacent second pattern area P2 have the same shape and characteristic size, and the shapes and characteristic sizes of the first test pattern 21 and the second test pattern 22 in the same monitoring pattern 2 are the same, so the first design pattern 11 and the second design pattern 12 have the same shape and characteristic size, and the first mask Y1 and the second mask Y2 have mask patterns corresponding to the same design pattern.

[0108] Some embodiments of the present disclosure also provide a method for monitoring a photolithography process, see Figure 8 , including the following steps:

[0109] S100: providing a substrate, wherein the substrate has a pattern area and a cutting path located at at least one side of the pattern area.

[0110] S200: forming a photoresist layer on a substrate.

[0111] S300: exposing and developing the photoresist layer in the pattern area to form a design pattern, and synchronously exposing and developing the photoresist layer in the cutting path to form a monitoring pattern; wherein the monitoring pattern includes: a spliced ​​pattern formed by overlapping at least two patterns to be tested, and different patterns to be tested are formed by at least using different exposure processes.

[0112] S400: Observe the development contour of the overlapping area of ​​the pattern to be tested in the monitoring pattern.

[0113] S500: Determine whether there is an abnormality in the exposure process of the design pattern in the pattern area according to the observation result of the development profile.

[0114] In the disclosed embodiment, the photoresist layer in the pattern area is exposed and developed to form a design pattern, and the photoresist layer in the cutting path is exposed and developed to form a monitoring pattern. In this way, the overlapping area of ​​the pattern to be tested in the monitoring pattern will be exposed multiple times. By comparing the contour difference between the overlapping area and the non-overlapping area of ​​the pattern to be tested, it can be clearly judged whether the exposure process is normal. In this way, the photolithography process can be monitored online in a simple and efficient manner, which is conducive to ensuring the yield of the chip.

[0115] In some embodiments, the method for monitoring the photolithography process further includes:

[0116] While forming the monitoring pattern in step S300, at least two reference patterns are formed by exposing and developing in the photoresist layer of the cutting path; the reference patterns correspond to the patterns to be tested one by one, and the reference patterns and the corresponding patterns to be tested have the same shape and feature size as the reference patterns.

[0117] In the disclosed embodiment, while forming the monitoring pattern, at least two reference patterns are formed by exposure and development in the photoresist layer of the cutting path, wherein the reference patterns are arranged in a one-to-one correspondence with the pattern to be tested, and the reference patterns and the corresponding pattern to be tested have the same shape and feature size. In this way, by comparing the difference in the outline of the overlapping area of ​​the pattern to be tested with the reference pattern, it can be determined whether the exposure process is normal.

[0118] While observing the development profile of the overlapped area of ​​the pattern to be tested in the monitoring pattern in step S400, the development profile of the reference pattern is observed. Wherein, step S500 determines whether there is an abnormality in the exposure process according to the observation result of the development profile, and further includes: using the observation result of the development profile of the reference pattern as a reference, determining whether there is an abnormality in the development profile of the overlapped area of ​​the pattern to be tested in the monitoring pattern, so as to determine the abnormality of the corresponding exposure process according to the abnormality of the development profile.

[0119] In some embodiments, determining whether there is an abnormality in the exposure process in step S500 includes: determining whether the exposure amount of the exposure process is sufficient. Step S500 also includes: determining whether the development of the photoresist layer is complete according to the observation result of the development profile.

[0120] In some embodiments, see Fig. 9 The monitoring method of the photolithography process also includes: S600 to S800.

[0121] S600: When there is no abnormality in the exposure process, the design pattern is transferred to the substrate by an etching process to form a target pattern, and the monitoring pattern is transferred to the substrate to form a lithography monitoring pattern.

[0122] S700: Observe the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern.

[0123] S800: Determine whether there is any abnormality in the etching process according to the observation result of the etching profile.

[0124] In some embodiments, the method for monitoring a photolithography process further includes: S900.

[0125] S900: Determine the bottom morphology of the target graphic according to the observation result of the etching profile.

[0126] In the disclosed embodiment, when there is no abnormality in the exposure process, the design pattern is transferred to the substrate by the etching process to form a target pattern, and the monitoring pattern is transferred to the substrate to form a photolithography monitoring pattern. In this way, by comparing the contour difference between the overlapping area and the non-overlapping area of ​​the pattern to be tested, it can be determined whether the etching process is normal. In this way, the photolithography process can be monitored online in a simple and efficient manner, which is conducive to ensuring the yield of the chip.

[0127] In some embodiments, the observation results of the development profile of the overlapping area of ​​the pattern to be tested in the monitoring pattern and the observation results of the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern can be obtained by scanning electron microscope observation.

[0128] In order to more clearly illustrate the monitoring method of the photolithography process in some of the above embodiments, the following embodiments are combined with Figure 10 to Figure 14 Understand.

[0129] In step S100, refer to Fig.10 In step S100 , a substrate 4 is provided. The substrate 4 has a pattern area P and a cutting path S located on at least one side of the pattern area P.

[0130] For example, the substrate 4 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 4 can be a single-layer structure or a multi-layer structure. For example, the substrate 4 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 4 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0131] In some examples, the substrate 4 includes but is not limited to a silicon substrate or a silicon-based substrate. Optionally, the substrate 4 is a sapphire substrate, a silicon germanium substrate or a silicon carbide substrate.

[0132] For example, in Fig.10 In the semiconductor structure shown, two pattern areas P are arranged side by side and the cutting path S is located between the two pattern areas P. However, it can be understood that the number and arrangement of the pattern areas P, as well as the setting of each cutting path S, can be implemented in a variety of ways according to the needs. The embodiments of the present disclosure are not limited to this.

[0133] In step S200 , referring to FIG. 11 ( a ) and FIG. 11 ( b ), a photoresist layer 200 is formed on the substrate 4 .

[0134] In some examples, a protective layer is disposed on the substrate 4 , and the photoresist layer 200 is formed on the surface of the protective layer.

[0135] For example, the protective layer is an oxide layer 300 . Before forming the photoresist layer 200 on the substrate 4 in step S200 , the method for preparing the semiconductor structure may further include: forming the oxide layer 300 on the substrate 4 . Accordingly, the photoresist layer 200 is formed on the surface of the oxide layer 300 .

[0136] For example, the oxide layer 300 may cover the entire surface of the substrate 4 or partially cover the surface of the substrate 4. Similarly, the photoresist layer 200 may also cover the entire surface of the oxide layer 300 or partially cover the surface of the oxide layer 300.

[0137] In some embodiments, the pattern to be tested is a pattern in a photoresist layer.

[0138] In step S300, exposing and developing the photoresist layer in the pattern area to form a design pattern, and exposing and developing the photoresist layer in the cut lane to form a monitoring pattern simultaneously, further comprises: based on any mask set as described in the above embodiments, exposing and developing the photoresist layer in the pattern area to form a design pattern, and exposing and developing the photoresist layer in the cut lane to form a monitoring pattern simultaneously. Wherein, the monitoring pattern comprises: a spliced ​​pattern formed by overlapping at least two patterns to be tested, and different patterns to be tested are formed by at least using different exposure processes.

[0139] In addition, in some embodiments, while forming the monitoring pattern in step S300, at least two reference patterns can be formed by exposing and developing in the photoresist layer of the cutting path; the reference pattern and the pattern to be tested correspond one-to-one, and the reference pattern and the corresponding pattern to be tested have the same shape and feature size as the reference pattern.

[0140] For example, see Fig.12 , the photoresist layer 200 in the first pattern area P1 and the second pattern area P2 is exposed and developed to form the first design pattern 11 and the second design pattern 12, and the photoresist layer 200 in the cutting street S is exposed and developed to form the monitoring pattern 2 simultaneously.

[0141] Here, Fig.12 In the figure, the first design pattern 11 and the second design pattern 12 are taken as opening patterns for illustration. However, it can be understood that in other embodiments, the first design pattern 11 and the second design pattern 12 can also be entity reserved patterns of the photoresist layer 200.

[0142] By way of further example, the monitoring pattern 2 includes a spliced ​​pattern formed by overlapping a first pattern to be tested 21 and a second pattern to be tested 22. The first pattern to be tested 21 and the second pattern to be tested 22 are formed by different exposure processes. In addition, while forming the monitoring pattern 2, a first reference pattern 31 can be formed by synchronously exposing and developing with the first pattern to be tested 21 in the photoresist layer 200 of the cutting path S, and a second reference pattern 32 can be formed by synchronously exposing and developing with the second pattern to be tested 22. The first reference pattern 31 corresponds to the first pattern to be tested 21 and can have the same shape and feature size reference pattern; the second reference pattern 32 corresponds to the second pattern to be tested 22 and can have the same shape and feature size reference pattern.

[0143] In steps S400 and S500, refer to Figure 13(a) to Figure 13(d) , observe the development profile of the overlapped area O of the to-be-tested pattern in the monitoring pattern 2, and determine whether there is an abnormality in the exposure process of the design pattern in the pattern area based on the observation result of the development profile.

[0144] For example, taking the pattern to be tested as a linear pattern as an example, FIG13(a) shows the development profile of the overlapping area O of the pattern to be tested in the monitoring pattern 2 under a scanning electron microscope after the photoresist layer 200 is well exposed and developed, and FIG13(b) shows a cross-sectional structure of the monitoring pattern 2 shown in FIG13(a). As shown in FIG13(a) and FIG13(b), the exposure and development of the monitoring pattern 2 are complete, and the overlapping area O of the pattern to be tested in the monitoring pattern 2 is formed by a double exposure process, and there will be a very obvious raised contour, so that a clear and smooth contour boundary can be effectively observed. FIG13(c) shows the development profile of the overlapping area O of the pattern to be tested in the monitoring pattern 2 under a scanning electron microscope after the photoresist layer 200 is not fully exposed and developed, and FIG13(d) shows a schematic diagram of the cross-sectional structure of the monitoring pattern 2 shown in FIG13(c). As shown in FIG. 13( c ) and FIG. 13( d ), the exposure and development of the monitoring pattern 2 is incomplete. The overlapping area O of the pattern to be tested in the monitoring pattern 2 is formed by a double exposure process, and there will be a very obvious raised contour so that the fuzzy and rough contour boundary can be effectively observed.

[0145] It can be seen that the embodiment of the present disclosure can clearly determine whether the corresponding exposure process is abnormal by monitoring the contour boundary of the overlapping area O of the pattern to be tested in the pattern 2 through the online detection of the scanning electron microscope. Therefore, the optimal conditions of the photolithography process, such as the optimal process window, can be effectively determined without performing slice detection.

[0146] In addition, in some embodiments, while executing step S400 to observe the development profile of the overlapped region O of the pattern to be tested in the monitoring pattern 2, the development profiles of the first reference pattern 31 and the second reference pattern 32 may also be observed synchronously, so as to use the observation results of the development profiles of the first reference pattern 31 and the second reference pattern 32 as a reference to determine whether there is an abnormality in the development profile of the overlapped region O of the pattern to be tested in the monitoring pattern 2, so as to determine the abnormality of the corresponding exposure process according to the abnormality of the development profile. For example, in the case where there is an exposure process in the overlapped region O of the pattern to be tested, the difference between the overlapped region profile and the corresponding reference pattern profile may further determine whether the abnormality of the overlapped region is caused by the abnormality of the first pattern to be tested or the abnormality of the second pattern to be tested, thereby facilitating further improving the accuracy of online detection.

[0147] It should be added that the above determination of the abnormality of the corresponding exposure process includes determining whether the exposure amount is sufficient and determining whether the development of the photoresist layer is complete.

[0148] In steps S600 to S800, please refer to Fig.14 When it is determined that there is no abnormality in the exposure process, the design pattern is transferred to the substrate 4 by an etching process to form a target pattern M, and the monitoring pattern 2 is transferred to the substrate 4 to form a photolithography monitoring pattern N1. In this way, by observing the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the photolithography monitoring pattern N1, it is also possible to determine whether there is an abnormality in the etching process based on the observation result of the etching profile.

[0149] Here, determining whether the etching process is abnormal includes determining whether the etching amount of the etching process is sufficient.

[0150] In some examples, the aforementioned etching process can also be used to transfer the reference pattern to the substrate 4 to form a photolithography reference pattern, such as a first photolithography reference pattern N21 corresponding to the first reference pattern 31 and a second photolithography reference pattern N22 corresponding to the second reference pattern 32. In this way, the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the photolithography monitoring pattern N1 can also be compared with the etching profile of the first photolithography reference pattern N21 and the etching profile of the second photolithography reference pattern N22 to comprehensively determine whether there is an abnormality in the etching process and analyze the cause of the abnormality.

[0151] In addition, in step S900, the bottom morphology of the target pattern may be determined according to the observation result of the aforementioned etching profile, for example, the bottom sidewall morphology of a structure having a depth dimension feature may be determined.

[0152] In some embodiments, the observation results of the development profile of the overlapping area of ​​the pattern to be tested in the monitoring pattern and the observation results of the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern can be obtained by online observation using a scanning electron microscope.

[0153] It should be added that, for some embodiments in which the monitoring pattern 2 is an etching pattern, the monitoring pattern 2 can be obtained by directly etching the structure to be etched using each mask in the aforementioned mask set. Accordingly, the observation and determination of the monitoring pattern 2 can be performed with reference to the observation and determination when the aforementioned monitoring pattern 2 is a pattern in the photoresist layer. This embodiment of the present disclosure will not be described in detail.

[0154] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A pattern area and a cutting path located on at least one side of the pattern area; The semiconductor structure further comprises: a design pattern located in the pattern area, and a monitoring pattern located in the cutting path; wherein the monitoring pattern comprises: a splicing pattern formed by overlapping at least two patterns to be tested.

2. The semiconductor structure according to claim 1, characterized in that: Different patterns to be tested within the same monitoring pattern are formed by using different exposure processes or different etching processes.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes: at least two reference patterns located on the scribe line; The reference pattern and the pattern to be tested correspond to each other one by one, and the reference pattern and the corresponding pattern to be tested have the same shape and characteristic size.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The number of the pattern areas is at least two; The monitoring pattern is located in the cutting path between adjacent pattern areas; Each of the patterns to be tested in the monitoring pattern and the corresponding design pattern in the adjacent pattern area have the same shape and characteristic size.

5. The semiconductor structure according to claim 4, characterized in that: The patterns to be tested in the same monitoring pattern correspond to the adjacent pattern areas one by one; and the patterns to be tested in the same monitoring pattern overlap in the same area.

6. The semiconductor structure according to claim 4, characterized in that: The shapes and characteristic sizes of the patterns to be tested within the same monitoring pattern are the same.

7. The semiconductor structure according to claim 4, characterized in that: The pattern to be tested includes a linear pattern or a hole-shaped pattern.

8. A mask set, characterized in that: Used to prepare a semiconductor structure as described in any one of claims 1 to 7; wherein the mask set includes: at least two masks, and each of the masks has a mask pattern corresponding to the design pattern and corresponding to any of the patterns to be tested in the monitoring pattern.

9. The mask set according to claim 8, characterized in that: Different mask plates have mask patterns corresponding to the same design pattern.

10. A method for monitoring a photolithography process, characterized in that: include: Providing a substrate, wherein the substrate has a pattern area and a cutting path located at at least one side of the pattern area; forming a photoresist layer on the substrate; Expose and develop the photoresist layer in the pattern area to form a design pattern, and simultaneously expose and develop the photoresist layer in the cutting path to form a monitoring pattern; wherein the monitoring pattern includes: a spliced ​​pattern formed by overlapping at least two patterns to be tested, and different patterns to be tested are formed by at least using different exposure processes; Observing the development contour of the overlapping area of ​​the pattern to be tested in the monitoring pattern; According to the observation result of the development profile, it is determined whether there is an abnormality in the exposure process of the design pattern in the pattern area.

11. The method for monitoring a photolithography process according to claim 10, characterized in that: Also includes: While forming the monitoring pattern, exposing and developing in the photoresist layer of the cutting path to form at least two reference patterns; The reference pattern and the pattern to be tested correspond to each other one by one, and the reference pattern and the corresponding pattern to be tested have the same shape and characteristic size reference pattern; While observing the development contour of the overlapping area of ​​the pattern to be tested in the monitoring pattern, observing the development contour of the reference pattern; Wherein, determining whether there is an abnormality in the exposure process based on the observation result of the development profile also includes: using the observation result of the development profile of the reference pattern as a reference to determine whether there is an abnormality in the development profile of the overlapping area of ​​the pattern to be tested in the monitoring pattern, so as to determine the abnormality corresponding to the exposure process based on the abnormality of the development profile.

12. The method for monitoring a photolithography process according to claim 10, characterized in that: The determining whether there is an abnormality in the exposure process includes: determining whether the exposure amount of the exposure process is sufficient; The monitoring method further includes: determining whether the development of the photoresist layer is complete according to the observation result of the development profile.

13. The method for monitoring a photolithography process according to any one of claims 10 to 12, characterized in that: Also includes: When there is no abnormality in the exposure process, the design pattern is transferred to the substrate by an etching process to form a target pattern, and the monitoring pattern is transferred to the substrate to form a photolithography monitoring pattern; Observing the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern; According to the observation result of the etching profile, it is determined whether there is any abnormality in the etching process.

14. The method for monitoring a photolithography process according to claim 13, characterized in that: Also includes: The bottom morphology of the target pattern is determined according to the observation result of the etching profile.

15. The method for monitoring a photolithography process according to claim 13, characterized in that: The observation result of the development profile of the overlapping area of ​​the pattern to be tested in the monitoring pattern and the observation result of the etching profile corresponding to the overlapping area of ​​the pattern to be tested in the lithography monitoring pattern are both obtained by observation using a scanning electron microscope.

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