Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, which comprises the steps of providing a substrate, synchronously forming a connecting hole and a groove in the substrate, and enabling the width of the groove to be greater than that of the connecting hole; forming a metal layer to fill the connecting hole, and covering the bottom and the side wall of the groove and the surface of the substrate; executing a chemical mechanical polishing process, removing the metal layer on the surface of the substrate, and enabling the top surface of the metal layer in the connecting hole and the top surface of the metal layer on the side wall of the groove to be flush with the surface of the substrate; forming a storage material layer to cover the top surface of the metal layer in the contact hole, the metal layer at the bottom and the side wall of the groove and the surface of the substrate; and taking the groove as a photoetching alignment mark, executing a photoetching process to carry out patterning on the storage material layer to obtain a storage pattern, and covering the top surface of the metal layer in the contact hole with the storage pattern. According to the invention, the step of additionally forming a specific photoetching alignment mark can be saved, a photoetching process is saved, and the preparation cost is saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] The storage material layer in the new memory is generally made of opaque material, such as the phase change material of the phase change memory, the resistive material of the resistive memory and the magnetoresistive material of the magnetoresistive memory, all of which contain one or more layers of opaque material. When the storage material layer is subjected to the photolithography process, it is necessary to form additional specific photolithography alignment marks beforehand. When the photolithography process is subsequently performed, the specific photolithography alignment marks are used to achieve alignment exposure. The additional formation of specific photolithography alignment marks adds a photolithography process, which increases the manufacturing cost. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor device, so as to save preparation costs.

[0004] In order to achieve the above object, the present invention provides a method for preparing a semiconductor device, comprising:

[0005] Providing a substrate, in which a connection hole and a groove are simultaneously formed, wherein the width of the groove is greater than the width of the connection hole;

[0006] forming a metal layer to fill the connection hole, cover the bottom and sidewalls of the groove and cover the surface of the substrate;

[0007] Performing a chemical mechanical polishing process to remove the metal layer on the surface of the substrate and make the top surface of the metal layer in the connection hole and the top surface of the metal layer on the side wall of the groove flush with the surface of the substrate;

[0008] forming a storage material layer covering the top surface of the metal layer in the contact hole, the metal layer at the bottom and sidewall of the groove, and the surface of the substrate; and,

[0009] The groove is used as a photolithography alignment mark, and a photolithography process is performed to pattern the storage material layer to obtain a storage pattern, and the storage pattern covers the top surface of the metal layer in the contact hole.

[0010] Optionally, the groove is located in a scribe line of the substrate, and the connection hole is located in a device region of the substrate.

[0011] Optionally, the width of the connection hole is 50 nm to 100 nm, and the width of the groove is 1 μm to 3 μm.

[0012] Optionally, the cross-sectional shape of the connecting hole is circular, and the cross-sectional shape of the groove is rectangular.

[0013] Optionally, the material of the metal layer includes tungsten, and the thickness of the metal layer is 600 angstroms to 1200 angstroms.

[0014] Optionally, after performing a chemical mechanical polishing process, the surface verticality of the metal layer on the sidewall of the groove is 80 degrees to 90 degrees.

[0015] Optionally, after the chemical mechanical polishing process is performed, the height difference between the surface of the metal layer at the bottom of the groove and the surface of the substrate is 1500 angstroms to 2000 angstroms.

[0016] Optionally, the material of the storage material layer includes phase change memory storage material, resistive change memory storage material or magnetoresistive memory storage material.

[0017] Optionally, before forming a metal layer to fill the connection hole, cover the bottom and sidewalls of the groove, and cover the surface of the substrate, the method further includes forming a barrier layer between the substrate and the metal layer.

[0018] Optionally, the material of the barrier layer includes titanium or titanium nitride.

[0019] In the method for preparing a semiconductor device provided by the present invention, a substrate is provided, a connection hole and a groove are formed in the substrate simultaneously, and the width of the groove is greater than the width of the connection hole; a metal layer is formed to fill the connection hole, and covers the bottom and side walls of the groove and the surface of the substrate; a chemical mechanical polishing process is performed to remove the metal layer on the surface of the substrate, and the top surface of the metal layer in the connection hole and the top surface of the metal layer on the side wall of the groove are flush with the surface of the substrate; a storage material layer is formed to cover the top surface of the metal layer in the contact hole, the metal layer at the bottom and side walls of the groove, and the surface of the substrate; and the groove is used as a photolithography alignment mark, and a photolithography process is performed to pattern the storage material layer to obtain a storage pattern, and the storage pattern covers the top surface of the metal layer in the contact hole. The present invention forms a groove simultaneously when forming a connection hole, and uses the filling process of the connection hole and the chemical mechanical polishing process to make the groove have photolithography alignment recognition. The subsequent groove is used as a photolithography alignment mark to perform a photolithography process, which can save the step of additionally forming a specific photolithography alignment mark, save a photolithography process, and save the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a method for preparing a semiconductor device provided by one embodiment of the present invention;

[0021] Figures 2A to 2F A schematic cross-sectional view of corresponding steps in a method for preparing a semiconductor device provided in one embodiment of the present invention.

[0022] Wherein, the accompanying drawings are marked as follows:

[0023] 10 - substrate; 11 - device area; 12 - dicing road; 21 - connection hole; 22 - groove; 30 - barrier layer; 40 - metal layer; 50 - storage material layer; 52 - storage pattern; 60 - photoresist layer; 62 - patterned photoresist layer. DETAILED DESCRIPTION

[0024] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0025] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] Figure 1 This is a flow chart of the method for preparing a semiconductor device provided in this embodiment. Please refer to Figure 1 , this embodiment provides a method for preparing a semiconductor device, comprising:

[0027] Step S1: providing a substrate, in which a connection hole and a groove are simultaneously formed, wherein the width of the groove is greater than the width of the connection hole;

[0028] Step S2: forming a metal layer to fill the connection hole, cover the bottom and sidewalls of the groove and cover the surface of the substrate;

[0029] Step S3: performing a chemical mechanical polishing process to remove the metal layer on the surface of the substrate and make the top surface of the metal layer in the connection hole and the top surface of the metal layer on the side wall of the groove flush with the surface of the substrate;

[0030] Step S4: forming a storage material layer to cover the top surface of the metal layer in the contact hole, the bottom and sidewall of the groove, and the surface of the substrate;

[0031] Step S5: using the groove as a photolithography alignment mark, performing a photolithography process to pattern the storage material layer to obtain a storage pattern, and the storage pattern covers the top surface of the metal layer in the contact hole.

[0032] Figures 2A to 2F The cross-sectional schematic diagram of the corresponding steps in the method for preparing the semiconductor device provided in this embodiment is shown below in combination with Figures 2A to 2F The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0033] Please refer to Figure 2A , perform step S1: provide a substrate 10, the substrate 10 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate; the substrate 10 may also include an integrated circuit, such as a MOS tube, a triode, a diode; the substrate 10 may also include an interconnection layer, such as a copper interconnection layer, a graphene interconnection layer; the substrate 10 may also include an insulating dielectric layer, such as a silicon oxide layer, a silicon nitride layer. Perform an etching process to simultaneously form a connection hole 21 and a groove 22 in the substrate 10, wherein the width of the groove 22 is much larger than the width of the connection hole 21 (the width is Figure 2A In the present embodiment, the width of the connection hole 21 may be 50 nm to 100 nm, the width of the groove 22 may be 1 μm to 3 μm, and the depth of the groove 22 may be 2500 angstroms to 3000 angstroms; the cross-section of the connection hole 21 (the cross-section is not the profile, but the top view) is preferably circular, and the cross-section of the groove 22 is preferably rectangular (long strip), and is not limited to the above width range and shape.

[0034] In this embodiment, the substrate 10 includes a device area 11 and a scribe line 12. The device area 11 and the scribe line 12 may be adjacent or non-adjacent (adjacent in the figure). The connection hole 21 is located in the device area 11 of the substrate 10. The formed connection hole 21 is necessary in the preparation process of the semiconductor device as an interconnection structure; the groove 22 is located in the scribe line 12 of the substrate 10, and the scribe line 12 is the position for subsequent chip cutting. The groove 22 is formed simultaneously when the connection hole 21 is formed. The groove 22 has photolithography alignment recognition after subsequent process steps. The groove 22 will be used as a photolithography alignment mark later, which can save the step of additionally forming a specific photolithography alignment mark, that is, save a photolithography process.

[0035] Please refer to Figure 2B, perform step S2: form a metal layer 40 to fill the connection hole 21, and cover the bottom and sidewalls of the groove 22 and the surface of the substrate 10. Since the width of the groove 22 is much larger than the width of the connection hole 21, after the metal 40 is formed, the metal layer 40 can completely fill the connection hole 21 and will not fill the groove 22 (only covers the bottom and sidewalls of the groove 22). After the metal layer 40 is formed, the height difference H between the surface of the metal layer 40 at the bottom of the groove 22 and the surface of the substrate 10 is preferably 1500 angstroms to 2000 angstroms. In this embodiment, the material of the metal layer 40 includes tungsten, and the thickness of the metal layer 40 can be 600 angstroms to 1200 angstroms, but is not limited to the above material and thickness. Before forming the metal layer 40 to fill the connection hole 21, cover the bottom and side walls of the groove 22, and cover the surface of the substrate 10, it also includes forming a barrier layer 30 located between the substrate 10 and the metal layer 40, that is, the barrier layer 30 covers the bottom and side walls of the connection hole 21, the bottom and side walls of the groove 22, and the surface of the substrate 10, and the metal layer 40 covers the barrier layer 30. In this embodiment, the material of the barrier layer 30 includes titanium or titanium nitride, and the thickness of the barrier layer 30 can be 50 angstroms to 150 angstroms, but is not limited to the above material and thickness.

[0036] Please refer to Figure 2C , perform step S3: perform a chemical mechanical polishing process to remove the metal layer 30 and the barrier layer 40 on the surface of the substrate 10 to expose the surface of the substrate 10, retain the barrier layer 30 and the filled metal layer 40 on the inner wall of the connecting hole 21 and the barrier layer 30 and the metal layer 40 on the inner wall of the groove 22, and make the top surface of the metal layer 30 in the connecting hole 21 and the top surface of the metal layer 30 on the side wall of the groove 22 flush with the surface of the substrate 10 through the chemical mechanical polishing process, and after performing the chemical mechanical polishing process, the surface verticality of the metal layer 40 on the side wall of the groove 22 is 80 degrees to 90 degrees; after performing the chemical mechanical polishing process, the height difference between the surface of the metal layer 40 at the bottom of the groove 22 and the surface of the substrate 10 is consistent with the height difference before performing the chemical mechanical polishing process, that is, the height difference H between the surface of the metal layer 40 at the bottom of the groove 22 and the surface of the substrate 10 is preferably 1500 angstroms to 2000 angstroms. In this embodiment, the filling process of the connecting hole 21 and the chemical mechanical polishing process are synchronously used to make the groove 22 have lithography alignment recognition. The lithography alignment recognition means that the groove 22 has a certain depth (the height difference H between the surface of the metal layer 40 at the bottom of the groove 22 and the surface of the substrate 10 is preferably 1500 angstroms to 2000 angstroms) and verticality (the surface verticality of the metal layer 40 on the side wall of the groove 22 is 80 degrees to 90 degrees), and the groove 22 can be used for exposure alignment in the subsequent lithography process.

[0037] Please refer to Figure 2D, perform step S4: forming a storage material layer 50 to cover the top surface of the metal layer 40 in the contact hole 21, the metal layer 40 at the bottom and sidewall of the groove 22, and the surface of the substrate 10, and covering the top surface of the barrier layer 30 in the contact hole 21 and the top surface of the barrier layer 30 in the groove 22. In this embodiment, the storage material layer 50 does not fill the groove 22, but only covers the metal layer 40 at the bottom and sidewall of the groove 22, so that the groove 22 can be exposed. In this embodiment, the material of the storage material layer 50 includes a phase change memory storage material, a resistive memory storage material, or a magnetoresistive memory storage material, wherein the phase change memory storage material includes Ge 2 Sb 2 Te 5 ,Ge 2 Sb 2 Te 5 doping, GeSbTe series alloy, SbTe series alloy material, GeTe series alloy material and other chalcogenide alloy materials, the resistive memory storage material includes Ta 2 O 5 , TaOx, HfOx, TiOx, AlOx, ZnOx, CuOx and a combination material layer of metal materials such as TaN, TiN, Pt, Ir, Ti, Ta, etc. The magnetoresistive memory storage material includes a combination of various materials such as MgOx, CoFeB, Co, CoPt, Pt, Ru, Ni, Cr, Ta, etc.

[0038] Please refer to Figure 2E and 2F , execute step S5: use the groove 22 as a lithography alignment mark, perform a lithography process to pattern the storage material layer 50 to obtain a storage pattern 52, specifically, use a spin coating process to form a photoresist layer 60 to cover the substrate 10 and fill the groove 22. Since the material of the photoresist layer 60 is a light-transmitting material, the groove 22 is used as a lithography alignment mark, and the photolithography machine can smoothly identify the height difference and verticality of the groove 22 when performing exposure alignment, thereby achieving exposure alignment; and perform a patterning process on the photoresist layer 60 to form a patterned photoresist layer 62, and use the patterned photoresist layer 62 as a mask to etch the storage material layer 50 to form a storage pattern 52, and the storage pattern 52 covers the top surface of the metal layer 40 and the barrier layer 30 in the contact hole 21; and then remove the patterned photoresist layer 62.

[0039] In the present embodiment, the requirements for the lithography alignment marks of the opaque storage material are met in the connection hole process of the normal logic process line, thereby saving a lithography process for the opaque storage material. By adjusting the tungsten filling process and the tungsten chemical mechanical polishing process in the connection hole process of the normal logic process line, the groove has a certain depth and verticality (with lithography alignment recognition), thereby meeting the lithography alignment requirements of the opaque material and saving the cost of a lithography process.

[0040] In summary, in the method for preparing a semiconductor device provided by the present invention, a substrate is provided, a connection hole and a groove are formed in the substrate simultaneously, and the width of the groove is greater than the width of the connection hole; a metal layer is formed to fill the connection hole, and covers the bottom and side walls of the groove and the surface of the substrate; a chemical mechanical polishing process is performed to remove the metal layer on the surface of the substrate, and the top surface of the metal layer in the connection hole and the top surface of the metal layer on the side wall of the groove are flush with the surface of the substrate; a storage material layer is formed to cover the top surface of the metal layer in the contact hole, the metal layer at the bottom and side walls of the groove, and the surface of the substrate; and the groove is used as a lithography alignment mark, and a lithography process is performed to pattern the storage material layer to obtain a storage pattern, and the storage pattern covers the top surface of the metal layer in the contact hole. The present invention forms a groove simultaneously when forming a connection hole, and uses the filling process of the connection hole and the chemical mechanical polishing process to make the groove have lithography alignment recognition. The subsequent groove is used as a lithography alignment mark to perform a lithography process, which can save the step of additionally forming a specific lithography alignment mark, save a lithography process, and save the preparation cost.

[0041] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, in which a connection hole and a groove are simultaneously formed, wherein the width of the groove is greater than the width of the connection hole; forming a metal layer to fill the connection hole, cover the bottom and sidewalls of the groove and cover the surface of the substrate; Performing a chemical mechanical polishing process to remove the metal layer on the surface of the substrate and make the top surface of the metal layer in the connection hole and the top surface of the metal layer on the side wall of the groove flush with the surface of the substrate; forming a storage material layer covering the top surface of the metal layer in the contact hole, the metal layer at the bottom and sidewall of the groove, and the surface of the substrate; and, The groove is used as a photolithography alignment mark, and a photolithography process is performed to pattern the storage material layer to obtain a storage pattern, and the storage pattern covers the top surface of the metal layer in the contact hole.

2. The method for preparing a semiconductor device according to claim 1, wherein: The groove is located in a scribe line of the substrate, and the connection hole is located in a device region of the substrate.

3. The method for preparing a semiconductor device according to claim 1, wherein: The width of the connection hole is 50nm-100nm, and the width of the groove is 1μm-3μm.

4. The method for preparing a semiconductor device according to claim 3, wherein: The cross-sectional shape of the connecting hole is circular, and the cross-sectional shape of the groove is rectangular.

5. The method for preparing a semiconductor device according to claim 1, wherein: The material of the metal layer includes tungsten, and the thickness of the metal layer is 600 angstroms to 1200 angstroms.

6. The method for preparing a semiconductor device according to claim 1, wherein: After the chemical mechanical polishing process is performed, the surface verticality of the metal layer on the sidewall of the groove is 80 degrees to 90 degrees.

7. The method for preparing a semiconductor device according to claim 1, wherein: After the chemical mechanical polishing process is performed, the height difference between the surface of the metal layer at the bottom of the groove and the surface of the substrate is 1500 angstroms to 2000 angstroms.

8. The method for preparing a semiconductor device according to claim 1, wherein: The material of the storage material layer includes a phase change memory storage material, a resistive memory storage material or a magnetoresistive memory storage material.

9. The method for preparing a semiconductor device according to claim 1, wherein: Before forming a metal layer to fill the connection hole, cover the bottom and sidewall of the groove and cover the surface of the substrate, the method further includes forming a barrier layer between the substrate and the metal layer.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The material of the barrier layer includes titanium or titanium nitride.

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