Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate which comprises a first region, a second region and a third region located between the first region and the second region; the first reflecting mirror structure is positioned in the first region of the substrate; the second reflecting mirror structure is located in the second area of the substrate, and the second reflecting mirror structure and the first reflecting mirror structure are located on the same side of the substrate; the light-emitting structure is located in the third area of the substrate, and the light-emitting structure and the first reflector structure are located on the same side of the substrate; and the reflecting surfaces of the first reflecting mirror structure and the second reflecting mirror structure directly face the side wall of the light-emitting structure. And the luminous efficiency and the service life of the semiconductor structure are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Semiconductor lasers, also known as laser diodes, are lasers that use semiconductor materials such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), zinc sulfide (ZnS), etc. as working materials. They have the advantages of small size, high efficiency and long life.

[0003] At present, the first reflector, active area and second reflector in the semiconductor laser are stacked on the substrate; the reflector material is generally a dielectric material, such as SiO2 / SiN stacked material. When preparing III-nitride materials on dielectric materials, the crystal quality of the film layer is low. Therefore, stacking the active area on the reflector has the problem of low crystal quality of the active area, which leads to a decrease in the light extraction efficiency of the semiconductor laser and increases the risk of film cracking in the semiconductor laser, affecting the service life of the semiconductor laser. Summary of the invention

[0004] The embodiment of the present invention provides a semiconductor structure and a preparation method thereof, so as to improve the light extraction efficiency and service life of the semiconductor structure.

[0005] According to one aspect of the present invention, there is provided a semiconductor structure, comprising:

[0006] A substrate comprising a first region, a second region, and a third region located between the first region and the second region;

[0007] a first reflector structure located in a first region of the substrate;

[0008] a second reflector structure located in a second region of the substrate and on the same side of the substrate as the first reflector structure;

[0009] a light emitting structure, located in a third region of the substrate and on the same side of the substrate as the first reflector structure;

[0010] Wherein, the reflective surfaces of the first reflector structure and the second reflector structure face the side wall of the light emitting structure.

[0011] Optionally, the first reflector structure and / or the second reflector structure is a Bragg reflector structure, wherein:

[0012] The first reflector structure includes a first sub-dielectric layer covering the side wall of the light emitting structure, the first sub-dielectric layer is provided with a plurality of evenly distributed first grooves and a third semiconductor layer prepared in the first grooves,

[0013] The second reflector structure includes a second sub-dielectric layer covering the side wall of the light emitting structure, and the second sub-dielectric layer is provided with a plurality of evenly distributed second grooves and a fourth semiconductor layer prepared in the second grooves.

[0014] Optionally, the first groove extends along a first direction, and the plurality of first grooves are arranged at intervals along a second direction;

[0015] The second groove extends along the first direction, and the plurality of second grooves are arranged at intervals along the second direction;

[0016] The second direction is the direction from the first reflector structure to the light emitting structure, and the first direction and the second direction are perpendicular to each other.

[0017] Optionally, the number of the first grooves is smaller than the number of the second grooves.

[0018] Optionally, the width of the first groove is less than 100 nm, and the interval between the plurality of first grooves is less than 150 nm;

[0019] The width of the second groove is less than 100 nm, and the interval between the plurality of second grooves is less than 150 nm.

[0020] Optionally, the first sub-dielectric layer and the second sub-dielectric layer are single-layer material layers; wherein the material of the first sub-dielectric layer includes SiO2 or SiN; and the material of the second sub-dielectric layer includes SiO2 or SiN;

[0021] Alternatively, the first sub-dielectric layer and the second sub-dielectric layer are stacked material layers, and the first sub-dielectric layer and the second sub-dielectric layer include multiple DBR material layers stacked vertically to the substrate; wherein the material of the first sub-dielectric layer includes SiO2 and SiN; and the material of the second sub-dielectric layer includes SiO2 and SiN.

[0022] Optionally, the first groove passes through or partially passes through the first sub-dielectric layer;

[0023] And / or, the second groove passes through or partially passes through the second sub-dielectric layer.

[0024] Optionally, the materials of the third semiconductor layer and the fourth semiconductor layer include group III nitride materials;

[0025] The first reflector structure further includes a first separation groove, the first separation groove extends along the second direction, and the first separation groove is connected with the first groove; a group III nitride material is prepared in the first separation groove;

[0026] The second reflector structure also includes a second separation groove, which extends along a second direction and is connected to the second groove; and a group III nitride material is prepared in the second separation groove.

[0027] Optionally, the group III nitride material includes gallium nitride material;

[0028] The first direction is the [11-20] crystal direction of the hexagonal system of the gallium nitride material; and the second direction is the [1-100] crystal direction of the hexagonal system of the gallium nitride material.

[0029] Optionally, along a direction perpendicular to the substrate, a depth of the first separation groove is greater than or equal to a thickness of the first reflector structure;

[0030] And / or, along a direction perpendicular to the substrate, a depth of the second separation groove is greater than or equal to a thickness of the second reflector structure.

[0031] Optionally, the light emitting structure includes:

[0032] A first semiconductor layer, an active layer and a second semiconductor layer are sequentially stacked on the substrate.

[0033] Optionally, materials of the first semiconductor layer, the active layer and the second semiconductor layer include Group III nitride materials.

[0034] Optionally, the first semiconductor layer and the second semiconductor layer have opposite conductivity types.

[0035] Optionally, the semiconductor structure further includes a first electrode and a second electrode; the first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

[0036] According to one aspect of the present invention, a method for preparing a semiconductor structure is provided, which is used to prepare the semiconductor structure according to any embodiment of the present invention; the method comprises:

[0037] Providing a substrate; the substrate comprising a first region, a second region, and a third region located between the first region and the second region;

[0038] forming a first reflector structure and a second reflector structure in a first region and a second region of the substrate, respectively;

[0039] A light emitting structure is formed in the third region of the substrate; wherein the first reflector structure, the second reflector structure and the light emitting structure are located on the same side of the substrate, and the reflective surfaces of the first reflector structure and the second reflector structure face the side wall of the light emitting structure.

[0040] Optionally, after forming a first reflector structure and a second reflector structure in the first region and the second region of the substrate respectively, a light emitting structure is formed in the third region of the substrate;

[0041] Alternatively, after forming the light emitting structure in the third region of the substrate, a first reflector structure and a second reflector structure are formed in the first region and the second region of the substrate respectively.

[0042] Optionally, forming a first reflector structure and a second reflector structure in the first region and the second region of the substrate respectively includes:

[0043] Forming a dielectric material layer on the surface of one side of the substrate; wherein the dielectric material layer is a single film layer structure or a multi-film layer structure;

[0044] Patterning the dielectric material layer to form a plurality of first grooves extending along a first direction and evenly spaced along a second direction in a first region, and to form a plurality of second grooves extending along the first direction and evenly spaced along a second direction in a second region, wherein the second direction is a direction in which the first reflector structure points to the light-emitting structure, and the first direction and the second direction are perpendicular to each other;

[0045] A group III nitride material is prepared in the first groove to form a third semiconductor layer, and a group III nitride material is prepared in the second groove to form a fourth semiconductor layer; wherein the dielectric material layer located in the first region is used to form a first sub-dielectric layer, and the dielectric material layer located in the second region is used to form a second sub-dielectric layer.

[0046] Optionally, preparing a group III nitride material in the first groove to form a third semiconductor layer, and preparing a group III nitride material in the second groove to form a fourth semiconductor layer, comprises:

[0047] Patterning the dielectric material layer to form at least one first separation groove extending along the second direction and penetrating the first groove in the first region, and forming at least one second separation groove extending along the second direction and penetrating the second groove in the second region; wherein the depth of the first separation groove is greater than or equal to the depth of the first groove; and the depth of the second separation groove is greater than or equal to the depth of the second groove;

[0048] Preparing a group III nitride material in the first dividing groove and the second dividing groove;

[0049] The third semiconductor layer is formed by preparing a III-nitride material in the first groove by lateral epitaxy from the first separation groove, and the fourth semiconductor layer is formed by preparing a III-nitride material in the second groove by lateral epitaxy from the second separation groove.

[0050] Optionally, forming a light emitting structure in the third region of the substrate includes:

[0051] Etching the dielectric material layer located in the third region until the substrate is exposed;

[0052] forming a first semiconductor layer in the third region;

[0053] forming an active layer on a surface of the first semiconductor layer away from the substrate;

[0054] A second semiconductor layer is formed on a surface of the active layer away from the substrate.

[0055] Optionally, after forming the light emitting structure in the third region of the substrate, the method further includes:

[0056] forming a first electrode on a side of the second semiconductor layer away from the substrate;

[0057] forming a second electrode on a side of the substrate away from the light emitting structure;

[0058] Alternatively, after forming the light emitting structure in the third region of the substrate, the method further comprises:

[0059] Sequentially etching portions of the second semiconductor layer and the active layer until portions of the first semiconductor layer are exposed;

[0060] forming a first electrode on a side of the second semiconductor layer away from the substrate;

[0061] A second electrode is formed on the exposed side of the first semiconductor layer away from the substrate.

[0062] The technical solution provided by the embodiment of the present invention is to arrange a first reflector structure, a light-emitting structure, and a second reflector structure side by side on the same side of a substrate, and to arrange the light-emitting structure between the first reflector structure and the second reflector structure, so that the reflecting surfaces of the first reflector structure and the second reflector structure are directly opposite to the side walls of the light-emitting structure, so that the first reflector structure and the second reflector structure reflect the light generated by the light-emitting structure in a direction parallel to the substrate, and light is emitted from the side of the semiconductor structure; since the light-emitting structure is formed on the substrate, instead of the method of stacking the light-emitting structure on the reflector in the prior art, the crystal quality of the group III nitride material of the light-emitting structure can be improved, thereby improving the light extraction efficiency of the semiconductor structure, reducing the risk of film cracking in the semiconductor structure, and ensuring the service life of the semiconductor structure.

[0063] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 is a three-dimensional diagram of a semiconductor laser provided by an embodiment of the present invention;

[0066] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the section line AA1 in the structure shown;

[0067] Figure 3 is a three-dimensional diagram of another semiconductor laser provided by an embodiment of the present invention;

[0068] Figure 4 is another cross-sectional structural schematic diagram provided by an embodiment of the present invention;

[0069] Figure 5 is another cross-sectional structural schematic diagram provided by an embodiment of the present invention;

[0070] Figure 6 is a flow chart of a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0071] Figure 7 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0072] Figure 8 is a schematic cross-sectional structural diagram of step S210 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0073] Fig. 9 is a schematic cross-sectional structural diagram of step S220 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0074] Fig.10 is a schematic cross-sectional structural diagram of step S230 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0075] Fig.11 is a schematic cross-sectional structural diagram of step S240 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0076] Figure 12 to Figure 16 is a schematic cross-sectional structural diagram of step S250 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0077] Fig.17 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0078] Fig.18 is a schematic cross-sectional structural diagram of step S340 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0079] Fig.19 is a schematic cross-sectional structural diagram of step S360 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0080] Figure 20-21 is a schematic cross-sectional structural diagram of step S370 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0081] Fig. 22 is a schematic cross-sectional structural diagram of step S380 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0082] Fig.23 is a schematic cross-sectional structural diagram of step S390 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0083] Fig.24 is a schematic cross-sectional structural diagram of step S3100 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0084] Fig.25 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0085] Figure 26-27 is a schematic cross-sectional structural diagram of step S430 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0086] Figure 28-29 is a schematic cross-sectional structural diagram of step S440 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0087] Fig.30 is a schematic cross-sectional structural diagram of step S450 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0088] Fig.31 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0089] Fig.32 is a schematic cross-sectional structural diagram of step S550 in a method for preparing a semiconductor laser provided by an embodiment of the present invention;

[0090] Fig.33 It is a schematic cross-sectional structural diagram of step S570 in a method for preparing a semiconductor laser according to an embodiment of the present invention. DETAILED DESCRIPTION

[0091] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0092] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0093] An embodiment of the present invention provides a semiconductor structure. Figure 1 is a three-dimensional diagram of a semiconductor laser provided by an embodiment of the present invention, Figure 2 yes Figure 1 The schematic diagram of the cross-sectional structure along the section line AA1 in the structure shown, refer to Figure 1 and Figure 2 , the semiconductor structure includes:

[0094] The substrate 10 includes a first region Q1, a second region Q2, and a third region Q3 located between the first region Q1 and the second region Q2;

[0095] A first reflector structure 21, located in a first region Q1 of the substrate 10;

[0096] The second reflector structure 22 is located in the second region Q2 of the substrate 10 and is located on the same side of the substrate 10 as the first reflector structure 21;

[0097] The light emitting structure 30 is located in the third region Q3 of the substrate 10 and is located on the same side of the substrate 10 as the first reflector structure 21 ; wherein the reflective surfaces of the first reflector structure 21 and the second reflector structure 22 face the sidewall of the light emitting structure 30 .

[0098] Specifically, the third region Q3 is located between the first region Q1 and the second region Q2, and is connected to the first region Q1 and the second region Q2. The first reflector structure 21, the second reflector structure 22 and the light emitting structure 30 are all located on the same side of the substrate 10, and are respectively located in the first region Q1, the second region Q2 and the third region Q3 of the substrate 10. By arranging the first reflector structure 21, the light emitting structure 30 and the second reflector structure 22 side by side on the same side of the substrate 10, and arranging the light emitting structure 30 between the first reflector structure 21 and the light emitting structure 30 and the second reflector structure 22, the reflection surfaces of the first reflector structure 21 and the second reflector structure 22 face the side wall of the light emitting structure 30, so that the first reflector structure 21 and the second reflector structure 22 reflect the light generated by the light emitting structure 30 in a direction parallel to the substrate 10 and generate resonance between the first reflector structure 21 and the second reflector structure 22, and then emit light in a direction parallel to the substrate 10.

[0099] Since the light-emitting structure 30 is directly formed on the substrate 10, it replaces the method of stacking the light-emitting structure 30 on the reflector structure in the prior art, and avoids the formation of the III-nitride material of the light-emitting structure 30 on the dielectric material film layer, effectively improving the crystal quality of the light-emitting structure 30 and improving the light extraction efficiency. Among them, the material of the substrate 10 can be silicon, sapphire, SiC, AlN or GaN and other materials. Optionally, a buffer layer can also be provided on the surface of the substrate 10 close to the semiconductor layer, so that the quality and surface of the substrate 10 can meet the requirements of directly preparing the light-emitting structure 30. The crystal quality of the III-nitride material of the light-emitting structure 30 is improved, thereby improving the light extraction efficiency of the semiconductor structure, reducing the risk of film cracking in the semiconductor structure, and ensuring the service life of the semiconductor structure. The material of the buffer layer can be the same as the material of the light-emitting structure 30 or a material with similar properties. Thereby, the crystal quality of the III-nitride material of the light-emitting structure 30 can be further improved, the light extraction efficiency of the semiconductor structure can be improved, and the service life of the semiconductor structure can be ensured.

[0100] The semiconductor structure provided by the embodiment of the present invention, by arranging a first reflector structure, a light-emitting structure, and a second reflector structure side by side on the same side of a substrate, only needs to ensure that the quality and surface of the substrate can meet the requirements of directly preparing the light-emitting structure, so as to improve the light extraction efficiency of the semiconductor structure, reduce the risk of cracking of the film layer in the semiconductor structure, and ensure the service life of the semiconductor structure.

[0101] In one embodiment of the present invention, reference Figure 1 and Figure 2 , the first reflector structure 21 and / or the second reflector structure 22 is a Bragg reflector structure, wherein:

[0102] The first reflector structure 21 includes a first sub-dielectric layer 211 covering the side wall of the light emitting structure 30, and the first sub-dielectric layer 211 is provided with a plurality of uniformly distributed first grooves and a third semiconductor layer 212 prepared in the first grooves.

[0103] The second reflector structure 22 includes a second sub-dielectric layer 221 covering the sidewall of the light emitting structure 30 . The second sub-dielectric layer 221 is provided with a plurality of evenly distributed second grooves and a fourth semiconductor layer 222 formed in the second grooves.

[0104] The first reflector structure 21 includes a first sub-dielectric layer 211 covering the side wall of the light emitting structure 30, and a plurality of uniformly distributed first grooves and a third semiconductor layer 212 prepared in the first grooves are provided in the first sub-dielectric layer 211. Along the direction from the first reflector structure 21 to the light emitting structure 30, the third semiconductor layer 212 and the first sub-dielectric layer 211 are alternately arranged in sequence, and the material of the third semiconductor layer 212 and the material of the first sub-dielectric layer 211 have different refractive indices, and a plurality of material layers are alternately arranged according to high and low refractive indices to form a Bragg reflector structure.

[0105] The second reflector structure 22 includes a second sub-dielectric layer 221 covering the side wall of the light emitting structure 30, and a plurality of uniformly distributed second grooves and a fourth semiconductor layer 222 prepared in the second grooves are provided in the second sub-dielectric layer 221. Along the direction from the second reflector structure 22 to the light emitting structure 30, the fourth semiconductor layer 222 and the second sub-dielectric layer 221 are alternately arranged in sequence, and the material of the fourth semiconductor layer 222 and the material of the second sub-dielectric layer 221 have different refractive indices, and the plurality of material layers are alternately arranged in a Bragg reflector structure with high and low refractive indices.

[0106] In one embodiment of the present invention, optionally, the first groove extends along the first direction Y, and multiple first grooves are arranged at intervals along the second direction X; the second groove extends along the first direction Y, and multiple second grooves are arranged at intervals along the second direction X; wherein the second direction X is the direction in which the first reflector structure 21 points to the light-emitting structure 30, and the first direction Y and the second direction X are perpendicular to each other.

[0107] Specifically, the extension direction of the first groove is set to be perpendicular to the direction in which the first reflector structure 21 points to the light emitting structure 30, so that each reflection surface in the first reflector structure 21 (the interface between the third semiconductor layer 212 and the first dielectric layer 211) can be parallel to the side wall of the light emitting structure 30, ensuring that each reflection surface in the first reflector structure 21 faces the side wall of the light emitting structure 30, preventing the light reflected by the first reflector structure 21 from leaking from a position other than the light emitting angle, and increasing the amount of light reflected back to the light emitting structure 30 by the first reflector structure 21. The extension direction of the second groove is set to be perpendicular to the direction in which the first reflector structure 21 points to the light emitting structure 30, so that each reflection surface in the second reflector structure 22 (the interface between the fourth semiconductor layer 222 and the second dielectric layer 221) can be parallel to the side wall of the light emitting structure 30, ensuring that each reflection surface in the second reflector structure 22 faces the side wall of the light emitting structure 30, preventing the light reflected by the second reflector structure 22 from leaking from a position other than the light emitting angle, and increasing the amount of light reflected back to the light emitting structure 30 by the second reflector structure 22.

[0108] Optionally, the number of the first grooves is smaller than the number of the second grooves. Specifically, the number of the first grooves is set to be smaller than the number of the second grooves, so that the logarithm of the film layer composition of the first reflector structure 21 is smaller than the logarithm of the film layer composition of the second reflector structure 22. Since the DBR reflectivity is determined by the refractive index difference of each layer of material constituting the DBR and the logarithm of the film layer composition. In the case where the film layer materials in the first reflector structure 21 and the second reflector structure 22 are the same, the logarithm of the film layer composition of the second reflector structure 22 is greater than the logarithm of the composition of the first reflector structure 21, so that the overall reflectivity of the second reflector structure 22 is greater than the overall reflectivity of the first reflector structure 21, that is, the overall transmittance of the first reflector structure 21 is greater than the overall transmittance of the second reflector structure 22, and the light-emitting surface of the semiconductor structure is the surface of the first reflector structure 21 away from the second reflector structure 22.

[0109] In other embodiments of the present invention, the number of second grooves can also be set to be smaller than the number of first grooves, so that the overall reflectivity of the first reflector structure 21 is greater than the overall reflectivity of the first reflector structure 21, and the light-emitting surface of the semiconductor structure is the surface of the second reflector structure 22 away from the side of the first reflector structure 21.

[0110] In one embodiment of the present invention, reference Figure 1 and Figure 2 The width L1 of the first groove is less than 100 nm, and the interval L2 between the multiple first grooves is less than 150 nm; the width L3 of the second groove is less than 100 nm, and the interval L4 between the multiple second grooves is less than 150 nm.

[0111] Specifically, the width L1 of the first groove is set to be less than 100 nm, and the interval L2 of the plurality of first grooves is set to be less than 150 nm, so that the thickness of the first reflector structure 21 in the second direction X can be small, the volume of the semiconductor structure can be reduced, and the miniaturization of the device can be facilitated. The width L3 of the second groove is set to be less than 100 nm, and the interval L4 of the plurality of second grooves is set to be less than 150 nm, so that the thickness of the second reflector structure 22 in the second direction X can be small, the volume of the semiconductor structure can be reduced, and the miniaturization of the device can be facilitated.

[0112] In one embodiment of the present invention, optionally, the first sub-dielectric layer 211 and the second sub-dielectric layer 221 are single-layer material layers; wherein the material of the first sub-dielectric layer 211 includes SiO2 or SiN; and the material of the second sub-dielectric layer 221 includes SiO2 or SiN.

[0113] Alternatively, the first sub-dielectric layer 211 and the second sub-dielectric layer 221 are stacked material layers, and the first sub-dielectric layer 211 and the second sub-dielectric layer 221 include multiple DBR material layers stacked vertically to the substrate 10; wherein the material of the first sub-dielectric layer 211 includes SiO2 and SiN; in the first sub-dielectric layer 211, the SiO2 film layer and the SiN film layer are stacked in a direction vertical to the substrate 10. The material of the second sub-dielectric layer 221 includes SiO2 and SiN; in the second sub-dielectric layer 221, the SiO2 film layer and the SiN film layer are stacked in a direction vertical to the substrate 10.

[0114] It should be noted that in the first reflector structure 21, the film layer in contact with the side wall of the light emitting structure 30 is the first sub-dielectric layer 211, which prevents the third semiconductor layer 212 from contacting the side wall of the light emitting structure 30 and causing a short circuit of the device. In the second reflector structure 22, the film layer in contact with the side wall of the light emitting structure 30 is the second sub-dielectric layer 221, which prevents the fourth semiconductor layer 222 from contacting the side wall of the light emitting structure 30 and causing a short circuit of the device.

[0115] In one embodiment of the present invention, optionally, the first groove penetrates or partially penetrates the first sub-dielectric layer 211; and / or, the second groove penetrates or partially penetrates the second sub-dielectric layer 221. Specifically, in the first direction Y, the first groove may penetrate the first sub-dielectric layer 211, and the third semiconductor layer 212 located in the first groove penetrates the first sub-dielectric layer 211, and the length of the third semiconductor layer 212 in the first direction Y is equal to the length of the first sub-dielectric layer 211 in the first direction Y. Alternatively, in the first direction Y, the first groove may partially penetrate the first sub-dielectric layer 211, and the third semiconductor layer 212 located in the first groove partially penetrates the first sub-dielectric layer 211, and the length of the third semiconductor layer 212 in the first direction Y is less than the length of the first sub-dielectric layer 211 in the first direction Y. Preferably, the length of the third semiconductor layer 212 in the first direction Y is greater than or equal to the length of the light emitting structure 30 in the first direction Y, so that the reflective surface in the first reflector structure 21 can reflect the outgoing light of the entire area of ​​the side surface of the light emitting structure 30 close to the first reflector structure 21.

[0116] In addition, in the first direction Y, the second groove may penetrate the second sub-dielectric layer 221, and the fourth semiconductor layer 222 located in the second groove penetrates the second sub-dielectric layer 221, and the length of the fourth semiconductor layer 222 in the first direction Y is equal to the length of the second sub-dielectric layer 221 in the first direction Y. Alternatively, in the first direction Y, the second groove may partially penetrate the second sub-dielectric layer 221, and the fourth semiconductor layer 222 located in the second groove partially penetrates the second sub-dielectric layer 221, and the length of the third semiconductor layer 212 in the first direction Y is less than the length of the first sub-dielectric layer 211 in the first direction Y. Preferably, the length of the fourth semiconductor layer 222 in the first direction Y is greater than or equal to the length of the light emitting structure 30 in the first direction Y, so that the reflective surface in the second reflector structure 22 can reflect the emitted light of the entire area of ​​the side surface of the light emitting structure 30 close to the second reflector structure 22.

[0117] In one embodiment of the present invention, reference Figure 3 Optionally, the material of the third semiconductor layer 212 and the fourth semiconductor layer 222 includes a group III nitride material; the first reflector structure 21 also includes a first separation groove 201, the first separation groove 201 extends along the second direction X, and the first separation groove 201 is connected to the first groove; the first separation groove 201 is prepared with a group III nitride material; the second reflector structure 22 also includes a second separation groove 202, the second separation groove 202 extends along the second direction X, and the second separation groove 202 is connected to the second groove; the second separation groove 202 is prepared with a group III nitride material.

[0118] It can be understood that the first groove, the second groove, the first separation groove 201 and the second separation groove 202 are all prepared with group III nitride materials. The group III nitride materials prepared in the first groove, the second groove, the first separation groove 201 and the second separation groove 202 can be the same or different. The first separation groove 201 in the first reflector structure 21 extends along the second direction X, the first separation groove 201 is connected with the first groove, and the first separation groove 201 is used to separate the first reflector structure 21 into two parts; the second separation groove 202 in the second reflector structure 22 extends along the second direction X, the second separation groove 202 is connected with the second groove, and the second separation groove 202 is used to separate the second reflector structure 22 into two parts. Each pair of reflector structures and the light-emitting structure 30 located between the pair of reflector structures can form a light-emitting unit, which is equivalent to setting two light-emitting units in the semiconductor structure, and two laser beams can be emitted. Optionally, the number of the first separation grooves 201 in the first reflector structure 21 may be multiple, and the second reflector structure 22 may have the same number of second separation grooves 202, so that more than two light-emitting units can be formed in the semiconductor structure, which is not limited in the present invention.

[0119] In one embodiment of the present invention, optionally, the group III nitride material includes a gallium nitride material;

[0120] The first direction Y is the [11-20] crystal direction of the hexagonal system of the gallium nitride material; and the second direction X is the [1-100] crystal direction of the hexagonal system of the gallium nitride material.

[0121] Specifically, gallium nitride material is prepared in the first groove, the second groove, the first separation groove 201 and the second separation groove 202. During the preparation process, a dielectric material layer can be formed on the surface of one side of the substrate 10; the dielectric material layer is etched to form a plurality of first grooves extending along the first direction Y and arranged evenly spaced along the second direction X in the first region Q1, and a plurality of second grooves extending along the first direction Y and arranged evenly spaced along the second direction X in the second region Q2. The dielectric material layer is further etched to form at least one first separation groove 201 extending along the second direction X in the first region Q1, and at least one second separation groove 202 extending along the second direction X in the second region Q2. Gallium nitride material is epitaxially grown in the first separation groove 201 and the second separation groove 202, and then a group III nitride material is prepared in the first groove by lateral epitaxy (ELOG) to form a third semiconductor layer 212, and a group III nitride material is prepared in the second groove to form a fourth semiconductor layer 222. The extension direction (first direction Y) of the first groove and the second groove is set to the [11-20] crystal direction of the hexagonal system of the gallium nitride material; the extension direction (second direction X) of the first separation groove 201 and the second separation groove 202 is set to the [1-100] crystal direction of the hexagonal system of the gallium nitride material, which can improve the crystal quality of the third semiconductor layer 212 formed in the first groove and the crystal quality of the fourth semiconductor layer 222 formed in the second groove, thereby effectively improving the reflectivity of the first reflector structure 21 and the second reflector structure 22, and through lateral epitaxy, effectively reducing the difficulty of preparing the third semiconductor layer 212 formed in the first groove and the fourth semiconductor layer 222 in the second groove. Optionally, the cross-sectional width of the first separation groove 201 and the second separation groove 202 is greater than the width of the first groove and the second groove, and the cross-sectional width is parallel to the plane of the substrate (10), so that the III-group nitride material is first formed in the first separation groove 201 and the second separation groove 202, and then laterally epitaxially grows from the first separation groove 201 and the second separation groove 202 to the first groove and the second groove. In other embodiments, the first groove and the second groove do not penetrate the dielectric material layer, that is, the depth of the first groove and the second groove is less than the thickness of the dielectric material layer, so as to ensure that the third semiconductor layer 212 and the fourth semiconductor layer 222 are prepared by the above-mentioned lateral epitaxy method.

[0122] Based on the above embodiments, in one embodiment of the present invention, reference is made to Figure 1 to Figure 3 , the light emitting structure 30 comprises:

[0123] The first semiconductor layer 31 , the active layer 33 , and the second semiconductor layer 32 are sequentially stacked on the substrate 10 .

[0124] Specifically, the first semiconductor layer 31 is located on one side of the substrate 10 ; the active layer 33 is located on a side of the first semiconductor layer 31 away from the substrate 10 ; and the second semiconductor layer 32 is located on a side of the active layer 33 away from the substrate 10 .

[0125] The materials of the first semiconductor layer 31, the active layer 33 and the second semiconductor layer 32 include group III nitride materials. The semiconductor structure can be a laser using semiconductor materials such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), aluminum nitride (AlN), indium gallium nitride (InGaN), cadmium sulfide (CdS), zinc sulfide (ZnS) and the like as working materials. A semiconductor laser is a miniaturized laser using a PN junction composed of a direct bandgap semiconductor material as a working material. The first semiconductor layer 31 and the second semiconductor layer 32 have opposite conductivity types. If the first semiconductor layer 31 is an N-type semiconductor layer, the second semiconductor layer 32 is a P-type semiconductor layer. If the first semiconductor layer 31 is a P-type semiconductor layer, the second semiconductor layer 32 is an N-type semiconductor layer.

[0126] In one embodiment of the present invention, reference Figure 4 and Figure 5 The semiconductor structure further includes a first electrode 51 and a second electrode 52 ; the first electrode 51 is electrically connected to the first semiconductor layer 31 , and the second electrode 52 is electrically connected to the second semiconductor layer 32 .

[0127] refer to Figure 5 , the first electrode 51 and the second electrode 52 may be located on the same side of the substrate 10; or, referring to Figure 4 , the first electrode 51 and the second electrode 52 may be located on different sides of the substrate 10. When the first electrode 51 and the second electrode 52 are located on the same side of the substrate 10, the first electrode 51 is located on the side of the second semiconductor layer 32 away from the substrate 10; by sequentially etching a portion of the second semiconductor layer 32 and the active layer 33, an opening exposing a portion of the first semiconductor layer 31 is formed in the light emitting structure 30, and the second electrode 52 is disposed on the side of the exposed first semiconductor layer 31 away from the substrate 10. When the first electrode 51 and the second electrode 52 may be located on different sides of the substrate 10, the first electrode 51 is located on the side of the second semiconductor layer 32 away from the substrate 10, and the second electrode 52 is located on the side of the substrate 10 away from the light emitting structure 30.

[0128] An embodiment of the present invention further provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure described in any of the above embodiments; Figure 6 is a flow chart of a method for preparing a semiconductor laser provided by an embodiment of the present invention, with reference to Figure 6 , the method for preparing the semiconductor structure comprises:

[0129] S110, providing a substrate; the substrate comprises a first region, a second region, and a third region located between the first region and the second region.

[0130] Specifically, the material of the substrate may be silicon, sapphire or SiC. A buffer layer is provided on the surface of the substrate so that the quality and surface of the substrate can meet the requirements of directly preparing the light-emitting structure. The material of the buffer layer may be the same as the material of the light-emitting structure or a material with similar properties, thereby improving the crystal quality of the III-nitride material of the light-emitting structure.

[0131] S120, forming a first reflector structure and a second reflector structure in the first region and the second region of the substrate respectively.

[0132] Specifically, the first reflector structure and / or the second reflector structure may be a Bragg reflector structure. The more the number of DBR components, the higher the reflectivity. Setting the first reflector structure and the second reflector structure as a Bragg reflector structure can enhance the light emitted by the light emitting structure.

[0133] S130, forming a light-emitting structure in the third region of the substrate; wherein the first reflector structure, the second reflector structure and the light-emitting structure are located on the same side of the substrate, and the reflective surfaces of the first reflector structure and the second reflector structure face the side wall of the light-emitting structure.

[0134] Specifically, by forming a first reflector structure, a light-emitting structure, and a second reflector structure side by side on the same side of the substrate, and arranging the light-emitting structure between the first reflector structure and the second reflector structure, the reflection surfaces of the first reflector structure and the second reflector structure are directly opposite to the side wall of the light-emitting structure, so that the first reflector structure and the second reflector structure reflect the light generated by the light-emitting structure in a direction parallel to the substrate, and the light is emitted from the side of the light-emitting structure. Since the light-emitting structure can be formed on the substrate, it replaces the method of stacking the light-emitting structure on the reflector structure in the prior art, and prevents the III-nitride material of the light-emitting structure from being formed on the dielectric material film layer, thereby improving the crystal quality of the III-nitride material of the light-emitting structure, thereby improving the light extraction efficiency of the semiconductor structure, reducing the risk of film cracking in the semiconductor structure, and ensuring the service life of the semiconductor structure.

[0135] Figure 7 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention, with reference to Figure 7 , the method for preparing the semiconductor structure comprises:

[0136] S210, providing a substrate; the substrate comprises a first region, a second region, and a third region located between the first region and the second region.

[0137] Specifically, refer to Figure 8 The material of the substrate 10 can be silicon, sapphire or SiC etc. A buffer layer is arranged on the surface of the substrate 10 so that the quality and surface of the substrate 10 can meet the requirements of directly preparing the light emitting structure 30 .

[0138] S220, forming a dielectric material layer on a surface of one side of the substrate; wherein the dielectric material layer is a single film layer structure or a multi-film layer structure.

[0139] Specifically, refer to Fig. 9 , a dielectric material layer 200 is formed on the surface of one side of the substrate 10; wherein the dielectric material layer 200 is a single film layer structure, or a multi-film layer structure. When the dielectric material layer 200 is a single film layer structure, the material of the dielectric material layer 200 may include SiO2 or SiN. When the dielectric material layer 200 is a multi-film layer structure, the material of the dielectric material layer 200 may include SiO2 and SiN, and the SiO2 film layer and the SiN film layer are stacked in a direction perpendicular to the substrate 10.

[0140] S230, patterning the dielectric material layer, forming a plurality of first grooves extending along the first direction and evenly spaced along the second direction in the first region, and forming a plurality of second grooves extending along the first direction and evenly spaced along the second direction in the second region, wherein the second direction is the direction from the first reflector structure to the light-emitting structure, and the first direction and the second direction are perpendicular to each other.

[0141] Specifically, refer to Fig.10 The dielectric material layer 200 can be patterned by a mask plate, and the pattern in the mask plate can be transferred to the dielectric material layer 200. A plurality of first grooves 2120 extending along the first direction Y and arranged evenly in the second direction X are formed in the first region Q1 of the substrate 10, and a plurality of second grooves 2220 extending along the first direction Y and arranged evenly in the second direction X are formed in the second region Q2.

[0142] S240, preparing a group III nitride material in the first groove to form a third semiconductor layer, and preparing a group III nitride material in the second groove to form a fourth semiconductor layer; wherein the dielectric material layer located in the first area is used to form a first sub-dielectric layer, and the dielectric material layer located in the second area is used to form a second sub-dielectric layer.

[0143] Specifically, refer to Fig.11, a group III nitride material is prepared in the first groove 2120 to form a third semiconductor layer 212, and a group III nitride material is prepared in the second groove 2220 to form a fourth semiconductor layer 222. It should be noted that in the first reflector structure 21, the film layer in contact with the side wall of the light emitting structure 30 is the first sub-dielectric layer 211, which prevents the third semiconductor layer 212 from contacting the side wall of the light emitting structure 30 and causing a short circuit of the device. In the second reflector structure 22, the film layer in contact with the side wall of the light emitting structure 30 is the second sub-dielectric layer 221, which prevents the fourth semiconductor layer 222 from contacting the side wall of the light emitting structure 30 and causing a short circuit of the device.

[0144] S250, forming a light-emitting structure in the third region of the substrate; wherein the first reflector structure, the second reflector structure and the light-emitting structure are located on the same side of the substrate, and the reflective surfaces of the first reflector structure and the second reflector structure face the side wall of the light-emitting structure.

[0145] For details, refer to Fig.12 A passivation layer 300 is formed on the first region Q1, the second region Q2, and the third region Q3. The passivation layer 300 may be made of dielectric materials such as SiO2 or SiN. Fig.13 , the passivation layer 300 and the dielectric material layer 200 in the third region Q3 are etched to expose the substrate 10. Figure 14 to Figure 16 , a first semiconductor layer 31, an active layer 33 and a second semiconductor layer 32 are sequentially grown in the third region Q3 on the substrate 10 to form a light-emitting structure 30. Among them, the passivation layer 300 is used to prevent the semiconductor material from growing on the first region Q1 and the second region Q2 when the semiconductor material is grown in the third region Q3. The passivation layer 300 is also used to protect the DBR material layers on both sides. By arranging the first reflector structure 21, the light-emitting structure 30 and the second reflector structure 22 side by side on the same side of the substrate 10, it is only necessary to ensure that the quality and surface of the substrate 10 can meet the requirements of directly preparing the light-emitting structure 30, so as to improve the light extraction efficiency of the semiconductor structure, reduce the risk of film cracking in the semiconductor structure, and ensure the service life of the semiconductor structure.

[0146] Fig.17 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention, with reference to Fig.17 , the method for preparing the semiconductor structure comprises:

[0147] S310, providing a substrate; the substrate includes a first region, a second region, and a third region located between the first region and the second region.

[0148] S320, forming a dielectric material layer on a surface of one side of the substrate; wherein the dielectric material layer is a single film layer structure or a multi-film layer structure.

[0149] S330, patterning the dielectric material layer, forming a plurality of first grooves extending along the first direction and evenly spaced along the second direction in the first region, and forming a plurality of second grooves extending along the first direction and evenly spaced along the second direction in the second region, wherein the second direction is the direction from the first reflector structure to the light-emitting structure, and the first direction and the second direction are perpendicular to each other.

[0150] S340, continue to pattern the dielectric material layer to form at least one first separation groove extending along the second direction and penetrating the first groove in the first region, and to form at least one second separation groove extending along the second direction and penetrating the second groove in the second region; wherein the depth of the first separation groove is greater than or equal to the depth of the first groove; and the depth of the second separation groove is greater than or equal to the depth of the second groove.

[0151] Specifically, refer to Fig.18 The first separation groove 201 extends along the second direction X, and the first separation groove 201 is connected to the first groove 2120. The second separation groove 202 extends along the second direction X, and the second separation groove 202 is connected to the second groove 2220.

[0152] S350 , preparing a Group III nitride material in the first separation groove and the second separation groove.

[0153] S360, preparing a full III-nitride material from the first separation groove into the first groove by lateral epitaxy to form a third semiconductor layer, and preparing a full III-nitride material from the second separation groove into the second groove by lateral epitaxy to form a fourth semiconductor layer.

[0154] Specifically, refer to Fig.19 , Group III nitride materials, such as gallium nitride materials, are prepared in the first groove 2120, the second groove 2220, the first separation groove 201, and the second separation groove 202. Gallium nitride materials are grown epitaxially in the first separation groove 201 and the second separation groove 202, and then a full Group III nitride material is grown in the first groove 2120 by lateral epitaxy to form the third semiconductor layer 212, and a full Group III nitride material is grown in the second groove 2220 to form the fourth semiconductor layer 222. The extension direction (first direction Y) of the first groove 2120 and the second groove 2220 is set to the [11-20] crystal direction of the hexagonal system of the gallium nitride material; the extension direction (second direction X) of the first separation groove 201 and the second separation groove 202 is set to the [1-100] crystal direction of the hexagonal system of the gallium nitride material, which can improve the crystal quality of the third semiconductor layer 212 formed in the first groove 2120, and improve the crystal quality of the fourth semiconductor layer 222 formed in the second groove 2220.

[0155] S370, etching the dielectric material layer located in the third region until the substrate is exposed. Fig. 20 Before etching the dielectric material layer located in the third region, a passivation layer 300 is formed on the surface of the device. The function of the passivation layer 300 can be referred to the above embodiment and will not be described in detail here. Fig.21 , the passivation layer 300 and the dielectric material layer located in the third region Q3 are etched until the substrate 10 is exposed.

[0156] S380: forming a first semiconductor layer in the third region. Fig. 22 , a first semiconductor layer 31 is formed in the third region Q3. The material of the first semiconductor layer 31 includes a group III nitride material.

[0157] S390, forming an active layer on a surface of the first semiconductor layer away from the substrate. Fig.23 An active layer 33 is formed on a surface of the first semiconductor layer 31 away from the substrate 10. The material of the active layer 33 includes a group III nitride material.

[0158] S3100, forming a second semiconductor layer on a surface of the active layer away from the substrate. Fig.24 A second semiconductor layer 32 is formed on the surface of the active layer 33 away from the substrate 10. The material of the second semiconductor layer 32 includes a group III nitride material. The first semiconductor layer 31 and the second semiconductor layer 32 have different conductivity types.

[0159] On the basis of the above embodiments, in the semiconductor preparation method provided by the embodiment of the present invention, a full III-nitride material is prepared in the first groove 2120 to form a third semiconductor layer 212, and a full III-nitride material is prepared in the second groove 2220 to form a fourth semiconductor layer 222, specifically comprising: patterning the dielectric material layer to form at least one first separation groove 201 extending along the second direction X in the first area Q1, and forming at least one second separation groove 202 extending along the second direction X in the second area Q2; the depth of the first separation groove 201 is greater than or equal to the depth of the first groove 2120; the depth of the second separation groove 202 is greater than or equal to the depth of the second groove 2220; preparing the III-nitride material in the first separation groove 201 and the second separation groove 202; preparing the full III-nitride material in the first groove 2120 by lateral epitaxy to form the third semiconductor layer 212, and preparing the full III-nitride material in the second groove 2220 to form the fourth semiconductor layer 222. A light emitting structure 30 is formed in the third region Q3 of the substrate 10, specifically comprising: etching the dielectric material layer located in the third region Q3 until the substrate 10 is exposed; forming a first semiconductor layer 31 in the third region Q3; forming an active layer 33 on a surface of the first semiconductor layer 31 away from the substrate 10; and forming a second semiconductor layer 32 on a surface of the active layer 33 away from the substrate 10.

[0160] In the methods for preparing semiconductor lasers of the above-mentioned embodiments, after forming the first reflector structure and the second reflector structure in the first region and the second region of the substrate respectively, the light emitting structure is formed in the third region of the substrate. Alternatively, after forming the light emitting structure in the third region of the substrate, the first reflector structure and the second reflector structure are formed in the first region and the second region of the substrate respectively.

[0161] Fig.25 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention, with reference to Fig.25 , the method for preparing the semiconductor structure comprises:

[0162] S410, providing a substrate; the substrate includes a first region, a second region, and a third region located between the first region and the second region. For specific structure, please refer to Figure 8 , I will not go into details here.

[0163] S420, forming a dielectric material layer on the surface of one side of the substrate; wherein the dielectric material layer is a single film layer structure or a multi-film layer structure. For specific structures, please refer to Fig. 9 , I will not go into details here.

[0164] S430, etching the dielectric material layer in the third region until the substrate is exposed, and forming a light emitting structure in the third region of the substrate. Fig.26 and Fig. 27 , I will not go into details here.

[0165] S440, patterning the dielectric material layer, forming a plurality of first grooves extending along the first direction and evenly spaced along the second direction in the first region, and forming a plurality of second grooves extending along the first direction and evenly spaced along the second direction in the second region; wherein the second direction is the direction from the first reflector structure to the light-emitting structure, and the first direction and the second direction are perpendicular to each other.

[0166] S450, prepare a third semiconductor layer made of a full III-group nitride material in the first groove to form a first reflector structure in the first region; and prepare a fourth semiconductor layer made of a full III-group nitride material in the second groove to form a second reflector structure in the second region; wherein the first reflector structure, the second reflector structure and the light-emitting structure are located on the same side of the substrate, and the reflection surfaces of the first reflector structure and the second reflector structure face the side wall of the light-emitting structure; the dielectric material layer located in the first region is used to form a first sub-dielectric layer, and the dielectric material layer located in the second region is used to form a second sub-dielectric layer. For specific structures, please refer to Fig.30 , which will not be described here. Optionally, refer to Fig.28 Before step S450, a passivation layer 300 may be formed on the light emitting structure. The function of the passivation layer 300 is to protect the light emitting structure and prevent the epitaxial growth of group III nitride materials on the light emitting structure.

[0167] Fig.31 is a flow chart of another method for preparing a semiconductor laser provided by an embodiment of the present invention, with reference to Fig.31 , the method for preparing the semiconductor structure comprises:

[0168] S510, providing a substrate; the substrate includes a first region, a second region, and a third region located between the first region and the second region. For specific structure, please refer to Figure 8 , I will not go into details here.

[0169] S520, forming a dielectric material layer on the surface of one side of the substrate; wherein the dielectric material layer is a single film layer structure or a multi-film layer structure. For specific structures, please refer to Fig. 9 , I will not go into details here.

[0170] S530, etching the dielectric material layer in the third region until the substrate is exposed, and forming a light emitting structure in the third region of the substrate. For a specific structure, refer to Fig.26 and Fig. 27 , I will not go into details here.

[0171] S540, patterning the dielectric material layer, forming a plurality of first grooves extending along the first direction and arranged evenly in the second direction in the first region, and forming a plurality of second grooves extending along the first direction and arranged evenly in the second direction in the second region, wherein the second direction is the direction in which the first reflector structure points to the light emitting structure, and the first direction and the second direction are perpendicular to each other. For specific structures, please refer to Fig.28 and Fig.29 , I will not go into details here.

[0172] S550, continue to pattern the dielectric material layer to form at least one first separation groove extending along the second direction and penetrating the first groove in the first region, and at least one second separation groove extending along the second direction and penetrating the second groove in the second region; wherein the depth of the first separation groove is greater than or equal to the depth of the first groove; and the depth of the second separation groove is greater than or equal to the depth of the second groove. For specific structure reference Fig.32 , I will not go into details here.

[0173] S560, preparing a group III nitride material in the first separation groove and the second separation groove. Optionally, as Fig.32 Before step S560, a passivation layer 300 may be prepared on the light emitting structure in the third region. The function of the passivation layer 300 is to protect the light emitting structure and prevent the epitaxial growth of group III nitride materials on the light emitting structure.

[0174] S570, forming a third semiconductor layer by preparing a full III-group nitride material from the first separation groove to the first groove by lateral epitaxy, and forming a fourth semiconductor layer by preparing a full III-group nitride material from the second separation groove to the second groove by lateral epitaxy. Fig.33 , I will not go into details here.

[0175] Based on any of the above embodiments, optionally, refer to Figure 5 , after forming the light emitting structure 30 in the third region Q3 of the substrate 10, further comprising:

[0176] A first electrode 51 is formed on a side of the second semiconductor layer 32 away from the substrate 10;

[0177] A second electrode 52 is formed on a side of the substrate 10 away from the light emitting structure 30;

[0178] Alternatively, refer to Figure 4 , after forming the light emitting structure 30 in the third region Q3 of the substrate 10, further comprising:

[0179] Sequentially etching portions of the second semiconductor layer 32 and the active layer 33 until portions of the first semiconductor layer 31 are exposed;

[0180] A first electrode 51 is formed on a side of the second semiconductor layer 32 away from the substrate 10;

[0181] A second electrode 52 is formed on a side of the exposed first semiconductor layer 31 away from the substrate 10 .

[0182] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate (10) comprising a first region (Q1), a second region (Q2), and a third region (Q3) located between the first region (Q1) and the second region (Q2); A first reflector structure (21) located in a first region (Q1) of the substrate (10); A second reflector structure (22) is located in a second region (Q2) of the substrate (10) and is located on the same side of the substrate (10) as the first reflector structure (21); a light emitting structure (30) located in a third region (Q3) of the substrate (10) and located on the same side of the substrate (10) as the first reflector structure (21); The reflective surfaces of the first reflector structure (21) and the second reflector structure (22) face the side walls of the light-emitting structure (30).

2. The semiconductor structure according to claim 1, characterized in that: The first reflector structure (21) and / or the second reflector structure (22) is a Bragg reflector structure, wherein: The first reflector structure (21) comprises a first sub-medium layer (211) covering the side wall of the light emitting structure (30), the first sub-medium layer (211) being provided with a plurality of evenly distributed first grooves (2120) and a third semiconductor layer (212) prepared in the first grooves (2120), The second reflector structure (22) comprises a second sub-medium layer (221) covering the side wall of the light-emitting structure (30), wherein the second sub-medium layer (221) is provided with a plurality of evenly distributed second grooves (2220) and a fourth semiconductor layer (222) prepared in the second grooves (2220).

3. The semiconductor structure according to claim 2, characterized in that: The first groove (2120) extends along a first direction (Y), and the plurality of first grooves (2120) are arranged at intervals along a second direction (X); The second groove (2220) extends along the first direction (Y), and the plurality of second grooves (2220) are arranged at intervals along the second direction (X); The second direction (X) is the direction in which the first reflector structure (21) points to the light-emitting structure (30), and the first direction (Y) and the second direction (X) are perpendicular to each other.

4. The semiconductor structure according to claim 2, characterized in that: The number of the first grooves (2120) is less than the number of the second grooves (2220).

5. The semiconductor structure according to claim 2, characterized in that: The width (L1) of the first groove (2120) is less than 100 nm, and the interval (L2) between the plurality of first grooves (2120) is less than 150 nm; The width (L3) of the second groove (2220) is less than 100 nm, and the interval (L4) between the plurality of second grooves (2220) is less than 150 nm.

6. The semiconductor structure according to claim 2, characterized in that: The first sub-dielectric layer (211) and the second sub-dielectric layer (221) are single-layer material layers; wherein the material of the first sub-dielectric layer (211) includes SiO2 or SiN; and the material of the second sub-dielectric layer (221) includes SiO2 or SiN; Alternatively, the first sub-dielectric layer (211) and the second sub-dielectric layer (221) are stacked material layers, and the first sub-dielectric layer (211) and the second sub-dielectric layer (221) include multiple DBR material layers stacked vertically to the substrate (10); wherein the material of the first sub-dielectric layer (211) includes SiO2 and SiN; and the material of the second sub-dielectric layer (221) includes SiO2 and SiN.

7. The semiconductor structure according to claim 2, characterized in that: The first groove penetrates through or partially penetrates through the first sub-dielectric layer; And / or, the second groove passes through or partially passes through the second sub-dielectric layer.

8. The semiconductor structure according to claim 3, characterized in that: The materials of the third semiconductor layer and the fourth semiconductor layer include group III nitride materials; The first reflector structure (21) further comprises a first separation groove (201), the first separation groove (201) extending along the second direction (X), the first separation groove (201) being connected to the first groove (2120); a group III nitride material is prepared in the first separation groove (201); The second reflector structure (22) also includes a second separation groove (202), the second separation groove (202) extending along a second direction (X), the second separation groove (202) being connected to the second groove (2220); and a group III nitride material is prepared in the second separation groove (202).

9. The semiconductor structure according to claim 8, characterized in that: The group III nitride material includes gallium nitride material; The first direction (Y) is the [11-20] crystal direction of the hexagonal system of the gallium nitride material; and the second direction (X) is the [1-100] crystal direction of the hexagonal system of the gallium nitride material.

10. The semiconductor structure according to claim 8, characterized in that Along a direction perpendicular to the substrate (10), the depth of the first separation groove (201) is greater than or equal to the thickness of the first reflector structure (21); And / or, along a direction (Z) perpendicular to the substrate (10), the depth of the second separation groove (202) is greater than or equal to the thickness of the second reflector structure (22).

11. The semiconductor structure according to claim 1, characterized in that: The light emitting structure (30) comprises: A first semiconductor layer (31), an active layer (33) and a second semiconductor layer (32) are sequentially stacked on the substrate (10); The conductivity types of the first semiconductor layer (31) and the second semiconductor layer (32) are opposite.

12. The semiconductor structure according to claim 11, characterized in that: The materials of the first semiconductor layer (31), the active layer (33) and the second semiconductor layer (32) include group III nitride materials.

13. The semiconductor structure according to claim 11, characterized in that: It also includes a first electrode (51) and a second electrode (52); the first electrode (51) is electrically connected to the first semiconductor layer (31), and the second electrode (52) is electrically connected to the second semiconductor layer (32).

14. A method for preparing a semiconductor structure, characterized in that: Used for preparing the semiconductor structure according to any one of claims 1 to 13; comprising: A substrate (10) is provided; the substrate (10) comprises a first region (Q1), a second region (Q2), and a third region (Q3) located between the first region (Q1) and the second region (Q2); Forming a first reflector structure (21) and a second reflector structure (22) in the first region (Q1) and the second region (Q2) of the substrate (10), respectively; A light-emitting structure (30) is formed in a third region (Q3) of the substrate (10); wherein the first reflector structure (21), the second reflector structure (22) and the light-emitting structure (30) are located on the same side of the substrate (10), and the reflective surfaces of the first reflector structure (21) and the second reflector structure (22) face the side walls of the light-emitting structure (30).

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: After forming a first reflector structure (21) and a second reflector structure (22) in the first region (Q1) and the second region (Q2) of the substrate (10), respectively, a light emitting structure (30) is formed in the third region (Q3) of the substrate (10); Alternatively, after forming the light emitting structure (30) in the third region (Q3) of the substrate (10), a first reflector structure (21) and a second reflector structure (22) are respectively formed in the first region (Q1) and the second region (Q2) of the substrate (10).

16. The method for preparing a semiconductor structure according to claim 14, characterized in that: A first reflector structure (21) and a second reflector structure (22) are formed in the first region (Q1) and the second region (Q2) of the substrate (10), respectively, comprising: A dielectric material layer is formed on a surface of one side of the substrate (10); wherein the dielectric material layer (200) is a single film layer structure or a multi-film layer structure; The dielectric material layer (200) is patterned to form a plurality of first grooves (2120) extending along a first direction (Y) and arranged evenly at intervals along a second direction (X) in a first region (Q1), and a plurality of second grooves (2220) extending along the first direction (Y) and arranged evenly at intervals along a second direction (X) in a second region (Q2), wherein the second direction (X) is the direction in which the first reflector structure (21) points toward the light-emitting structure (30), and the first direction (Y) and the second direction (X) are perpendicular to each other; A group III nitride material is prepared in the first groove (2120) to form a third semiconductor layer (212), and a group III nitride material is prepared in the second groove (2220) to form a fourth semiconductor layer (222); wherein the dielectric material layer located in the first region is used to form a first sub-dielectric layer (211), and the dielectric material layer located in the second region is used to form a second sub-dielectric layer (222).

17. The method for preparing a semiconductor structure according to claim 16, characterized in that: The patterning of the dielectric material layer (200) further comprises forming at least one first separation groove (201) extending along the second direction (Y) and penetrating the first groove (2120) in the first region (Q1), and forming at least one second separation groove (202) extending along the second direction (Y) and penetrating the second groove (2220) in the second region (Q2); wherein the depth of the first separation groove (201) is greater than or equal to the depth of the first groove (2120); and the depth of the second separation groove (202) is greater than or equal to the depth of the second groove (2220); The method of preparing a group III nitride material in the first groove (2120) to form a third semiconductor layer (212), and preparing a group III nitride material in the second groove (2220) to form a fourth semiconductor layer (222), comprises: Preparing a group III nitride material in the first dividing groove (201) and the second dividing groove (202); The third semiconductor layer (212) is formed by preparing a group III nitride material from the first separation groove (201) into the first groove (2120) by lateral epitaxy, and the fourth semiconductor layer (222) is formed by preparing a group III nitride material from the second separation groove (202) into the second groove (2220) by lateral epitaxy.

18. The method for preparing a semiconductor structure according to claim 14, characterized in that: A light emitting structure (30) is formed in the third region (Q3) of the substrate (10), comprising: Etching the dielectric material layer located in the third region (Q3) until the substrate (10) is exposed; forming a first semiconductor layer (31) in the third region (Q3); forming an active layer (33) on a surface of the first semiconductor layer (31) that is away from the substrate (10); A second semiconductor layer (32) is formed on a surface of the active layer (33) that is away from the substrate (10).

19. The method for preparing a semiconductor structure according to claim 18, characterized in that: After forming a light emitting structure (30) in the third region (Q3) of the substrate (10), the method further comprises: forming a first electrode (51) on a side of the second semiconductor layer (32) away from the substrate (10); forming a second electrode (52) on a side of the substrate (10) away from the light-emitting structure (30); Alternatively, after forming the light emitting structure (30) in the third region (Q3) of the substrate (10), the method further comprises: Sequentially etching portions of the second semiconductor layer (32) and the active layer (33) until portions of the first semiconductor layer (31) are exposed; forming a first electrode (51) on a side of the second semiconductor layer (32) away from the substrate (10); A second electrode (52) is formed on the side of the exposed first semiconductor layer (31) away from the substrate (10).

Images