Semiconductor optical amplification chip with long carrier lifetime

Abstract

The invention relates to the technical field of semiconductor light amplification, and particularly provides a semi-inventive conductor light amplification chip with long carrier lifetime. Comprising a substrate, a lower cladding, an N-type carrier limiting layer, an N-type carrier storage layer, a lower waveguide layer, a tunneling lower limiting layer, a lower limiting layer, a source layer, an upper limiting layer, a tunneling upper limiting layer, an upper waveguide layer, a P-type carrier storage layer, a P-type carrier limiting layer, an upper cladding and an upper contact layer which are sequentially arranged from bottom to top. The semiconductor material structure is optimally designed, the stored energy band structure material layer is limited, the carrier life of the optical amplification chip is prolonged, the nonlinear effect of the optical amplification chip is greatly reduced, the nonlinear characteristic of the SOA is remarkably improved, and signal distortion is reduced, so that a better application effect is achieved in the fields of optical communication and sensing; therefore, higher efficiency, stability and economical efficiency are brought to the future optical communication technology, and the SOA becomes a new-generation optical amplifier technology capable of replacing an EDFA (erbium-doped fiber amplifier).

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor light amplification, and in particular to a semiconductor light amplification chip with a long carrier lifetime. Background Art

[0002] In the application of optical amplifiers, fields such as optical fiber communication and optical sensing play a vital role. At present, erbium-doped fiber amplifiers (EDFA) are the most widely used optical amplifiers in the field of optical communications due to their excellent characteristics of long carrier lifetime, low nonlinearity, high saturation power and low noise. However, with the continuous expansion of application scenarios in the future, EDFA also faces a series of challenges in certain fields, such as high cost, high power consumption and large size.

[0003] In contrast, semiconductor optical amplifiers (SOAs) are gaining more and more attention and applications due to their advantages of low power consumption, small size and low cost. Especially in some scenarios with high space requirements and sensitive energy consumption, SOAs have shown great potential. However, compared with EDFA, there is still a significant gap in the performance of SOAs, especially in the nonlinear characteristics caused by the short carrier lifetime. Specifically, due to the characteristics of its semiconductor PN junction, SOAs usually have a very short carrier lifetime, generally on the order of 0.1 nanoseconds (ns), while EDFAs have a longer carrier lifetime, usually on the order of milliseconds (ms). This difference makes SOAs prone to significant optical signal distortion and signal degradation during the optical signal amplification process, thus affecting their application in high-performance optical communications.

[0004] The carriers of the chip include holes and electrons. Holes and electrons are two types of carriers in semiconductors. There is a close relationship between them. The generation mechanism of holes and electrons is as follows:

[0005] Electrons: In semiconductors, when the temperature rises (such as room temperature) or is affected by external factors such as light, the valence electrons in certain covalent bonds will gain enough energy to break free from the constraints of the covalent bonds, jump to the conduction band, and become free electrons. For example, in pure silicon materials, if pentavalent elements (such as phosphorus, arsenic or antimony) are added, the excess electrons of these impurity atoms are also likely to become free electrons. The formed semiconductor is called an n-type semiconductor, in which electrons are the majority carriers.

[0006] Hole: When valence electrons jump to the conduction band and become free electrons, the same number of vacancies will be left in the covalent bond, and this vacancy is called a hole. When trivalent elements (such as boron, aluminum or indium) are added to pure silicon materials, a lack of electrons will occur, thus generating holes. This type of semiconductor is called a p-type semiconductor, and holes are the majority carriers.

[0007] Electrons carry negative charges, while holes carry positive charges, and the amount of charge they carry is equal. In the absence of an external electric field, the movement of carriers is irregular and there is no directional movement, so no current is formed. Under the action of an external electric field, electrons will move in the opposite direction of the electric field, forming an electron current; while the movement of holes is more special. Because they are positively charged, their movement direction is opposite to that of electrons, and they move along the direction of the electric field. And the valence electrons in the adjacent covalent bonds can easily jump over to fill the holes, so that the holes are transferred to the adjacent covalent bonds. The movement effect of the valence electrons filling the holes in turn is similar to the movement of holes along the electric field, forming a hole current. In pure semiconductors, electrons and holes will continue to be generated and recombined. When the temperature rises or there is external energy excitation, more electron-hole pairs will be generated; at the same time, electrons and holes will meet and combine, reducing their number. At a certain temperature, the generation rate and recombination rate of electrons and holes will reach a dynamic equilibrium, and the concentration of carriers will remain relatively stable at this time. The conductivity of semiconductors depends on the concentration and mobility of carriers. In n-type semiconductors, the electron concentration is high and electrons are the main carriers, so the movement of electrons contributes more to the current; in p-type semiconductors, the hole concentration is high and holes are the main carriers, and the movement of holes determines the magnitude of the current.

[0008] Therefore, in order to improve the overall performance of SOA, extending its carrier lifetime becomes a key research direction. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor optical amplifier chip with a long carrier lifetime, so as to solve the problem of short carrier lifetime of semiconductor optical amplifiers in the prior art.

[0010] To achieve the above-mentioned object and other related objects, the present invention provides a semiconductor optical amplifier chip with a long carrier lifetime, comprising:

[0011] N-type doped InP substrate;

[0012] N-type doped InP lower cladding layer;

[0013] N-type doped InGaAsP lower waveguide layer;

[0014] Undoped InGaAsP lower confinement layer;

[0015] Undoped InGaAsP active layer;

[0016] Undoped InGaAsP upper confinement layer;

[0017] P-type doped InGaAsP upper waveguide layer;

[0018] P-type doped InP upper cladding layer;

[0019] P-type doped InGaAsP upper contact layer;

[0020] The semiconductor optical amplifier chip further includes:

[0021] N-type carrier confinement layer of N-type doped InP-InGaAsP;

[0022] N-type carrier storage layer of N-type doped InGaAsP;

[0023] Undoped InGaAsP tunneling lower confinement layer;

[0024] Undoped InGaAsP tunneling confinement layer;

[0025] P-type carrier storage layer of P-type doped InGaAsP;

[0026] P-type carrier confinement layer of P-type doped InGaAsP-InP;

[0027] The N-type carrier storage layer is arranged on the upper end of the N-type carrier confinement layer, and the N-type carrier confinement layer is arranged on the upper end of the lower cladding layer;

[0028] The tunneling lower confinement layer is disposed between the lower waveguide layer and the lower confinement layer;

[0029] The tunneling upper limiting layer is arranged between the upper limiting layer and the upper waveguide layer;

[0030] The P-type carrier confinement layer is arranged on the upper end of the P-type carrier storage layer, and the P-type carrier storage layer is arranged on the upper end of the upper waveguide layer.

[0031] In one embodiment of the present invention, the N-type doped impurities are silicon, and the P-type doped impurities are zinc.

[0032] In one embodiment of the present invention, the thickness of the substrate is 400-550 μm, and the concentration of N-type doping is greater than 2E+18 cm -3 ;

[0033] The thickness of the lower cladding layer is 150-230nm, and the concentration of N-type doping is 2E+18cm -3 ;

[0034] The thickness of the lower waveguide layer is 80-120 nm, and the concentration of N-type doping is 5E+17 cm -3 ;

[0035] The thickness of the lower limiting layer is 40-60nm;

[0036] The thickness of the active layer is 20-35 nm;

[0037] The thickness of the upper limiting layer is 40-60nm;

[0038] The thickness of the upper waveguide layer is 90-110 nm, and the concentration of its P-type doping is 5E+17 cm -3 ;

[0039] The thickness of the upper cladding layer is 1900-2100nm, and the concentration of P-type doping is 1E+18cm -3 ;

[0040] The thickness of the upper contact layer is 180-210 nm, and the concentration of P-type doping is greater than 1E+19 cm -3 .

[0041] In one embodiment of the present invention, the thickness of the N-type carrier confinement layer is 90-110 nm, and the concentration of the N-type doping is 1E+18 cm -3 ;

[0042] The thickness of the N-type carrier storage layer is 490-510 nm, and the concentration of the N-type doping is 7E+17 cm -3 ;

[0043] The thickness of the lower limiting layer is 8-12nm;

[0044] The thickness of the upper limiting layer is 8-12 nm;

[0045] The thickness of the P-type carrier storage layer is 450-520nm, and the concentration of the P-type doping is 7E+17cm -3 ;

[0046] The thickness of the P-type carrier confinement layer is 80-120 nm, and the concentration of the P-type doping is 1E+18 cm -3 .

[0047] In one embodiment of the present invention, the material structure of the N-type carrier confinement layer is gradually distributed from InP to InGaAsP from bottom to top.

[0048] In one embodiment of the present invention, the material structure of the P-type carrier confinement layer is gradually distributed from InGaAsP to InP from bottom to top.

[0049] As described above, the semiconductor optical amplifier chip with a long carrier lifetime of the present invention has the following beneficial effects:

[0050] 1. The present invention optimizes the semiconductor material structure by setting a tunneling upper limiting layer, a tunneling lower limiting layer, a P-type carrier storage layer, a P-type carrier limiting layer, an N-type carrier storage layer, and an N-type carrier limiting layer, and limits the stored band structure material layer respectively, wherein the tunneling upper limiting layer cooperates with the P-type carrier storage layer and the P-type carrier limiting layer to realize temporary storage of holes, slow down the time for them to enter the active area for recombination, thereby greatly increasing the life of holes; the tunneling lower limiting layer cooperates with the N-type carrier storage layer and the N-type carrier limiting layer to realize temporary storage of electrons, slow down the time for them to enter the active area for recombination, thereby greatly increasing the life of electrons; thereby extending the carrier life, significantly improving the nonlinear characteristics of SOA, reducing signal distortion, and achieving better application effects in the fields of optical communication and sensing.

[0051] 2. The present invention optimizes the design of the semiconductor material structure, limits the stored energy band structure material layer respectively, and realizes a 10-100 times increase in the carrier lifetime of the optical amplifier chip, greatly reduces the nonlinear effect of the optical amplifier chip, and significantly improves the nonlinear characteristics of SOA. While maintaining miniaturization and low cost, it also has high-performance optical signal amplification characteristics, effectively reduces signal distortion, and thus achieves better application effects in the fields of optical communication and sensing. This will bring higher efficiency, stability and economy to future optical communication technologies, making SOA a new generation of optical amplifier technology that can replace EDFA. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 Shown is a material structure diagram of a semiconductor optical amplifier chip in the prior art.

[0053] Figure 2 Shown is a material structure diagram of a semiconductor light amplifying chip with a long carrier lifetime disclosed in the present invention.

[0054] Figure 3 Shown is a schematic diagram of the energy band structure of the P-side material of the active layer measured in Example 3.

[0055] Figure 4 Shown is a schematic diagram of the energy band structure of the N-side material of the active layer measured in Example 3.

[0056] Figure 5 Shown is a schematic cross-sectional view of a typical ridge waveguide type semiconductor optical amplifier chip disclosed in the present invention.

[0057] Figure 6 Shown is a schematic cross-sectional view of a typical buried heterojunction semiconductor optical amplifier disclosed in the present invention.

[0058] Figure 7It shows a schematic diagram of carrier distribution in a semiconductor optical amplifier chip with a long carrier lifetime disclosed in the present invention under equilibrium state.

[0059] Figure 8 It shows a simulation diagram of the effect of the energy band width of the carrier storage layer on the carrier lifetime disclosed in Example 4.

[0060] Fig. 9 It shows a simulation diagram of the effect of the thickness of the carrier storage layer on the carrier lifetime disclosed in Example 4.

[0061] Component number description

[0062] Substrate 1; lower cladding layer 2; N-type carrier confinement layer 3; N-type carrier storage layer 4; lower waveguide layer 5; tunneling lower confinement layer 6; lower confinement layer 7; active layer 8; upper confinement layer 9; tunneling upper confinement layer 10; upper waveguide layer 11; P-type carrier storage layer 12; P-type carrier confinement layer 13; upper cladding layer 14; upper contact layer 15. DETAILED DESCRIPTION

[0063] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0064] See also Figures 1 to 9 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportion or adjustment of size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0065] Example 1, please refer to Figure 2 , Figure 5 , Figure 6 , Figure 7 , Figure 7 The X-axis is the material layer position, 601 is the P-type carrier storage layer, 602 is the active layer, 603 is the N-type carrier storage layer, 604 is the P-type carrier concentration distribution, and 605 is the N-type carrier concentration distribution; the Y-axis is the carrier concentration, in cm -3The present embodiment provides a semiconductor light amplifying chip with a long carrier lifetime, comprising an N-type doped InP substrate 1, an N-type doped InP lower cladding layer 2, an N-type doped InGaAsP lower waveguide layer 5, an undoped InGaAsP lower confinement layer 7, an undoped InGaAsP active layer 8, an undoped InGaAsP upper confinement layer 9, a P-type doped InGaAsP upper waveguide layer 11, a P-type doped InP upper cladding layer 14, and a P-type doped InGaAsP upper contact layer 15, which are arranged in sequence from bottom to top; the semiconductor light amplifying chip also comprises an N-type carrier confinement layer 3 of N-type doped InP-InGaAsP, an N-type carrier storage layer 4 of N-type doped InGaAsP, an undoped InGaAsP tunneling lower confinement layer 6, an undoped InGaAsP tunneling upper confinement layer 10, a P-type doped InGaAsP P-type carrier storage layer 12, a P-doped InGaAsP-InP P-type carrier confinement layer 13; the N-type carrier storage layer 4 is arranged on the upper end of the N-type carrier confinement layer 3, the N-type carrier confinement layer 3 is arranged on the upper end of the lower cladding layer 2, and the material structure of the N-type carrier confinement layer 3 is gradually distributed from InP to InGaAsP from bottom to top; the tunneling lower confinement layer 6 is arranged between the lower waveguide layer 5 and the lower confinement layer 7; on the P-doped side of the active region, that is, the upper end of the active region, by arranging the tunneling upper confinement layer 10, the P-type carrier storage layer 12 and the P-type carrier confinement layer 13, temporary storage of holes can be achieved, slowing down the time for the holes to enter the active region for recombination, thereby greatly increasing the life of the holes, wherein the P-type carrier storage layer 12 and the P-type carrier confinement layer 13 can play the role of storing holes, and the tunneling upper confinement layer 10 can reduce the probability of holes entering the active region and reduce the probability of electrons escaping from the active region to the P-doped region. The tunneling upper limiting layer 10 is arranged between the upper limiting layer 9 and the upper waveguide layer 11; the P-type carrier limiting layer 13 is arranged on the upper end of the P-type carrier storage layer 12, the P-type carrier storage layer 12 is arranged on the upper end of the upper waveguide layer 11, and the material structure of the P-type carrier limiting layer 13 is gradually distributed from InGaAsP to InP from bottom to top; on the N-doped side of the active area, that is, the lower end of the active area, by arranging the tunneling lower limiting layer 6, the N-type carrier storage layer 4 and the N-type carrier limiting layer 3, temporary storage of electrons can be achieved, slowing down the time for electrons to enter the active area for recombination, thereby greatly increasing the life span of electrons, wherein the N-type carrier storage layer 4 and the N-type carrier limiting layer 3 can play the role of storing electrons, and the tunneling upper limiting layer 10 can reduce the probability of electrons entering the active area and reduce the probability of holes escaping from the active area to the N-doped area.

[0066] The thickness of the substrate 1 is 400-550 μm, and the concentration of N-type doping is greater than 2E+18 cm -3 The thickness of the lower cladding layer 2 is 150-230nm, and the concentration of N-type doping is 2E+18cm-3 The thickness of the lower waveguide layer 5 is 80-120nm, and the concentration of N-type doping is 5E+17cm -3 The thickness of the lower limiting layer 7 is 40-60nm; the thickness of the active layer 8 is 20-35nm; the thickness of the upper limiting layer 9 is 40-60nm; the thickness of the upper waveguide layer 11 is 90-110nm, and the concentration of the P-type doping is 5E+17cm -3 The thickness of the upper cladding layer 14 is 1900-2100nm, and the concentration of the P-type doping is 1E+18cm -3 The thickness of the upper contact layer 15 is 180-210nm, and the concentration of the P-type doping is greater than 1E+19cm -3 The thickness of the N-type carrier confinement layer 3 is 90-110nm, and the concentration of the N-type doping is 1E+18cm -3 The thickness of the N-type carrier storage layer 4 is 490-510nm, and the concentration of the N-type doping is 7E+17cm -3 The thickness of the lower limiting layer is 8-12nm; the thickness of the upper limiting layer is 8-12nm; the thickness of the P-type carrier storage layer 12 is 450-520nm, and the concentration of the P-type doping is 7E+17cm -3 The thickness of the P-type carrier confinement layer 13 is 80-120nm, and the concentration of the P-type doping is 1E+18cm -3 .

[0067] The present invention optimizes the semiconductor material structure by setting a tunneling upper limiting layer 10, a tunneling lower limiting layer 6, a P-type carrier storage layer 12, a P-type carrier limiting layer 13, an N-type carrier storage layer 4, and an N-type carrier limiting layer 5, and limits the stored energy band structure material layers respectively, wherein the tunneling upper limiting layer 10 cooperates with the P-type carrier storage layer 12 and the P-type carrier limiting layer 13 to realize temporary storage of holes, slow down the time for them to enter the active area for recombination, thereby greatly increasing the life of holes; the tunneling lower limiting layer 6 cooperates with the N-type carrier storage layer 4 and the N-type carrier limiting layer 5 to realize temporary storage of electrons, slow down the time for them to enter the active area for recombination, thereby greatly increasing the life of electrons; thereby extending the carrier life, significantly improving the nonlinear characteristics of SOA, reducing signal distortion, and achieving better application effects in the fields of optical communication and sensing.

[0068] Example 2, based on Example 1, this example provides a 1.55um semiconductor optical amplifier chip with a long carrier lifetime. The 1.55um semiconductor optical amplifier chip is an optical amplifier device that works in a 1.55um wavelength window and is mainly used in optical fiber communication systems to amplify optical signals. This chip has the characteristics of high gain, low noise, and wide spectral response, and is suitable for long-distance, high-capacity optical fiber communication systems. Its material structure is shown in Table 1 below:

[0069]

[0070]

[0071] Table 1

[0072] The thickness of the substrate 1 is 500 μm, and the concentration of N-type doping is greater than 2E+18 cm -3 The thickness of the lower cladding layer 2 is 200nm, and the concentration of N-type doping is 2E+18cm -3 The thickness of the lower waveguide layer 5 is 100nm, and the concentration of N-type doping is 5E+17cm -3 The thickness of the lower limiting layer is 50nm; the thickness of the active layer 8 is 30nm; the thickness of the upper limiting layer is 50nm; the thickness of the upper waveguide layer 11 is 100nm, and the concentration of the P-type doping is 5E+17cm -3 The thickness of the upper cladding layer 14 is 2000nm, and the concentration of P-type doping is 1E+18cm -3 The thickness of the upper contact layer 15 is 200nm, and the concentration of the P-type doping is greater than 1E+19cm -3 The thickness of the N-type carrier confinement layer 3 is 100 nm, and the concentration of the N-type doping is 1E+18 cm -3 The thickness of the N-type carrier storage layer 4 is 500nm, and the concentration of the N-type doping is 7E+17cm -3 The thickness of the lower limiting layer is 10nm; the thickness of the upper limiting layer is 10nm; the thickness of the P-type carrier storage layer 12 is 500nm, and the concentration of the P-type doping is 7E+17cm -3 The thickness of the P-type carrier confinement layer 13 is 100 nm, and the concentration of the P-type doping is 1E+18 cm -3 .

[0073] Example 3, please refer to Figure 3 , Figure 4 , Figure 3 , Figure 4The X-axis is the material layer position, and the Y-axis is the energy width, with the unit of Eg; this embodiment provides a test method for testing the energy band width of different material layers in the 1.55um semiconductor optical amplifier chip prepared in Example 2. Specifically, in a multi-layer InGaAsP epitaxial structure, the components and energy band width of different material layers are analyzed by transmission electron microscope energy dispersive spectroscopy (TEM-EDS). The required equipment is as follows:

[0074] (1) Transmission electron microscopy (TEM): used for high-resolution imaging and analysis of the microscopic morphology of multilayer structures. It is recommended to use a transmission electron microscope equipped with high spatial resolution (such as JEOL JEM-2100F).

[0075] (2) Energy dispersive spectroscopy (EDS): usually integrated with TEM to detect the elemental composition of different material layers.

[0076] (3) Sample preparation equipment: including ion milling equipment, focused ion beam system (FIB), etc., used to prepare thin layer samples suitable for TEM observation.

[0077] The specific test steps are as follows:

[0078] (1) Sample preparation

[0079] Mechanical grinding and ion thinning are used to prepare ultra-thin slices suitable for TEM observation, with a thickness of usually less than 100nm. To obtain higher resolution, focused ion beam (FIB) can also be used to finely prepare thin layer samples to ensure the integrity and interface quality of the sample.

[0080] (2) TEM test preparation

[0081] The thin slice sample is mounted on the TEM sample holder, ensuring that the multilayer structure of the sample is parallel to the electron beam direction in order to obtain a clear image of the interlayer interface. The sample is placed in the TEM chamber and evacuated to eliminate impurity interference.

[0082] (3) TEM imaging

[0083] First, low-magnification imaging is performed to observe the overall layered structure and determine the distribution of different material layers. Gradually zoom in to high resolution to observe the interface between layers at the atomic resolution level to confirm the layering and thickness of the sample.

[0084] (4) EDS point analysis

[0085] Focus the electron beam on the target layer and start EDS analysis. The EDS detector detects the elemental composition of each material layer and identifies elements such as In, Ga, As, and P through energy peaks. The chemical composition of each layer is analyzed layer by layer, the content of In, Ga, As, and P in each layer is recorded, and their component ratios are calculated.

[0086] (5) Bandwidth analysis

[0087] Based on the chemical composition analysis results of EDS, the energy band width of each layer is calculated through physical formulas and models (such as the relationship between the energy band width and composition in the material). TEM electron energy loss spectroscopy (EELS) is used to further obtain local energy band structure information to verify the accuracy of the EDS analysis results.

[0088] (6) Data processing and analysis

[0089] According to the element content measured by EDS, the distribution diagrams of In, Ga, As, and P in different layers are analyzed and plotted, so that the energy band width of each layer of InGaAsP can be calculated and the results can be calibrated in combination with EELS data.

[0090] It can be seen from this embodiment that the 1.55 um semiconductor optical amplifier chip prepared by the present invention can significantly reduce the nonlinear effect of the optical amplifier chip compared with the traditional chip.

[0091] Example 4, please refer to Figure 8 , Fig. 9 , Figure 8 The X-axis is the energy band width of the carrier storage layer in eV, the Y-axis is the carrier lifetime in ns, and a is the carrier lifetime curve; Fig. 9 The X-axis is the thickness of the carrier storage layer in nm, the Y-axis is the carrier lifetime in ns, and a is the carrier lifetime curve; this embodiment provides a simulation method for testing the influence of the energy band width of the carrier storage layer of the 1.55um semiconductor optical amplifier chip prepared in Example 2 on the carrier lifetime, and the influence of the thickness of the carrier storage layer on the carrier lifetime. The simulation method is as follows:

[0092] 1). Combined with the known doping concentration and band gap information of InGaAsP material, a material model is established based on the k·p model. And the concentrations of electrons and holes are calculated according to the doping type (n-type or p-type) and doping concentration.

[0093] 2). Use Matlab numerical simulation software to write custom code, set up the physical model, and set up solvers including the drift-diffusion equation, Poisson equation, and recombination rate equation.

[0094] 3) Set boundary conditions according to the physical structure of the device, including injection current density and temperature. Initial conditions usually include the initial concentration of carriers and the light injection intensity of the optical amplifier.

[0095] 4). Run numerical simulation, calculate the recombination rate under different carrier concentrations, and calculate the spontaneous radiation recombination coefficient based on the carrier concentration output by the simulation. Then, the carrier lifetime τ = 1 / (B×n) is obtained based on the spontaneous radiation recombination coefficient and the carrier concentration, where B is the spontaneous radiation recombination coefficient and n is the carrier concentration.

[0096] It can be seen from this embodiment that the 1.55um semiconductor optical amplifier chip prepared by the present invention can increase the carrier lifetime of the optical amplifier chip by 10 to 100 times compared with the traditional chip.

[0097] In summary, the present invention optimizes the design of semiconductor material structure, limits the stored band structure material layer respectively, realizes the increase of carrier lifetime of optical amplifier chip by 10-100 times, greatly reduces the nonlinear effect of optical amplifier chip, and significantly improves the nonlinear characteristics of SOA. While maintaining miniaturization and low cost, it also has high-performance optical signal amplification characteristics, effectively reduces signal distortion, and thus achieves better application effects in the field of optical communication and sensing. This will bring higher efficiency, stability and economy to future optical communication technology, making SOA a new generation of optical amplifier technology that can replace EDFA. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor optical amplifier chip with a long carrier lifetime, comprising: N-type doped InP substrate; N-type doped InP lower cladding layer; N-type doped InGaAsP lower waveguide layer; Undoped InGaAsP lower confinement layer; Undoped InGaAsP active layer; Undoped InGaAsP upper confinement layer; P-type doped InGaAsP upper waveguide layer; P-type doped InP upper cladding layer; P-type doped InGaAsP upper contact layer; Characterized in that the semiconductor optical amplifier chip also includes: N-type carrier confinement layer of N-type doped InP-InGaAsP; N-type carrier storage layer of N-type doped InGaAsP; Undoped InGaAsP tunneling lower confinement layer; Undoped InGaAsP tunneling confinement layer; P-type carrier storage layer of P-type doped InGaAsP; P-type carrier confinement layer of P-type doped InGaAsP-InP; The N-type carrier storage layer is arranged on the upper end of the N-type carrier confinement layer, and the N-type carrier confinement layer is arranged on the upper end of the lower cladding layer; The tunneling lower confinement layer is disposed between the lower waveguide layer and the lower confinement layer; The tunneling upper limiting layer is arranged between the upper limiting layer and the upper waveguide layer; The P-type carrier confinement layer is arranged on the upper end of the P-type carrier storage layer, and the P-type carrier storage layer is arranged on the upper end of the upper waveguide layer.

2. The semiconductor light amplifier chip with long carrier lifetime according to claim 1, characterized in that: The N-type doped impurities are silicon, and the P-type doped impurities are zinc.

3. The semiconductor light amplifier chip with long carrier lifetime according to claim 2, characterized in that: The thickness of the substrate is 400-550 μm, and the concentration of N-type doping is greater than 2E+18 cm -3 ; The thickness of the lower cladding layer is 150-230nm, and the concentration of N-type doping is 2E+18cm -3 ; The thickness of the lower waveguide layer is 80-120 nm, and the concentration of N-type doping is 5E+17 cm -3 ; The thickness of the lower limiting layer is 40-60nm; The thickness of the active layer is 20-35 nm; The thickness of the upper limiting layer is 40-60nm; The thickness of the upper waveguide layer is 90-110 nm, and the concentration of its P-type doping is 5E+17 cm -3 ; The thickness of the upper cladding layer is 1900-2100nm, and the concentration of P-type doping is 1E+18cm -3 ; The thickness of the upper contact layer is 180-210 nm, and the concentration of P-type doping is greater than 1E+19 cm -3 .

4. The semiconductor light amplifier chip with long carrier lifetime according to claim 3, characterized in that The thickness of the N-type carrier confinement layer is 90-110 nm, and the concentration of the N-type doping is 1E+18 cm -3 ; The thickness of the N-type carrier storage layer is 490-510 nm, and the concentration of the N-type doping is 7E+17 cm -3 ; The thickness of the lower limiting layer is 8-12nm; The thickness of the upper limiting layer is 8-12 nm; The thickness of the P-type carrier storage layer is 450-520nm, and the concentration of the P-type doping is 7E+17cm -3 The thickness of the P-type carrier confinement layer is 80-120nm, and the concentration of the P-type doping is 1E+18cm -3 .

5. The semiconductor light amplifier chip with long carrier lifetime according to claim 1, characterized in that: The material structure of the N-type carrier confinement layer is gradually distributed from InP to InGaAsP from bottom to top.

6. The semiconductor light amplifier chip with long carrier lifetime according to claim 1, characterized in that: The material structure of the P-type carrier confinement layer is gradually distributed from InGaAsP to InP from bottom to top.

Images