Selector

Abstract

The selector provided by the embodiment of the invention comprises a control module and an access module, the access module comprises a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch unit, a second switch unit, a voltage control circuit and a sampling transistor; after the control module controls the grid voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, the control module firstly controls the voltage control circuit to enable the voltage of the control end of the sampling transistor to be the first preset value so as to conduct the sampling transistor, and then controls the first switch unit and the second switch unit to change from the off state to the on state after a preset time. The voltage of the control end of the sampling transistor is bootstrapped from the first preset value to the sum of the first preset value and the voltage of the input signal of the input end, and the overvoltage problem of the sampling transistor is avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to a selector. Background Art

[0002] In many industries such as industry, instrumentation, optical communication and medical, multi-channel data acquisition systems are increasingly being used. To reduce costs, multiple inputs are usually multiplexed into an analog-to-digital conversion circuit through a multiplexer circuit, and each channel shares one analog-to-digital conversion circuit, thereby reducing the overall circuit area. In order to improve the linearity of the analog-to-digital conversion circuit, a gate voltage bootstrap circuit is usually set between the multiplexer circuit and the analog-to-digital conversion circuit to improve the sampling linearity of the analog-to-digital conversion circuit.

[0003] According to the working principle of the gate voltage bootstrap circuit, the voltage generated by the gate voltage bootstrap circuit at the gate of the sampling transistor is VIN+VDD. In a single-channel data acquisition system, the input signal is a DC signal or an AC sinusoidal signal. The input signal remains unchanged or changes slowly as a sinusoidal function. There is no sudden signal jump. Therefore, there is no overvoltage problem at any two ends of the sampling transistor. In a multi-channel data acquisition system, the input signals between the channels are not correlated, and there are signal mutations. For example, when the multi-channel selection circuit switches from one input signal 0V to another input signal VDD, since the common output node of the sampling transistor corresponding to each output channel still remembers the voltage value of the previous input terminal 0V, the voltage difference between the two ends of the sampling transistor corresponding to the current output channel will be greater than the power supply voltage, which may break down or burn out the sampling transistor, thereby affecting the circuit function and chip service life. Summary of the invention

[0004] The embodiments described herein provide a selector that helps avoid overvoltage problems that may occur in sampling transistors.

[0005] According to the present disclosure, there is provided a selector, including: a selector including a control module and a passage module;

[0006] The path module includes a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch unit, a second switch unit, a voltage control circuit and a sampling transistor, wherein the first end of the bootstrap capacitor is connected to the first end of the sampling transistor through the first switch unit, the second end of the bootstrap capacitor is connected to the control end of the sampling transistor through the second switch unit, the first end of the sampling transistor is the input end of the path module, and the second end of the sampling transistor is the output end of the path module;

[0007] The control module is configured to, after controlling the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, first control the voltage control circuit to make the voltage at the control end of the sampling transistor the first preset value to turn on the sampling transistor, and then control the first switch unit and the second switch unit to change from an off state to an on state after a preset time, so as to bootstrap the voltage at the control end of the sampling transistor from the first preset value to the sum of the first preset value and the voltage of the input signal at the input end.

[0008] In some embodiments of the present disclosure,

[0009] The control module is configured to control the first switch unit and the second switch unit to be in an off state during a charging phase, and control the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, and control the voltage control circuit to make the voltage at the control end of the sampling transistor a second preset value, so as to turn off the sampling transistor;

[0010] The control module is also configured to control the voltage control circuit to make the voltage at the control end of the sampling transistor the first preset value during the bootstrap phase to turn on the sampling transistor, and then control the first switch unit and the second switch unit to change from an off state to an on state after a preset time, so as to bootstrap the voltage at the control end of the sampling transistor from the first preset value to the sum of the first preset value and the voltage of the input signal at the input end.

[0011] In some embodiments of the present disclosure, a plurality of the pathway modules are included.

[0012] In some embodiments of the present disclosure, a plurality of the pass modules share the same gate voltage bootstrap circuit and the same bootstrap capacitor.

[0013] In some embodiments of the present disclosure, the voltage-controlled voltage circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor, the first end of the twelfth transistor is electrically connected to the ground node, the first end of the fourteenth transistor is electrically connected to the power supply node, the second end of the twelfth transistor and the second end of the fourteenth transistor are respectively electrically connected to the first end of the thirteenth transistor, the second end of the thirteenth transistor is electrically connected to the control end of the sampling transistor, and the control ends of the twelfth transistor, the thirteenth transistor and the fourteenth transistor receive the control signal output by the control module.

[0014] In some embodiments of the present disclosure, the control module includes a first buffer, a first inverter, a delay device, an AND gate and a first controller, the input ends of the first buffer and the first inverter receive an initial clock signal, the output end of the first buffer outputs a first clock signal to the first controller, the output end of the first inverter is electrically connected to the first input end of the AND gate and the input end of the delay device, respectively, the output end of the delay device is electrically connected to the second input end of the AND gate, the output end of the AND gate outputs a second clock signal to the first controller, and the first controller outputs a control signal according to the first clock signal and the second clock signal.

[0015] In some embodiments of the present disclosure, the control module includes a second inverter, a second buffer, a first NOR gate, a second NOR gate, and a second controller, the input end of the second inverter and the input end of the second buffer receive an initial clock signal, the output end of the second inverter is electrically connected to the first input end of the first NOR gate, the second input end of the first NOR gate is electrically connected to the output end of the second NOR gate, the output end of the first NOR gate outputs a first clock signal to the second controller, the output end of the second buffer is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate is electrically connected to the output end of the first NOR gate, the output end of the second NOR gate outputs a second clock signal to the second controller, and the second controller outputs a control signal according to the first clock signal and the second clock signal.

[0016] In some embodiments of the present disclosure, the gate voltage bootstrap circuit includes a fifteenth transistor and a sixteenth transistor, the control ends of the fifteenth transistor and the sixteenth transistor receive control signals output by a control module, the first end of the fifteenth transistor is electrically connected to a ground node, the first end of the sixteenth transistor is electrically connected to a power supply node, the second end of the fifteenth transistor is electrically connected to a first end of the bootstrap capacitor, and the second end of the sixteenth transistor is electrically connected to a second end of the bootstrap capacitor.

[0017] In some embodiments of the present disclosure, the first switch unit includes a first transistor and a second transistor, the first end of the first transistor and the first end of the second transistor respectively receive the voltage of an input signal of an input end, the second end of the first transistor and the second end of the second transistor are respectively electrically connected to the first end of the bootstrap capacitor, and the control end of the first transistor and the control end of the second transistor receive a control signal output by a control module.

[0018] In some embodiments of the present disclosure, the second switch unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and an eleventh transistor, the first end of the third transistor and the fourth transistor is electrically connected to the voltage of the input signal of the receiving input end, the second end of the third transistor and the fourth transistor is electrically connected to the first node, the first end of the fifth transistor and the sixth transistor is electrically connected to the second end of the bootstrap capacitor, the second end of the fifth transistor and the sixth transistor is electrically connected to the second node, the first end of the seventh transistor and the first end of the eighth transistor are electrically connected to the power supply node respectively, the second end of the seventh transistor is electrically connected to the first node, the second end of the eighth transistor is electrically connected to the second node, the first end of the eleventh transistor is electrically connected to the second node, the second end of the eleventh transistor is electrically connected to the third node, and the control end of the eleventh transistor is electrically connected to the first node. The control ends of the third, fourth, fifth, sixth, seventh and eighth transistors receive the control signal output by the control module.

[0019] The selector provided by the embodiment of the present disclosure includes a control module and a path module, wherein the path module includes a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch unit, a second switch unit, a voltage control circuit, and a sampling transistor. After the control module controls the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, the voltage control circuit is first controlled to make the voltage at the control end of the sampling transistor the first preset value to turn on the sampling transistor, and then the first switch unit and the second switch unit are controlled to change from an off state to an on state after a preset time, so as to bootstrap the voltage at the control end of the sampling transistor from the first preset value to the first preset value. The voltage of the second terminal of the sampling transistor corresponding to the input terminal is raised to a certain extent and close to the voltage of the input signal at the input terminal before the control terminal of the sampling transistor at the input terminal is bootstrapped to the sum of the first preset value and the voltage of the input signal at the input terminal. Even if the voltage of the control terminal of the sampling transistor corresponding to the input terminal acted by the second switch unit corresponding to the input terminal on the input terminal is the sum of the first preset value and the voltage of the input signal at the input terminal, the voltage difference between any two nodes of the sampling transistor at the input terminal is less than or equal to the power supply voltage, thereby avoiding the overvoltage problem of the sampling transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0021] Figure 1is a structural diagram of a selector provided by an embodiment of the present disclosure;

[0022] Figure 2 is a schematic diagram of the structure of another selector provided by an embodiment of the present disclosure;

[0023] Figure 3 is a timing diagram of a clock signal provided by an embodiment of the present disclosure;

[0024] Figure 4 is a structural diagram of another selector provided by an embodiment of the present disclosure;

[0025] Figure 5 is a timing diagram of another clock signal provided by an embodiment of the present disclosure;

[0026] Figure 6 is a state schematic diagram of a second switch unit provided by an embodiment of the present disclosure;

[0027] Figure 7 This is a state diagram of another second switch unit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0030] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0031] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0032] Based on the problems existing in the prior art, the present disclosure provides a selector. Figure 1 is a schematic diagram of the structure of a selector provided by an embodiment of the present disclosure, such as Figure 1 As shown, the selector includes: a control module 100 and a path module 200; the path module 200 includes a gate voltage bootstrap circuit 30, a bootstrap capacitor C, a first switch unit 20, a second switch unit 40, a voltage control circuit 50 and a sampling transistor M, the first end of the bootstrap capacitor C is connected to the first end of the sampling transistor M through the first switch unit 20, the second end of the bootstrap capacitor C is connected to the control end of the sampling transistor M through the second switch unit 40, the first end of the sampling transistor M is the input end of the path module 200, and the second end of the sampling transistor M is the output end of the path module 200; the control module 100 is configured to control the voltage control circuit 50 to make the voltage of the control end of the sampling transistor M the first preset value after controlling the gate voltage bootstrap circuit 30 to charge the bootstrap capacitor C to the first preset value, so as to turn on the sampling transistor M, and then control the first switch unit 20 and the second switch unit 40 to change from the off state to the on state after a preset time, so as to bootstrap the voltage of the control end of the sampling transistor M from the first preset value to the sum of the first preset value and the voltage of the input signal at the input end.

[0033] The selector provided in the embodiment of the present disclosure is used to output the voltage of the input signal of a selected input terminal to the analog-to-digital conversion circuit through a sampling transistor. Therefore, the selector includes multiple input terminals, and one input terminal receives one input signal. The following embodiment will be explained by selecting an input terminal and outputting the voltage of the selected input signal of the input terminal.

[0034] For example, the output ends of multiple path modules can be connected to the same analog-to-digital conversion circuit.

[0035] In a specific implementation, in an exemplary embodiment, when the selector is in the first bootstrap phase, the first input terminal is selected, that is, the sampling transistor corresponding to the first input terminal outputs the voltage of the input signal of the first input terminal. If the voltage of the input signal of the first input terminal is 0, at this time, the common output node of the sampling transistor, that is, the voltage of the second terminal of the sampling transistor is 0 (without considering the conduction voltage drop of the sampling transistor); when the selector is in the second bootstrap phase, the first input terminal is still selected, if the voltage of the input signal of the first input terminal is Vdd, at this time, the voltage of the control terminal of the sampling transistor corresponding to the first input terminal acting on the bootstrap capacitor through the second switch unit is the sum of the first preset value and the voltage of the input signal of the first input terminal, because In the first bootstrap phase, the voltage at the second terminal of the sampling transistor corresponding to the first input terminal is 0. When the voltage of the control terminal of the sampling transistor corresponding to the first input terminal acted by the bootstrap capacitor through the second switch unit is the sum of the first preset value and the voltage of the input signal of the first input terminal, at this time, if the first preset value is Vdd, the voltage of the control terminal of the sampling transistor corresponding to the first input terminal acted by the bootstrap capacitor through the second switch unit is 2Vdd, and the difference between the control terminal and the second terminal voltage of the sampling transistor corresponding to the first input terminal is 2Vdd. The difference between the control terminal and the second terminal voltage of the sampling transistor corresponding to the first input terminal is greater than the power supply voltage, which may break down or burn out the sampling transistor, thereby affecting the circuit function and the service life of the chip.

[0036] Based on the problems existing in the prior art, in the selector provided in the embodiment of the present disclosure, an exemplary selector selects the first input terminal in the first bootstrap phase, that is, the sampling transistor corresponding to the first input terminal outputs the voltage of the input signal of the first input terminal. If the voltage of the input signal of the first input terminal is 0, at this time, the common output node of the sampling transistor, that is, the second terminal voltage of the sampling transistor is 0 (without considering the conduction voltage drop of the sampling transistor); the selector continues to select the first input terminal in the second bootstrap phase. At this time, the control module controls the second switch unit to bootstrap the control terminal of the sampling transistor of the first input terminal to the sum of the first preset value and the voltage of the input signal of the first input terminal, first The voltage control circuit is controlled so that the voltage at the control end of the sampling transistor corresponding to the first input end is a first preset value, so that the sampling transistor corresponding to the first input end is turned on, and then based on the voltage of the input signal corresponding to the first input end, the common output node of the sampling transistor (that is, the second end of the sampling transistor) is gradually increased from the voltage value of the previous bootstrap phase and approaches the voltage of the input signal of the first input end; then after a preset time, the control module controls the first switch unit and the second switch unit corresponding to the first input end from the off state to the on state, so as to realize the bootstrapping of the voltage at the control end of the sampling transistor of the first input end from the first preset value to the sum of the first preset value and the voltage of the input signal of the first input end. Because the voltage of the second terminal of the sampling transistor corresponding to the first input terminal has been raised to a certain extent and is close to the voltage of the input signal of the first input terminal before the control terminal of the sampling transistor at the first input terminal is bootstrapped to the sum of the first preset value and the voltage of the input signal of the first input terminal, even if the voltage applied by the second switch unit corresponding to the first input terminal to the control terminal of the sampling transistor corresponding to the first input terminal is the sum of the first preset value and the voltage of the input signal of the input terminal of the first input terminal, the voltage difference between any two nodes of the sampling transistor at the first input terminal is less than or equal to the power supply voltage, thereby avoiding the overvoltage problem of the sampling transistor.

[0037] The selector provided by the embodiment of the present disclosure includes a control module and a path module, wherein the path module includes a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch unit, a second switch unit, a voltage control circuit, and a sampling transistor. After the control module controls the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, the voltage control circuit is first controlled to make the voltage at the control end of the sampling transistor the first preset value to turn on the sampling transistor, and then the first switch unit and the second switch unit are controlled to change from an off state to an on state after a preset time, so as to bootstrap the voltage at the control end of the sampling transistor from the first preset value to the first preset value. The voltage of the second terminal of the sampling transistor corresponding to the input terminal is raised to a certain extent and close to the voltage of the input signal at the input terminal before the control terminal of the sampling transistor at the input terminal is bootstrapped to the sum of the voltage of the first preset value and the input signal at the input terminal. Even if the voltage of the control terminal of the sampling transistor corresponding to the input terminal by the second switch unit acting on the input terminal is the sum of the voltage of the first preset value and the input signal at the input terminal, the voltage difference between any two nodes of the sampling transistor at the input terminal is less than or equal to the power supply voltage, thereby avoiding the overvoltage problem of the sampling transistor. In addition, since the gate-source voltage of the sampling transistor is a fixed first preset value, the on-resistance of the sampling transistor is a fixed value, and the time constant (τ=R·C1, R is the on-resistance of the sampling transistor, and C1 is the bootstrap capacitance value of the analog-to-digital conversion circuit of the sampling transistor) output by the selector to the analog-to-digital conversion circuit is a fixed value, so that the bandwidth of the selector is independent of the voltage of the input signal, thereby improving the sampling linearity of the analog-to-digital conversion circuit.

[0038] As a specific implementation, the control module is configured to control the first switch unit and the second switch unit to be in an off state during the charging phase, and control the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, and control the voltage control circuit to make the voltage at the control end of the sampling transistor a second preset value to turn off the sampling transistor; the control module is also configured to control the voltage control circuit to make the voltage at the control end of the sampling transistor the first preset value during the bootstrap phase to turn on the sampling transistor, and then control the first switch unit and the second switch unit to change from an off state to an on state after a preset time, and bootstrap the voltage at the control end of the sampling transistor from the first preset value to the sum of the first preset value and the voltage of the input signal at the input end.

[0039] In an exemplary embodiment, when the selector is in the charging phase, the control module controls the first switch unit and the second switch unit corresponding to each input terminal to turn off, controls the gate voltage bootstrap circuit to charge the bootstrap capacitor to the first preset value, and controls the voltage control circuit corresponding to each input terminal to make the voltage of the control terminal of the sampling transistor corresponding to each input terminal a second preset value, so as to turn off the sampling transistor corresponding to each input terminal. When the selector changes from the charging phase to the bootstrap phase, the control module first controls the gate voltage bootstrap circuit to turn off, and controls the voltage control circuit corresponding to the selected input terminal to output the first preset value to the control terminal of the sampling transistor corresponding to the selected input terminal, so as to turn on the sampling transistor corresponding to the selected input terminal, and then based on the voltage of the input signal corresponding to the selected input terminal, the common output node of each sampling transistor (i.e., the second terminal of the sampling transistor) gradually increases and approaches the voltage of the input signal of the selected input terminal, and then after a preset time, the control module controls the first switch unit and the second switch unit corresponding to the selected input terminal to turn on ... The second switch unit is turned on. At this time, the first switch unit corresponding to the selected input terminal outputs the voltage of the input signal corresponding to the selected input terminal to the first terminal of the bootstrap capacitor. According to the characteristic that the voltage across the bootstrap capacitor cannot change suddenly, the second terminal of the bootstrap capacitor is raised to the sum of the first preset value and the voltage of the input signal of the selected input terminal, and the second terminal voltage of the bootstrap capacitor is output to the control terminal of the selected sampling transistor through the second switch unit, that is, the voltage of the control terminal of the sampling transistor corresponding to the selected input terminal is raised from the first preset value to the sum of the first preset value and the voltage of the input signal of the selected input terminal. Because the voltage of the second terminal of the sampling transistor corresponding to the selected input terminal has been raised to a certain extent and is close to the voltage of the input signal of the selected input terminal before the control terminal of the sampling transistor of the selected input terminal is bootstrapped to the sum of the first preset value and the voltage of the input signal of the selected input terminal, after the preset time, even if the voltage of the control terminal of the sampling transistor corresponding to the selected input terminal applied by the second switch unit is the sum of the first preset value and the voltage of the input signal of the input terminal of the selected input terminal, the voltage difference between any two nodes of the sampling transistor of the selected input terminal can be maintained within a range less than or equal to the power supply voltage, thereby avoiding the overvoltage problem of the sampling transistor.

[0040] In addition, in the above embodiment, when the selector changes from the charging phase to the bootstrap phase, the control module first controls the gate voltage bootstrap circuit to turn off, and controls the voltage control circuit corresponding to the non-selected input end to output a second preset value to the control end of the sampling transistor corresponding to the non-selected input end, so that the sampling transistor corresponding to the non-selected input end is turned off, and then after a preset time, the control module controls the first switch unit and the second switch unit corresponding to the non-selected input end to turn off. At this time, the first switch unit and the second switch unit corresponding to the non-selected input end are turned off.

[0041] It should be noted that, in the above embodiment, the first preset value is the power supply voltage Vdd, and the second preset value is 0.

[0042] As a specific implementation, the selector includes a plurality of pathway modules.

[0043] The number of the path modules included in the selector is the same as the number of the input terminals of the selector. One path module corresponds to one input terminal. The control module in the selector selects the sampling transistor in the path module corresponding to the input terminal to output the voltage input to the input terminal.

[0044] Specifically, Figure 1 The exemplary representation selector includes four path modules, one path module corresponding to one input terminal.

[0045] As a preferred embodiment, continue to refer to Figure 1 , multiple pass modules share the same gate voltage bootstrap circuit and the same bootstrap capacitor.

[0046] By arranging a plurality of path modules to share a gate voltage bootstrap circuit and a same bootstrap capacitor, the overall circuit area of ​​the selector is reduced.

[0047] As a specific implementation method, Figure 2 As shown, the voltage control circuit 50 includes a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14, the first end of the twelfth transistor M12 is electrically connected to the ground node, the first end of the fourteenth transistor M14 is electrically connected to the power supply node, the second end of the twelfth transistor M12 and the second end of the fourteenth transistor M14 are respectively electrically connected to the first end of the thirteenth transistor M13, the second end of the thirteenth transistor M13 is electrically connected to the control end of the sampling transistor, and the control ends of the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 receive the control signal output by the control module.

[0048] In a specific implementation, when the selector is in a charging phase, the voltage control circuit corresponding to each input terminal is turned on in a first manner under the action of a control signal output by the control module. Specifically, the twelfth transistor M12 and the thirteenth transistor M13 are turned on under the action of a control signal output by the control module, and the fourteenth transistor M14 is turned off under the action of a control signal output by the control module. At this time, the control terminal voltage of each sampling transistor acted on by the voltage control circuit is a ground node voltage, and each sampling transistor is not selected. When the selector is in a bootstrap phase, first, the control module turns on the voltage control circuit corresponding to the selected input terminal in a second manner, and turns on the voltage control circuit corresponding to the non-selected input terminal in a first manner. Specifically, in the voltage control circuit corresponding to the selected input terminal, the thirteenth transistor M13 and the fourteenth transistor M14 is turned on under the action of the control signal, and the twelfth transistor M12 is turned off under the action of the control signal. In the voltage control circuit corresponding to the input end that is not selected, the twelfth transistor M12 and the thirteenth transistor M13 are turned on under the action of the control signal output by the control module, and the fourteenth transistor M14 is turned off under the action of the control signal output by the control module. At this time, the control terminal voltage of the sampling transistor corresponding to the selected input end by the voltage control circuit corresponding to the selected input end is the power supply voltage, and the control terminal voltage of the sampling transistor corresponding to the unselected input end by the voltage control circuit corresponding to the unselected input end is the ground node voltage. The sampling transistor corresponding to the selected input end is selected, and the second terminal voltage of the sampling transistor corresponding to the selected input end is raised to a voltage close to the input signal of the selected input end.

[0049] In addition, since the second terminals of the sampling transistors corresponding to the input terminals are connected, the voltages of the second terminals of the sampling transistors corresponding to the input terminals are raised to a voltage close to the voltage of the input signal of the selected input terminal. Therefore, even if the sampling transistors corresponding to different input terminals are selected in two different bootstrap phases, it can be ensured that in the bootstrap phase, the voltages of any two nodes of the sampling transistors are less than or equal to the power supply voltage, thereby avoiding the overvoltage problem of the sampling transistors.

[0050] As a specific implementation, referring to Figure 2, the control module includes a first buffer K1, a first inverter F1, a delay device D, an AND gate AND and a first controller C1. The input ends of the first buffer K1 and the first inverter F1 receive an initial clock signal, the output end of the first buffer K1 outputs a first clock signal CLK1 to the first controller C1, the output end of the first inverter F1 is electrically connected to the first input end of the AND gate AND and the input end of the delay device D, respectively, the output end of the delay device D is electrically connected to the second input end of the AND gate AND, and the output end of the AND gate AND outputs a second clock signal CLK2 to the first controller C1.

[0051] Combination Figure 2 and Figure 3 First, the first buffer K1, the first inverter F1, the delay device D and the AND gate AND generate the first clock signal CLK1 and the second clock signal CLK2 according to the initial clock signal CLK, and then the controller generates the control signal according to the first clock signal and the second clock signal.

[0052] As another specific implementation, Figure 4 As shown, the control module includes a second inverter F2, a second buffer K2, a first NOR gate NOR1, a second NOR gate NOR2 and a second controller C2, the input end of the second inverter F2 and the input end of the second buffer K2 receive the initial clock signal CLK, the output end of the second inverter F2 is electrically connected to the first input end of the first NOR gate NOR1, the second input end of the first NOR gate NOR1 is electrically connected to the output end of the second NOR gate NOR2, the output end of the first NOR gate NOR1 outputs the first clock signal CLK1 to the second controller, the output end of the second buffer K2 is electrically connected to the first input end of the second NOR gate NOR2, the second input end of the second NOR gate NOR2 is electrically connected to the output end of the first NOR gate NOR1, and the output end of the second NOR gate NOR2 outputs the second clock signal to the second controller.

[0053] Combination Figure 4 and Figure 5 First, the second inverter F2, the second buffer K2, the first NOR gate NOR1, and the second NOR gate NOR2 generate the first clock signal CLK1 and the second clock signal CLK2 according to the initial clock signal CLK, and then the controller generates a control signal according to the first clock signal and the second clock signal.

[0054] Specific, combined Figure 3 and Figure 5 , the time corresponding to the rising edge of the first clock signal is the time corresponding to the change of the selector from the bootstrap phase to the charging phase, the time corresponding to the falling edge of the first clock signal is the time corresponding to the change of the selector from the charging phase to the bootstrap phase, and the time difference between the time corresponding to the falling edge of the first clock signal and the time corresponding to the rising edge of the second clock signal ( Figure 5 T1 or Figure 7t2) in the figure is the preset time, that is, at the rising edge of the first clock signal, the controller controls the first switch unit and the second switch unit to be in the off state, controls the gate voltage bootstrap circuit to charge the second end of the bootstrap capacitor to the first preset value, and controls the voltage control circuit to make the voltage at the control end of the sampling transistor the second preset value, so as to turn off the sampling transistor; at the falling edge of the first clock signal, the controller controls the voltage control circuit to make the voltage at the control end of the sampling transistor the first preset value, so as to turn on the sampling transistor; at the rising edge of the second clock signal, the controller controls the first switch unit and the second switch unit to change from the off state to the on state, and bootstraps the voltage at the control end of the sampling transistor from the first preset value to the sum of the voltage of the first preset value and the input signal at the input end.

[0055] It should be noted that, in the above embodiment, the time corresponding to the high level of the first clock signal is within the time corresponding to the low level of the second clock signal.

[0056] As a specific implementation method, continue to refer to Figure 2 or Figure 4 The gate voltage bootstrap circuit includes a fifteenth transistor M15 and a sixteenth transistor M16, the control ends of the fifteenth transistor M15 and the sixteenth transistor M16 receive control signals output by the control module, the first end of the fifteenth transistor M15 is electrically connected to the ground node, the first end of the sixteenth transistor M16 is electrically connected to the power supply node, the second end of the fifteenth transistor M13 is electrically connected to the first end of the bootstrap capacitor C, and the second end of the sixteenth transistor M15 is electrically connected to the second end of the bootstrap capacitor C.

[0057] Specifically, when the selector is in the charging phase, the control module 10 outputs a control signal to control the fifteenth transistor M15 and the sixteenth transistor M16 to be turned on, and the voltage at the second end of the bootstrap capacitor is charged to the first preset value, that is, the power supply voltage; when the selector is in the bootstrap phase, the control module 10 outputs a control signal to control the fifteenth transistor M15 and the sixteenth transistor M16 to be turned off. When the control module controls the first switch unit and the second switch unit corresponding to the selected input end to be turned on, the first end of the bootstrap capacitor receives the voltage of the input signal corresponding to the selected input end. Combined with the characteristic that the voltage across the bootstrap capacitor cannot change suddenly, the voltage at the second end of the bootstrap capacitor will be raised to the sum of the first preset value and the voltage of the input signal of the selected input end, that is, the sum of the power supply voltage and the voltage of the input signal of the selected input end. At this time, the second switch unit corresponding to the selected input end outputs the sum of the first preset value and the voltage of the input signal of the selected input end to the control end of the sampling transistor corresponding to the selected input end, so that the gate-source voltage of the sampling transistor corresponding to the selected input end is a fixed value, thereby ensuring the sampling linearity of the selector.

[0058] As a specific implementation method, continue to refer to Figure 2 or Figure 4 The first switch unit includes a first transistor M1 and a second transistor M2, the first ends of the first transistor M1 and the second transistor M2 are connected to the voltage of an input signal received at an input end, the second end of the first transistor M1 and the second end of the second transistor M2 are electrically connected to the first end of the bootstrap capacitor C, and the control ends of the first transistor M1 and the second transistor M2 receive the control signal output by the control module.

[0059] The first switch unit includes a first transistor M1 and a second transistor M2, which are connected in parallel. When the first transistor M1 is an NMOS transistor, the second transistor M2 is a PMOS transistor. When the first transistor M2 is a PMOS transistor, the second transistor M2 is an NMOS transistor.

[0060] The first switch unit is configured to include a first transistor M1 and a second transistor M2 connected in parallel. The first transistor M1 and the second transistor M2 are two different types of transistors. Based on the characteristics of the on-resistance of the PMOS tube and the NMOS tube, the on-resistance of the first switch unit is reduced by connecting the PMOS tube and the NMOS tube in parallel, thereby improving the signal-to-noise ratio of the voltage of the input signal at the input end.

[0061] When the selector is in the bootstrap phase, the control module controls the first transistor and the second transistor in the first switch unit corresponding to the selected input end to turn on after a preset time, and transmits the voltage of the input signal of the selected input end to the first end of the bootstrap capacitor through the first transistor and the second transistor.

[0062] As a specific implementation method, Figure 6 and Figure 7As shown, the second switch unit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and an eleventh transistor M11, a first end of the third transistor M3 and the fourth transistor M4 is electrically connected to the voltage of the input signal of the receiving input end, a second end of the third transistor M3 and the fourth transistor M4 is electrically connected to the first node A1, a first end of the fifth transistor M5 and the sixth transistor M6 is electrically connected to the second end of the bootstrap capacitor C, a second end of the fifth transistor M5 and the sixth transistor M6 is electrically connected to the second node A2, and a seventh transistor M7 is electrically connected to the eleventh transistor M8. The first end of the first transistor M11 and the first end of the eighth transistor M8 are electrically connected to the power supply node respectively, the second end of the seventh transistor M7 is electrically connected to the first node A1, the second end of the eighth transistor M8 is electrically connected to the second node A2, the first end of the eleventh transistor M11 is electrically connected to the second node A2, the second end of the eleventh transistor M11 is electrically connected to the third node A3, the control end of the eleventh transistor M11 is electrically connected to the first node A1, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 receive the control signal output by the control module.

[0063] In a specific implementation, the third transistor M3 , the fifth transistor M5 , the seventh transistor M7 and the eleventh transistor M11 are PMOS transistors, and the fourth transistor M4 , the sixth transistor M6 , the eighth transistor M8 , the ninth transistor M9 and the tenth transistor M10 are NMOS transistors.

[0064] In an exemplary embodiment, when the selector is in the charging phase, see Figure 6 , the voltage of the control signal output by the control module to the control end of the third transistor M3 and the sixth transistor M6 in the second switch unit corresponding to each input terminal is Vdd, the voltage of the control signal output by the control module to the fourth transistor M4 and the seventh transistor M7 is 0, and the voltage of the control signal output by the control module to the control end of the fifth transistor M5 and the eighth transistor M8 is 2Vdd. At this time, the gate-source voltage of the third transistor M3 and the fifth transistor M5 in the second switch unit corresponding to each input terminal is greater than the transistor threshold voltage, the gate-source voltage of the fourth transistor M4 and the sixth transistor M6 is less than the transistor threshold voltage, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, the gate-source power supply of the seventh transistor M7 is less than the transistor threshold voltage, the gate-source voltage of the eighth transistor M8 is greater than the transistor threshold voltage, the seventh transistor M7 and the eighth transistor M8 are turned on, the control end of the eleventh transistor M11 has the same voltage as the first end, and the eleventh transistor M11 is turned off. At this time, the voltage output by the second switch unit corresponding to each input terminal to the control end of the connected sampling transistor is 0. When the selector is in the bootstrap phase and the preset time has passed, refer to Figure 7, the voltage of the control signal of the third transistor M3 in the second switch unit corresponding to the selected input terminal output by the control module is 0, the voltage of the control signal of the control module output to the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 is Vdd, and the voltage of the control signal of the control module output to the control terminal of the sixth transistor M6 is 2Vdd. At this time, the gate-source voltage of the third transistor M3 and the fifth transistor M5 is less than the transistor threshold voltage, the gate-source voltage of the fourth transistor M4 and the sixth transistor M6 is greater than the transistor threshold voltage, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned on, the gate-source voltage of the seventh transistor M7 and the eighth transistor M8 is 0, the seventh transistor M7 and the eighth transistor M8 are turned off, the control terminal of the eleventh transistor M11 is Vdd, the first terminal voltage of the eleventh transistor M11 is Vdd+IN1, and the eleventh transistor M11 is turned on. At this time, the voltage of the control terminal of the connected sampling transistor output by the second switch unit corresponding to the selected input terminal is IN1+Vdd.

[0065] A specific embodiment is used to illustrate. Figure 2 , Figure 3 and Figure 6, assuming that the power supply voltage Vdd is 5V, input channel 3 is selected in the previous sampling cycle, and the input signal VIN3 input by input channel 3 is 0V. At this time, the voltage of the second end of the sampling transistor corresponding to the different input channels is the input signal input by input channel 3, that is, the voltage of the common output node VOUT of each sampling transistor is 0V. In the next sampling cycle, if input channel 3 is still selected, the input signal VIN3 input by input channel 3 is 5V. In this sampling cycle, when the selector is in the charging phase, the first clock signal CLK1 changes from a low level to a high level, and the control module charges the bootstrap capacitor to the power supply voltage 5V according to the gate voltage bootstrap circuit controlled by the first clock signal CLK1. At the same time, the control module turns on the twelfth transistor M12 and the thirteenth transistor M13 controlled by the first clock signal CLK1, and the fourteenth transistor M14 is turned off. The gate voltage of the sampling transistor M is 0V, and the sampling transistor is turned off. When the selector changes from the charging phase to the bootstrap phase, the first clock signal CLK1 changes from a high level to a low level. At this time, the control module controls the fourteenth transistor M14 to be turned on according to the first clock signal. After the fourteenth transistor M14 is turned on, the power supply voltage Vdd is transmitted to the first end of the thirteenth transistor. The source and drain of the thirteenth transistor M13 are interchanged, and the gate voltage of the sampling transistor is 5V. The source and drain of the sampling transistor are interchanged and turned on, and the input signal VIN3 is transmitted to the common output node VOUT. The common output node VOUT gradually increases from the voltage value of 0V in the previous sampling cycle. After waiting for a period of time t1, the second clock signal CLK2 changes from a low level to a high level. The control module controls the first switch unit and the second switch unit to be turned on according to the second clock signal CLK2. The gate voltage of the sampling transistor is bootstrapped to 10V through the first switch unit, the bootstrap capacitor and the second switch unit. The gate-source voltage difference of the sampling transistor is raised to the power supply voltage 5V, thereby reducing the on-resistance of the sampling tube and improving the sampling linearity. During this process, the voltage difference between any two ends of the sampling transistor of the selected input channel is less than the power supply voltage, and there is no overvoltage. The gate voltage of the sampling transistor of the unselected input channel is always maintained at 0V, and there is no overvoltage problem in the sampling transistors of each input channel.

[0066] It should be noted that in the above embodiments, corresponding to the NMOS type transistor, the end with a lower potential between the first and second ends of the transistor is the source end, and corresponding to the PMOS type transistor, the end with a higher potential between the first and second ends of the transistor is the source end.

[0067] In the embodiment of the present disclosure, when the first preset value generated by the gate voltage bootstrap circuit or the sum of the voltage of the first preset value and the input signal at the input end acts on the second switch unit, the voltages at both ends of any transistor included in the second switch unit are within the range of the power supply voltage VDD, thereby avoiding the risk of burning out the chip and fully ensuring the reliability and service life of the chip.

[0068] In the disclosed embodiment, each sampling transistor is an NMOS transistor.

[0069] It should be noted that, in the embodiments of the present disclosure, each sampling transistor is exemplified as an NMOS transistor for specific illustration. In other possible implementations, when each sampling transistor is a PMOS transistor, the transistor types of other transistors except the third transistor, the fourth transistor, the fifth transistor and the sixth transistor in the second switch unit need to be interchanged, and the control signal acting on the second switch unit is modified accordingly. The embodiments of the present disclosure do not specifically limit this.

[0070] In the disclosed embodiment, the first switch unit, the second switch unit and the voltage control circuit in the selector all adopt conventional, non-high-voltage CMOS process, the circuit layout area is greatly reduced, and the parasitic effects of transistor devices are less affected. On the other hand, the technical solution of the present invention can control the establishment process of the sampling tube gate voltage by adopting two-phase timing without introducing additional parasitic effects at the output node of the sampling circuit, which is beneficial to ensure the sampling linearity of the ADC input signal and achieve high-precision performance of the ADC.

[0071] The embodiment of the present disclosure further provides an electronic chip, which includes the selector according to the embodiment of the present disclosure.

[0072] The embodiments of the present disclosure also provide an electronic device. The electronic device includes an electronic chip according to the embodiments of the present disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer, a smart phone, etc.

[0073] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0074] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0075] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0076] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A selector, characterized in that: It includes a control module and a passage module; The path module includes a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch unit, a second switch unit, a voltage control circuit and a sampling transistor, wherein the first end of the bootstrap capacitor is connected to the first end of the sampling transistor through the first switch unit, the second end of the bootstrap capacitor is connected to the control end of the sampling transistor through the second switch unit, the first end of the sampling transistor is the input end of the path module, and the second end of the sampling transistor is the output end of the path module; The control module is configured to, after controlling the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, first control the voltage control circuit to make the voltage at the control end of the sampling transistor the first preset value to turn on the sampling transistor, and then control the first switch unit and the second switch unit to change from an off state to an on state after a preset time, so as to bootstrap the voltage at the control end of the sampling transistor from the first preset value to the sum of the first preset value and the voltage of the input signal at the input end.

2. The selector according to claim 1, characterized in that The control module is configured to control the first switch unit and the second switch unit to be in an off state during a charging phase, and control the gate voltage bootstrap circuit to charge the bootstrap capacitor to a first preset value, and control the voltage control circuit to make the voltage at the control end of the sampling transistor a second preset value, so as to turn off the sampling transistor; The control module is also configured to control the voltage control circuit to make the voltage at the control end of the sampling transistor the first preset value during the bootstrap phase to turn on the sampling transistor, and then control the first switch unit and the second switch unit to change from an off state to an on state after a preset time, so as to bootstrap the voltage at the control end of the sampling transistor from the first preset value to the sum of the first preset value and the voltage of the input signal at the input end.

3. The selector according to claim 1, characterized in that: It comprises a plurality of said pathway modules.

4. The selector according to claim 3, characterized in that: A plurality of the pass modules share the same gate voltage bootstrap circuit and the same bootstrap capacitor.

5. The selector according to claim 1, characterized in that: The voltage-controlled voltage circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor, wherein a first end of the twelfth transistor is electrically connected to a ground node, a first end of the fourteenth transistor is electrically connected to a power supply node, a second end of the twelfth transistor and a second end of the fourteenth transistor are electrically connected to a first end of the thirteenth transistor respectively, a second end of the thirteenth transistor is electrically connected to a control end of the sampling transistor, and the control ends of the twelfth transistor, the thirteenth transistor and the fourteenth transistor receive control signals output by a control module.

6. The selector according to claim 1, characterized in that: The control module includes a first buffer, a first inverter, a delay device, an AND gate and a first controller. The input ends of the first buffer and the first inverter receive an initial clock signal. The output end of the first buffer outputs a first clock signal to the first controller. The output end of the first inverter is electrically connected to the first input end of the AND gate and the input end of the delay device, respectively. The output end of the delay device is electrically connected to the second input end of the AND gate. The output end of the AND gate outputs a second clock signal to the first controller. The first controller outputs a control signal according to the first clock signal and the second clock signal.

7. The selector according to claim 1, characterized in that: The control module includes a second inverter, a second buffer, a first NOR gate, a second NOR gate, and a second controller, the input end of the second inverter and the input end of the second buffer receive an initial clock signal, the output end of the second inverter is electrically connected to the first input end of the first NOR gate, the second input end of the first NOR gate is electrically connected to the output end of the second NOR gate, the output end of the first NOR gate outputs a first clock signal to the second controller, the output end of the second buffer is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate is electrically connected to the output end of the first NOR gate, the output end of the second NOR gate outputs a second clock signal to the second controller, and the second controller outputs a control signal according to the first clock signal and the second clock signal.

8. The selector according to claim 1, characterized in that: The gate voltage bootstrap circuit includes a fifteenth transistor and a sixteenth transistor, wherein the control ends of the fifteenth transistor and the sixteenth transistor receive control signals output by a control module, the first end of the fifteenth transistor is electrically connected to a ground node, the first end of the sixteenth transistor is electrically connected to a power supply node, the second end of the fifteenth transistor is electrically connected to a first end of the bootstrap capacitor, and the second end of the sixteenth transistor is electrically connected to a second end of the bootstrap capacitor.

9. The selector according to claim 1, characterized in that: The first switch unit includes a first transistor and a second transistor, the first end of the first transistor and the first end of the second transistor respectively receive the voltage of an input signal of an input end, the second end of the first transistor and the second end of the second transistor are respectively electrically connected to the first end of the bootstrap capacitor, and the control end of the first transistor and the control end of the second transistor receive a control signal output by a control module.

10. The selector according to claim 1, characterized in that The second switch unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and an eleventh transistor, the first end of the third transistor and the fourth transistor is electrically connected to the voltage of the input signal of the receiving input end, the second end of the third transistor and the fourth transistor is electrically connected to the first node, the first end of the fifth transistor and the sixth transistor is electrically connected to the second end of the bootstrap capacitor, the second end of the fifth transistor and the sixth transistor is electrically connected to the second node, the first end of the seventh transistor and the first end of the eighth transistor are electrically connected to the power supply node respectively, the second end of the seventh transistor is electrically connected to the first node, the second end of the eighth transistor is electrically connected to the second node, the first end of the eleventh transistor is electrically connected to the second node, the second end of the eleventh transistor is electrically connected to the third node, and the control end of the eleventh transistor is electrically connected to the first node. The control ends of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor receive the control signal output by the control module.

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