A power-on reset circuit

Abstract

A power-on reset circuit includes a reference current generating circuit, the reference current generating circuit includes a sixth P tube and a seventh P tube whose sources are both connected to a power supply, the gates of the sixth and seventh P tubes are connected and connected to the drain of the sixth P tube, the drain of the sixth P tube is connected to one end of a resistor, and the other end of the resistor is connected to the drain of a fourth N tube; the power-on reset circuit also includes a voltage comparison circuit, the voltage comparison circuit includes an eighth P tube and a ninth P tube whose sources are both connected to a power supply, the gate of the eighth P tube is connected to the gate of the sixth P tube in the reference current generating circuit, and the gate of the ninth P tube is connected to the gate and drain of the seventh N tube. The present invention can significantly reduce the temperature coefficient of the flip level, reduce the influence of temperature on the flip level, and improve the stability of the reset signal output by the power-on reset circuit by adjusting the mirror copy ratio of the reference current.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a power-on reset circuit. Background Art

[0002] The power-on reset circuit (POWER ON RESET) is a circuit module that starts working when the circuit power goes from zero to power on and outputs a jump signal to start the circuit module, providing a stable power supply voltage for the entire circuit. Before the power is turned on, the entire circuit may be in an undefined state or an unstable state. In order to make the system state controllable, the power-on reset circuit is designed to ensure that it can start running from a certain voltage starting point.

[0003] The power-on reset circuit generally uses a resistor as the core component of the reference current generation circuit, such as Figure 2 The figure shows a typical circuit of an existing power-on reset circuit. The reference current module generates a reference current, which is copied to the voltage detection circuit through a current mirror. The current of the reference current generating circuit is compared with the current of the MOS tube in the voltage detection circuit, thereby generating a threshold voltage of the power-on reset circuit as a comparison flip voltage when the power-on reset signal output flips the level. Under the influence of factors such as process and temperature, the comparison flip voltage fluctuates greatly, resulting in instability of the power-on reset signal output point. Summary of the invention

[0004] In view of the above defects in the prior art, the present invention discloses a power-on reset circuit.

[0005] The power-on reset circuit of the present invention comprises a reference current generating circuit, wherein the reference current generating circuit comprises a sixth P tube and a seventh P tube, both of which have source electrodes connected to a power supply, the gate electrodes of the sixth and seventh P tubes are connected and connected to the drain electrode of the sixth P tube, the drain electrode of the sixth P tube is connected to one end of a resistor, the other end of the resistor is connected to the drain electrode of a fourth N tube, the gate electrodes of the fourth N tube and the fifth N tube are connected and connected to the drain electrode of the fifth N tube, the source electrode of the fifth N tube is grounded, and the drain electrode is also connected to the drain electrode of the seventh P tube, the source electrode of the fourth N tube is connected to the drain electrode of the sixth N tube, and the source electrode of the sixth N tube is grounded;

[0006] The width-to-length ratios of the sixth P tube and the seventh P tube are equal, and the width-to-length ratios of the fourth N tube, the fifth N tube and the sixth N tube are m:1:n;

[0007] The gate of the sixth P transistor in the reference current generating circuit is also connected to a start-up circuit for starting the sixth P transistor when powered on;

[0008] The power-on reset circuit also includes a voltage comparison circuit, which includes an eighth P tube and a ninth P tube, both of which have sources connected to a power supply, a gate of the eighth P tube connected to the gate of the sixth P tube in the reference current generating circuit, a gate of the ninth P tube connected to the gate and drain of the seventh N tube, a source of the seventh N tube connected to ground, a drain of the ninth P tube connected to the gate of the eighth N tube, a source of the eighth N tube connected to ground, a drain connected to the drain of the eighth P tube, and a drain of the eighth P tube serving as an output end of the voltage comparison circuit; the eighth P tube and the sixth P tube have the same width-to-length ratio, and the ratio of the width-to-length ratio of the fifth N tube to the eighth N tube is 1:x.

[0009] Preferably, the startup circuit includes a first P tube and a second P tube, both of which have sources connected to a power supply, a gate of the first P tube connected to a drain and connected to a gate of a first N tube, a source of the first N tube grounded, a drain connected to the gate of the second P tube, a drain of the second P tube connected to the drain of the second N tube, a source of the second N tube grounded, a gate connected to the gate of a fourth N tube in a reference current generating circuit, a drain of the second P tube also connected to the gate of a third N tube, a source of the third N tube grounded, and a drain connected to the gate of a sixth P tube in the reference current generating circuit as the output end of the startup circuit.

[0010] Preferably, the second P tube is an inverse ratio tube whose length is greater than its width.

[0011] Preferably, the output end of the voltage comparison circuit, i.e., the drain of the eighth P tube, is also connected to the input end of a Schmitt trigger, the Schmitt trigger is connected by gates connected together, and is connected to the eleventh P tube, the twelfth P tube, the thirteenth N tube and the fourteenth N tube which are sequentially connected from the power supply to the ground source and drain, the drain of the eleventh P tube is also connected to the source of the thirteenth P tube, the source of the thirteenth N tube is also connected to the source of the fifteenth N tube, and the gates of the thirteenth P tube and the fifteenth N tube are both connected to the drain of the twelfth P tube;

[0012] The drain of the thirteenth P tube is also connected to the drain of the sixteenth N tube, the source of the sixteenth N tube is grounded, and the gate is connected to the gate of the eighth N tube; the drain of the fifteenth N tube is also connected to the drain of the fourteenth P tube, the source of the fourteenth P tube is connected to the power supply, and the gate is connected to the drain of the twelfth N tube, the source of the twelfth N tube is grounded, the gate is connected to the drain and gate of the tenth P tube, and the source of the tenth P tube is connected to the power supply; the drain of the twelfth P tube serves as the output end of the Schmitt trigger.

[0013] Preferably, the output end of the Schmitt trigger is connected to a buffer to output a power-on reset signal.

[0014] The power-on reset circuit of the present invention can significantly reduce the temperature coefficient of the flip level by adjusting the mirror copy ratio of the reference current, reduce the influence of temperature on the flip level, and improve the stability of the reset signal output by the power-on reset circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 1 is a schematic diagram showing a specific implementation of the power-on reset circuit of the present invention;

[0016] Figure 2 A schematic diagram of a specific implementation of a power-on reset circuit in the prior art;

[0017] Figure 3 The figure shows a schematic diagram of a simulation curve of the power-on reset circuit of the present invention under different process conditions;

[0018] Figure 4 The figure shows a schematic diagram of a simulation curve of the power-on reset circuit of the present invention under different temperature conditions;

[0019] The reference numerals in the figure are: N1-first N tube, N2-second N tube, N3-third N tube, N4-fourth N tube, N5-fifth N tube, N6-sixth N tube, N7-seventh N tube, N8-eighth N tube, N9-ninth N tube, N10-tenth N tube, N11-eleventh N tube, N12-twelfth N tube, N13-thirteenth N tube, N14-fourteenth N tube, N15-fifteenth N tube, N16-sixteenth N tube , P1-first P tube, P2-second P tube, P3-third P tube, P4-fourth P tube, P5-fifth P tube, P6-sixth P tube, P7-seventh P tube, P8-eighth P tube, P9-ninth P tube, P10-tenth P tube, P11-eleventh P tube, P12-twelfth P tube, P13-thirteenth P tube, P14-fourteenth P tube, BUF-buffer, VDD-power supply voltage, POR-power-on reset signal. DETAILED DESCRIPTION

[0020] In order to more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be given below in conjunction with specific embodiments and example drawings.

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] like Figure 1As shown, the power-on reset circuit of the present invention includes a reference current generating circuit, the reference current generating circuit includes a sixth P-tube P6 and a seventh P-tube P7, both of which have source electrodes connected to a power supply, the gate electrodes of the sixth P-tube P6 and the seventh P-tube P7 are connected and connected to the drain electrode of the sixth P-tube P6, the drain electrode of the sixth P-tube is connected to one end of a resistor, the other end of the resistor is connected to the drain electrode of a fourth N-tube, the gate electrodes of the fourth N-tube N4 and the fifth N-tube N5 are connected and connected to the drain electrode of the fifth N-tube N5, the source electrode of the fifth N-tube is grounded, and the drain electrode is also connected to the drain electrode of the seventh P-tube, the source electrode of the fourth N-tube N4 is connected to the drain electrode of the sixth N-tube N6, and the source electrode of the sixth N-tube is grounded;

[0023] The sixth P tube P6 and the seventh P tube P7 have the same width-to-length ratio, and the fourth N tube N4, the fifth N tube N5 and the sixth N tube N6 have a width-to-length ratio of m:1:n;

[0024] The gate of the sixth P-tube P6 in the reference current generating circuit is also connected to a start-up circuit for starting the sixth P-tube when powered on;

[0025] The power-on reset circuit also includes a voltage comparison circuit, which includes an eighth P-tube P8 and a ninth P-tube P9, both of which have sources connected to a power supply, a gate of the eighth P-tube connected to the gate of the sixth P-tube P6 in the reference current generating circuit, a gate of the ninth P-tube P9 connected to the gate and drain of the seventh N-tube N7, a source of the seventh N-tube N7 connected to ground, a drain of the ninth P-tube P9 connected to the gate of the eighth N-tube N8, a source of the eighth N-tube grounded, a drain connected to the drain of the eighth P-tube P8, and a drain of the eighth P-tube P8 serving as an output end of the voltage comparison circuit; the eighth P-tube P8 and the sixth P-tube P6 have the same width-to-length ratio, and the ratio of the width-to-length ratio of the fifth N-tube N5 to the eighth N-tube N8 is 1:x.

[0026] When not powered on, the voltage at the power supply terminal is zero, and the power-on reset circuit does not work, but a small amount of undischarged charge may be temporarily stored on the gate of some devices; when powered on, the voltage at the power supply terminal continues to rise, and the startup circuit outputs a bias voltage, turning on the sixth P tube, so that the reference current generating circuit starts working.

[0027] Since the sixth P-tube P6 and the seventh P-tube P7 are of current mirror structures and have the same width-to-length ratio, the currents of the sixth P-tube P6 and the seventh P-tube P7 are equal.

[0028] Assume that the turn-on voltage of each N tube is and transduction coefficient β are equal, and the PMOS ,and are also equal, and the reference current generating circuit can be obtained:

[0029] ;

[0030] Where I0 represents the current flowing through the resistor R, and the MOS tube transconductance coefficient β=μ*C OX , μ is the carrier mobility, C OX is the gate oxide capacitance per unit area of ​​the MOS tube, V THNM4 and V THNM5 Respectively represent the threshold voltages of the fourth N-tube and the fifth N-tube, and Respectively represent the width-to-length ratios of the fourth N-tube and the fifth N-tube; the on-resistance of the sixth N-tube

[0031] , V GSNM6 and V THNM6 Respectively represent the gate-source voltage and threshold voltage of the sixth N-tube, represents the width-to-length ratio of the sixth N tube;

[0032] and , , then the above formula can be written as:

[0033] ,

[0034] Simplifying, we can get the current flowing through the resistor R

[0035] That is, the reference current is as follows: .

[0036] At the beginning of power-on, the drain voltage of the eighth P-tube P8 rises with the rise of the power supply voltage. When the power supply voltage is low in the early stage, the eighth P-tube P8 is in the linear region, and the sixth P-tube is in the saturation region due to the diode connection method of gate-source connection, and the width-to-length ratio of the two is equal, so the current of the eighth P-tube is smaller than the current of the sixth P-tube, and the eighth N-tube N8 is in the saturation region. At this time, I NM8 = I PM8 ﹤I PM6 = I NM6 ;I NM8 ,I PM8 ,I PM6 ,I NM6 They are respectively the leakage currents of the eighth N-transistor N8, the eighth P-transistor P8, the sixth P-transistor P6 and the sixth N-transistor N6.

[0037] As the power supply voltage further increases, the current of the eighth N-tube N8 gradually increases, and the drain voltage of the eighth N-tube is gradually pulled down. The flip point occurs when the currents of the sixth N-tube N6 and the eighth N-tube N8 are equal. At this time, the drain voltage of the eighth N-tube drops to make the eighth P-tube P8 in the saturation region, and the eighth N-tube N8 in the linear region. The drain-source voltage of the eighth N-tube N8 Slightly less than ,

[0038] have , the leakage current of the eighth N-tube N8 is:

[0039]

[0040] Where V GSNM8 、V THNM8 and V DSNM8 They represent the gate-source voltage, threshold voltage and drain-source voltage of the eighth N-tube N8 respectively, represents the width-to-length ratio of the eighth N-type transistor N8; according to formula 1, the current flowing through the resistor R is the current flowing through the sixth N-type transistor. Combining formula 1 and formula 2, we have:

[0041] Since the ninth P tube is fully turned on, it is approximately considered that V GSNM6 =V GSNM8 =VDDD POR , VDDD POR Represents the power supply voltage at the flip time, and , x represents the ratio of the width to length ratio of the eighth N-tube N8 to the fifth N-tube N5; and it is approximately assumed that the threshold voltage of each NMOS tube is equal to the threshold voltage empirical value V TH , so we have:

[0042] Simplified, the flip point voltage VDDD of the voltage detection circuit can be obtained as POR for: The drain-source voltage difference is positively correlated with the on-resistance, while the on-resistance is negatively correlated with the doping concentration of the active area, while the threshold voltage is the opposite. For example, due to process deviation, the doping concentration increases, which reduces the on-resistance, but the threshold voltage increases. When the temperature changes, the threshold voltage and on-resistance have negative and positive temperature coefficients, respectively. It can be seen that V DSNM8 And the threshold voltage empirical value V TH It shows an opposite trend with the change of process and temperature; so when the process and temperature change, as long as Get a suitable value so that [4n 2 *(m-1) / x*m]﹤1, the flip point voltage generated by the voltage detection circuit can be less affected by process changes, and due to the uniformity of the devices, the flip point voltage generated by the voltage detection circuit can also be less affected by temperature, thereby making the threshold voltage of the power-on reset circuit less affected by process, voltage and temperature.

[0043] For example, if m=4, n=1 / 16, x=1 / 80, then [4n 2 *(m-1) / x*m]=0.9375, we can get VDDD POR ≈1.32*V DSNM8+V TH , for example V TH =0.5V, V DSNM8 =0.35V, VDDD can be calculated POR =0.962 V. It can be seen that the magnitude of the first term and the second term of the flip point voltage formula of the voltage detection circuit are in the same order of magnitude.

[0044] like Figure 3 The figure shows the simulation curves of the flip point voltage of the present invention and the prior art under different processes. Figure 3 The upper middle part is the simulation curve of the present invention, and the lower part is the simulation curve of the prior art. The horizontal axis is the power-on reset signal voltage value VPOR, and the vertical axis is the power supply voltage. VF, VT, and VS respectively represent the turning points of the power-on reset signal from a low level to a high level when the integrated circuit manufacturing process angles are FF, TT, and SS. It can be seen that compared with the prior art, the voltage difference of the turning points between different process angles of the present invention is significantly reduced.

[0045] like Figure 4 The figure shows the simulation curves of the flip point voltage at different temperatures of the present invention and the prior art. Figure 3 The upper middle part is the simulation curve of the present invention, and the lower part is the simulation curve of the prior art. The horizontal axis is the power-on reset signal voltage value VPOR, and the vertical axis is the power supply voltage VDD. V125, V25, and VN40 represent the turning points of the power-on reset signal from a low level to a high level when the temperatures are 125, 25, and -40 degrees Celsius, respectively. It can be seen that compared with the prior art, the voltage difference of the turning points between different temperatures is significantly reduced in the present invention.

[0046] Figure 1 In the specific implementation manner shown, the startup circuit includes a first P-tube P1 and a second P-tube P2, both of which have sources connected to a power supply, a gate of the first P-tube P1 connected to a drain and connected to a gate of a first N-tube N1, a source of the first N-tube N1 grounded, a drain connected to the gate of the second P-tube, a drain of the second P-tube P2 connected to the drain of the second N-tube N2, a source of the second N-tube grounded, a gate connected to a gate of a fourth N-tube N4 in a reference current generating circuit, a drain of the second P-tube P2 also connected to a gate of a third N-tube N3, a source of the third N-tube N3 grounded, and a drain connected to the gate of a sixth P-tube in a reference current generating circuit as an output end of the startup circuit.

[0047] After the power supply voltage starts to increase, the drain voltage of the first P-tube P1 increases, the first N-tube N1 is turned on and pulls down the gate voltage of the second P-tube, so that the second P-tube P2 is turned on. The second P-tube is usually a MOS tube with a large on-resistance and a reverse width-to-length ratio. After being turned on, the gate capacitance of the third N-tube N3 is charged with a small current, so that the third N-tube is turned on. After the third N-tube N3 is turned on, the gate voltage of the sixth P-tube is lowered, and the sixth P-tube is turned on, so that the reference current generating circuit starts to work.

[0048] When the reference current generating circuit starts to work, the gate voltage of the fourth N-tube N4 is established to turn on the second N-tube N2. Since the pull-up current of the second P-tube P2 is very small, the gate of the third N-tube N3 is pulled down to turn off the third N-tube, thereby turning off the startup circuit and avoiding current discharge from the third N-tube N3, resulting in a decrease in the current on the resistor and reducing the accuracy of the reference current.

[0049] To obtain a steeper voltage reversal curve, Figure 1 In the specific implementation manner shown, the output end of the voltage comparison circuit, i.e., the drain of the eighth P-tube P8, is also connected to the input end of a Schmitt trigger, and the Schmitt trigger is connected by gates connected together, and is connected to the eleventh P-tube P11, the twelfth P-tube P12, the thirteenth N-tube N13, and the fourteenth N-tube N14, which are sequentially connected from the power supply to the ground source and drain, the drain of the eleventh P-tube is also connected to the source of the thirteenth P-tube, the source of the thirteenth N-tube N13 is also connected to the source of the fifteenth N-tube N15, and the gates of the thirteenth P-tube and the fifteenth N-tube N15 are both connected to the drain of the twelfth P-tube;

[0050] The drain of the thirteenth P-tube P13 is also connected to the drain of the sixteenth N-tube N16, the source of the sixteenth N-tube N16 is grounded, and the gate is connected to the gate of the eighth N-tube N8; the drain of the fifteenth N-tube N15 is also connected to the drain of the fourteenth P-tube P14, the source of the fourteenth P-tube P14 is connected to the power supply, and the gate is connected to the drain of the twelfth N-tube N12, the source of the twelfth N-tube N12 is grounded, and the gate is connected to the drain and gate of the tenth P-tube P10, and the source of the tenth P-tube P10 is connected to the power supply. The drain of the twelfth P-tube P12 serves as the output end of the Schmitt trigger, and outputs a power-on reset signal POR after being connected to the buffer BUF.

[0051] Compared with the traditional Schmitt trigger, the gates of the fourteenth P-tube P14 and the sixteenth N-tube N16 in the present invention are respectively connected to the twelfth N-tube N12 and the ninth P-tube P9 which are stably turned on only when powered on, which can eliminate the indefinite state caused by the low power supply voltage during the power-on process and avoid the Schmitt trigger from outputting abnormal pulse signals. And certain ESD protection can be provided to the fifteenth N-tube N15 and the thirteenth P-tube P13 respectively.

[0052] The foregoing describes various preferred embodiments of the present invention. Unless the preferred implementation modes in various preferred embodiments are obviously self-contradictory or based on a certain preferred implementation mode, various preferred implementation modes can be arbitrarily superimposed and used in combination. The embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. All equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.

Claims

1. A power-on reset circuit, characterized in that , including a reference current generating circuit, the reference current generating circuit including a sixth P tube and a seventh P tube, both of which have source electrodes connected to a power supply, the gate electrodes of the sixth and seventh P tubes are connected and connected to the drain electrode of the sixth P tube, the drain electrode of the sixth P tube is connected to one end of a resistor, the other end of the resistor is connected to the drain electrode of a fourth N tube, the gate electrodes of the fourth N tube and the fifth N tube are connected and connected to the drain electrode of the fifth N tube, the source electrode of the fifth N tube is grounded, and the drain electrode is also connected to the drain electrode of the seventh P tube, the source electrode of the fourth N tube is connected to the drain electrode of the sixth N tube, and the source electrode of the sixth N tube is grounded; The width-to-length ratios of the sixth P tube and the seventh P tube are equal, and the width-to-length ratios of the fourth N tube, the fifth N tube and the sixth N tube are m:1:n; The gate of the sixth P transistor in the reference current generating circuit is also connected to a start-up circuit for starting the sixth P transistor when powered on; The power-on reset circuit also includes a voltage comparison circuit, which includes an eighth P tube and a ninth P tube, both of which have source electrodes connected to a power supply, a gate of the eighth P tube connected to the gate of the sixth P tube in the reference current generating circuit, a gate of the ninth P tube connected to the gate and drain of the seventh N tube, a source of the seventh N tube connected to ground, a drain of the ninth P tube connected to the gate of the eighth N tube, a source of the eighth N tube connected to ground, a drain connected to the drain of the eighth P tube, and a drain of the eighth P tube serving as an output end of the voltage comparison circuit; the eighth P tube and the sixth P tube have the same width-to-length ratio, and the ratio of the width-to-length ratio of the fifth N tube to the eighth N tube is 1:x; The startup circuit includes a first P tube and a second P tube, both of which have sources connected to a power supply, a gate of the first P tube connected to a drain and connected to a gate of a first N tube, a source of the first N tube grounded, a drain connected to the gate of the second P tube, a drain of the second P tube connected to the drain of the second N tube, a source of the second N tube grounded, a gate connected to the gate of a fourth N tube in a reference current generating circuit, a drain of the second P tube also connected to the gate of a third N tube, a source of the third N tube grounded, and a drain connected to the gate of a sixth P tube in the reference current generating circuit as an output end of the startup circuit.

2. The power-on reset circuit as claimed in claim 1, characterized in that: The second P tube is an inverse ratio tube whose length is greater than its width.

3. The power-on reset circuit as claimed in claim 1, characterized in that: The output end of the voltage comparison circuit, i.e., the drain of the eighth P tube, is also connected to the input end of a Schmitt trigger, and the Schmitt trigger is connected by gates connected together, and is connected to the eleventh P tube, the twelfth P tube, the thirteenth N tube, and the fourteenth N tube, which are sequentially connected from the power supply to the ground source and drain, the drain of the eleventh P tube is also connected to the source of the thirteenth P tube, the source of the thirteenth N tube is also connected to the source of the fifteenth N tube, and the gates of the thirteenth P tube and the fifteenth N tube are both connected to the drain of the twelfth P tube; The drain of the thirteenth P tube is also connected to the drain of the sixteenth N tube, the source of the sixteenth N tube is grounded, and the gate is connected to the gate of the eighth N tube; the drain of the fifteenth N tube is also connected to the drain of the fourteenth P tube, the source of the fourteenth P tube is connected to the power supply, and the gate is connected to the drain of the twelfth N tube, the source of the twelfth N tube is grounded, the gate is connected to the drain and gate of the tenth P tube, and the source of the tenth P tube is connected to the power supply; the drain of the twelfth P tube serves as the output end of the Schmitt trigger.

4. The power-on reset circuit as claimed in claim 3, characterized in that: The output end of the Schmitt trigger is connected to a buffer and then outputs a power-on reset signal.

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