Capacitor mismatch self-calibration circuit and method for high-precision low-delay analog-to-digital converter

Abstract

The invention discloses a capacitor mismatch self-calibration circuit and method for a high-precision low-delay analog-to-digital converter. The calibration process mainly comprises a sampling and setting stage, a quantification stage, an amplification stage and an integration stage. Part of DAC units of the ADC are used as the calibration DAC, the error voltage generated by the DAC units to be calibrated is subjected to exponential increment type quantitative estimation, then compensation is carried out in a digital domain or an analog domain, and calibration of the capacitor mismatch error is achieved. On the premise of increasing small hardware overhead, by combining the quantization principle of the index increment type ADC, the original error detection range is broken through, the error smaller than 1LSB can be estimated, the limitation of the calibration effect of the calibration DAC self mismatch is optimized, and the accurate calibration of the 24-bit high-precision low-delay ADC capacitor mismatch error can be realized.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and in particular relates to a high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit and method. Background Art

[0002] Precision instruments, medical imaging and other applications urgently need 24-bit high-precision, low-latency analog-to-digital converter (ADC) chips, which are the core components of systems such as instant measurement and real-time image processing. Successive approximation ADC (SAR ADC) has become the mainstream architecture of high-precision, low-latency analog-to-digital converters due to its low power consumption and simple circuit structure. However, the nonlinear error introduced by capacitor mismatch limits the possibility of SAR ADC to develop in the direction of high precision and high speed. Therefore, in order to achieve high-precision SAR ADC, additional calibration technology needs to be introduced to calibrate the capacitor mismatch.

[0003] A common front-end self-calibration method for capacitor mismatch is to use its own low-bit DAC as a calibration DAC to estimate the error of the high-bit DAC from top to bottom, and then perform error compensation in the analog or digital domain. However, this calibration method can only estimate errors greater than 1LSB, and when calibrating a high-precision ADC higher than 16 bits, the mismatch of its own low-bit DAC will limit the calibration effect. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision and low-delay analog-to-digital converter capacitance mismatch self-calibration circuit and method.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit, comprising:

[0007] A noise shaping unit, used to amplify the upper plate residual voltage of the CDAC array in the self-calibration circuit by G times and then store it according to the control of the signal clk_ns1, and input the stored residual voltage into the CDAC array according to the control of the signal clk_ns2; each CDAC array includes M-bit main capacitors;

[0008] A residual clearing unit, used for clearing the upper plate residual voltage stored in the noise shaping unit according to the control of the signal clk_reset before calibrating the m-th capacitor; M is a positive integer greater than 1, m is a positive integer, the value of m is a preset integer x to M-1, x is a first preset positive integer;

[0009] A sampling switch unit, used for accessing the common mode voltage VCM according to the control of the signal clk_sample when calibrating the m-th capacitor, so as to be sampled by each CDAC array;

[0010] A setting and quantization unit, used for, when calibrating the m-th capacitor, alternately performing two different setting operations on the m-th capacitor according to the control of signals clk_set and clk_comp, and performing a round of quantization on the m-1th to 1st capacitors after each setting operation, inputting the upper plate residual voltage generated by the current round of quantization into the noise shaping unit, and then performing the next round of quantization according to the upper plate residual voltage stored in the noise shaping unit, until p rounds of quantization are performed on the m-1th to 1st capacitors under each setting operation; p is a second preset positive integer;

[0011] A calibration and storage unit, for determining the weight of the m-th capacitor based on the calibration code of the m-1th to 1st capacitors generated by the p-round quantization according to the control of the signal clk_cal, and the weights and amplification factors G of the m-1th to 1st capacitors, completing the calibration of the m-th capacitor, and storing the weight of the m-th capacitor for calibration of the m+1th capacitor.

[0012] The present invention also provides a high-precision, low-latency analog-to-digital converter capacitance mismatch self-calibration method, which is implemented by the high-precision, low-latency analog-to-digital converter capacitance mismatch self-calibration circuit described above, wherein the self-calibration circuit comprises a CDAC array, each CDAC array comprises an M-bit main capacitor; the method comprises:

[0013] Residue clearing step: clearing the stored upper plate residual voltage of each CDAC array;

[0014] The first sampling step: use each CDAC array to measure the common-mode voltage V CM Perform a sampling, and sample the stored upper plate residual voltage at the same time, then compare the voltages of the upper plates of different CDAC arrays to obtain a first comparison result; m is a positive integer, and the value of m is a preset integer x to M-1, and x is a first preset positive integer; wherein, when the first sampling step is performed for the first time, the voltage value obtained after sampling the stored upper plate residual voltage is 0;

[0015] A first setting step: generating a first calibration code for the m-th capacitor according to the first comparison result, generating a first control code for the m-th capacitor according to the first calibration code for the m-th capacitor, and performing a setting operation on the m-th capacitor according to the first control code for the m-th capacitor;

[0016] The first quantization step: after the m-th capacitor is set to 1, a round of quantization is performed on the m-1th to 1st capacitors, after the round of quantization is completed, the calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained, and the upper plate residual voltage generated by the round of quantization is amplified G times and stored;

[0017] The second sampling step: using each CDAC array to measure the common mode voltage V CM Performing a sampling operation, sampling the stored upper plate residual voltage at the same time, and then comparing the voltages of the upper plates of different CDAC arrays to obtain a second comparison result;

[0018] A second setting step: generating a second calibration code for the m-th capacitor according to the second comparison result, generating a second control code for the m-th capacitor according to the second calibration code for the m-th capacitor, and performing a zero setting operation on the m-th capacitor according to the second control code for the m-th capacitor;

[0019] The second quantization step: after the m-th capacitor is set to 0, a round of quantization is performed on the m-1th to 1st capacitors, after the round of quantization is completed, a calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained, and the upper plate residual voltage generated by the round of quantization is amplified G times and stored;

[0020] Return to the first sampling step and continue to execute until the first sampling step to the second quantization step are all executed p times, and the calibration code of the m-1th to 1st capacitors generated by each round of quantization by setting the mth capacitor to 0 and setting it to 1 is obtained;

[0021] Based on the weights of the m-1th to 1st capacitors, the amplification factor G, and the calibration codes of the m-1th to 1st capacitors generated in each round of quantization when the m-1th capacitor is set to 0 and set to 1, the weight of the m-th capacitor is determined to complete the calibration of the m-th capacitor.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] Under the premise of increasing the hardware overhead, the present invention breaks through the original error detection range by combining the quantization principle of exponential incremental ADC, so that errors less than 1LSB can also be estimated, and optimizes the limitation of the calibration DAC's own mismatch on the calibration effect, and can realize the accurate calibration of the 24-bit high-precision and low-delay ADC capacitor mismatch error.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is an overall circuit structure diagram of a self-calibration circuit provided by an embodiment of the present invention;

[0026] Figure 2 is a working clock timing diagram of a self-calibration circuit provided by an embodiment of the present invention;

[0027] Figure 3 It is a schematic diagram of a capacitance DAC array of a self-calibration circuit and a specific calibration switching process provided by an embodiment of the present invention;

[0028] Figure 4 It is a 16384-point FFT spectrum comparison diagram after modeling and verification in Matlab Simulink of the conventional calibration method for expanding the number of bits provided in the embodiment of the present invention and the calibration method of the present invention;

[0029] Figure 5 It is a comparison diagram of SNDR and SFDR convergence speed of the calibration circuit and method designed by the present invention provided in the embodiment of the present invention and the conventional calibration circuit and method. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0031] The present invention provides a high-precision low-delay analog-to-digital converter capacitor mismatch self-calibration circuit, comprising: a CDAC array, a noise shaping unit, a margin clearing unit, a sampling switch unit, a setting and quantization unit, and a calibration and storage unit; wherein the noise shaping unit is connected to the CDAC array and the margin clearing unit respectively, the sampling switch unit is connected to the CDAC array, and the setting and quantization unit is connected to the calibration and storage unit and the CDAC array respectively. The noise shaping unit amplifies, stores, and outputs the upper plate margin voltage of the CDAC array according to the control of signals clk_ns1 and clk_ns2; the margin clearing unit clears the upper plate margin voltage stored in the noise shaping unit according to the control of signal clk_reset; the sampling switch unit performs a common mode voltage V according to the control of signal clk_sample. CM intervention; the setting and quantization unit performs the quantization operation of the capacitance according to the control of the signals clk_set and clk_comp; the calibration and storage unit performs the weight calculation of the capacitance and the storage and output of the data according to the control of the signal clk_cal.

[0032] The noise shaping unit is used to amplify the upper plate margin voltage of the CDAC array in the self-calibration circuit by G times and then store it according to the control of the signal clk_ns1, and input the stored margin voltage into the CDAC array according to the control of the signal clk_ns2; each CDAC array includes M-bit main capacitors.

[0033] The margin clearing unit is used to clear the upper plate margin voltage stored in the noise shaping unit according to the control of the signal clk_reset before calibrating the m-th capacitor; M is a positive integer greater than 1, m is a positive integer, and the value of m is a preset integer from x to M-1, and x is a first preset positive integer.

[0034] The sampling switch unit is used to access the common mode voltage VCM according to the control of the signal clk_sample when calibrating the m-th capacitance, so as to be sampled by each CDAC array.

[0035] A setting and quantization unit is used to perform two different setting operations on the m-th capacitor alternately according to the control of signals clk_set and clk_comp when calibrating the m-th capacitor, and perform a round of quantization on the m-1th to 1st capacitors after each setting operation, input the upper plate residual voltage generated by the current round of quantization into the noise shaping unit, and then perform the next round of quantization according to the upper plate residual voltage stored in the noise shaping unit, until p rounds of quantization are performed on the m-1th to 1st capacitors under each setting operation; p is a second preset positive integer.

[0036] The calibration and storage unit is used to determine the weight of the m-th capacitor based on the calibration code of the m-1th to 1st capacitors generated by p-round iterative quantization according to the control of the signal clk_cal, as well as the weights and amplification factors G of the m-1th to 1st capacitors, complete the calibration of the m-th capacitor, and store the weight of the m-th capacitor for calibration of the m+1th capacitor.

[0037] Here, the values ​​of x and p can be set according to actual needs, and the present invention does not limit this.

[0038] Please refer to Figure 1 The self-calibration circuit further includes: a first adder and a second adder, specifically as follows Figure 1 Symbols in Furthermore, the self-calibration circuit includes a first CDAC array and a second CDAC array, specifically Figure 1CAP-P and CAP-N in the circuit; the noise shaping unit includes: a first noise shaping module and a second noise shaping module. One input end of the first adder is connected to an output end of the sampling switch unit, another input end of the first adder is connected to the output end of the first noise shaping module, and the output end of the first adder is connected to the sampling end of the first CDAC array CAP-P. One input end of the second adder is connected to another output end of the sampling switch unit, another input end of the second adder is connected to the output end of the second noise shaping module, and the output end of the second adder is connected to the sampling end of the second CDAC array CAP-N. The input end of the first noise shaping module is connected to the upper plate margin voltage output end of the first CDAC array CAP-P, and the first noise shaping module is used to amplify the input upper plate margin voltage of the first CDAC array CAP-P by G times according to the control of the signal clk_ns1 and then store it, and input the stored margin voltage into the first CDAC array CAP-P through the first adder according to the control of the signal clk_ns2. The input end of the second noise shaping module is connected to the upper plate margin voltage output end of the second CDAC array CAP-N. The second noise shaping module is used to amplify the input upper plate margin voltage of the second CDAC array CAP-N by G times according to the control of the signal clk_ns1 and then store it, and input the stored margin voltage into the second CDAC array CAP-N through the second adder according to the control of the signal clk_ns2. The upper plate of the first CDAC array CAP-P is connected to the positive input end (such as Figure 1 The first CDAC array CAP-P is used to collect voltage from the output end of the first adder; the upper plate of the second CDAC array CAP-N is connected to the negative input end of the setting and quantization unit (such as Figure 1 The N terminal in the second adder is connected to collect the voltage from the output terminal of the second adder.

[0039] Here, the first CDAC array CAP-P and the second CDAC array CAP-N include main capacitors and redundant capacitors, and the number of capacitors and the arrangement of capacitors in the first CDAC array CAP-P and the second CDAC array CAP-N are the same; for example, the first CDAC array CAP-P and the second CDAC array can both include 28-bit capacitors, 20-bit capacitors or 18-bit capacitors, and so on; for example, when the first CDAC array CAP-P and the second CDAC array both include 28-bit capacitors (i.e., 28 capacitors), specifically 24-bit main capacitors and 4-bit redundant capacitors can be included. It should be noted that the number of main capacitors and redundant capacitors included in the CDAC array can be set according to actual needs, and the present invention is not limited to this.

[0040] Continue to refer Figure 1The first noise shaping module and the second noise shaping module both include: a first switch S1, a margin voltage memory ( Figure 1 The symbol "Z -1 ”), the second switch S2, an amplifier with a magnification of G ( Figure 1 The first switch S1, the residual voltage memory, the second switch S2 and the amplifier are connected in series in sequence, and the end of the first switch S1 not connected to the residual voltage memory is used as the output end of the noise shaping module, and the end of the amplifier not connected to the second switch S2 is used as the input end of the noise shaping module. The first switch S1 is opened or closed under the control of the signal clk_ns1, and the second switch S2 is opened or closed under the control of the signal clk_ns2. It should be noted that the specific value of G can be set according to actual needs, and the present invention is not limited to this. Exemplarily, the residual voltage memory is a capacitor.

[0041] Continue to refer Figure 1 The setting and quantization unit includes: a SAR logic unit and a comparator. The upper plate of the first CDAC array CAP-P is connected to the positive input terminal of the comparator ( Figure 1 The upper plate of the second CDAC array CAP-N is connected to the negative input terminal of the comparator ( Figure 1 An input terminal of the SAR logic unit is connected to the output terminal of the comparator, another input / output terminal of the SAR logic unit is connected to the calibration and storage unit, an output terminal of the SAR logic unit is connected to the first CDAC array CAP-P, and another output terminal is connected to the second CDAC array CAP-N. The SAR logic unit performs a set operation according to the control of the signal clk_set, and the comparator performs a comparison operation according to the control of the signal clk_comp.

[0042] Continue to refer Figure 1 The calibration and storage unit includes: a calibration logic unit and a memory. An input / output terminal of the calibration logic unit is connected to the input / output terminal of the SAR logic unit, and another input / output terminal of the calibration logic unit is connected to an input / output terminal of the memory. The calibration logic unit and the memory both work according to the control of the signal clk_cal.

[0043] Continue to refer Figure 1 The residual clearing unit includes: a third switch S3 and a fourth switch S4. One end of the third switch S3 is connected to the first switch S1 in the first noise shaping module and one end of the residual voltage memory, and the other end is grounded; one end of the fourth switch S4 is connected to the first switch S1 in the second noise shaping module and one end of the residual voltage memory, and the other end is grounded. The third switch S3 and the fourth switch S4 are opened or closed at the same time under the control of the signal clk_reset.

[0044] Continue to refer Figure 1 The sampling switch unit includes: a fifth switch S5 and a sixth switch S6. One end of the fifth switch S5 is connected to the common mode voltage V CM The other end is connected to an input end of the first adder. One end of the sixth switch S6 is connected to the common mode voltage V CM The other end is connected to an input end of the second adder. The fifth switch S5 and the sixth switch S6 are used to be opened or closed simultaneously under the control of the signal clk_sample.

[0045] In the present invention, the sampling switch unit is also used to connect the common mode voltage V once before performing each setting operation on the m-th capacitor according to the control of the signal clk_sample. CM. The first noise shaping module is also used to, according to the control of the signal clk_ns1, after each round of quantization of the m-1th to the 1st capacitor is completed, amplify the upper plate margin voltage of the first CDAC array generated in this round by G times and store it, and then, according to the control of the signal clk_ns2, input the stored upper plate margin voltage to the first adder, so that the first CDAC array is sampled before the next round of quantization. The second noise shaping module is also used to, according to the control of the signal clk_ns1, after each round of quantization of the m-1th to the 1st capacitor is completed, amplify the upper plate margin voltage of the second CDAC array generated in this round by G times and store it, and then, according to the control of the signal clk_ns2, input the stored upper plate margin voltage to the second adder, so that the second CDAC array is sampled before the next round of quantization. The comparator is also used to compare the upper plate voltage of the first CDAC array with the upper plate voltage of the second CDAC array after the m-th capacitor or any one of the m-1 to 1-th capacitors is set according to the control of the signal clk_comp, obtain a corresponding comparison result, and output the comparison result to the SAR logic unit. The SAR logic unit is also used to generate a first calibration code and a second calibration code of the m-th capacitor according to the comparison result fed back by the comparator in real time according to the control of the signal clk_set when calibrating the m-th capacitor, perform two different set operations on the m-th capacitor alternately according to the first calibration code and the second calibration code of the m-th capacitor, and perform a round of quantization of the m-1 to 1-th capacitors in combination with the comparator, the first CDAC array and the second CDAC array after each set operation, and convert the comparison result fed back by the comparator in real time into the calibration code of the m-1 to 1-th capacitors during the quantization process and send it to the calibration and storage unit, until p rounds of quantization of the m-1 to 1-th capacitors are completed under each set operation. The calibration logic unit is used to receive the calibration code generated by the SAR logic unit according to the control of the signal clk_cal, and to obtain the weights and amplification factors G of the stored m-1 to 1 capacitors from the memory, calculate the weight of the m-th capacitor according to the received calibration code and the weights and amplification factors G of the m-1 to 1 capacitors, and store the weight of the m-th capacitor in the memory.

[0046] Specifically, when the self-calibration circuit of the present invention needs to perform the j-th setting operation on the m-th capacitor, and perform a round of quantization on the m-1-th to 1-th capacitors after performing the j-th setting operation on the m-th capacitor, the working principles of the SAR logic unit, the first CDAC array, the second CDAC array and the comparator are as follows:

[0047] The SAR logic unit generates the jth calibration code of the mth capacitor according to the comparison result fed back by the comparator, and generates the jth control code of the mth capacitor according to the jth calibration code of the mth capacitor (for example, Figure 1 D calP and D calN ), according to the jth control code of the mth capacitor, the mth capacitor is set to 1 or 0, and then, the comparator, the first CDAC array and the second CDAC array are combined to perform a round of quantization on the m-1th to 1st capacitors. In the process of performing the round of quantization on the m-1th to 1st capacitors, the comparison result of the mth capacitor after the operation of setting 1 or setting 0 is received from the comparator, and when the received comparison result is 1, 1 is used as the calibration code of the m-1th capacitor, and when the received comparison result is 0, -1 is used as the calibration code of the m-1th capacitor, and the calibration code of the m-1th capacitor is sent to the calibration and storage unit, and the comparison result after the operation of setting 1 on the mth capacitor is sent to the first CDAC array and the second CDAC array; j is a positive integer, and the value of j is 1 to 2p;

[0048] When the comparison result fed back by the comparator after the set operation on the m-th capacitor is 1, the first CDAC array and the second CDAC array perform a set operation on the m-1-th capacitor, and when the comparison result fed back by the comparator after the set operation on the m-th capacitor is 0, the set operation on the m-1-th capacitor is performed;

[0049] The comparator generates a comparison result after setting the m-1th capacitor to 1 or 0 and sends the comparison result to the SAR logic unit;

[0050] The SAR logic unit receives the comparison result fed back by the comparator after the m-1th capacitor is set to 1 or set to 0, continues to generate the calibration code of the m-2th capacitor according to the received comparison result, and sends the calibration code of the m-2th capacitor to the calibration and storage unit, and also sends the comparison result fed back by the comparator after the m-1th capacitor is set to 1 or set to 0 to the first CDAC array and the second CDAC array, so that the m-2th capacitor is set by the first CDAC array and the second CDAC array, and iterates and cycles until the comparator, the first CDAC array and the second CDAC array complete a set operation on the m-1th to 1st capacitors, and then the round of quantization of the m-1th to 1st capacitors is ended, and the calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained.

[0051] In the present invention, when a set operation is performed on any capacitor in the first CDAC array and the second CDAC array, when the signal connected to the lower plate of the capacitor in the first CDAC array is switched to the reference voltage V REF, at the same time, when the signal connected to the lower plate of any capacitor in the second CDAC array is switched to GND, it indicates that a set operation is performed on any capacitor in the first CDAC array and the second CDAC array. Such a set operation is called SET1; when the signal connected to the lower plate of any capacitor in the first CDAC array is switched to the reference voltage GND, at the same time, the signal connected to the lower plate of any capacitor in the second CDAC array is switched to V REF When , it indicates that a setting operation is performed on any one capacitor in the first CDAC array and the second CDAC array. Such a setting operation is called SET0.

[0052] For example, Figure 2 FIG. 1 is a timing diagram of the working clock of the self-calibration circuit of the present invention. Figure 2 As shown, before the calibration of a certain main capacitor is started, the signal clk_reset appears at a high level once to control the fifth switch S5 and the sixth switch S6 to be turned on, thereby clearing the upper board margin voltage stored in the margin voltage memory. Then, when the calibration of the certain main capacitor is started, the signal clk_cal changes from a low level to a high level to enable the calibration logic unit and the memory to start working. At the same time, the signal clk_sample appears at a high level once to access a common mode voltage V CM , so that the first CDAC array CAP-P and the second CDAC array CAP-N are responsive to the common mode voltage V CM A sampling is performed, and then, after the high level of the signal clk_sample ends, the signal clk_set appears a high level, so that the SAR logic unit performs a set 1 operation on the certain main capacitor. At the same time, the signal clk_ns2 also appears a high level to input the stored upper board margin voltage into the first CDAC array CAP-P and the second CDAC array CAP-N. Then, multiple high levels appear in the signal clk_comp to perform a round of quantization on the low-order capacitance of the certain main capacitor; after that, after a round of quantization of the low-order capacitance of the certain main capacitor ends, the signal clk_ns1 appears a high level to input the upper board voltage generated by this round of quantization into an amplifier with an amplification factor of G for amplification and then storage; then, the signal clk_sample appears a high level again to access the common mode voltage V again. CM , so that the first CDAC array CAP-P and the second CDAC array CAP-N are responsive to the common mode voltage V CMAnother sampling is performed, after which the signal clk_ns2 appears high again to input the stored upper board margin voltage into the first CDAC array CAP-P and the second CDAC array CAP-N. At the same time, the signal clk_set appears high again to enable the SAR logic unit to set the certain main capacitor to 0. After that, multiple high levels appear in the signal clk_comp to perform another round of iterative quantization on the low-order capacitance of the certain main capacitor. This cycle is iterated until p rounds of quantization are completed, and the calibration logic unit calculates the weight of the certain main capacitor.

[0053] For example, Figure 3 The present invention is a capacitor DAC array of a self-calibration circuit and a specific calibration switching process. Figure 2 and Figure 3 For further explanation. Figure 3 As shown in FIG. 1 , the capacitor DAC array connected to the P-terminal of the comparator (referred to as the P-terminal CDAC array) and the capacitor DAC array connected to the N-terminal of the comparator (referred to as the N-terminal CDAC array) are both composed of 28-bit capacitor bridges, wherein the 28-bit capacitors include 24-bit main capacitors and 4-bit redundant capacitors, with the capacitor C m Take for example (m can be any main capacitor in the capacitor array), the specific calibration process is as follows:

[0054] 1) Sampling stage: Figure 3 As shown in Figure A, the clk_sample signal goes high, sampling switches S5 and S6 are closed, and the upper plate of each capacitor in the CDAC array is connected to V CM Connect( Figure 3 In A, the operation of adding a margin voltage is omitted. Figure 3 The sampling switches S5 and S6 are then disconnected, and the sampling is completed. At this time, the expressions of the upper plate voltages of the P-end CDAC array and the N-end CDAC array are:

[0055] V P =V CM ;

[0056] V N =V CM ;

[0057] 2) Setting stage: Figure 3 As shown in Figure B, the clk_set signal goes high, and the SAR logic unit responds to C m Set the CDAC in the P terminal to 1. mP Connect V REF At the same time, the N-terminal capacitor C mN Connect to GND, and the other capacitors remain unchanged, still connected to V CMAt this time, the expressions of the upper plate voltages of the P-end CDAC array and the N-end CDAC array become:

[0058]

[0059] Among them, W TOT is the total weight of the single-ended capacitor. It should be noted that in the above expression, W mP With W mN Refers to the capacitance C m The two true weights including the mismatch error.

[0060] 3) Quantification stage: Figure 3 As shown in the figure C, after the sampling and setting are completed, select the capacitor C to be calibrated. m Low capacitance of all bits (i.e. C m-1 To C1) as a calibration DAC, the upper plate voltage of the P-end and N-end CDAC array is quantized. When quantization is performed, the comparator starts working according to the clk_comp clock signal. For the i-th quantized capacitor, when the comparator output is 1, the lower plate of the i-th quantized capacitor in the P-end CDAC array is switched to GND, and the lower plate of the i-th quantized capacitor in the N-end CDAC array is switched to V REF , and record the calibration code D of the i-th quantized capacitor cal,i When the comparator output is 0, the lower plate of the i-th quantized capacitor in the P-terminal CDAC array is switched to V REF , switch the lower plate of the i-th quantized capacitor in the N-end CDAC array to GND, and record the calibration code Dcal of the i-th quantized capacitor i is -1( Figure 3 C6 to C in Figure C 1r The switching is only an example). During the quantization process, the ratio C m High capacitance of all bits with V CM Connected and remain unchanged, not participating in the quantization process. In addition, in each round of quantization, the redundant bit capacitance encountered in this round of quantization is quantized in the same way as the main capacitance to be quantized in this round. After a round of quantization is completed, the expression of the upper plate voltage of the P-end CDAC array and the N-end CDAC array becomes:

[0061]

[0062] Among them, n represents the m The number of redundant capacitors between i represents the weight of the i-th capacitor, W ir Represents the weight of the ir-th redundant capacitor.

[0063] The margin voltage expression is:

[0064]

[0065] 4) Amplification stage: Figure 3 As shown in Figure D, after the last switch of the lower board is switched and the residual voltage is established and stabilized, V RES It is amplified G times, clk_ns1 becomes high, and the amplified residual voltage is stored through the capacitor.

[0066] 5) Integration stage: Figure 3 As shown in Figure E, after the next round of sampling, clk_ns2 becomes high, and the residual voltage is amplified and the sampling voltage V CM Adding together, the expression for the voltage actually compared by the comparator becomes:

[0067]

[0068] Since the capacitor C to be calibrated m Before calibration begins, the integrated voltage needs to be reset according to the clk_reset clock. Therefore, when calibrating each bit of capacitance, the margin voltage V added in the first round of quantization is RES is 0. For the i-th capacitor, the calibration code obtained after the first round of quantization is recorded as D cali1 At this time, the capacitor C to be calibrated m The weight calculation formula is:

[0069]

[0070] The margin voltage V added during the second round of quantization RES From the first round of quantization, for the i-th capacitor, after the second round of quantization, the calibration code obtained by quantization is recorded as D cal,i,2 At this time, the capacitor C to be calibrated m The weight calculation formula is modified to:

[0071]

[0072] Except for the first round of quantization, the residual voltage added by other rounds of quantization comes from the previous round of quantization. Repeat the above process for p times. For the i-th capacitor, the j-th round of quantization output code is recorded as D cal,i,j Then the capacitor to be calibrated C m The true weight expression is:

[0073]

[0074] Ideally, the capacitor to be calibrated contains the true weight of the mismatch error, D cal,i,j However, considering the ADC system offset error VOFFSET , the true value of the above expression is actually:

[0075]

[0076] In order to eliminate V OFFSET , it is necessary to perform two kinds of settings alternately during the calibration process of each bit of the capacitor to be calibrated, and perform a round of quantization after each setting operation. For convenience, the capacitor to be calibrated C at the P end during the setting phase is mP The lower plate is switched to V REF At the same time, the N-terminal capacitor C mN The setting operation of switching the lower plate of the capacitor to GND is called SET1; the capacitor C to be calibrated at the P end during the setting phase mP Switch the lower plate of the capacitor to GND and at the same time, mN The lower plate is switched to V REF The setting operation is called SET0. After quantizing the error voltage introduced by SET1, it is necessary to quantize the error voltage introduced by SET0 again. During the quantization process, the two calibration codes obtained are D cal,i,j,SET1 and D cal,i,j,SET0 At this time, the capacitance C to be calibrated calculated by p rounds of quantization under each of the two setting operations is m The expressions of the weights are:

[0077]

[0078] Therefore, the capacitance to be calibrated C m The weight expression can be calculated using the following formula:

[0079]

[0080] Among them, W m,cal Indicates the capacitance to be calibrated C m The weight, W i represents the weight of the i-th capacitor, D cal,i,(p-k+1),SET1 Indicates that in C m In the case of a set operation, m-1 The i-th capacitor C generated when C1 performs the p-k+1th round of quantization i Calibration code, W ir Indicates the irth redundant capacitor C ir The weight of D cal,ir,(p-k+1),SEI1 Indicates that in C m In the case of a set operation, m-1 The calibration code of the ir-th redundant capacitor generated when C1 performs the p-k+1th round of quantization, V OFFSET Denotes the system offset error of the ADC, D cal,i,(p-k+1),SET0Indicates that in C m In the reset operation, m-1 The calibration code of the i-th capacitor generated when C1 performs the p-k+1th round of quantization, D cal,ir,(p-k+1),SET0 Indicates that in C m In the reset operation, m-1 The calibration code of the ir-th redundant capacitor is generated when C1 performs the p-k+1-th round of quantization.

[0081] The calibration logic unit calculates W m,cal After that, W m,cal Write to memory, then choose to complete the C in the digital domain or analog domain m The digital domain compensation specifically refers to the use of W m,cal As the digital weight of the final output, analog domain compensation specifically refers to the use of additional programmable capacitor arrays to C m The capacitance of the mth bit is corrected on the chip, and the completion of the correction operation indicates that the mth bit main capacitor C m Calibration is complete.

[0082] The entire calibration process of the present invention is performed from bottom to top. After the lower capacitor is calibrated, the next capacitor is calibrated using the updated digital weight or capacitance.

[0083] Since the capacitance to be calibrated C m The actual capacitance value may be greater than the ideal capacitance value. In order to accurately measure C m The actual capacitance value, theoretically the calibration DAC measurement range provided by the ADC itself should be larger than C m The ideal capacitance is at least 2% (2% is a typical value of capacitor mismatch). In the present invention, 4 bits of redundancy (C 1r ,C 4r ,C 8r and C 16r ) to solve this problem, the specific location of the redundant bits is as follows Figure 3 At the same time, the exponential incremental ADC quantization method adopted by the present invention needs to consider the margin voltage V RES and the sampling voltage V CM Is the actual quantized voltage after addition within the quantization range of the calibration DAC? m When being calibrated, the specific requirements are: Therefore, it is necessary to carefully select the position of the redundant bits and the amplification factor G of the amplifier. The appropriate increase of the redundant bits can allow the amplification factor G to increase, thereby achieving a faster convergence speed. In addition, the residual voltage V added after sampling in the present invention RES It is completely random and can be regarded as a kind of random jitter, which is beneficial to the averaging of noise (such as sampling noise, comparator noise). This relaxes the requirement on the number of calibration rounds for each bit of capacitance and also speeds up the calibration.

[0084] The present invention also provides a high-precision, low-delay analog-to-digital converter capacitor mismatch self-calibration method, which is implemented using the high-precision, low-delay analog-to-digital converter capacitor mismatch self-calibration circuit described above. The method comprises:

[0085] S1, residual clearing step: clearing the stored upper plate residual voltage of each CDAC array;

[0086] S2, a first sampling step: using each CDAC array to sample the common mode voltage VCM once, and sampling the stored upper plate residual voltage at the same time, and then comparing the voltages of the upper plates of different CDAC arrays to obtain a first comparison result; m is a positive integer, and the value of m is a preset integer x to M-1, and x is a first preset positive integer; wherein, when the first sampling step is executed for the first time, the voltage value obtained after sampling the stored upper plate residual voltage is 0;

[0087] S3, a first setting step: generating a first calibration code for the m-th capacitor according to the first comparison result, generating a first control code for the m-th capacitor according to the first calibration code for the m-th capacitor, and performing a setting operation on the m-th capacitor according to the first control code for the m-th capacitor;

[0088] S4, first quantization step: after the m-th capacitor is set to 1, a round of quantization is performed on the m-1th to 1st capacitors, after the round of quantization is completed, the calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained, and the upper plate residual voltage generated by the round of quantization is amplified G times and stored;

[0089] S5, a second sampling step: using each CDAC array to sample the common mode voltage VCM once, and at the same time sampling the stored upper plate margin voltage, and then comparing the voltages of the upper plates of different CDAC arrays to obtain a second comparison result;

[0090] S6, a second setting step: generating a second calibration code for the m-th capacitor according to the second comparison result, generating a second control code for the m-th capacitor according to the second calibration code for the m-th capacitor, and performing a 0 operation on the m-th capacitor according to the second control code for the m-th capacitor;

[0091] S7, second quantization step: after the m-th capacitor is set to 0, a round of quantization is performed on the m-1th to 1st capacitors, after the round of quantization is completed, the calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained, and the upper plate residual voltage generated by the round of quantization is amplified G times and stored;

[0092] S8, return to the above S2 and continue to execute until the first sampling step to the second quantization step are all executed p times and then terminated, and the calibration code of the m-1th to 1st capacitors generated by each round of quantization under the operation of setting 0 and setting 1 for the mth capacitor is obtained;

[0093] S9. Based on the weights of the m-1th to 1st capacitors, the amplification factor G, and the calibration codes of the m-1th to 1st capacitors generated by each round of quantization when the m-1th capacitor is set to 0 and set to 1, the weight of the m-th capacitor is determined to complete the calibration of the m-th capacitor.

[0094] It should be noted that since the calibration codes generated in the above-mentioned first setting step and the second setting step are different, the calibration code in the above-mentioned first setting step is called the first calibration code, and the calibration code in the above-mentioned second setting step is called the second calibration code, and the same applies to the above-mentioned first control code and the second control code.

[0095] Under the premise of increasing the hardware overhead, the present invention breaks through the original error detection range by combining the quantization principle of exponential incremental ADC, so that errors less than 1LSB can also be estimated, and optimizes the limitation of the calibration DAC's own mismatch on the calibration effect, and can realize the accurate calibration of the 24-bit high-precision and low-delay ADC capacitor mismatch error.

[0096] In order to further illustrate the technical effect of the present invention, the self-calibration circuit of the present invention is modeled and verified in Matlab Simulink software. The number of bits of the calibration DAC can be reduced to optimize the influence of the mismatch of the calibration DAC itself on the calibration accuracy. The entire circuit model uses a 1V power supply voltage, a sampling frequency of 2MS / s, and an input signal amplitude of 2V V pp , the input signal frequency is 11.84KHz, the number of sampling points is 16384, the DAC array mismatch standard deviation is 2%, and the spectrum diagrams before and after calibration are shown in the following figure. Figure 4 As shown, by using the capacitor mismatch error calibration circuit and method proposed in the present invention, compared with before calibration, the SFDR is improved by 50.23dB and the SNDR is improved by 33.51dB.

[0097] In order to verify the optimization of the calibration circuit and method designed by the present invention on the mismatch of the calibration DAC itself, a conventional calibration circuit and method (the DAC arrays of the two are exactly the same) are designed for comparison. Compared with the conventional calibration circuit and method, the calibration circuit and method designed by the present invention improves the SFDR by 24.00dB and the SNDR by 7.49dB after calibration, and the harmonics related to the input signal frequency are significantly suppressed, and the calibration effect is remarkable.

[0098] It can be deduced from the mathematical formula that if the calibration effect is to be achieved as the calibration circuit and method designed by the present invention, the traditional calibration DAC needs to be additionally expanded The unit capacitance will be reduced times, the mismatch error will worsen The DAC area will also increase accordingly. The calibration circuit and method designed in the present invention optimize these problems. Figure 5 The figure shows the SNDR and SFDR convergence speed comparison between the calibration circuit and method designed in the present invention and the conventional calibration circuit and method. In the modeling verification, when the calibration rounds p for each bit capacitor is 8, both SFDR and SNDR are greatly improved. Compared with the conventional calibration circuit and method, the stability of the SNDR after calibration by the calibration circuit and method designed in the present invention is also greatly improved. The calibration effect is stable, and the speed is significantly improved compared with the conventional self-calibration rounds of 128, thereby realizing fast foreground self-calibration.

[0099] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0101] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0102] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision, low-delay analog-to-digital converter capacitor mismatch self-calibration circuit, characterized in that: include: A noise shaping unit, used to amplify the upper plate residual voltage of the CDAC array in the self-calibration circuit by G times and then store it according to the control of the signal clk_ns1, and input the stored residual voltage into the CDAC array according to the control of the signal clk_ns2; each CDAC array includes M-bit main capacitors; A residual clearing unit, used for clearing the upper plate residual voltage stored in the noise shaping unit according to the control of the signal clk_reset before calibrating the m-th capacitor; M is a positive integer greater than 1, m is a positive integer, the value of m is a preset integer x to M-1, x is a first preset positive integer; The sampling switch unit is used to calibrate the m-th capacitor according to the control of the signal clk_sample to perform common mode voltage V CM access to be sampled by each CDAC array; A setting and quantization unit, used for, when calibrating the m-th capacitor, alternately performing two different setting operations on the m-th capacitor according to the control of signals clk_set and clk_comp, and performing a round of quantization on the m-1th to 1st capacitors after each setting operation, inputting the upper plate residual voltage generated by the current round of quantization into the noise shaping unit, and then performing the next round of quantization according to the upper plate residual voltage stored in the noise shaping unit, until p rounds of quantization are performed on the m-1th to 1st capacitors under each setting operation; p is a second preset positive integer; A calibration and storage unit, for determining the weight of the m-th capacitor based on the calibration code of the m-1th to 1st capacitors generated by the p-round quantization according to the control of the signal clk_cal, and the weights and amplification factors G of the m-1th to 1st capacitors, completing the calibration of the m-th capacitor, and storing the weight of the m-th capacitor for calibration of the m+1th capacitor.

2. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 1, characterized in that: The self-calibration circuit further comprises: a first adder, a second adder, and the self-calibration circuit comprises a first CDAC array and a second CDAC array; the noise shaping unit comprises: a first noise shaping module and a second noise shaping module; The first adder has one input end connected to an output end of the sampling switch unit, another input end connected to the output end of the first noise shaping module, and an output end connected to the sampling end of the first CDAC array; The second adder has one input terminal connected to the other output terminal of the sampling switch unit, another input terminal connected to the output terminal of the second noise shaping module, and an output terminal connected to the sampling terminal of the second CDAC array; The first noise shaping module, whose input end is connected to the upper plate margin voltage output end of the first CDAC array, is used to amplify the input upper plate margin voltage of the first CDAC array by G times and then store it according to the control of the signal clk_ns1, and to input the stored margin voltage into the first CDAC array through the first adder according to the control of the signal clk_ns2; The second noise shaping module, whose input end is connected to the upper plate margin voltage output end of the second CDAC array, is used to amplify the input upper plate margin voltage of the second CDAC array by G times according to the control of the signal clk_ns1 and then store it, and to input the stored margin voltage into the second CDAC array through the second adder according to the control of the signal clk_ns2; The first CDAC array, the upper plate is connected to the positive input terminal of the setting and quantization unit, and is used to collect voltage from the output terminal of the first adder; the second CDAC array, the upper plate is connected to the negative input terminal of the setting and quantization unit, and is used to collect voltage from the output terminal of the second adder.

3. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 2, characterized in that: The first noise shaping module and the second noise shaping module both include: a first switch, a margin voltage memory, a second switch, and an amplifier; wherein the first switch, the margin voltage memory, the second switch, and the amplifier are sequentially connected in series, an end of the first switch not connected to the margin voltage memory serves as an output end of the noise shaping module, and an end of the amplifier not connected to the second switch serves as an input end of the noise shaping module; the amplification factor of the amplifier is G; the first switch is opened or closed under the control of the signal clk_ns1, and the second switch is opened or closed under the control of the signal clk_ns2.

4. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 2, characterized in that: The setting and quantization unit includes: a SAR logic unit and a comparator; The upper plate of the first CDAC array is connected to the positive input terminal of the comparator, and the upper plate of the second CDAC array is connected to the negative input terminal of the comparator; The SAR logic unit has one input terminal connected to the output terminal of the comparator, another input / output terminal connected to the calibration and storage unit, one output terminal connected to the first CDAC array, and another output terminal connected to the second CDAC array; The SAR logic unit performs a setting operation according to the control of the signal clk_set, and the comparator performs a comparison operation according to the control of the signal clk_comp.

5. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 4, characterized in that: The sampling switch unit is further used to connect the common mode voltage V once before performing each setting operation on the m-th capacitor according to the control of the signal clk_sample. CM ; The first noise shaping module is further used for, according to the control of the signal clk_ns1, after each round of quantization of the capacitors from the m-1th to the 1st bit is completed, amplifying the upper plate margin voltage of the first CDAC array generated in the round by G times and storing it, and then, according to the control of the signal clk_ns2, inputting the stored upper plate margin voltage into the first adder, so that the first CDAC array is sampled before the next round of quantization; The second noise shaping module is further used for, according to the control of the signal clk_ns1, after each round of quantization of the capacitors from the m-1th to the 1st bit is completed, amplifying the upper plate margin voltage of the second CDAC array generated in the round by G times and storing it, and then, according to the control of the signal clk_ns2, inputting the stored upper plate margin voltage into the second adder, so that the second CDAC array is sampled before the next round of quantization; The comparator is further used for comparing the upper plate voltage of the first CDAC array with the upper plate voltage of the second CDAC array after the m-th capacitor or any one of the m-1-th to 1-th capacitors is set according to the control of the signal clk_comp, obtaining a corresponding comparison result, and outputting the comparison result to the SAR logic unit; The SAR logic unit is further used for generating a first calibration code and a second calibration code for the m-th capacitor according to a comparison result fed back in real time by the comparator under the control of the signal clk_set when calibrating the m-th capacitor, performing two different setting operations on the m-th capacitor alternately according to the first calibration code and the second calibration code of the m-th capacitor, and performing a round of quantization of the m-1th to 1st capacitors in combination with the comparator, the first CDAC array and the second CDAC array after each setting operation, and converting the comparison result fed back in real time by the comparator into the calibration code of the m-1th to 1st capacitors and sending it to the calibration and storage unit during the quantization process, until p rounds of quantization of the m-1th to 1st capacitors are completed under each setting operation.

6. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 5, characterized in that: The SAR logic unit is further used to generate a j-th calibration code of the m-th capacitor according to the comparison result fed back by the comparator, generate a j-th control code of the m-th capacitor according to the j-th calibration code of the m-th capacitor, and perform a 1-setting or 0-setting operation on the m-th capacitor according to the j-th control code of the m-th capacitor, and then, combine the comparator, the first CDAC array and the second CDAC array to perform a round of quantization on the m-1-th to 1-th capacitors, and in the process of performing the round of quantization on the m-1-th to 1-th capacitors In the process, a comparison result fed back by the comparator after the m-th capacitor is set to 1 or set to 0 is received, and when the received comparison result is 1, 1 is used as the calibration code of the m-1-th capacitor, and when the received comparison result is 0, -1 is used as the calibration code of the m-1-th capacitor, and the calibration code of the m-1-th capacitor is sent to the calibration and storage unit, and the comparison result after the m-th capacitor is set to 1 is sent to the first CDAC array and the second CDAC array; j is a positive integer, and the value of j is 1 to 2p; The first CDAC array and the second CDAC array are further used to set the m-1th capacitor to 0 when the comparison result fed back by the comparator after the m-th capacitor is set to 1 is 1, otherwise, the m-1th capacitor is set to 1; The comparator is further used to generate a comparison result after setting the (m-1)th capacitor to 1 or 0 and send the comparison result to the SAR logic unit; The SAR logic unit is further used for receiving the comparison result fed back by the comparator after the m-1th capacitor is set to 1 or set to 0, continuing to generate the calibration code of the m-2th capacitor according to the received comparison result, and sending the calibration code of the m-2th capacitor to the calibration and storage unit, and also sending the comparison result fed back by the comparator after the m-1th capacitor is set to 1 or set to 0 to the first CDAC array and the second CDAC array, so that the first CDAC array and the second CDAC array set the m-2th capacitor, and iterating and looping in this way until the comparator, the first CDAC array and the second CDAC array complete a setting operation on the m-1th to 1st capacitors, and then ending the round quantization of the m-1th to 1st capacitors, and obtaining the calibration code of the m-1th to 1st capacitors generated by the round quantization.

7. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 1, characterized in that: The two different set operations include a set-1 operation and a set-0 operation; when each CDAC array also includes redundant capacitors, the weight of the m-th capacitor in each CDAC array calculated by the calibration and storage unit is expressed as follows: Among them, W m,cal represents the weight of the m-th capacitor, n represents the n-bit redundant capacitor located between the 1st to the m-th capacitor, W i represents the weight of the i-th capacitor, D cal,i,(p-k+1),SET1 represents the calibration code of the i-th capacitor generated when the p-k+1-th round of quantization is performed on the m-1-th to 1-th capacitors under the setting operation of the m-th capacitor, W ir represents the weight of the ir-th redundant capacitor, D cal,ir,(p-k+1),SEI1 represents the calibration code of the ir-th redundant capacitor generated when the p-k+1-th round of quantization is performed on the m-1-th to 1-th capacitors under the setting operation of the m-th capacitor, V OFFSET Denotes the system offset error of the ADC, D cal,i,(p-k+1),SET0 represents the calibration code of the i-th capacitor generated when the p-k+1-th round of quantization is performed on the m-1-th to 1-th capacitors under the condition that the m-th capacitor is set to 0, D cal,ir,(p-k+1),SET0 It represents the calibration code of the ir-th redundant capacitor generated when the p-k+1-th round of quantization is performed on the m-1-th to 1-th capacitors under the condition that the m-th capacitor is set to 0.

8. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 4, characterized in that: The calibration and storage unit includes: a calibration logic unit and a memory; The calibration logic unit has one input / output terminal connected to the input / output terminal of the SAR logic unit, and another input / output terminal connected to an input / output terminal of the memory, and is used to receive the calibration code generated by the SAR logic unit according to the control of the signal clk_cal, and obtain the weights and amplification factors G of the stored capacitors from the memory, calculate the weight of the m-1th to 1st capacitors according to the received calibration code and the weights of the capacitors from the m-1th to 1st and the amplification factor G, and store the weight of the m-1th capacitor in the memory.

9. The high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration circuit according to claim 3, characterized in that: The residual clearing unit includes: a third switch and a fourth switch; The third switch has one end connected to both the first switch in the first noise shaping module and one end of the margin voltage memory, and the other end connected to ground; The fourth switch has one end connected to the first switch in the second noise shaping module and one end of the margin voltage memory, and the other end connected to the ground. The third switch and the fourth switch are opened or closed simultaneously under the control of the signal clk_reset.

10. A high-precision, low-delay analog-to-digital converter capacitance mismatch self-calibration method, characterized in that: The method is implemented by using the high-precision, low-latency analog-to-digital converter capacitor mismatch self-calibration circuit as described in any one of claims 1 to 9, wherein the self-calibration circuit comprises a CDAC array, each CDAC array comprises an M-bit main capacitor; and the method comprises: Residue clearing step: clearing the stored upper plate residual voltage of each CDAC array; The first sampling step: use each CDAC array to measure the common-mode voltage V CM Perform a sampling, and sample the stored upper plate residual voltage at the same time, then compare the voltages of the upper plates of different CDAC arrays to obtain a first comparison result; m is a positive integer, and the value of m is a preset integer x to M-1, and x is a first preset positive integer; wherein, when the first sampling step is performed for the first time, the voltage value obtained after sampling the stored upper plate residual voltage is 0; A first setting step: generating a first calibration code for the m-th capacitor according to the first comparison result, generating a first control code for the m-th capacitor according to the first calibration code for the m-th capacitor, and performing a setting operation on the m-th capacitor according to the first control code for the m-th capacitor; The first quantization step: after the m-th capacitor is set to 1, a round of quantization is performed on the m-1th to 1st capacitors, after the round of quantization is completed, the calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained, and the upper plate residual voltage generated by the round of quantization is amplified G times and stored; The second sampling step: using each CDAC array to measure the common mode voltage V CM Performing a sampling operation, sampling the stored upper plate residual voltage at the same time, and then comparing the voltages of the upper plates of different CDAC arrays to obtain a second comparison result; A second setting step: generating a second calibration code for the m-th capacitor according to the second comparison result, generating a second control code for the m-th capacitor according to the second calibration code for the m-th capacitor, and performing a zero setting operation on the m-th capacitor according to the second control code for the m-th capacitor; The second quantization step: after the m-th capacitor is set to 0, a round of quantization is performed on the m-1th to 1st capacitors, after the round of quantization is completed, a calibration code of the m-1th to 1st capacitors generated by the round of quantization is obtained, and the upper plate residual voltage generated by the round of quantization is amplified G times and stored; Return to the first sampling step and continue to execute until the first sampling step to the second quantization step are all executed p times, and the calibration code of the m-1th to 1st capacitors generated by each round of quantization by setting the mth capacitor to 0 and setting it to 1 is obtained; Based on the weights of the m-1th to 1st capacitors, the amplification factor G, and the calibration codes of the m-1th to 1st capacitors generated in each round of quantization when the m-1th capacitor is set to 0 and set to 1, the weight of the m-th capacitor is determined to complete the calibration of the m-th capacitor.

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