An input sparsity adaptive ADC circuit and module

Abstract

The present invention relates to the technical field of analog-to-digital conversion circuit design, and in particular to an input sparsity adaptive ADC circuit and module. The present invention discloses an input sparsity adaptive ADC circuit, comprising: a sparsity detection circuit unit, a sparsity control circuit unit, a timing generation circuit unit, and a SAR‑ADC main circuit unit. The present invention adds sparsity detection to the input array, and can detect the sparsity of the array input, adaptively reduce the comparison cycle, shorten the quantization time, thereby reducing power consumption and improving quantization efficiency while maintaining the same accuracy. The present invention solves the problem of redundant comparison processes when the existing ADC processes array inputs.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion circuit design, and more specifically to: 1. an input sparsity adaptive ADC circuit; 2. an input sparsity adaptive ADC module. Background Art

[0002] As the core module of the in-memory computing quantization circuit, the power consumption and area of ​​the analog to digital converter (ADC) affect the energy efficiency and integration of the integrated memory and computing chip.

[0003] ADC and DAC (Digital to Analog Converter) account for about 15% of the area and about 50% of the energy consumption in CIM design respectively. Therefore, CIM still faces a major challenge because ADC will cause a large power and area overhead. If a lower power ADC suitable for in-memory computing can be developed, the overall performance of the memory computing circuit will be greatly improved.

[0004] When the existing ADC processes array input, it will perform the same number of comparison cycles regardless of the sparsity of the array input. However, the inventor believes that in some cases, it is not necessary to perform some comparison cycles. Therefore, the inventor has designed an input sparsity adaptive ADC circuit and module, which can predict the output of the ADC in advance according to the sparsity of the array input, reduce the comparison cycle, shorten the quantization time, and reduce power consumption while maintaining the same accuracy. Summary of the invention

[0005] Based on this, it is necessary to provide an input sparsity adaptive ADC circuit and module to address the problem of redundant comparison process when the existing ADC processes array input.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention provides an input sparsity adaptive ADC circuit, comprising: a sparsity detection circuit portion, a sparsity control circuit portion, a timing generation circuit portion, and a SAR-ADC main circuit portion.

[0008] The sparsity detection circuit unit is used to perform sparsity detection on the array input IN<0:63> according to the enable signal SAEN, the control signal CAP_RST, and the reference signals VREF1 - VREF2 to generate control signals OUTN1 - OUTN2 and control signals OUTP1 - OUTP2.

[0009] The sparsity control circuit unit is used to process OUTN1 to OUTN2 in combination with the timing signal CLK and the reset signal RST to generate an enable signal SAEN5 , an enable signal SAENB5 , and a reset signal RST5 .

[0010] The timing generation circuit section is used to process OUTP1~OUTP2 in combination with RST5, RST, and SAEN5 to generate SAEN, signal sequence DB<1:2>, and signal sequence D<3:4>.

[0011] The SAR-ADC main circuit section is used to process DB<1:2>, D<3:4> in combination with the array voltages VCAL, SAEN5, SAENB5, OUTN1~OUTN2, OUTP1~OUTP2 to generate ADC outputs OUT1~OUT2.

[0012] Among them, if the sparsity of IN<0:63> is less than 50%, OUTN1=1, OUTP1=0, OUTN2=1, OUTP2=0, and the SAR-ADC main circuit generates OUT1~OUT2 after 5 comparison cycles;

[0013] If the sparsity of IN<0:63> is between 50% and 75%, OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0, and the SAR-ADC main circuit generates OUT1~OUT2 after 4 comparison cycles;

[0014] If the sparsity of IN<0:63> is greater than 75%, OUTN1=0, OUTP1=1, OUTN2=0, OUTP2=1, and the SAR-ADC main circuit generates OUT1~OUT2 after 3 comparison cycles.

[0015] The implementation of such input sparsity adaptive ADC circuit is based on the method or process of an embodiment of the present disclosure.

[0016] In a second aspect, the present invention discloses an input sparsity adaptive ADC module, which adopts the layout of the input sparsity adaptive ADC circuit disclosed in the first aspect.

[0017] The implementation of the storage and calculation circuit based on the input sparsity adaptive ADC circuit is based on the method or process of the embodiment of the present disclosure.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The present invention designs an input sparsity adaptive ADC, which increases the sparsity detection of the input array and can detect the sparsity of the array input, adaptively reduce the comparison cycle and shorten the quantization time, thereby reducing power consumption and improving quantization efficiency without changing the accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 This is a structural diagram of an input sparsity adaptive ADC circuit provided in Embodiment 1 of the present invention;

[0022] Figure 2 for Figure 1 Schematic diagram of input and output signals of each part of the circuit;

[0023] Figure 3 for Figure 2 A circuit diagram of a sparseness detection circuit section;

[0024] Figure 4 for Figure 3 Middle comparator SA 0,1 Circuit diagram of

[0025] Figure 5 for Figure 3 Middle comparator SA 0,2 Circuit diagram of

[0026] Figure 6 for Figure 2 A circuit diagram of a sparseness control circuit section;

[0027] Figure 7 The timing diagram of the enable signal SAEN corresponding to the array input of different sparsity;

[0028] Figure 8 for Figure 2 The circuit diagram of the timing generation circuit section;

[0029] Fig. 9 for Figure 2 Circuit diagram of the main circuit part of SAR-ADC;

[0030] Fig.10 for Fig. 9 The circuit diagram of the comparator SA1;

[0031] Fig.11It is a timing diagram of the signal sequence D<1:4> corresponding to when the sparsity of the array input is less than 50%;

[0032] Fig.12 It is a timing diagram of the signal sequence D<1:4> corresponding to when the sparsity of the array input is between 50% and 75%;

[0033] Fig.13 FIG. 4 is a timing diagram of the signal sequence D<1:4> corresponding to when the sparsity of the array input is greater than 75%. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0037] Example 1

[0038] See also Figure 1 , which shows the structure and signal flow diagram of an input sparsity adaptive ADC circuit provided by this embodiment 1. For more details, see Figure 2 , which shows Figure 1 Schematic diagram of the input and output signals of each part.

[0039] like Figure 1 , Figure 2 As shown, the input sparsity adaptive ADC circuit can be functionally divided into four parts: a sparsity detection circuit part, a sparsity control circuit part, a timing generation circuit part, and a SAR-ADC main circuit part.

[0040] The circuit structures are introduced one by one below:

[0041] 1. The sparsity detection circuit unit is used to perform sparsity detection on the array input IN<0:63> according to the enable signal SAEN, the control signal CAP_RST, and the reference signals VREF1-VREF2, and generate control signals OUTN1-OUTN2 and control signals OUTP1-OUTP2.

[0042] For details, see Figure 3 The sparseness detection circuit part can be designed to include: capacitor array CIN0~CIN 63 、Switch array S0~S 63 , 2 comparators SA 0,1 ~SA 0,2 .

[0043] like Figure 3 As shown, CIN m The upper plate is connected to the m+1th signal IN in IN<0:63> <m>; m∈[0,63].

[0044] S m It is a single-pole double-throw switch; S m The control end is connected to CAP_RST, and the fixed end is connected to CIN m The lower electrode plate of the switching terminal forms a signal INN1, and the switching terminal 2 is connected to VSS.

[0045] Among them, CAP_RST controls the switch array uniformly: when CAP_RST is 1, S m Connect switch terminal 2, CIN m The lower substrate of the capacitor is connected to VSS to reset the capacitor array; when CAP_RST is 0, S m Connect switch terminal 1, CIN m The lower substrate is connected to INN1.

[0046] S 0,1 The positive input terminal is connected to VREF1, the negative input terminal is connected to INN1, the control terminal is connected to SAEN, the output terminal 1 is used to output OUTN1, and the output terminal 2 is used to output OUTP1;

[0047] S 0,2 The positive input terminal is connected to VREF2, the negative input terminal is connected to INN1, the control terminal is connected to SAEN, the output terminal 1 is used to output OUTN2, and the output terminal 2 is used to output OUTP2.

[0048] Among them, SAEN is 0,1 ~SA 0,2 Unified control: When SAEN is 1, SA 0,1 ~SA 0,2 Reset; when SAEN is 0, SA 0,1 ~SA 0,2 Work.

[0049] It should be noted that OUTP1 and OUTN1 are opposite signals to each other; OUTP2 and OUTN2 are opposite signals to each other; VREF1=VDD / 2; VREF2=VDD / 4.

[0050] It should be noted that SA 0,1 ~SA 0,2 Conventional comparator design can be used, or Figure 4 , Figure 5 Circuit design.

[0051] For details, see Figure 4 , S.A. 0,1 The design includes: 12 PMOS tubes PM1~PM12, 8 NMOS tubes NM1~NM8, 1 transmission gate GM1, and 1 inverter INVM1.

[0052] The gate of NM1 is connected to SAEN, and the source is connected to VSS;

[0053] The gate of NM2 is connected to SAEN, and the source is connected to VSS;

[0054] The drain of NM3 acts as the SA 0,1 The output terminal 1, the source is connected to VSS;

[0055] The drain of NM4 acts as the SA 0,1 The output terminal 2, the source is connected to VSS;

[0056] The gate of NM5 is connected to the drain of NM1;

[0057] The gate of NM6 is connected to the drain of NM2;

[0058] The drain of NM7 is connected to the source of NM5, the source is connected to VSS, and the gate is connected to the drain of NM6;

[0059] The drain of NM8 is connected to the source of NM6, the source is connected to VSS, and the gate is connected to the drain of NM5;

[0060] The gate of PM1 is connected to VSS;

[0061] The gate of PM2 is connected to VREF1, and the source is connected to the drain of PM1;

[0062] The gate of PM3 is connected to INN1, and the source is connected to the drain of PM1;

[0063] The gate of PM4 is connected to SAEN, the source is connected to VDD, and the drain is connected to the source of PM1;

[0064] The gate of PM5 is connected to VSS, the drain is connected to the drain of NM1, the gate of PM9, the gate of NM5, and the source is connected to the drain of PM2;

[0065] The gate of PM6 is connected to VSS, the drain is connected to the drain of NM2, the gate of PM10, the gate of NM6, and the source is connected to the drain of PM3;

[0066] The gate of PM7 is connected to the gate of NM3, the source is connected to VDD, and the drain is connected to the drain of NM3;

[0067] The gate of PM8 is connected to the gate of NM4, the source is connected to VDD, and the drain is connected to the drain of NM4;

[0068] The gate of PM9 is connected to the gate of NM5, the source is connected to VDD, and the drain is connected to the gate of PM7;

[0069] The gate of PM10 is connected to the gate of NM6, the source is connected to VDD, and the drain is connected to the gate of PM8;

[0070] The gate of PM11 is connected to the gate of NM7, the source is connected to VDD, and the drain is connected to the gate of PM7;

[0071] The gate of PM12 is connected to the gate of NM8, the source is connected to VDD, and the drain is connected to the gate of PM8;

[0072] The input terminal of INVM1 is connected to SAEN;

[0073] The control terminal 1 of GM1 is connected to the drain of PM2, the control terminal 2 is connected to the drain of PM3, the input / output terminal 1 is connected to SAEN, and the input / output terminal 2 is connected to the output terminal of INVM1.

[0074] See also Figure 5 , S.A. 0,2 The design includes: 12 PMOS tubes PN1~PN12, 8 NMOS tubes NN1~NN8, 1 transmission gate GN1, and 1 inverter INVN1.

[0075] The gate of NN1 is connected to SAEN, and the source is connected to VSS;

[0076] The gate of NN2 is connected to SAEN, and the source is connected to VSS;

[0077] The drain of NN3 acts as SA 0,2 The output terminal 1, the source is connected to VSS;

[0078] The drain of NN4 acts as SA 0,2 The output terminal 2, the source is connected to VSS;

[0079] The gate of NN5 is connected to the drain of NN1;

[0080] The gate of NN6 is connected to the drain of NN2;

[0081] The drain of NN7 is connected to the source of NN5, the source is connected to VSS, and the gate is connected to the drain of NN6;

[0082] The drain of NN8 is connected to the source of NN6, the source is connected to the VSS gate, and the gate is connected to the drain of NN5;

[0083] The gate of PN1 is connected to VSS;

[0084] The gate of PN2 is connected to VREF2, and the source is connected to the drain of PN1;

[0085] The gate of PN3 is connected to INN1, and the source is connected to the drain of PN1;

[0086] The gate of PN4 is connected to SAEN, the source is connected to VDD, and the drain is connected to the source of PN1;

[0087] The gate of PN5 is connected to VSS, the drain is connected to the drain of NN1, the gate of PN9, the gate of NN5, and the source is connected to the drain of PN2;

[0088] The gate of PN6 is connected to VSS, the drain is connected to the drain of NN2, the gate of PN10, the gate of NN6, and the source is connected to the drain of PN3;

[0089] The gate of PN7 is connected to the gate of NN3, the source is connected to VDD, and the drain is connected to the drain of NN3;

[0090] The gate of PN8 is connected to the gate of NN4, the source is connected to VDD, and the drain is connected to the drain of NN4;

[0091] The gate of PN9 is connected to the gate of NN5, the source is connected to VDD, and the drain is connected to the gate of PN7;

[0092] The gate of PN10 is connected to the gate of NN6, the source is connected to VDD, and the drain is connected to the gate of PN8;

[0093] The gate of PN11 is connected to the gate of NN7, the source is connected to VDD, and the drain is connected to the gate of PN7;

[0094] The gate of PN12 is connected to the gate of NN8, the source is connected to VDD, and the drain is connected to the gate of PN8;

[0095] The input terminal of INVN1 is connected to SAEN;

[0096] The control terminal 1 of GN1 is connected to the drain of PN2, the control terminal 2 is connected to the drain of PN3, the input / output terminal 1 is connected to SAEN, and the input / output terminal 2 is connected to the output terminal of INVN1.

[0097] Since SA 0,1 and SA 0,2 Same structure, with SA 0,1 Take the comparator principle as an example for detailed description:

[0098] If INN1>VREF1, the drain voltage of PM3 is less than PM2, which in turn causes the drain voltage of PM6 to be less than PM5, which in turn causes PM9 to close early and NM5 to open early; since PM11~PM12 and NM5~NM8 form a latch structure (the drain of PM11 forms a P node and the drain of PM12 forms an N node), the voltage drop rate of the N node is lower than that of the P node, and the P node becomes 0 first, making OUTN1 1 and OUTP1 0.

[0099] Similarly, if INN1<VREF1, OUTN1=0, OUTP1=1.

[0100] Similarly, for SA 0,2 For example:

[0101] If INN1<VREF2, OUTN2=0, OUTP2=1;

[0102] If INN1>VREF2, OUTN2=1, OUTP2=0.

[0103] Based on the circuit structure of the above-mentioned sparseness detection circuit unit, IN <m>Input in the form of a square wave: Let the number of "1" signals in IN<0:63> be n, then n∈[0,64]; then, the voltage at INN1 is n*VDD / 64.

[0104] ① If the sparsity of IN<0:63> is less than 50%, then n∈[33,64], INN1>VREF1, INN1>VREF2, then OUTN1=1, OUTP1=0, OUTN2=1, OUTP2=0.

[0105] ② If the sparsity of IN<0:63> is between 50% and 75%, then n∈[16,32], INN1> VREF2, INN1<VREF1, then OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0;

[0106] ③ If the sparsity of IN<0:63> is greater than 75%, then n∈[0,15], INN1<VREF1, INN1<VREF2, then OUTN1=0, OUTP1=1, OUTN2=0, OUTP2=1.

[0107] 2. The sparsity control circuit unit is used to process OUTP1-OUTP2 in combination with the timing signal CLK and the reset signal RST to generate an enable signal SAEN5, an enable signal SAENB5, and a reset signal RST5.

[0108] For details, see Figure 6 The sparsity control circuit part can be designed to include: 6 D flip-flops D0~D5, and 3 AND gates AND1~AND3.

[0109] Input terminal 1 of AND1 is connected to OUTN1, output terminal 2 is connected to the Q output terminal of D1, and the output terminal is electrically connected to the D input terminal of D2;

[0110] Input terminal 1 of AND2 is connected to OUTN2, output terminal 2 is connected to the Q output terminal of D2, and the output terminal is electrically connected to the D input terminal of D3;

[0111] The Clk terminal of D0 is connected to CLK, the inverted Q output terminal is used to output SAENB5 and is connected to the D input terminal, and the Q output terminal is used to output SAEN5;

[0112] The Clk end of D1~D5 is connected to SAEN5, and the reset end is connected to RST;

[0113] The D input of D1 is connected to VSS;

[0114] The Q output terminal of D3 is connected to the D input terminal of D4; the Q output terminal of D4 is connected to the D input terminal of D5; the Q output terminal of D5 is used to output RST5;

[0115] Input terminal 1 of AND3 is connected to RST, input terminal 2 is connected to RST5, and the output terminal is connected to the reset terminal of D0.

[0116] Among them, CLK is the overall clock signal; SAEN5 is a two-frequency signal generated based on CLK;

[0117] RST controls D1~D5 uniformly: when RST is 0, D1~D5 are reset; when RST is 1, D1~D5 work.

[0118] See also Figure 7 , based on the circuit structure of the above sparsity control circuit unit:

[0119] ① If the sparsity of IN<0:63> is less than 50%, OUTN1=1, OUTP1=0, OUTN2=1, OUTP2=0, the output of AND1 depends on the Q output of D1, the output of AND2 depends on the Q output of D2, RST5 becomes 0 after 5 clock cycles T of SAEN5, and AND3 outputs 0, that is: D0 is reset after 5 clock cycles T, and SAEN5 becomes high-level reset after 5 clock cycles T.

[0120] ② If the sparsity of IN<0:63> is between 50% and 75%, OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0, AND1 outputs 0, the output of AND2 depends on the Q output of D2, RST5 becomes 0 after 4 clock cycles T of SAEN5, and AND3 outputs 0, that is: D0 is reset after 4 clock cycles T, and SAEN5 becomes high-level reset after 4 clock cycles T.

[0121] ③ If the sparsity of IN<0:63> is greater than 75%, OUTN1=0, OUTP1=1, OUTN2=0, OUTP2=1, AND1 and AND2 both output 0, RST5 becomes 0 after 3 clock cycles T of SAEN5, and AND3 outputs 0, that is: D0 is reset after 3 clock cycles T, and SAEN5 becomes high-level reset after 3 clock cycles T.

[0122] 3. The timing generation circuit section is used to process OUTP1~OUTP2 in combination with RST5, RST, and SAEN5 to generate SAEN, signal sequence DB<1:2>, and signal sequence D<3:4>.

[0123] For details, see Figure 8 The timing generation circuit part can be designed to include: 5 D flip-flops D6~D10, 2 OR gates OR1~OR2, 1 NAND gate NAND1, and 1 inverter INV1.

[0124] Input terminal 1 of NAND1 is connected to RST, input terminal 2 is connected to RST5, and the output terminal is used to output SAEN;

[0125] The input end of INV1 is connected to SAEN, and the output end is used to output the reset signal rst;

[0126] The Clk end of D6~D10 is connected to SAEN5, and the reset end is connected to rst;

[0127] The D input of D6 is connected to the Q output of D10, and the Q output is connected to the D input of D7;

[0128] The Q output of D7 is connected to the input of OR1, and the inverted Q output is used to output the signal DB <1> ;

[0129] The second input terminal of OR1 is connected to OUTP1, and the output terminal is used to output signal D <1> ;

[0130] The D input terminal of D8 is connected to D <1> , the Q output terminal is connected to the input terminal 1 of OR2, and the inverted Q output terminal is used to output the signal DB <2> ;

[0131] The second input terminal of OR2 is connected to OUTP2, and the output terminal is used to output signal D <2> ;

[0132] D9's D input terminal is connected to D <2> , Q output terminal is used to output signal D <3> ;

[0133] The D input terminal of D10 is connected to D <3> , Q output terminal is used to output signal D <4> .

[0134] Among them, rst controls D6~D10 uniformly: when rst is 0, D6~D10 are reset; when rst is 1, D6~D10 work.

[0135] Finally, DB <1> , DB <2> Composition DB<1:2>; D <3> , D <4> Composition D<3:4>.

[0136] Of course, D <1> , D <2> , D <3> , D <4> The signal sequence D<1:4> is also formed.

[0137] 4. The SAR-ADC main circuit is used to process DB<1:2> and D<3:4> in combination with the array voltages VCAL, SAEN5, SAENB5, OUTN1~OUTN2, and OUTP1~OUTP2 to generate ADC outputs OUT1~OUT2.

[0138] For details, see Fig. 9 The SAR-ADC main circuit can be designed to include: 1 comparator SA1, 8 D flip-flops D11~D18, 10 capacitors C11~C20, 2 XOR gates XOR1~XOR2, 1 NAND gate NAND0, 1 inverter NAND0, 7 OR gates OR11~OR17, 2 NOR gates NOR11~NOR12, and 1 transmission gate G0.

[0139] It should be noted that the capacitance ratio of C11 to C20 is 8:8:4:4:2:2:1:1:1:1, so as to facilitate the subsequent application of ADC comparison dichotomy.

[0140] The upper boards of C11~C20 are connected together and form signal INN2;

[0141] The positive input terminal of SA1 is connected to VCAL, the negative input terminal is connected to INN2 and the control terminal 1 of G0, the output terminal 1 is used to output OUT1, and the output terminal 2 is used to output OUT2;

[0142] The lower board of C11 is connected to the output end of OR11; the lower board of C12 is connected to the output end of OR12;

[0143] The lower board of C13 is connected to the output end of OR13; the lower board of C14 is connected to the output end of OR14; the lower board of C15 is connected to the reverse Q output end of D15; the lower board of C16 is connected to the output end of OR15; the lower board of C17 is connected to the reverse Q output end of D17; the lower board of C18 is connected to the output end of OR16; the lower board of C19 is connected to VSS; the lower board of C20 is connected to the output end of OR17;

[0144] Input terminal 1 of OR11 is connected to OUTP1, input terminal 2 is connected to enable signal EN, and input terminal 3 is connected to the inverted Q output terminal of D11;

[0145] Input 1 of OR12 is connected to OUTP1, input 2 is connected to EN, and input 3 is connected to the Q output of D12;

[0146] Input 1 of OR13 is connected to OUTP2, input 2 is connected to EN, and input 3 is connected to the inverted Q output of D13;

[0147] Input 1 of OR14 is connected to OUTP2, input 2 is connected to EN, and input 3 is connected to the Q output of D14;

[0148] Input 1 of OR15 is connected to the Q output of D16, and input 2 is connected to EN;

[0149] Input 1 of OR16 is connected to the Q output of D18, and input 2 is connected to EN;

[0150] Input 1 of OR17 is connected to VSS, and input 2 is connected to EN;

[0151] The reset terminal of D11~D18 is connected to RST;

[0152] The input end of D11 is connected to OUT2, and the Clk end is connected to the output end of NOR11;

[0153] The input end of D12 is connected to OUT1, and the Clk end is connected to the output end of NOR11;

[0154] The input end of D13 is connected to OUT2, and the Clk end is connected to the output end of NOR12;

[0155] The input end of D14 is connected to OUT1, and the Clk end is connected to the output end of NOR12;

[0156] The input end of D15 is connected to OUT2, and the Clk end is connected to D <3> ;

[0157] The input end of D16 is connected to OUT1, and the Clk end is connected to D <3> ;

[0158] The input end of D17 is connected to OUT2, and the Clk end is connected to D <4> ;

[0159] The input end of D18 is connected to OUT1, and the Clk end is connected to D <4> ;

[0160] NOR11 input terminal one connects DB <1> , input terminal 2 is connected to OUTP1;

[0161] NOR12 input terminal one connects DB <2> , input terminal 2 is connected to OUTP2;

[0162] The input end of INV0 is connected to RST, and the output end is connected to the input and output terminal 1 of G0;

[0163] The input and output terminal 2 of G0 is connected to RST, and the control terminal 2 is connected to VDD;

[0164] Input 1 of XOR1 is connected to OUTP1, and input 2 is connected to OUTN1;

[0165] Input 1 of XOR2 is connected to OUTP2, and input 2 is connected to OUTN2;

[0166] Input terminal 1 of NAND0 is connected to the output terminal of XOR1, input terminal 2 is connected to the output terminal of XOR2, and the output terminal is used to output EN.

[0167] Among them, EN is controlled by OUTP1, OUTP2, OUTN1, and OUTP2;

[0168] The lower plate of C11 is controlled by the output of OR11; the lower plate of C12 is controlled by the output of OR12;

[0169] The lower plate of C13 is controlled by the output of OR13; the lower plate of C14 is controlled by the output of OR14;

[0170] The lower plate of C15 is controlled by the reverse Q output of D15; the lower plate of C16 is controlled by the output of OR15;

[0171] The lower plate of C17 is controlled by the reverse Q output terminal of D17; the lower plate of C18 is controlled by the output of OR16;

[0172] The lower plate of C19 is always connected to VSS; the lower plate of C20 is controlled by the output of OR17.

[0173] It should be noted that SA1 recommends the use of Fig.10 The circuit design includes: 12 PMOS tubes P1~P12, 16 NNOS tubes N1~N16, and 1 transmission gate G1.

[0174] The gate of N1 is connected to VDD, the source is connected to the drain of N6, and the drain is connected to the source of N2 and the source of N3;

[0175] The source of N2 is connected to the drain of N1 and the source of N3, the gate serves as the negative input terminal of SA1, and the drain is connected to the source of N4 and the control terminal 1 of G2;

[0176] The gate of N3 serves as the positive input terminal of SA1, and the drain is connected to the control terminal 2 of G2 and the source of N5;

[0177] The gate of N4 is connected to the gate of N5, the source is connected to the drain of N2, and the drain serves as the A node;

[0178] The drain of N5 serves as the B node;

[0179] The gate of N6 is connected to SAEN5, and the source is connected to VSS;

[0180] The source of N7 is connected to VSS, the drain is connected to the control signal ON_LATCH, and the gate is connected to the gate of P6;

[0181] The gate of N8 is connected to the gate of P1, the drain is connected to the control signal OP_LATCH, and the source is connected to VSS;

[0182] The source of N9 is connected to VSS, the gate is connected to A, and the drain is connected to ON_LATCH;

[0183] The source of N10 is connected to VSS, the drain is connected to OP_LATCH, and the gate is connected to B;

[0184] The source of N11 is connected to VSS, the drain is connected to ON_LATCH, and the gate is connected to the control signal ON;

[0185] The gate of N12 is connected to ON_LATCH, the drain is connected to the control signal OP, and the source is connected to VSS;

[0186] The source of N13 is connected to VSS, the gate is connected to OP, and the drain is used to output OUT2;

[0187] The source of N14 is connected to VSS, the gate is connected to OP, and the drain is connected to OP_LATCH;

[0188] The source of N15 is connected to VSS, the drain is connected to ON, and the gate is connected to OP_LATCH;

[0189] The source of N16 is connected to VSS, the gate is connected to ON, and the drain is used to output OUT1;

[0190] The source of P1 is connected to VDD, the gate is connected to ON_LATCH, and the drain is connected to the source of P3;

[0191] The gate of P2 is connected to A, the drain is connected to ON_LATCH, and the source is connected to the drain of P6;

[0192] The gate of P3 is connected to B, and the drain is connected to OP_LATCH;

[0193] The source of P4 is connected to VDD, the drain is connected to A, and the gate is connected to SAENB5;

[0194] The source of P5 is connected to VDD, the gate is connected to SAENB5, and the drain is connected to B;

[0195] The source of P6 is connected to VDD, and the gate is connected to OP_LATCH;

[0196] The source of P7 is connected to VDD, the gate is connected to ON, and the drain is connected to the source of P8;

[0197] The gate of P8 is connected to ON_LATCH, and the drain is connected to OP;

[0198] The source of P9 is connected to VDD, the gate is connected to OP, and the drain is connected to the drain of N13;

[0199] The source of P10 is connected to VDD, the drain is connected to the source of P11, and the gate is connected to OP;

[0200] The gate of P11 is connected to OP_LATCH, and the drain is connected to ON;

[0201] The source of P12 is connected to VDD, the drain is connected to the drain of N16, and the gate is connected to ON;

[0202] The input and output end 1 of G2 is connected to SAEN5, and the input and output end 2 is connected to SAENB5.

[0203] Based on the circuit structure of the above SAR-ADC main circuit part:

[0204] RST is used as the operation start signal of the SAR-ADC main circuit unit: when RST is 1, the SAR-ADC main circuit unit is in the reset stage; when RST is 0, the SAR-ADC main circuit unit is working.

[0205] When the SAR-ADC main circuit is in the reset stage, RST is 1, G0 is turned on, INN2 is connected to VDD, and the upper plate voltage of C11~C20 is reset to VDD; except for the lower plate of C19 in C11~C20 which is directly connected to VSS, the lower plate voltages of other capacitors are reset to VDD.

[0206] When the sparseness detection circuit starts working, RST is 0, G0 is closed, INN2 is disconnected from VDD, and the upper plates of C11~C20 are disconnected from VDD.

[0207] When the sparsity detection circuit is finished:

[0208] ① See Fig.11 , if the sparsity of IN<0:63> is less than 50%, OUTN1=1, OUTP1=0, OUTN2=1, OUTP2=0, then, based on the ADC comparison binary method, for C12, C14, C16, C18, and C20, their lower plate voltage becomes 0 and the upper plate voltage decreases by VDD / 2; SA1 starts the first comparison;

[0209] SA1 The first comparison is completed, D <1> It starts to rise, C11 and C12 are switched according to the output result of the first comparison of SA1, then the voltage on the upper plates of C11 and C12 is added or subtracted by VDD / 4 accordingly, and the second comparison of SA1 is performed after the switching is completed;

[0210] SA1 The second comparison is completed, D <2> It starts to rise, C13 and C14 are switched according to the second comparison output of SA1, then the voltage of the upper plates of C13 and C14 is added or subtracted VDD / 8 accordingly, and the third comparison of SA1 is performed after the switching is completed;

[0211] SA1 The third comparison is over, D <3> It starts to rise, C15 and C16 are switched according to the third comparison output of SA1, then the voltage of the upper plate of C15 and C16 is added or subtracted VDD / 16 accordingly, and the fourth comparison of SA1 is performed after the switching is completed;

[0212] SA1 The fourth comparison is over, D <4> It starts to rise, C17 and C18 are switched according to the fourth comparison output of SA1, then the voltage of the upper plate of C17 and C18 is added or subtracted by VDD / 32 accordingly, and the fifth comparison of SA1 is performed after the switching is completed;

[0213] The fifth comparison of SA1 is completed, and the operation of the SAR-ADC main circuit part is completed, that is, the quantization of IN<0:63> is completed.

[0214] ② See Fig.12 , if the sparseness of the input signal is between 50% and 75%, OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0, then based on the ADC comparison binary method, the lower plate voltage of C11 and C12 remains unchanged, the lower plate voltage of C14, C16, C18, and C20 becomes 0, and the upper plate voltage decreases by VDD / 4; SA1 starts the first comparison;

[0215] SA1 The first comparison is completed, D <2> It starts to rise, C13 and C14 are switched according to the first comparison output result of SA1, then the upper plate voltage of C13 and C14 is added or subtracted VDD / 8 accordingly, and the second comparison of SA1 is performed after the switching is completed;

[0216] SA1 The second comparison is completed, D <3> It starts to rise, C15 and C16 are switched according to the second comparison output of SA1, then the voltage on the upper plate of C15 and C16 is added or subtracted VDD / 16 accordingly, and the third comparison of SA1 is performed after the switching is completed;

[0217] SA1 The third comparison is over, D <4> It starts to rise, C17 and C18 are switched according to the third comparison output of SA1, then the upper plate voltage of C17 and C18 is increased or decreased by VDD / 32 accordingly, and the fourth comparison of SA1 is performed after the switching is completed;

[0218] The fourth comparison of SA1 is completed, and the operation of the SAR-ADC main circuit part is completed, that is, the quantization of IN<0:63> is completed.

[0219] ③ See Fig.13 , if the sparseness of the input signal is greater than 75%, OUTN1=0, OUTP1=1, OUTN2=0, OUTP2=1, then based on the ADC comparison binary method, the lower plate voltages of C11, C12, C13, and C14 remain unchanged, the lower plate voltages of C16, C18, and C20 become 0, and the upper plate voltage decreases by VDD / 8; SA1 starts the first comparison;

[0220] SA1 The first comparison is completed, D <3> It starts to rise, C15 and C16 are switched according to the first comparison output of SA1, then the upper plate voltage of C15 and C16 is added or subtracted VDD / 16 accordingly, and the second comparison of SA1 is performed after the switching is completed;

[0221] SA1 The second comparison is completed, D <4> It starts to rise, C17 and C18 are switched according to the second comparison output of SA1, then the voltage of the upper plates of C17 and C18 is added or subtracted by VDD / 32 accordingly, and the third comparison of SA1 is performed after the switching is completed;

[0222] The third comparison of SA1 is completed, and the operation of the SAR-ADC main circuit is completed, that is, the quantization of IN<0:63> is completed.

[0223] In summary, the input sparsity adaptive ADC circuit based on the above circuit design can adaptively reduce the comparison cycle and shorten the quantization time according to the detected array input sparsity, thereby reducing power consumption and improving quantization efficiency without changing the accuracy.

[0224] Example 2

[0225] This embodiment 2 discloses an input sparsity adaptive ADC module, which adopts the layout of the input sparsity adaptive ADC circuit disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0226] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0227] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.< / m> < / m>

Claims

1. An input sparsity adaptive ADC circuit, characterized in that: include: A sparsity detection circuit unit, which is used to perform sparsity detection on the array input IN<0:63> according to the enable signal SAEN, the control signal CAP_RST, and the reference signals VREF1-VREF2, and generate control signals OUTN1-OUTN2 and control signals OUTP1-OUTP2; The sparseness detection circuit includes: capacitor array CIN0~CIN 63 、Switch array S0~S 63 , 2 comparators SA 0,1 ~SA 0,2 ; CIN m The upper plate is connected to the m+1th signal IN in IN<0:63> <m> ；m∈[0,63]；< / m> S m It is a single-pole double-throw switch; S m The control end is connected to CAP_RST, and the fixed end is connected to CIN m The lower plate of the switch terminal 1 forms a signal INN1, and the switch terminal 2 is connected to VSS; SA 0,1 The positive input terminal is connected to VREF1, the negative input terminal is connected to INN1, the control terminal is connected to SAEN, the output terminal 1 is used to output OUTN1, and the output terminal 2 is used to output OUTP1; SA 0,2 The positive input terminal is connected to VREF2, the negative input terminal is connected to INN1, the control terminal is connected to SAEN, the output terminal 1 is used to output OUTN2, and the output terminal 2 is used to output OUTP2; a sparsity control circuit part, which is used to process OUTN1~OUTN2 in combination with the timing signal CLK and the reset signal RST to generate an enable signal SAEN5, an enable signal SAENB5, and a reset signal RST5; A timing generation circuit portion, which is used to process OUTP1-OUTP2 in combination with RST5, RST, and SAEN5 to generate SAEN, a signal sequence DB<1:2>, and a signal sequence D<3:4>; and SAR-ADC main circuit part, which is used to process DB<1:2>, D<3:4> in combination with array voltage VCAL, SAEN5, SAENB5, OUTN1~OUTN2, OUTP1~OUTP2 to generate ADC output OUT1~OUT2; Among them, if the sparsity of IN<0:63> is less than 50%, OUTN1=1, OUTP1=0, OUTN2=1, OUTP2=0, and the SAR-ADC main circuit generates OUT1~OUT2 after 5 comparison cycles; If the sparsity of IN<0:63> is between 50% and 75%, OUTN1=0, OUTP1=1, OUTN2=1, OUTP2=0, and the SAR-ADC main circuit generates OUT1~OUT2 after 4 comparison cycles; If the sparsity of IN<0:63> is greater than 75%, OUTN1=0, OUTP1=1, OUTN2=0, OUTP2=1, and the SAR-ADC main circuit generates OUT1~OUT2 after 3 comparison cycles.

2. The input sparsity adaptive ADC circuit according to claim 1, characterized in that: SA 0,1 Includes: 12 PMOS tubes PM1~PM12, 8 NMOS tubes NM1~NM8, 1 transmission gate GM1, 1 inverter INVM1; The gate of NM1 is connected to SAEN, and the source is connected to VSS; The gate of NM2 is connected to SAEN, and the source is connected to VSS; The drain of NM3 acts as the SA 0,1 The output terminal 1, the source is connected to VSS; The drain of NM4 acts as the SA 0,1 The output terminal 2, the source is connected to VSS; The gate of NM5 is connected to the drain of NM1; The gate of NM6 is connected to the drain of NM2; The drain of NM7 is connected to the source of NM5, the source is connected to VSS, and the gate is connected to the drain of NM6; The drain of NM8 is connected to the source of NM6, the source is connected to VSS, and the gate is connected to the drain of NM5; The gate of PM1 is connected to VSS; The gate of PM2 is connected to VREF1, and the source is connected to the drain of PM1; The gate of PM3 is connected to INN1, and the source is connected to the drain of PM1; The gate of PM4 is connected to SAEN, the source is connected to VDD, and the drain is connected to the source of PM1; The gate of PM5 is connected to VSS, the drain is connected to the drain of NM1, the gate of PM9, the gate of NM5, and the source is connected to the drain of PM2; The gate of PM6 is connected to VSS, the drain is connected to the drain of NM2, the gate of PM10, the gate of NM6, and the source is connected to the drain of PM3; The gate of PM7 is connected to the gate of NM3, the source is connected to VDD, and the drain is connected to the drain of NM3; The gate of PM8 is connected to the gate of NM4, the source is connected to VDD, and the drain is connected to the drain of NM4; The gate of PM9 is connected to the gate of NM5, the source is connected to VDD, and the drain is connected to the gate of PM7; The gate of PM10 is connected to the gate of NM6, the source is connected to VDD, and the drain is connected to the gate of PM8; The gate of PM11 is connected to the gate of NM7, the source is connected to VDD, and the drain is connected to the gate of PM7; The gate of PM12 is connected to the gate of NM8, the source is connected to VDD, and the drain is connected to the gate of PM8; The input terminal of INVM1 is connected to SAEN; The control terminal 1 of GM1 is connected to the drain of PM2, the control terminal 2 is connected to the drain of PM3, the input / output terminal 1 is connected to SAEN, and the input / output terminal 2 is connected to the output terminal of INVM1.

3. The input sparsity adaptive ADC circuit according to claim 1, characterized in that: SA 0,2 Includes: 12 PMOS tubes PN1~PN12, 8 NMOS tubes NN1~NN8, 1 transmission gate GN1, and 1 inverter INVN1; The gate of NN1 is connected to SAEN, and the source is connected to VSS; The gate of NN2 is connected to SAEN, and the source is connected to VSS; The drain of NN3 acts as SA 0,2 The output terminal 1, the source is connected to VSS; The drain of NN4 acts as SA 0,2 The output terminal 2, the source is connected to VSS; The gate of NN5 is connected to the drain of NN1; The gate of NN6 is connected to the drain of NN2; The drain of NN7 is connected to the source of NN5, the source is connected to VSS, and the gate is connected to the drain of NN6; The drain of NN8 is connected to the source of NN6, the source is connected to the VSS gate, and the gate is connected to the drain of NN5; The gate of PN1 is connected to VSS; The gate of PN2 is connected to VREF2, and the source is connected to the drain of PN1; The gate of PN3 is connected to INN1, and the source is connected to the drain of PN1; The gate of PN4 is connected to SAEN, the source is connected to VDD, and the drain is connected to the source of PN1; The gate of PN5 is connected to VSS, the drain is connected to the drain of NN1, the gate of PN9, the gate of NN5, and the source is connected to the drain of PN2; The gate of PN6 is connected to VSS, the drain is connected to the drain of NN2, the gate of PN10, the gate of NN6, and the source is connected to the drain of PN3; The gate of PN7 is connected to the gate of NN3, the source is connected to VDD, and the drain is connected to the drain of NN3; The gate of PN8 is connected to the gate of NN4, the source is connected to VDD, and the drain is connected to the drain of NN4; The gate of PN9 is connected to the gate of NN5, the source is connected to VDD, and the drain is connected to the gate of PN7; The gate of PN10 is connected to the gate of NN6, the source is connected to VDD, and the drain is connected to the gate of PN8; The gate of PN11 is connected to the gate of NN7, the source is connected to VDD, and the drain is connected to the gate of PN7; The gate of PN12 is connected to the gate of NN8, the source is connected to VDD, and the drain is connected to the gate of PN8; The input terminal of INVN1 is connected to SAEN; The control terminal 1 of GN1 is connected to the drain of PN2, the control terminal 2 is connected to the drain of PN3, the input / output terminal 1 is connected to SAEN, and the input / output terminal 2 is connected to the output terminal of INVN1.

4. The input sparsity adaptive ADC circuit according to claim 1, characterized in that: The sparsity control circuit unit includes: 6 D flip-flops D0-D5, 3 AND gates AND1-AND3; Input terminal 1 of AND1 is connected to OUTN1, output terminal 2 is connected to the Q output terminal of D1, and the output terminal is electrically connected to the D input terminal of D2; Input terminal 1 of AND2 is connected to OUTN2, output terminal 2 is connected to the Q output terminal of D2, and the output terminal is electrically connected to the D input terminal of D3; The Clk terminal of D0 is connected to CLK, the inverted Q output terminal is used to output SAENB5 and is connected to the D input terminal, and the Q output terminal is used to output SAEN5; The Clk end of D1~D5 is connected to SAEN5, and the reset end is connected to RST; The D input of D1 is connected to VSS; The Q output terminal of D3 is connected to the D input terminal of D4; the Q output terminal of D4 is connected to the D input terminal of D5; the Q output terminal of D5 is used to output RST5; Input terminal 1 of AND3 is connected to RST, input terminal 2 is connected to RST5, and the output terminal is connected to the reset terminal of D0.

5. The input sparsity adaptive ADC circuit according to claim 1, characterized in that: The timing generation circuit section includes: 5 D flip-flops D6-D10, 2 OR gates OR1-OR2, 1 NAND gate NAND1, and 1 inverter INV1; Input terminal 1 of NAND1 is connected to RST, input terminal 2 is connected to RST5, and the output terminal is used to output SAEN; The input end of INV1 is connected to SAEN, and the output end is used to output the reset signal rst; The Clk end of D6~D10 is connected to SAEN5, and the reset end is connected to rst; The D input of D6 is connected to the Q output of D10, and the Q output is connected to the D input of D7; The Q output of D7 is connected to the input of OR1, and the inverted Q output is used to output the signal DB <1> ; The second input terminal of OR1 is connected to OUTP1, and the output terminal is used to output signal D <1> ; The D input terminal of D8 is connected to D <1> , the Q output terminal is connected to the input terminal 1 of OR2, and the inverted Q output terminal is used to output the signal DB <2> ; The second input terminal of OR2 is connected to OUTP2, and the output terminal is used to output signal D <2> ; D9's D input terminal is connected to D <2> , Q output terminal is used to output signal D <3> ; The D input terminal of D10 is connected to D <3> , Q output terminal is used to output signal D <4> ; Among them, DB <1> , DB <2> Composition DB<1:2>; D <3> , D <4> Composition D<3:4>.

6. The input sparsity adaptive ADC circuit according to claim 1, characterized in that: The SAR-ADC main circuit includes: 1 comparator SA1, 8 D flip-flops D11-D18, 10 capacitors C11-C20, 2 XOR gates XOR1-XOR2, 1 NAND gate NAND0, 1 inverter NAND0, 7 OR gates OR11-OR17, 2 NOR gates NOR11-NOR12, and 1 transmission gate G0; The upper boards of C11~C20 are connected together and form signal INN2; The positive input terminal of SA1 is connected to VCAL, the negative input terminal is connected to INN2 and the control terminal 1 of G0, the output terminal 1 is used to output OUT1, and the output terminal 2 is used to output OUT2; The lower board of C11 is connected to the output end of OR11; the lower board of C12 is connected to the output end of OR12; The lower board of C13 is connected to the output end of OR13; the lower board of C14 is connected to the output end of OR14; the lower board of C15 is connected to the reverse Q output end of D15; the lower board of C16 is connected to the output end of OR15; the lower board of C17 is connected to the reverse Q output end of D17; the lower board of C18 is connected to the output end of OR16; the lower board of C19 is connected to VSS; the lower board of C20 is connected to the output end of OR17; Input terminal 1 of OR11 is connected to OUTP1, input terminal 2 is connected to enable signal EN, and input terminal 3 is connected to the inverted Q output terminal of D11; Input 1 of OR12 is connected to OUTP1, input 2 is connected to EN, and input 3 is connected to the Q output of D12; Input 1 of OR13 is connected to OUTP2, input 2 is connected to EN, and input 3 is connected to the inverted Q output of D13; Input 1 of OR14 is connected to OUTP2, input 2 is connected to EN, and input 3 is connected to the Q output of D14; Input 1 of OR15 is connected to the Q output of D16, and input 2 is connected to EN; Input 1 of OR16 is connected to the Q output of D18, and input 2 is connected to EN; Input 1 of OR17 is connected to VSS, and input 2 is connected to EN; The reset terminal of D11~D18 is connected to RST; The input end of D11 is connected to OUT2, and the Clk end is connected to the output end of NOR11; The input end of D12 is connected to OUT1, and the Clk end is connected to the output end of NOR11; The input end of D13 is connected to OUT2, and the Clk end is connected to the output end of NOR12; The input end of D14 is connected to OUT1, and the Clk end is connected to the output end of NOR12; The input end of D15 is connected to OUT2, and the Clk end is connected to D <3> ; The input end of D16 is connected to OUT1, and the Clk end is connected to D <3> ; The input end of D17 is connected to OUT2, and the Clk end is connected to D <4> ; The input end of D18 is connected to OUT1, and the Clk end is connected to D <4> ; NOR11 input terminal one connects DB <1> , input terminal 2 is connected to OUTP1; NOR12 input terminal one connects DB <2> , input terminal 2 is connected to OUTP2; The input end of INV0 is connected to RST, and the output end is connected to the input and output end 1 of G0; The input and output terminal 2 of G0 is connected to RST, and the control terminal 2 is connected to VDD; Input 1 of XOR1 is connected to OUTP1, and input 2 is connected to OUTN1; Input 1 of XOR2 is connected to OUTP2, and input 2 is connected to OUTN2; Input terminal 1 of NAND0 is connected to the output terminal of XOR1, input terminal 2 is connected to the output terminal of XOR2, and the output terminal is used to output EN.

7. The input sparsity adaptive ADC circuit according to claim 6, characterized in that: The capacitance ratio of C11~C20 is 8:8:4:4:2:2:1:1:1:

1.

8. The input sparsity adaptive ADC circuit according to claim 6, characterized in that: SA1 includes: 12 PMOS tubes P1~P12, 16 NNOS tubes N1~N16, and 1 transmission gate G1; The gate of N1 is connected to VDD, the source is connected to the drain of N6, and the drain is connected to the source of N2 and the source of N3; The source of N2 is connected to the drain of N1 and the source of N3, the gate serves as the negative input terminal of SA1, and the drain is connected to the source of N4 and the control terminal 1 of G2; The gate of N3 serves as the positive input terminal of SA1, and the drain is connected to the control terminal 2 of G2 and the source of N5; The gate of N4 is connected to the gate of N5, the source is connected to the drain of N2, and the drain serves as the A node; The drain of N5 serves as the B node; The gate of N6 is connected to SAEN5, and the source is connected to VSS; The source of N7 is connected to VSS, the drain is connected to the control signal ON_LATCH, and the gate is connected to the gate of P6; The gate of N8 is connected to the gate of P1, the drain is connected to the control signal OP_LATCH, and the source is connected to VSS; The source of N9 is connected to VSS, the gate is connected to A, and the drain is connected to ON_LATCH; The source of N10 is connected to VSS, the drain is connected to OP_LATCH, and the gate is connected to B; The source of N11 is connected to VSS, the drain is connected to ON_LATCH, and the gate is connected to the control signal ON; The gate of N12 is connected to ON_LATCH, the drain is connected to the control signal OP, and the source is connected to VSS; The source of N13 is connected to VSS, the gate is connected to OP, and the drain is used to output OUT2; The source of N14 is connected to VSS, the gate is connected to OP, and the drain is connected to OP_LATCH; The source of N15 is connected to VSS, the drain is connected to ON, and the gate is connected to OP_LATCH; The source of N16 is connected to VSS, the gate is connected to ON, and the drain is used to output OUT1; The source of P1 is connected to VDD, the gate is connected to ON_LATCH, and the drain is connected to the source of P3; The gate of P2 is connected to A, the drain is connected to ON_LATCH, and the source is connected to the drain of P6; The gate of P3 is connected to B, and the drain is connected to OP_LATCH; The source of P4 is connected to VDD, the drain is connected to A, and the gate is connected to SAENB5; The source of P5 is connected to VDD, the gate is connected to SAENB5, and the drain is connected to B; The source of P6 is connected to VDD, and the gate is connected to OP_LATCH; The source of P7 is connected to VDD, the gate is connected to ON, and the drain is connected to the source of P8; The gate of P8 is connected to ON_LATCH, and the drain is connected to OP; The source of P9 is connected to VDD, the gate is connected to OP, and the drain is connected to the drain of N13; The source of P10 is connected to VDD, the drain is connected to the source of P11, and the gate is connected to OP; The gate of P11 is connected to OP_LATCH, and the drain is connected to ON; The source of P12 is connected to VDD, the drain is connected to the drain of N16, and the gate is connected to ON; The input and output end 1 of G2 is connected to SAEN5, and the input and output end 2 is connected to SAENB5.

9. An input sparsity adaptive ADC module, characterized in that: It adopts the layout of the input sparsity adaptive ADC circuit as described in any one of claims 1-8.

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