IO scheduling method and device, medium and product

Abstract

The invention provides an IO scheduling method and device, a medium and a product, relates to the technical field of communication, and aims to solve the problem that a universal IO thread scheduling method is inflexible and inaccurate. The IO scheduling method comprises the steps of obtaining task information of a to-be-processed task and thread information of a to-be-scheduled IO thread; and determining a scheduling strategy of the IO thread to be scheduled according to the task information and the thread information.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an IO scheduling method, device, medium and product. Background Art

[0002] With the development of the fifth generation mobile communication technology (5G), users are increasingly demanding real-time information. 5G base stations interact with user devices through wireless communication interfaces. When the physical layer in the wireless communication interface processes data, the physical layer schedules the input output (IO) thread and hands it over to the processor to process the pending tasks in the IO thread.

[0003] A common IO scheduling method is to enable N IO threads, each of which has multiple pending tasks. When the pending tasks in an IO thread are empty, the IO thread obtains the pending tasks from the public IO thread and hands them over to the processor for processing.

[0004] However, the general IO scheduling method cannot flexibly and accurately schedule the IO threads according to the task information of the task to be processed and the thread information of the IO threads. Therefore, the general IO scheduling method is inflexible and inaccurate. Summary of the invention

[0005] The embodiments of the present disclosure provide an IO scheduling method, device, medium and product, aiming to solve the problem that the general IO thread scheduling method is inflexible and inaccurate.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, an IO scheduling method is provided, including: obtaining task information of a task to be processed and thread information of an IO thread to be scheduled; and determining a scheduling strategy of the IO thread to be scheduled according to the task information and the thread information.

[0008] Optionally, the scheduling policy includes the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled; determining the scheduling policy of the IO thread to be scheduled based on the task information and the thread information includes: determining the scheduling priority of the IO thread to be scheduled based on the task information and the thread information; determining the processor that processes the IO thread to be scheduled based on the task information; determining the scheduling policy of the IO thread to be scheduled based on the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled.

[0009] Optionally, the scheduling priority includes: a first scheduling priority and a second scheduling priority; determining the scheduling priority of the IO thread to be scheduled according to the task information and the thread information, including: determining the first scheduling priority of the IO thread to be scheduled according to the task information; the task information includes: time slot data and task direction; the time slot data is used to indicate the time for obtaining the task to be processed; the task direction includes: a downlink direction for processing downlink (Downlink, DL) tasks and an uplink direction for processing uplink (Uplink, UL) tasks; the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction is higher than the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction; determining the second scheduling priority of the IO thread to be scheduled according to the thread information; the thread information includes historical data of the IO thread to be scheduled; the historical data includes: the frequency of the IO thread to be scheduled processing the task to be processed; the second scheduling priority of the IO thread to be scheduled is proportional to the frequency; determining the scheduling priority of the IO thread to be scheduled according to the first scheduling priority and the second scheduling priority.

[0010] Optionally, the task information includes: task type; task types include: bit-level processing tasks, logic control tasks and symbol-level processing tasks; processors include: Field-Programmable Gate Array (FPGA) chip and Central Processing Unit (CPU); according to the task information, determining the processor for processing the IO thread to be scheduled, including: when the task type is a bit-level processing task, determining that the processor for processing the IO thread to be scheduled is the FPGA chip; when the task type is a logic control task or a symbol-level processing task, determining that the processor for processing the IO thread to be scheduled is the CPU.

[0011] Optionally, determining the scheduling priority of the IO thread to be scheduled according to the first scheduling priority and the second scheduling priority includes: obtaining a first weight parameter of the first scheduling priority and a second weight parameter of the second scheduling priority; and determining the scheduling priority of the IO thread to be scheduled as the sum of the product of the first scheduling priority and the first weight parameter and the product of the first scheduling priority and the first weight parameter.

[0012] Optionally, the IO scheduling method further includes: acquiring load information of the processor, and determining the number of IO threads to be scheduled to be processed by the processor according to the load information.

[0013] Optionally, the IO scheduling method also includes: obtaining historical physical channel quality data of a physical channel transmitting a task to be processed; predicting the physical channel quality based on the historical physical channel quality data; and executing a scheduling strategy when the physical channel quality is greater than a threshold.

[0014] Optionally, the IO scheduling method further includes: generating an identity identifier of the task to be processed according to the task information; and marking the task to be processed according to the identity identifier when the scheduling strategy is executed.

[0015] In a second aspect, an IO scheduling device is provided, which includes: a communication unit and a processing unit; the communication unit is used to obtain task information of a task to be processed and thread information of an IO thread to be scheduled; the processing unit is used to determine a scheduling strategy for the IO thread to be scheduled based on the task information and thread information.

[0016] Optionally, the scheduling strategy includes the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled; the processing unit is specifically used to: determine the scheduling priority of the IO thread to be scheduled according to the task information and the thread information; determine the processor that processes the IO thread to be scheduled according to the task information; determine the scheduling strategy of the IO thread to be scheduled according to the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled.

[0017] Optionally, the scheduling priority includes: a first scheduling priority and a second scheduling priority; the processing unit is specifically used to: determine the first scheduling priority of the IO thread to be scheduled according to the task information; the task information includes: time slot data and task direction; the time slot data is used to indicate the time for obtaining the task to be processed; the task direction includes: a downlink direction for processing downlink DL tasks and an uplink direction for processing uplink UL tasks; the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction is higher than the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction; determine the second scheduling priority of the IO thread to be scheduled according to the thread information; the thread information includes historical data of the IO thread to be scheduled; the historical data includes: the frequency of the IO thread to be scheduled processing the task to be processed; the second scheduling priority of the IO thread to be scheduled is proportional to the frequency; determine the scheduling priority of the IO thread to be scheduled according to the first scheduling priority and the second scheduling priority.

[0018] Optionally, the task information includes: task type; task types include: bit-level processing tasks, logic control tasks and symbol-level processing tasks; processors include: field programmable gate array FPGA chips and central processing units CPU; a processing unit is specifically used to: when the task type is a bit-level processing task, determine that the processor for processing the IO thread to be scheduled is the FPGA chip; when the task type is a logic control task or a symbol-level processing task, determine that the processor for processing the IO thread to be scheduled is the CPU.

[0019] Optionally, the processing unit is specifically used to: obtain a first weight parameter of a first scheduling priority and a second weight parameter of a second scheduling priority; determine the product of the first scheduling priority and the first weight parameter and the sum of the product of the first scheduling priority and the first weight parameter as the scheduling priority of the IO thread to be scheduled.

[0020] Optionally, the processing unit is further used to obtain load information of the processor, and determine the number of IO threads to be scheduled to be processed by the processor according to the load information.

[0021] Optionally, the communication unit is also used to obtain historical physical channel quality data of the physical channel for transmitting the task to be processed; the processing unit is also used to predict the physical channel quality based on the historical physical channel quality data; the processing unit is also used to execute the scheduling strategy when the physical channel quality is greater than a threshold.

[0022] Optionally, the processing unit is further used to generate an identity identifier of the task to be processed according to the task information; the processing unit is further used to mark the task to be processed according to the identity identifier when the scheduling strategy is executed.

[0023] In a third aspect, an IO scheduling device is provided, comprising a memory and a processor; the memory is used to store computer execution instructions, and the processor is connected to the memory through a bus; when the IO scheduling device is running, the processor executes the computer execution instructions stored in the memory, so that the IO scheduling device executes the IO scheduling method of the first aspect.

[0024] The IO scheduling device can be an electronic device, or a part of an electronic device, such as a chip system in an electronic device. The chip system is used to support the electronic device to implement the functions involved in the first aspect and any possible implementation thereof, for example, to obtain and determine the data and / or information involved in the above-mentioned IO scheduling method. The chip system includes a chip and may also include other discrete devices or circuit structures.

[0025] In a fourth aspect, a computer-readable storage medium is provided, the computer-readable storage medium comprising computer execution instructions, and when the computer execution instructions are executed on a computer, the computer executes the IO scheduling method described in the first aspect.

[0026] In a fifth aspect, a computer program product is also provided, which includes a computer program or instructions. When the computer instructions are executed on an IO scheduling device, the IO scheduling device executes the IO scheduling method as described in the first aspect above.

[0027] It should be noted that the above computer instructions may be stored in whole or in part on a computer-readable storage medium, wherein the computer-readable storage medium may be packaged together with the processor of the IO scheduling device, or may be packaged separately from the processor of the IO scheduling device, which is not limited in the embodiments of the present application.

[0028] The description of the second, third, fourth and fifth aspects of the present application can refer to the detailed description of the first aspect.

[0029] In the embodiments of the present application, the name of the IO scheduling device does not limit the device or functional module itself. In actual implementation, these devices or functional modules may appear with other names. For example, the receiving unit may also be called a receiving module, a receiver, etc. As long as the functions of each device or functional module are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalent technologies.

[0030] The technical solution provided by this application brings at least the following beneficial effects:

[0031] Based on any of the above aspects, an embodiment of the present application provides an IO scheduling method, which first obtains task information of the task to be processed and thread information of the IO thread to be scheduled, and then determines the scheduling strategy of the IO thread to be scheduled based on the task information and thread information.

[0032] From the above, it can be seen that when formulating the scheduling strategy of the IO thread to be scheduled, the present application fully considers the task information of the task to be processed and the thread information of the IO thread to be scheduled. In this way, the scheduling strategy of the IO thread to be scheduled can be accurately and flexibly determined based on the task information of the task to be processed and the thread information of the thread to be scheduled.

[0033] The beneficial effects of the first, second, third, fourth and fifth aspects of the present application can all be referred to the analysis of the above beneficial effects, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a 5G wireless base station system provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of a 5G base station provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the structure of a wireless interface provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the structure of an IO scheduling system provided in an embodiment of the present application;

[0038] Figure 5A schematic diagram of a hardware structure of a communication device provided in an embodiment of the present application;

[0039] Figure 6 A flowchart of an IO scheduling method provided in an embodiment of the present application;

[0040] Figure 7 A flowchart of another IO scheduling method provided in an embodiment of the present application;

[0041] Figure 8 A flowchart of another IO scheduling method provided in an embodiment of the present application;

[0042] Fig. 9 A flowchart of another IO scheduling method provided in an embodiment of the present application;

[0043] Fig.10 A schematic diagram of the cooperation between a CPU and an FPGA chip provided in an embodiment of the present application;

[0044] Fig.11 A schematic diagram of the structure of a QDMA provided in an embodiment of the present application;

[0045] Fig.12 A flowchart of another IO scheduling method provided in an embodiment of the present application;

[0046] Fig.13 A flowchart of another IO scheduling method provided in an embodiment of the present application;

[0047] Fig.14 A flowchart of another IO scheduling method provided in an embodiment of the present application;

[0048] Fig.15 A schematic diagram of obtaining a task to be processed provided in an embodiment of the present application;

[0049] Fig.16 A schematic diagram of the structure of an IO scheduling device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0052] In order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and order of execution.

[0053] Before introducing the IO scheduling method provided by the present application in detail, a brief introduction to the application scenarios and implementation environment involved in the present application is first given.

[0054] First, a brief introduction to the application scenarios involved in this application is given.

[0055] As described in the background technology, with the development of communication technology, 5G communication technology is widely used. User equipment interacts with a 5G base station in a 5G wireless base station system through a wireless interface.

[0056] Among them, 5G wireless base station systems such as Figure 1 shown.

[0057] 5G wireless base stations include: 5G Core Network (5G Core Network, 5GC) and Next Generation Radio Access Network (Next Generation Radio Access Network, NG-RAN).

[0058] 5GC consists of Access and Mobility Management Function (AMF) and User Plane Function (UPF) (5GC can also be represented by AMF / UPF).

[0059] NG-RAN includes: next generation base station (next Generation NodeB, gNB) (also known as 5G base station) and next generation evolved base station (next generation evolved NodeB, ng-eNB).

[0060] For ease of understanding, the figure takes two AMF / UPFs, two 5G base stations and two ng-eNBs as examples. The AMF / UPF is communicated with the gNB and ng-eNB respectively, the two gNBs are communicated, the two ng-eNBs are communicated, and the gNB is communicated with the ng-eNB.

[0061] 5GC is responsible for handling user authentication, authorization, mobility management, session management and other functions.

[0062] AMF is responsible for functions such as access control, mobility management, and registration management of user equipment.

[0063] UPF is responsible for forwarding and processing user data to achieve high-speed data transmission.

[0064] NG-RAN is used to connect user equipment to the core network to achieve wireless communication functions.

[0065] ng-eNB is used to connect with the 5G core network and provide users with a certain degree of 5G services.

[0066] 5G base stations are responsible for generating downlink wireless signals and receiving uplink wireless signals to enable wireless access for user terminals.

[0067] The structure of a 5G base station is as follows Figure 2 shown.

[0068] A 5G base station includes: a cluster of Pico Remote Radio Units (PRRU) (also called Radio Units (RU)) connected in sequence, an Ethernet Unit (EU), a Distributed Unit (DU) and a Centralized Unit (CU), as well as an Operation, Administration and Maintenance (Operation, Administration and Maintenance) module.

[0069] Among them, OAM is communicated with the PRRU cluster, EU, DU, and CU respectively.

[0070] The PRRU is responsible for the low-physical layer (Low-PHY) and radio frequency functions.

[0071] DU is responsible for the low-level protocol stack and high-level physical layer (High-PHY) functions.

[0072] CU is responsible for the high-level protocol stack and the interface with the core network.

[0073] As an external module of the base station, OAM has management interfaces with all modules of the base station to implement the management function of the entire base station.

[0074] In a 5G base station, a wireless interface is usually used for communication between PRRU and EU, between DU and EU, and between CU and DU. A wireless interface is also used for communication between a 5G base station and a user equipment.

[0075] The wireless interface includes: physical layer, data link layer and application layer.

[0076] Among them, the schematic diagram of the new radio (NR) wireless interface structure around the physical layer is as follows Figure 3 shown.

[0077] The physical layer is connected to the Medium Access Control (MAC) sublayer of the data link layer and the Radio Resource Control (RRC) sublayer of the application layer respectively.

[0078] The circles between the layers in the figure indicate service access points (SAPs). SAP is used to define how upper-layer services access services provided by lower layers.

[0079] The physical layer provides the MAC sublayer with transport channels, which are used to transmit information through the interface.

[0080] MAC provides logical channels for the RLC sublayer. Logical channels are used to determine the type of information to be transmitted.

[0081] The physical layer performs multiple tasks (including: forward error correction (FEC) encoding / decoding transport channels, hybrid automatic repeat reQues (HARQ) soft combining, rate matching of coded transport channels and physical channels, mapping of coded transport channels to physical channels, power control of physical channels, modulation and demodulation of physical channels, frequency and time synchronization, wireless signal measurement and indication to higher layers, multiple-input multiple-output (MIMO) antenna processing, and radio frequency processing) to provide data transmission services.

[0082] When the physical layer transmits data, it schedules the IO thread and lets the processor handle the pending tasks in the IO thread.

[0083] However, a common IO scheduling method is to start multiple IO processing threads, each IO processing thread corresponds to an IO request queue, and for each IO processing thread, when the IO request queue corresponding to the IO processing thread is empty, obtain the IO request set from the public IO request queue and process it, and after processing the IO request set, determine whether the IO request queue is empty, if the IO request queue is not empty, process the IO requests in the IO request queue; if the IO request queue is empty, execute the method of obtaining the IO request set from the public IO request queue and processing it.

[0084] The general scheduling method allocates computing resources to IO threads according to whether there are threads to be processed in the IO request queue, and processes the IO threads through shared computing resources. However, in actual applications, different IO threads have different task urgency and execution order requirements, and different IO threads have different task types and processing methods. Therefore, the general IO scheduling method is inflexible and inaccurate.

[0085] In response to the above problems, an embodiment of the present application provides an IO scheduling method. First, task information of the task to be processed and thread information of the IO thread to be scheduled are obtained, and then the scheduling strategy of the IO thread to be scheduled is determined based on the task information and thread information.

[0086] From the above, it can be seen that when formulating the scheduling strategy of the IO thread to be scheduled, the present application fully considers the task information of the task to be processed and the thread information of the IO thread to be scheduled. In this way, the scheduling strategy of the IO thread to be scheduled can be accurately and flexibly determined based on the task information of the task to be processed and the thread information of the thread to be scheduled.

[0087] The implementation environment of the above IO thread method may be the IO thread scheduling system provided in the embodiment of the present application.

[0088] Figure 4 FIG. 1 shows a schematic diagram of the structure of the IO scheduling system provided in an embodiment of the present application. Figure 4 As shown, the IO scheduling system includes: an IO scheduling device 401, a communication device 402, a thread storage device (also called a static thread pool) 403, and a task processing device (also called a processor of threads to be scheduled) 404.

[0089] The IO scheduling device 401 is in communication connection with the communication device 402, the thread storage device 403, and the task processing device 404. The communication device 402 is in communication connection with the thread storage device 403 and the task processing device 404. The thread storage device 403 is in communication connection with the task processing device 404.

[0090] In practical applications, the IO scheduling device 401 can be connected to any number of communication devices 402. For ease of understanding, Figure 4 An example of an IO scheduling device 401 connected to a communication device 402 is used for description.

[0091] The IO scheduling device 401 (also called a thread scheduler) is responsible for allocating and managing processor time slices and controlling the execution order of multi-threaded programs. The IO scheduling device 401 allocates pending tasks to processors for execution according to a scheduling policy.

[0092] Optionally, the IO scheduling device can also create threads, destroy threads, and monitor threads.

[0093] When multiple IO threads are running simultaneously, the IO scheduling device 401 switches between these threads so that each thread has an opportunity to use processor resources to achieve concurrent execution of tasks to be processed.

[0094] The IO scheduling device 401 may be a cloud server or a controller of a base station.

[0095] The IO scheduling device 401 has a ready state (the IO thread has been allocated hardware resources and is just waiting for system scheduling to run), a running state (the IO thread is executing tasks and occupies resources of the task processing device 404), and a blocked state (the IO thread is suspended because it cannot continue to execute tasks for some reason).

[0096] The communication device 402 is used to obtain data for determining the IO scheduling strategy (eg, tasks to be processed and task information of the tasks to be processed).

[0097] The thread storage device 403 is used to store and manage IO threads and pending tasks.

[0098] The thread storage device 403 is a static thread pool, which uses pooling technology to manage IO threads, including: reusing IO threads (i.e., reusing already created IO threads) and decoupling the creation of IO threads from the execution of pending tasks. This can reduce resource consumption caused by frequent creation and destruction of IO threads.

[0099] The task processing device 404 includes: an FPGA chip and a CPU. The task processing device is used to process pending tasks in the IO thread.

[0100] An FPGA chip is a special chip that can be configured into a customized circuit (i.e., various circuit functions can be implemented through configuration) to perform specific computing tasks according to specific computing needs. Unlike instruction-based processors (e.g., CPUs), FPGA chips do not require software programming, but instead perform computing tasks by directly configuring hardware circuits. FPGA chips do not rely on general architectures and software, so FPGAs can achieve higher performance and efficiency on specific computing tasks.

[0101] All CPU calculations, command acceptance / storage, and data processing are performed by the most important part of the CPU, the CPU core (also called the CPU kernel). The CPU core has a fixed logical structure, including: first-level cache, second-level cache, execution unit, instruction-level unit, and bus interface.

[0102] Optionally, the IO scheduling device 401 and the communication device 402 may be two devices independently set up, or may be integrated into the same device. When the IO scheduling device 401 and the communication device 402 are integrated into the same device, the communication device 402 may be a communication module of the IO scheduling device 401 .

[0103] It is easy to understand that when the IO scheduling device 401 and the communication device 402 are integrated into the same device, the communication mode between the IO scheduling device 401 and the communication device 402 is the communication between the internal modules of the device. In this case, the communication process between the two is the same as the communication process between the IO scheduling device 401 and the communication device 402 when they are independent of each other.

[0104] For ease of understanding, this application is described by taking the example that the IO scheduling device 401 and the communication device 402 are independent of each other.

[0105] Optionally, the IO scheduling device 401 and the thread storage device 403 may be two independent devices, or may be integrated in the same device. When the IO scheduling device 401 and the thread storage device 403 are integrated in the same device, the IO scheduling device 401 may be a processing unit in the thread storage device.

[0106] It is easy to understand that when the IO scheduling device 401 and the thread storage device 403 are integrated into the same device, the communication mode between the IO scheduling device 401 and the thread storage device 403 is the communication between the internal modules of the device. In this case, the communication process between the two is the same as the communication process between the IO scheduling device 401 and the thread storage device 403 when they are independent of each other.

[0107] The thread storage device 403 includes: a task queue and an IO thread (also referred to as a working thread).

[0108] The task queue is used to store pending tasks and is usually implemented using a blocking queue.

[0109] The IO thread is used to execute pending tasks in the task queue.

[0110] Optionally, the size of the thread storage device 403 and the size of the task queue are both determined by configuration parameters.

[0111] For ease of understanding, the present application is described by taking the example that the IO scheduling device 401 and the thread storage device 403 are independent of each other.

[0112] The IO scheduling devices in the IO scheduling system include: Figure 5 The following are the components included. Figure 5 Taking the communication device shown as an example, the hardware structure of the IO scheduling device is introduced.

[0113] Figure 5 , which is a schematic diagram of a hardware structure of a communication device provided in an embodiment of the present application. The communication device includes a processor 51, a memory 52, a communication interface 53, and a bus 54. The processor 51, the memory 52, and the communication interface 53 can be connected via a bus 54.

[0114] The processor 51 is the control center of the communication device, and can be a processor or a general term for multiple processing elements. For example, the processor 51 can be a general-purpose CPU or other general-purpose processors. Among them, the general-purpose processor can be a microprocessor or any conventional processor.

[0115] As an embodiment, the processor 51 may include one or more CPUs, such as Figure 5 CPU0 and CPU1 are shown in the figure.

[0116] The memory 52 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0117] In a possible implementation, the memory 52 may exist independently of the processor 51, and the memory 52 may be connected to the processor 51 via a bus 54 for storing instructions or program codes. When the processor 51 calls and executes the instructions or program codes stored in the memory 52, the IO scheduling method provided in the following embodiments of the present application can be implemented.

[0118] In the embodiment of the present application, for the communication device, the software programs stored in the memory 52 are different, so the functions implemented by the communication device are different. The functions performed by each device will be described in conjunction with the following flowchart.

[0119] In another possible implementation, the memory 52 may also be integrated with the processor 51 .

[0120] The communication interface 53 is used for the communication device to connect with other devices through a communication network, and the communication network may be Ethernet, wireless access network, wireless local area network (WLAN), etc. The communication interface 53 may include a receiving unit for receiving data and a sending unit for sending data.

[0121] The bus 54 may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0122] It should be pointed out that Figure 5 The structure shown in the figure does not constitute a limitation on the communication device, except Figure 5 In addition to the components shown, the communication device may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0123] The IO scheduling method provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0124] The IO scheduling method provided in the embodiment of the present application is applied to Figure 4 The IO scheduling device 401 in the IO scheduling system shown in FIG. Figure 6 As shown, the IO scheduling method provided in the embodiment of the present application includes:

[0125] S601: Obtain task information of tasks to be processed and thread information of IO threads to be scheduled.

[0126] In one achievable manner, the IO scheduling device can fully consider the task information of the task to be processed and the thread information of the IO thread to be scheduled, and accurately and flexibly determine the scheduling strategy of the IO thread to be scheduled based on the task information of the task to be processed and the thread information of the thread to be scheduled. Therefore, the IO scheduling device needs to obtain the task information of the task to be processed and the thread information of the IO thread to be scheduled.

[0127] The tasks to be processed include: data transmission tasks and signal processing tasks.

[0128] Combination Figure 4 ,The IO scheduling device can obtain the pending tasks and the task information of the pending tasks from the user device, the external system, the internal system and the cloud through the communication device.

[0129] Optionally, in the actual acquisition process, combined with Figure 3 ,The physical layer can obtain the tasks to be processed through the interface through which the physical layer interacts with the MAC.

[0130] Optional, combined Figure 2 ,The base station can obtain the tasks to be processed through the antenna interface of the PRRU cluster and the external communication.

[0131] Task information includes: time slot data, task direction and task type.

[0132] The task directions include: a downlink direction for processing downlink tasks and an uplink direction for processing uplink tasks.

[0133] Task types include: bit-level processing tasks, logic control tasks, and symbol-level processing tasks.

[0134] Combination Figure 4 , the IO scheduling device can obtain the thread information of the IO thread to be scheduled from the thread storage device.

[0135] Thread information includes: historical data of the IO threads to be scheduled.

[0136] The historical data includes: the frequency of the scheduled IO thread processing the pending tasks.

[0137] IO includes: disk IO and network IO.

[0138] The data loaded into the memory by disk IO and network IO requests are first placed in the IO thread of kernel space.

[0139] IO threads include: a receiving thread (also called a read thread) and a sending thread (also called a write thread).

[0140] The IO thread is mainly responsible for receiving / sending (RX / TX) data packets, timing processing and triggering tasks, checking the processing results of the accelerator card to control traffic and exception handling procedures.

[0141] The IO thread is also responsible for cell creation, cell closure, and cell reconfiguration.

[0142] The IO thread controls the RX / TX of the remote radio unit's enhanced Common Public Radio Interface (eCPRI, RRU eCPRI) packets through the Intel Data Plane Development Kit (Intel DPDK).

[0143] Data packet reception mainly processes the Physical Uplink Shared Channel (PUSCH) and time slot timing packets (timing is 0.5ms) to drive the uplink channel processing and system timing process. When the downlink data is fully processed and the data packet is ready, the DL eCPRI data packet will be sent. The DL data is the frequency domain in-phase and quadrature (IQ) data of the downlink, which is organized by antenna, time slot, and symbol.

[0144] Optional, combined Figure 4 After the IO scheduling device obtains the pending tasks, it can upload the pending tasks to the thread storage device.

[0145] S602: Determine a scheduling strategy for the IO thread to be scheduled according to the task information and the thread information.

[0146] In one practicable manner, the IO scheduling device may determine the scheduling strategy of the IO thread to be scheduled based on the task information and the thread information. Thus, the scheduling strategy of the IO thread to be scheduled determined after fully considering the characteristics of the task information and the thread information may improve the accuracy and flexibility of the IO thread scheduling.

[0147] Optionally, the IO scheduling device may schedule the IO thread according to a scheduling algorithm.

[0148] Scheduling algorithms include: First Come First Served (FIFO) algorithm, Shortest Job First (SJF) algorithm, Priority-based Scheduling algorithm, and Round Robin algorithm.

[0149] In some embodiments, the scheduling policy includes the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled, combined with Figure 6 ,like Figure 7 As shown, in S602, the scheduling strategy of the IO thread to be scheduled is determined according to the task information and the thread information, which specifically includes:

[0150] S701. Determine the scheduling priority of the IO thread to be scheduled according to the task information and the thread information.

[0151] In one achievable manner, the IO scheduling device can determine the scheduling priority of the IO thread to be scheduled based on the task information and the thread information. In this way, when scheduling multiple IO threads to be scheduled, the IO scheduling device can comprehensively consider the thread information of the IO thread and the task information of the tasks to be processed in the IO thread to be scheduled, determine the scheduling priority of the IO thread to be scheduled, and perform computing resource scheduling of the IO thread based on the scheduling priority, so that the scheduling strategy of the IO thread to be scheduled determined by the IO scheduling device is more reasonable.

[0152] Optionally, the IO scheduling device performs scheduling and transfer according to the scheduling priority of the IO thread.

[0153] In some embodiments, the scheduling priority includes: a first scheduling priority and a second scheduling priority, combined with Figure 7 ,like Figure 8 As shown, in S701, the scheduling priority of the IO thread to be scheduled is determined according to the task information and the thread information, specifically including:

[0154] S801. Determine a first scheduling priority of an IO thread to be scheduled according to task information.

[0155] Task information includes: time slot data and task direction.

[0156] The time slot data is used to indicate the time when the tasks to be processed are obtained.

[0157] The task directions include: a downlink direction for processing downlink DL tasks and an uplink direction for processing uplink UL tasks.

[0158] The scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction is higher than the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction.

[0159] In one achievable manner, the scheduling priority includes a first scheduling priority and a second scheduling priority, wherein the first scheduling priority is related to the task information, and the IO scheduling device can determine the first scheduling priority of the IO thread to be scheduled based on the task information, so that the IO scheduling device can determine the scheduling priority of the IO thread to be scheduled based on the first scheduling priority and the second scheduling priority, further making the scheduling strategy of the IO thread to be scheduled determined by the IO scheduling device more reasonable.

[0160] Optionally, the IO scheduling device may sort the tasks to be processed according to the time slot data.

[0161] When the time slot data of multiple pending tasks are different, the IO scheduling device sorts the pending tasks in the IO threads to be scheduled according to the time slot data of the pending tasks to determine the priority of the IO threads to be scheduled. The earlier the time slot data of the pending tasks in the IO threads to be scheduled is, the higher the second priority of the IO threads to be scheduled is.

[0162] When the time slot data of multiple tasks to be processed are the same, the second priority of the IO thread to be scheduled is determined according to the task direction of the tasks to be processed. The scheduling priority of the IO thread to be scheduled with the task direction of the downlink direction is higher than that of the IO thread to be scheduled with the task direction of the uplink direction. That is, when the time slot data are the same, the DL task is processed first, and then the UL task is processed.

[0163] Optionally, the IO scheduling device transmits signals (which may be the result of processing the tasks to be processed) in a time division multiplexing (TDM) manner.

[0164] TDM uses the same physical connection in different time periods to transmit different signals, achieving the purpose of multi-channel transmission.

[0165] TDM uses time as the parameter for signal segmentation.

[0166] The IO scheduling device can divide the time for transmitting information on the physical channel into several time slices (referred to as time slots) and allocate the time slots to each signal source to ensure resource utilization.

[0167] S802: Determine the second scheduling priority of the IO thread to be scheduled according to the thread information.

[0168] The thread information includes the historical data of the IO threads to be scheduled.

[0169] The historical data includes: the frequency of the IO thread to be scheduled processing the pending tasks; and the second scheduling priority of the IO thread to be scheduled is proportional to the frequency.

[0170] In one achievable manner, the scheduling priority includes a first scheduling priority and a second scheduling priority, wherein the second scheduling priority is related to thread information, and the IO scheduling device can determine the second scheduling priority of the IO thread to be scheduled based on the thread information, so that the IO scheduling device can determine the scheduling priority of the IO thread to be scheduled based on the first scheduling priority and the second scheduling priority, further making the scheduling strategy of the IO thread to be scheduled determined by the IO scheduling device more reasonable.

[0171] Optionally, the historical data includes: the processing frequency of multiple IO threads for various types of pending tasks within a period of time.

[0172] Optionally, the higher the historical processing frequency of the pending task, the more resources the IO thread has, and the greater the impact of the processing result of the pending task on the user, so the more critical the IO thread to be scheduled where the pending task is located. Therefore, the IO scheduling device can sort the processing frequencies of the pending tasks according to multiple IO threads, and the higher the processing frequency of the IO thread, the higher the second scheduling priority.

[0173] S803: Determine the scheduling priority of the IO thread to be scheduled according to the first scheduling priority and the second scheduling priority.

[0174] In one achievable manner, the scheduling priority includes a first scheduling priority and a second scheduling priority. The IO scheduling device can determine the scheduling priority of the IO thread to be scheduled based on the first scheduling priority and the second scheduling priority, so that the scheduling strategy of the IO thread to be scheduled determined by the IO scheduling device is more reasonable.

[0175] In some embodiments, a first weight parameter of the first scheduling priority and a second weight parameter of the second scheduling priority are obtained, and the sum of the product of the first scheduling priority and the first weight parameter and the product of the first scheduling priority and the first weight parameter is determined as the scheduling priority of the IO thread to be scheduled.

[0176] Optionally, the IO scheduling device may quantify the first scheduling priority and the second scheduling priority.

[0177] Exemplarily, when there are 5 IO threads to be scheduled, the first priority and the second priority of the IO threads to be scheduled can be quantized to 2, 4, 6, 8, and 10, respectively. When the first weight parameter is 0.6 and the second weight parameter is 0.4, the 5 IO threads to be scheduled are thread A, thread B, thread C, thread D, and thread E, wherein the first scheduling priority and the second scheduling priority of thread A are 8 and 10, respectively, wherein the first scheduling priority and the second scheduling priority of thread B are 6 and 10, respectively, wherein the first scheduling priority and the second scheduling priority of thread C are 10 and 2, respectively, wherein the first scheduling priority and the second scheduling priority of thread D are 4 and 4, respectively, wherein the first scheduling priority and the second scheduling priority of thread E are 6 and 4, respectively. After calculation, the scheduling priorities of thread A, thread B, thread C, thread D, and thread E are 8.8, 7.6, 6.8, 4, and 5.2, respectively. Therefore, the scheduling priority of thread A> the scheduling priority of thread B> the scheduling priority of thread C> the scheduling priority of thread E> the scheduling priority of thread D.

[0178] S702: Determine a processor for processing the IO thread to be scheduled according to the task information.

[0179] In one achievable manner, the IO scheduling device can determine the processor for processing the IO thread to be scheduled based on the task information. In this way, the IO scheduling device can reasonably allocate the processor to the IO thread to be scheduled based on the task information, thereby improving the accuracy of IO thread scheduling and the task processing efficiency of the IO thread.

[0180] Optionally, the task information includes: task parameters.

[0181] Optionally, the IO scheduling device may determine the task type of the task to be processed according to the task parameters of the task to be processed.

[0182] Specifically, first, the IO scheduling device determines the processing requirements and processing purposes of the pending tasks according to the task parameters. Then, the IO scheduling device determines the task type of the pending tasks according to the processing requirements and processing purposes of the pending tasks.

[0183] Task types include: bit-level processing tasks, logic control tasks, and symbol-level processing tasks.

[0184] Optionally, when a 5G base station sends data to a user device, the physical layer first performs bit-level processing on the data to be processed, and then performs symbol-level processing. When a 5G base station receives data sent by a user device, the physical layer first performs symbol-level processing on the data to be processed, and then performs bit-level processing.

[0185] Bit-level processing includes: adding cyclic redundancy check (CRC), channel coding, interleaving, rate matching, and scrambling to the binary bit data stream.

[0186] Symbol-level processing includes: modulation, layer mapping, precoding, resource block mapping, and antenna transmission.

[0187] In some embodiments, the task information includes: task type, the task type includes: bit-level processing tasks, logic control tasks and symbol-level processing tasks, the processor includes: field programmable gate array FPGA chip and central processing unit CPU, combined with Figure 8 ,like Fig. 9 As shown, in S702, according to the task information, determining the processor for processing the IO thread to be scheduled specifically includes:

[0188] S901. When the task type is a bit-level processing task, determine that the processor for processing the IO thread to be scheduled is an FPGA chip.

[0189] In one feasible way, FPGA chips have the characteristics of strong programmability, high-speed performance, low power consumption, high parallel processing capability and pipeline processing, and hardware-level acceleration based on gate circuits. FPGA chips are suitable for processing bit-level processing tasks. Therefore, when the task type is a bit-level processing task, the processor that processes the IO thread to be scheduled is determined to be an FPGA chip. In this way, the accuracy of IO thread scheduling and the task processing efficiency of IO threads are improved, the processing rate of the physical layer channel is accelerated, and the latency of the 5G wireless base station system is reduced.

[0190] Optionally, in the physical layer, the tasks to be processed by the processor mainly include: bit-level processing tasks and symbol-level processing tasks. Among them, the protocol in the physical layer has relatively complete provisions for processing bit-level tasks (also called bit-level processing), and the process is relatively fixed. In different application scenarios such as multi-user and multi-cell, the complexity and flexibility of bit-level processing are relatively low.

[0191] S902: When the task type is a logic control task or a symbol level processing task, determine that the processor for processing the IO thread to be scheduled is a CPU.

[0192] In one achievable method, the CPU is used to process logic control tasks and symbol-level processing tasks. Therefore, when the task type is a logic control task or a symbol-level processing task, the processor that processes the IO thread to be scheduled is determined to be the CPU. In this way, the accuracy of IO thread scheduling and the task processing efficiency of IO threads are improved, the processing rate of the physical layer channel is accelerated, and the latency of the 5G wireless base station system is reduced.

[0193] Optionally, the amount of data for symbol-level processing tasks is large, and the protocol requirements are highly open. In scenarios with multiple users and multiple antennas (e.g., Single User MIMO (SU-MIMO), Multi-User MIMO (MU-MIMO)), symbol-level processing tasks (also known as symbol-level processing) have different processing procedures and are relatively complex. However, the CPU has abundant computing and storage resources, and the processing is more flexible and easy to configure according to the application scenario.

[0194] Optionally, the FPGA chip has the ability to process logic control tasks or symbol-level processing tasks.

[0195] Optionally, the CPU has the capability to handle bit-level processing tasks.

[0196] When the CPU is unable to process pending tasks, the IO scheduling device can schedule the pending IO threads of storage logic control tasks and symbol-level processing tasks to the FPGA chip. Correspondingly, when the FPGA chip is unable to process pending tasks, the IO scheduling device can schedule the pending IO threads of storage bit-level processing tasks to the CPU, so as to achieve the purpose of no need for threads to wait, thereby improving task processing efficiency.

[0197] Optionally, when the CPU and FPGA chip work together, an effective communication interface needs to be established between the CPU and FPGA chip (which can be implemented through high-speed interfaces such as high-speed serial computer expansion bus standards (Peripheral Component Interconnect Express, PCIe), Ethernet (Ethernet), serial peripheral interface (Serial Peripheral Interface, SPI), or through shared memory or other parallel computing technologies) to facilitate the transmission of data and instructions. Optionally, there are differences in the way and speed of data processing between the CPU and FPGA chips, and the speed and bandwidth of data transmission need to be considered to avoid affecting the system operation due to insufficient data transmission speed. Optionally, when the CPU and FPGA chips work together, it is necessary to divide the tasks to be processed into parts suitable for each processing according to the task type of the tasks to be processed. Optionally, the CPU and FPGA chips can share resources (including: memory, cache) to improve resource utilization and reduce resource waste. Optionally, when the CPU and FPGA work together, it is necessary to perform reasonable power consumption management and optimization according to actual conditions to avoid affecting the stability and reliability of the system due to excessive power consumption. In this way, the efficient operation of the CPU and FPGA chips can be improved.

[0198] Optionally, the communication interface between the CPU and the FPGA chip is a PCIe bus.

[0199] The PCIe bus is an efficient and reliable computer bus standard suitable for high-speed data transmission and device connection.

[0200] The PCIe bus uses serial communication to provide higher bandwidth and lower transmission delay. It has high bandwidth utilization and fast transmission rate, and is suitable for high-speed data transmission (high-speed data transmission). The PCIe bus uses a point-to-point architecture, and each device is directly connected to a centralized controller (Root Complex) (flexible connection method). The PCIe bus supports hot plugging and automatic configuration, making it easier to add and remove devices (hot plugging and automatic configuration). The PCIe bus uses differential signal technology, which can reduce signal interference and noise and improve transmission reliability and stability.

[0201] For example, the CPU and FPGA chip collaboration diagram is as follows: Fig.10 shown.

[0202] CPU includes: DPDK and QDMA drivers.

[0203] The FPGA chip includes: a QDMA module, a downlink acceleration submodule and an uplink acceleration submodule.

[0204] The CPU and FPGA chip transmit data via the PCIe bus.

[0205] Specifically, the IO scheduling device will run the IO threads (including: IO thread 1, IO thread 2, IO thread N and other threads) in the CPU through the Data Plane Development Kit (DPDK) and Queued Direct Memory Access (QDMA) driver and PCIe bus in the CPU to initiate a processing request to the QDMA module in the FPGA chip to schedule the IO threads to the FPGA chip.

[0206] Optionally, traditional network devices (e.g., switches, routers) do not have a network process (NP) processor, but traditional network devices are embedded with NP processors in order to quickly process data packets, and built-in hardware circuits to achieve high-speed forwarding of data packets. Cloud computing requires high-speed processing of data packets, and users have high real-time requirements for data transmission. The physical layer uses the enhanced common public radio interface ECPRI, which is an Ethernet-based protocol data packet. Therefore, in order to retain the processing performance of the CPU's packet processing data, the CPU is developed using the DPDK software library.

[0207] DPDK is a software library for packet data processing acceleration and a data plane development tool set provided by Intel. It is used to provide library functions and driver support for efficient user space data packet processing under the Advanced RISC Machines (ARM) processor architecture. DPDK can also be widely used in various application scenarios that require high-speed data transmission and processing (for example, network acceleration, load balancing, firewalls).

[0208] DPDK includes: Peripheral Media Access Controller (PMD), Memory Management Unit (MMU) and Queue Management Unit (QMU).

[0209] PMD provides access to various types of hardware interfaces (e.g., PCIe, InfiniBand). The PMD driver is a user-mode driver that can bypass the Linux kernel protocol stack for packet processing, thereby avoiding copying messages between kernel mode and user mode.

[0210] MMU is used to manage memory page tables and memory mapping. MMU can provide large page memory (HugePage) and memory buffer (m_buf) management functions to reduce translation lookaside buffer misses (TLB Miss) and memory fragmentation, thereby improving message forwarding performance.

[0211] QMU is used to manage the queue and scheduling of data packets. QMU can provide lock-free message queue and vector instruction functions to improve the CPU pipeline efficiency and reduce memory waiting overhead.

[0212] QDMA is a technology used for high-speed data transmission and processing.

[0213] Optionally, QDMA also includes: priority management function (ensuring that high-priority data transmission takes precedence over low-priority transmission) and interrupt processing function (generating an interrupt signal after data transmission is completed) to facilitate subsequent processing by the user.

[0214] The architecture of QDMA includes both hardware and software aspects.

[0215] Among them, in terms of hardware, QDMA realizes fast data transmission through a direct memory access (DMA) engine.

[0216] The DMA engine is connected to the memory interface on the FPGA and can quickly transfer data from the source address to the target address. QDMA uses a queue management mechanism to control the transmission of the DMA engine. Each entry in the queue contains information such as the source address, target address, and data length.

[0217] In terms of software, QDMA provides the Application Programming Interface (API) of the Hardware Abstraction Layer (HAL) and the API of the Software Abstraction Layer (SAL) to facilitate user programming and configuration.

[0218] The HAL API provides an interface for direct interaction with the hardware, which can configure the parameters of the DMA engine, set queue management, etc.

[0219] SAL's API provides high-level functions and tools to facilitate users to process, schedule and manage data.

[0220] Exemplarily, the structural diagram of QDMA is as follows Fig.11 shown.

[0221] QDMA is divided into four parts: application, user space, kernel space and hardware.

[0222] Among them, the application is a Quick Direct Memory Access User Application (QDMA USER APP).

[0223] The user space is the Quick Direct Memory Access Utility Library (QDMA UTIL LIBRARY).

[0224] The fast direct memory access tool library includes: Register Read (REG READ), Read and Write (READ WRITE) and Quick Direct Memory Access Transfer (QDMA XFER).

[0225] The kernel space is the Quick Direct Memory Access Linux Driver (QDMA LINUX DRIVER).

[0226] The hardware is an FPGA chip.

[0227] S703: Determine a scheduling policy for the IO thread to be scheduled according to the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled.

[0228] In one practicable manner, the IO scheduling device determines the scheduling policy of the IO thread to be scheduled according to the scheduling priority of the IO thread to be scheduled and the processor processing the IO thread to be scheduled. In this way, the scheduling policy of the IO thread to be scheduled determined by the IO scheduling device is more accurate, so that the scheduling of the IO thread to be scheduled using this scheduling policy is more flexible.

[0229] In some embodiments, in combination Fig. 9 ,like Fig.12 As shown, the IO scheduling method also includes:

[0230] S1201. Obtain processor load information, and determine the number of IO threads to be scheduled to be processed by the processor according to the load information.

[0231] In one practicable manner, the IO scheduling device may obtain the load information of the processor, and determine the number of IO threads to be scheduled to be processed by the processor according to the load information. In this way, the IO scheduling device may determine the number of IO threads to be scheduled to be processed by the processor according to the load information of the processor. In this way, the IO scheduling device may allocate a reasonable number of IO threads to be scheduled to the processor, thereby improving the task processing efficiency.

[0232] The load information includes: the number of CPU cores occupied and the amount of data of tasks to be processed in the FPGA chip.

[0233] The CPUs include: dual-core CPU, quad-core CPU, hexa-core CPU, octa-core CPU, and twelve-core CPU.

[0234] When the CPU core frequency and CPU cache size are the same, the more CPU cores there are, the better the CPU performance.

[0235] For example, the performance of a 3.8 GHz hexa-core CPU is stronger than that of a 3.8 GHz dual-core CPU.

[0236] One core in the CPU processes one IO thread to be scheduled.

[0237] The total number of CPU cores is the product of the number of CPUs and the number of CPU cores.

[0238] Specifically, the IO scheduling device can determine the number of currently available CPU cores based on the load information of the CPU cores, and the IO scheduling device can determine the number of pending tasks that can be processed by the currently available FPGA chip based on the load information of the FPGA chip.

[0239] In some embodiments, in combination Fig.10 ,like Fig.13 As shown, the IO scheduling method also includes:

[0240] S1301. Obtain historical physical channel quality data of a physical channel that transmits a task to be processed.

[0241] In one achievable method, the IO scheduling device can obtain the historical physical channel quality of the physical signal transmitting the task to be processed, so that the IO thread predicts the physical channel quality based on the historical physical channel quality data, and executes the scheduling strategy when the physical channel quality is greater than a threshold. In this way, the upload efficiency of the task to be processed can be improved.

[0242] The physical channel is a channel between the user equipment (User Equipment) and the physical layer.

[0243] The physical channels include: a physical uplink control channel (Physical Uplink Control Channel, PUCCH) (also called an uplink physical channel) and a physical downlink control channel (Physical Downlink Control Channel, PDCCH) (also called a downlink physical channel).

[0244] The historical physical channel quality data includes: physical upper layer control channel quality data at multiple measurement time points and physical upper layer control channel quality data at multiple measurement time points.

[0245] S1302: Predict physical channel quality according to historical physical channel quality data.

[0246] In one practicable manner, the IO scheduling device may predict the physical channel quality based on historical physical channel quality data, so as to execute the scheduling strategy when the physical channel quality is greater than a threshold, thereby improving the upload efficiency of the tasks to be processed.

[0247] The IO scheduling device predicts the physical channel quality including: predicting the physical uplink control channel quality and predicting the physical downlink control channel quality.

[0248] Optionally, the IO scheduling device may construct a physical channel quality prediction model based on historical physical channel qualities.

[0249] Specifically, the IO scheduling device trains the physical uplink control channel quality prediction model according to the physical uplink control channel quality data, and trains the physical downlink control channel quality prediction model according to the physical downlink control channel quality data, so that the physical channel quality prediction model learns the law of physical channel quality changing over time.

[0250] The IO scheduling device predicts the physical channel quality according to the physical channel quality prediction model.

[0251] Predicting the physical channel quality includes: predicting the physical uplink control channel quality and predicting the physical downlink control channel quality.

[0252] In the uplink, the user equipment sends a channel sounding reference signal (SRS) to the base station.

[0253] SRS is used to estimate the frequency domain information of the uplink channel for frequency selective scheduling, and to estimate the downlink channel for downlink beamforming.

[0254] The IO scheduling device may determine the quality of the physical uplink control channel according to the SRS.

[0255] Optionally, when the physical channel quality changes too quickly and the signal transmission is delayed, the IO scheduling device determines that the result based on the SRS signal obtained at a low frequency is inaccurate, so the IO scheduling device can obtain the SRS signal at a high frequency and determine the physical uplink control channel quality based on the SRS signal.

[0256] In the downlink, the base station sends a cell specific reference signal (CRS) (also called a common reference signal) to the user equipment, and the user equipment sends a channel quality indicator (Channel Quality Indicator, CQI) to the base station according to the CRS.

[0257] The CRS estimates a channel used for a downlink physical channel and is used to obtain channel state information (Channel State Information, CSI).

[0258] CQI includes: channel quality and coding modulation mode.

[0259] The IO scheduling device can determine the quality of the physical downlink control channel according to the CQI.

[0260] Optionally, the IO scheduling device of the physical layer may allocate channel resources for the physical channel, including: physical downlink shared channel (Physical Downlink Shared Channel, PDSCH) resources and physical uplink shared channel (Physical Uplink Shared Channel, PUSCH) resources.

[0261] In the downlink, the user equipment needs to detect the PDCCH every other time slot. After detecting the PDCCH, the user equipment receives the signal in the PDSCH according to its settings. Then, the user equipment sends a HARQ confirmation signal for successful reception.

[0262] In the uplink, the user equipment sends a time-frequency resource request through the PUCCH, and the base station sends a scheduling grant through the PDCCH, allowing the user equipment to use specific time-frequency resources for transmission. Then, the user equipment transmits the signal through the PUSCH. Then, the user equipment receives the HARQ indication signal sent by the base station that it has been successfully transmitted.

[0263] Optionally, in order to support ultra-low latency transmission, time-frequency resources may be pre-configured for the user equipment, thereby avoiding the request step (which may be referred to as Grant-free transmission).

[0264] S1303: When the physical channel quality is greater than a threshold, execute a scheduling strategy.

[0265] In one practicable manner, when the physical channel quality is greater than a threshold, executing a scheduling strategy can improve the upload efficiency of the tasks to be processed.

[0266] The IO scheduling device determines whether the physical channel quality is qualified according to the physical channel quality data and the physical channel quality data. When the physical channel quality is greater than the threshold, the physical channel quality is qualified, and the IO scheduling device executes the scheduling strategy.

[0267] In some embodiments, in combination Fig.13 ,like Fig.14 As shown, the IO scheduling method also includes:

[0268] S1401. Generate an identity of the task to be processed according to the task information.

[0269] In one practicable manner, the IO scheduling device may generate an identity of the task to be processed according to the task information, and the identity of the task to be processed may reflect the uniqueness of the task to be processed, so that the IO scheduling device can mark the task to be processed.

[0270] The identity is unique and can be used to distinguish different tasks.

[0271] The identity identifier is used to indicate the identity information of each task to be processed.

[0272] Optionally, the identity identifier may correspond to an interface for acquiring (or receiving) the task to be processed.

[0273] Specifically, the IO scheduling device sets the same letter or coding method on the same interface, sets a task number for the pending tasks according to the order in which the pending tasks are obtained (ie, the time in which the pending tasks are obtained), and uses the task number as an identity identifier.

[0274] S1402: When the execution of the scheduling strategy is completed, the task to be processed is marked according to the identity identifier.

[0275] In one practicable manner, when the execution of the scheduling policy is completed, the task to be processed is marked according to the identity identifier, so that the IO scheduling device can avoid repeated scheduling of the IO thread.

[0276] The IO scheduling device performs identity marking on the pending tasks corresponding to the scheduled IO threads.

[0277] Optionally, before executing the scheduling strategy each time, the IO scheduling device compares the identity of the task to be processed corresponding to this thread with the marked identity, and performs scheduling only when the comparison result shows that the identities are different, so as to avoid repeated scheduling.

[0278] For example, Fig.15 A schematic diagram showing an IO scheduling device obtaining tasks to be processed.

[0279] The IO scheduling device obtains pending tasks provided by users, including: task 1 submitted by submitter 1, task 2 submitted by submitter 2, and task N submitted by submitter N.

[0280] The IO scheduling device stores the tasks to be processed in the thread storage device.

[0281] The IO scheduling device stores the pending tasks in the IO threads. That is, the IO scheduling device stores N tasks, such as Task 1, Task 2, Task N, in N IO threads, such as IO thread 1, IO thread 2, IO thread N, respectively.

[0282] In scenarios where a large number of concurrent requests need to be processed, thread storage devices can be used to effectively manage concurrent requests and improve system performance and response speed. For scenarios where the same task needs to be performed repeatedly, thread storage devices can be used to improve task execution efficiency. In resource-constrained scenarios (for example, embedded systems), thread storage devices can be used to effectively manage resources and avoid resource waste and competition.

[0283] When a pending task needs to be processed, the IO scheduling device determines whether the IO thread is idle and whether the task queue in the thread storage device is full, and then the IO scheduling device calls or creates an IO thread or adds it to the task queue.

[0284] After the IO thread completes its task, it is not destroyed immediately, but remains in the thread storage device waiting for the next task. If there is no new task after the survival time, it will be destroyed. By reusing IO threads in this way, the overhead can be reduced.

[0285] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0286] The embodiment of the present application can divide the functional modules of the IO scheduling device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. Optionally, the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0287] Fig.16 FIG. 1 shows a schematic diagram of the structure of an IO scheduling device provided in an embodiment of the present application. Fig.16 As shown, the IO scheduling device includes: a communication unit 1601 and a processing unit 1602;

[0288] The communication unit 1601 is used to obtain the task information of the task to be processed and the thread information of the IO thread to be scheduled; the processing unit 1602 is used to determine the scheduling strategy of the IO thread to be scheduled according to the task information and the thread information.

[0289] Optionally, the scheduling policy includes the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled; the processing unit 1602 is specifically used to: determine the scheduling priority of the IO thread to be scheduled according to the task information and the thread information; determine the processor that processes the IO thread to be scheduled according to the task information; determine the scheduling policy of the IO thread to be scheduled according to the scheduling priority of the IO thread to be scheduled and the processor that processes the IO thread to be scheduled.

[0290] Optionally, the scheduling priority includes: a first scheduling priority and a second scheduling priority; the processing unit 1602 is specifically used to: determine the first scheduling priority of the IO thread to be scheduled according to the task information; the task information includes: time slot data and task direction; the time slot data is used to indicate the time for obtaining the task to be processed; the task direction includes: a downlink direction for processing downlink DL tasks and an uplink direction for processing uplink UL tasks; the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction is higher than the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction; determine the second scheduling priority of the IO thread to be scheduled according to the thread information; the thread information includes historical data of the IO thread to be scheduled; the historical data includes: the frequency of the IO thread to be scheduled processing the task to be processed; the second scheduling priority of the IO thread to be scheduled is proportional to the frequency; determine the scheduling priority of the IO thread to be scheduled according to the first scheduling priority and the second scheduling priority.

[0291] Optionally, the task information includes: task type; task types include: bit-level processing tasks, logic control tasks and symbol-level processing tasks; processors include: field programmable gate array FPGA chips and central processing units CPU; processing unit 1602 is specifically used to: when the task type is a bit-level processing task, determine that the processor for processing the IO thread to be scheduled is the FPGA chip; when the task type is a logic control task or a symbol-level processing task, determine that the processor for processing the IO thread to be scheduled is the CPU.

[0292] Optionally, processing unit 1602 is specifically used to: obtain a first weight parameter of a first scheduling priority and a second weight parameter of a second scheduling priority; and determine the product of the first scheduling priority and the first weight parameter and the sum of the product of the first scheduling priority and the first weight parameter as the scheduling priority of the IO thread to be scheduled.

[0293] Optionally, the processing unit 1602 is further configured to obtain load information of the processor, and determine the number of IO threads to be scheduled to be processed by the processor according to the load information.

[0294] Optionally, the communication unit 1601 is also used to obtain historical physical channel quality data of the physical channel for transmitting the task to be processed; the processing unit 1602 is also used to predict the physical channel quality based on the historical physical channel quality data; the processing unit 1602 is also used to execute the scheduling strategy when the physical channel quality is greater than a threshold.

[0295] Optionally, the processing unit 1602 is further used to generate an identity identifier of the task to be processed according to the task information; the processing unit 1602 is further used to mark the task to be processed according to the identity identifier when the scheduling strategy is executed.

[0296] An embodiment of the present application also provides a computer-readable storage medium, which includes computer execution instructions. When the computer execution instructions are executed on a computer, the computer executes the IO scheduling method provided in the above embodiment.

[0297] An embodiment of the present application also provides a computer program, which can be directly loaded into a memory and contains software code. After being loaded and executed by a computer, the computer program can implement the IO scheduling method provided in the above embodiment.

[0298] Those skilled in the art should be aware that in one or more of the above examples, the functions described in this application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer-readable storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by general or special-purpose computers.

[0299] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0300] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be a physical unit or multiple physical units, that is, it may be located in one place, or it may be distributed in multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0301] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the general technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a ROM, a RAM, a disk, or an optical disk.

[0302] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An input / output (IO) scheduling method, characterized in that: The method comprises: Get the task information of the tasks to be processed and the thread information of the IO threads to be scheduled; A scheduling strategy for the IO thread to be scheduled is determined according to the task information and the thread information.

2. The method according to claim 1, characterized in that The scheduling strategy includes the scheduling priority of the IO thread to be scheduled and the processor for processing the IO thread to be scheduled; The determining, according to the task information and the thread information, a scheduling strategy for the IO thread to be scheduled includes: Determine the scheduling priority of the IO thread to be scheduled according to the task information and the thread information; Determine a processor for processing the IO thread to be scheduled according to the task information; The scheduling policy of the IO thread to be scheduled is determined according to the scheduling priority of the IO thread to be scheduled and the processor processing the IO thread to be scheduled.

3. The method according to claim 2, characterized in that The scheduling priority includes: a first scheduling priority and a second scheduling priority; and determining the scheduling priority of the IO thread to be scheduled according to the task information and the thread information includes: Determine the first scheduling priority of the IO thread to be scheduled according to the task information; the task information includes: time slot data and task direction; the time slot data is used to indicate the time of obtaining the task to be processed; the task direction includes: a downlink direction for processing a downlink DL task and an uplink direction for processing an uplink UL task; the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction is higher than the scheduling priority of the IO thread to be scheduled whose task direction is the downlink direction; Determine the second scheduling priority of the IO thread to be scheduled according to the thread information; the thread information includes historical data of the IO thread to be scheduled; the historical data includes: the frequency of the IO thread to be scheduled processing the task to be processed; the second scheduling priority of the IO thread to be scheduled is proportional to the frequency; The scheduling priority of the IO thread to be scheduled is determined according to the first scheduling priority and the second scheduling priority.

4. The method according to claim 2, characterized in that: The task information includes: task type; the task type includes: bit-level processing tasks, logic control tasks and symbol-level processing tasks; the processor includes: a field programmable gate array FPGA chip and a central processing unit CPU; the processor for processing the IO thread to be scheduled is determined according to the task information, including: In the case where the task type is a bit-level processing task, determining that the processor for processing the IO thread to be scheduled is the FPGA chip; In the case that the task type is a logic control task or a symbol level processing task, it is determined that the processor for processing the IO thread to be scheduled is the CPU.

5. The method according to claim 3, characterized in that: The determining the scheduling priority of the IO thread to be scheduled according to the first scheduling priority and the second scheduling priority includes: Obtaining a first weight parameter of the first scheduling priority and a second weight parameter of the second scheduling priority; The sum of the product of the first scheduling priority and the first weight parameter and the product of the first scheduling priority and the first weight parameter is determined as the scheduling priority of the IO thread to be scheduled.

6. The method according to claim 4, characterized in that The method further comprises: The load information of the processor is obtained, and the number of the to-be-scheduled IO threads to be processed by the processor is determined according to the load information.

7. The method according to claim 1, characterized in that The method further comprises: Acquire historical physical channel quality data of a physical channel for transmitting the task to be processed; Predicting physical channel quality according to the historical physical channel quality data; When the physical channel quality is greater than a threshold, the scheduling strategy is executed.

8. The method according to claim 1, characterized in that The method further comprises: Generate an identity of the task to be processed according to the task information; When the execution of the scheduling strategy is completed, the to-be-processed task is marked with an identity according to the identity identifier.

9. An IO scheduling device, characterized in that: The device comprises: a communication unit and a processing unit; The communication unit is used to obtain task information of tasks to be processed and thread information of IO threads to be scheduled; The processing unit is used to determine the scheduling strategy of the IO thread to be scheduled according to the task information and the thread information.

10. An IO scheduling device, characterized in that: include: A processor and a memory; wherein the memory is used to store one or more programs, and the one or more programs include computer-executable instructions. When the device is running, the processor executes the computer-executable instructions stored in the memory to enable the device to perform the method described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: When the computer-executable instructions stored in the computer-readable storage medium are executed by a processor of an IO scheduling device, the IO scheduling device can perform the method according to any one of claims 1 to 8.

12. A computer program product, characterized in that The computer program product comprises: a computer program or instructions, and when the computer program or instructions are run on a computer, the computer is caused to perform the method according to any one of claims 1 to 8.

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