Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate and a stacking structure located on the substrate. The stacked structure comprises first electrode layers and first dielectric layers which are alternately stacked; the stacking structure comprises a plurality of sub-stacking structures, each sub-stacking structure extends along a first direction, and the plurality of sub-stacking structures are arranged along a second direction; at least one of the two opposite side walls of each sub-stacking structure in the second direction at least comprises a curved surface, and the two opposite side walls of each sub-stacking structure in the thickness direction of the substrate are planes parallel to the substrate; the first direction and the second direction intersect and are perpendicular to the thickness direction of the substrate; the second dielectric layer covers the outer wall of each sub-stacking structure and the bottom surface of a first groove formed between two adjacent sub-stacking structures in a shape-preserving manner; and the second electrode layer covers the second dielectric layer in a shape-preserving manner.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. During the development of DRAM, as the size continues to shrink, bottlenecks encountered by vertical capacitor structures began to emerge. In order to increase the unit density of capacitors, stacked capacitors began to appear. How to improve the performance of stacked capacitors has become an urgent problem to be solved. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, including:

[0006] A substrate and a stacking structure located on the substrate; the stacking structure comprises a first electrode layer and a first dielectric layer alternately stacked; the stacking structure comprises a plurality of sub-stacked structures, each of the sub-stacked structures extends along a first direction, and the plurality of sub-stacked structures are arranged along a second direction; at least one of the two side walls opposite to each other along the second direction of each sub-stacked structure comprises at least a curved surface, and the two side walls opposite to each other along the thickness direction of the substrate of each sub-stacked structure are planes parallel to the substrate; the first direction intersects with the second direction and is perpendicular to the thickness direction of the substrate;

[0007] A second dielectric layer conformally covers the outer wall of each of the sub-stacked structures and the bottom surface of the first groove formed between two adjacent sub-stacked structures;

[0008] The second electrode layer conformally covers the second dielectric layer.

[0009] In some embodiments, the substrate includes a first region and a second region arranged in parallel along the first direction; each of the sub-stack structures includes a first portion located on the first region and a second portion extending to the second region, the second portion includes alternately stacked first electrode layers and first dielectric layers, the first portion includes the first dielectric layer, and the second dielectric layer and the second electrode layer are located between adjacent second portions;

[0010] At least one of the two side walls of the second part that are opposite to each other along the second direction comprises at least a curved surface; and the two side walls of the first part that are opposite to each other along the second direction are planes parallel to the first direction.

[0011] In some embodiments, the sub-stack structure includes a first sub-portion and a second sub-portion arranged alternately along a first direction; at least one of two opposite side walls of the first sub-portion along the second direction and two opposite side walls of the second sub-portion along the second direction is a curved surface.

[0012] In some embodiments, the curved surface is parallel to a thickness direction of the substrate, and the curved surface is concave toward another sidewall of the sub-stack structure opposite to the second direction.

[0013] In some embodiments, the first portion further includes: a plurality of transistors; each of the transistors is located between two adjacent first dielectric layers in the first portion, and each of the transistors includes a source and a drain at two opposite ends along a first direction, and a channel region located between the source and the drain;

[0014] A plurality of word line structures; each of the word line structures extends along the thickness direction of the substrate, and one of the word line structures is connected to the channel regions of the plurality of transistors in the first portion.

[0015] In some embodiments, the first part also includes: a plurality of bit line structures, each of the bit line structures extending along the second direction, and each of the bit line structures being located between two first dielectric layers adjacent to each other along the thickness direction of the substrate, and being connected to the source or drain of a plurality of the transistors in a layer, and the transistors being connected to the first electrode layer.

[0016] In some embodiments, each of the first electrode layers in each of the sub-stack structures includes a first sub-electrode layer and a second sub-electrode layer arranged at intervals along the second direction, and the first electrode layer also includes a first connecting structure located between the first sub-electrode layer and the second sub-electrode layer.

[0017] In a second aspect, the present disclosure also provides a method for forming a semiconductor structure, including:

[0018] forming an initial stacking structure of semiconductor layers and sacrificial layers alternately stacked on a substrate;

[0019] A plurality of first grooves are formed that penetrate the initial stacking structure, each of the first grooves extends along a first direction, and the plurality of first grooves are arranged along a second direction; the first grooves divide the initial stacking structure into a plurality of initial sub-stacked structures arranged along the second direction, and at least one of the two side walls of each initial sub-stacked structure that are opposite to each other along the second direction includes at least a curved surface; the first direction intersects with the second direction and is perpendicular to the thickness direction of the substrate;

[0020] removing the sacrificial layer to form a first filling area;

[0021] forming a first dielectric layer in the first filling region;

[0022] removing at least a portion of each semiconductor layer in each of the initial sub-stack structures to form a second filling region;

[0023] forming a first electrode layer in the second filling region to form a sub-stack structure;

[0024] A second dielectric layer conformally covering the outer wall of the sub-stack structure and the bottom wall of the first groove and a second electrode layer conformally covering the second dielectric layer are formed.

[0025] In some embodiments, the substrate includes a first region and a second region arranged in parallel along the first direction, the first groove extends from the first region to the second region, each of the initial sub-stack structures includes a first portion located on the first region and a second portion extending to the second region, at least one of two side walls of the second portion opposite to each other along the second direction includes at least a curved surface; and two side walls of the first portion opposite to each other along the second direction are planes parallel to the first direction;

[0026] The removing at least a portion of each semiconductor layer in each of the initial sub-stack structures comprises:

[0027] At least a portion of each semiconductor layer in each second portion is removed along the first groove; and a metallization process is performed on the remaining semiconductor layer on the second region to form a first connection structure.

[0028] In some embodiments, the first electrode layer includes a first sub-electrode layer and a second sub-electrode layer arranged at intervals along the second direction, the first electrode layer also includes a first connection structure located between the first sub-electrode layer and the second sub-electrode layer, and the metallization treatment of the remaining semiconductor layer on the second region to form the first connection structure includes:

[0029] After removing at least a portion of each semiconductor layer in each of the initial sub-stack structures, forming a first metal layer on the sidewalls of the remaining semiconductor layer on the second region;

[0030] Through a heat treatment process, the remaining semiconductor layer and a portion of the first metal layer on the second region form the first connection structure;

[0031] The remaining first metal layer is removed to form the second filling region.

[0032] In some embodiments, the method further comprises:

[0033] After forming a plurality of first grooves penetrating the stack structure, removing a portion of each semiconductor layer of each of the initial sub-stack structures on the first region from one side of the stack structure located on the first region and perpendicular to the first direction, to form a third filling region;

[0034] A bit line structure is formed in the third filling region, and the bit line structure is connected to the semiconductor layer remaining on the first region.

[0035] In some embodiments, the method further comprises:

[0036] Performing doping treatment on the remaining portion of each semiconductor layer on the first region at both ends along the first direction to form a source and a drain, thereby forming a plurality of transistors, wherein the semiconductor layer between the source and the drain constitutes a channel region of the transistor, and the transistor is connected to the first electrode layer;

[0037] A plurality of word line structures are formed, each of the word line structures extending along the thickness direction of the substrate, and one of the word line structures is connected to the channel regions of the plurality of transistors in one first portion.

[0038] In some embodiments, the sub-stack structure includes a first sub-portion and a second sub-portion alternately arranged along a first direction; at least one of two side walls of the first sub-portion opposite to each other along the second direction and two side walls of the second sub-portion opposite to each other along the second direction is a curved surface; and forming a plurality of first grooves passing through the initial stack structure includes:

[0039] Forming a plurality of first strip-shaped grooves penetrating the initial stacking structure, each of the first strip-shaped grooves extending along a first direction, and the plurality of first strip-shaped grooves arranged along a second direction;

[0040] Filling a sacrificial filling layer in the first strip-shaped groove;

[0041] Forming a hole-shaped groove penetrating the sacrificial filling layer and the remaining initial stacking structure, wherein the hole-shaped groove and the strip-shaped groove constitute the first groove, the size of the hole-shaped groove along the second direction is larger than the size of the strip-shaped groove along the second direction, and the hole-shaped grooves are arranged in an array along the first direction and the second direction at intervals;

[0042] The remaining sacrificial filling layer is removed.

[0043] In some embodiments, removing the sacrificial layer to form a first filling region includes:

[0044] forming a third dielectric layer in the first groove;

[0045] Removing a portion of the third dielectric layer to form a second groove penetrating the stacked structure, wherein the second groove exposes a portion of the sidewall of the sacrificial layer;

[0046] removing the sacrificial layer with exposed sidewalls to form a first sub-filling region;

[0047] forming a portion of the first dielectric layer in the first sub-filling region;

[0048] removing the remaining third dielectric layer to form a third groove penetrating the stacked structure, wherein the third groove exposes the remaining sidewall of the sacrificial layer;

[0049] removing the remaining sacrificial layer to form a second sub-filling area;

[0050] Another portion of the first dielectric layer is formed in the second sub-filling region.

[0051] In some embodiments, the first groove penetrates the stack structure and extends into the substrate;

[0052] The removing at least a portion of each semiconductor layer in each of the initial sub-stack structures to form a second filling region comprises:

[0053] A portion of each semiconductor layer and a portion of the substrate in each of the initial sub-stack structures are removed to form the second filling region.

[0054] In the technical solution provided by the present disclosure, the first electrode layer of the stacked structure can be used as the lower electrode of the capacitor, the second dielectric layer can be used as the dielectric layer of the capacitor, and the second electrode layer can be used as the upper electrode of the capacitor. In addition, at least one of the two side walls of the sub-stacked structure opposite to each other along the second direction includes at least a curved surface. In the first aspect, compared with the two side walls of the sub-stacked structure opposite to each other along the second direction being planes, the area of ​​the first electrode layer is enlarged, and the second dielectric layer is conformally covered on the outer wall of each sub-stacked structure and the bottom surface of the first groove formed between the two adjacent sub-stacked structures. The second electrode layer conformally covers the second dielectric layer, thereby correspondingly enlarging the area of ​​the second dielectric layer and the second electrode layer, thereby increasing the capacitance of the capacitor and improving the storage capacity of the capacitor; in the second aspect, since at least one of the two side walls of the sub-stacked structure opposite to each other along the second direction includes at least a curved surface, more space is left for the second electrode layer and the first dielectric layer, so that the integration of the semiconductor structure can be improved; in the third aspect, the distance between the first electrode layers of the capacitors adjacent to each other along the second direction becomes relatively far, so that the coupling effect between adjacent capacitors can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0056] Figure 2 A schematic diagram of a substrate and an initial stacking structure provided for an embodiment of the present disclosure;

[0057] Figure 3a A top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0058] Figure 3b for Figure 3a The schematic cross-sectional view of the semiconductor structure including a plurality of initial sub-stack structures along the line AA' and the schematic cross-sectional view along the line BB' shown;

[0059] Figures 4a to 4e A top view of an initial sub-stack structure provided for an embodiment of the present disclosure;

[0060] Figure 5 A schematic cross-sectional view of a semiconductor structure including a third dielectric layer along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0061] Figure 6 A schematic cross-sectional view of a semiconductor structure including a first sub-filling region along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0062] Figure 7A schematic cross-sectional view of a semiconductor structure including a third groove along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0063] Figure 8 A schematic cross-sectional view of a semiconductor structure including a second sub-filling region along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0064] Fig. 9 A schematic cross-sectional view of a semiconductor structure including a first dielectric layer along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0065] Fig.10 A top view of a semiconductor structure including a plurality of sub-stack structures provided in an embodiment of the present disclosure;

[0066] Fig.11 A schematic cross-sectional view of a semiconductor structure including a first groove along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0067] Fig.12 A schematic cross-sectional view of a semiconductor structure along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure, wherein at least a portion of each semiconductor layer in each second portion is removed;

[0068] Fig.13 A schematic cross-sectional view of a semiconductor structure including a second filling region along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0069] Fig.14 A schematic cross-sectional view of a semiconductor structure including a first metal material along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure;

[0070] Fig.15 A schematic cross-sectional view of a semiconductor structure including a first electrode layer provided in an embodiment of the present disclosure along line AA' and a schematic cross-sectional view along line BB';

[0071] 16a to 16d are top views of a semiconductor structure including alternately arranged first sub-portions and second sub-portions provided in an embodiment of the present disclosure;

[0072] 17 is a schematic cross-sectional view of a semiconductor structure including a second dielectric layer and a second electrode layer along line AA' and along line BB' provided by an embodiment of the present disclosure;

[0073] Fig.18 A schematic cross-sectional view of a semiconductor structure including a third filling region along line AA' provided in an embodiment of the present disclosure;

[0074] Fig.19 A schematic cross-sectional view of a semiconductor structure including a bit line structure along line AA' provided in an embodiment of the present disclosure;

[0075] Fig. 20 A schematic cross-sectional view of a semiconductor structure including a word line structure along line AA' provided in an embodiment of the present disclosure;

[0076] Fig.21 A schematic cross-sectional view of a semiconductor structure including a mask layer along line AA' provided in an embodiment of the present disclosure;

[0077] Fig. 22 A schematic cross-sectional view of a semiconductor structure along line AA' and a schematic cross-sectional view along line BB' provided by an embodiment of the present disclosure;

[0078] Fig.23 A top view of a semiconductor structure provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0080] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0081] In the drawings, like reference numerals refer to like elements throughout.

[0082] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0083] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0084] The present disclosure also provides a method for forming a semiconductor structure. Figure 1 Schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0085] Step S10: forming an initial stacking structure consisting of semiconductor layers and sacrificial layers alternately stacked on the substrate;

[0086] Step S20: forming a plurality of first grooves penetrating the initial stacking structure, each of the first grooves extending along the first direction, and the plurality of first grooves arranged along the second direction; the first grooves divide the initial stacking structure into a plurality of initial sub-stacked structures arranged along the second direction, and at least one of the two side walls of each initial sub-stacked structure opposite to each other along the second direction includes at least a curved surface; the first direction intersects with the second direction and is perpendicular to the thickness direction of the substrate;

[0087] Step S30: removing the sacrificial layer to form a first filling area;

[0088] Step S40: forming a first dielectric layer in the first filling region;

[0089] Step S50: removing at least a portion of each semiconductor layer in each initial sub-stack structure to form a second filling region;

[0090] Step S60: forming a first electrode layer in the second filling region to form a sub-stack structure;

[0091] Step S70: forming a second dielectric layer conformally covering the outer wall of the sub-stack structure and the bottom wall of the first groove, and a second electrode layer conformally covering the second dielectric layer.

[0092] The embodiment of the present disclosure is described by taking the first direction as the X direction, the second direction as the Y direction, and the thickness direction of the substrate as the Z direction as an example, but the above directions are not limited thereto. In the embodiment of the present disclosure, it is only necessary to satisfy that the first direction intersects with the second direction and the first direction and the second direction are both perpendicular to the thickness direction of the substrate. The following is an exemplary description by taking the first direction and the second direction being perpendicular as an example.

[0093] In the technical solution provided by the present disclosure, the first electrode layer of the stacked structure can be used as the lower electrode of the capacitor, the second dielectric layer can be used as the dielectric layer of the capacitor, and the second electrode layer can be used as the upper electrode of the capacitor. In addition, at least one of the two side walls of the sub-stacked structure opposite to each other along the second direction includes at least a curved surface. In the first aspect, compared with the two side walls of the sub-stacked structure opposite to each other along the second direction being planes, the area of ​​the first electrode layer is enlarged, and the second dielectric layer is conformally covered on the outer wall of each sub-stacked structure and the bottom surface of the first groove formed between the two adjacent sub-stacked structures. The second electrode layer conformally covers the second dielectric layer, thereby correspondingly enlarging the area of ​​the second dielectric layer and the second electrode layer, thereby increasing the capacitance of the capacitor and improving the storage capacity of the capacitor; in the second aspect, since at least one of the two side walls of the sub-stacked structure opposite to each other along the second direction includes at least a curved surface, more space is left for the second electrode layer and the first dielectric layer, so that the integration of the semiconductor structure can be improved; in the third aspect, the distance between the first electrode layers of the capacitors adjacent to each other along the second direction becomes relatively far, so that the coupling effect between adjacent capacitors can be reduced.

[0094] Figures 2 to 23 The schematic diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is as follows. Figures 1 to 23 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0095] Reference Figure 1 , executing step S10, forming an initial stacking structure consisting of semiconductor layers and sacrificial layers alternately stacked on the substrate.

[0096] In some embodiments, Figure 2As shown, the substrate 100 includes a semiconductor substrate. The semiconductor substrate may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0097] In some embodiments, forming Figure 2 The initial stacked structure 200 shown includes semiconductor layers 201 and sacrificial layers 202 that are alternately arranged in sequence along the Z direction by a deposition process.

[0098] It should be noted that the numbers of the semiconductor layers 201 and the sacrificial layers 202 in the figure are only examples, and the present disclosure does not limit the specific numbers of the semiconductor layers 201 and the sacrificial layers 202 .

[0099] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0100] In the embodiment of the present disclosure, the material of the semiconductor layer 201 includes at least one of the following: silicon and germanium. The material of the sacrificial layer 202 includes but is not limited to silicon germanium (SiGe). Here, the material of the sacrificial layer 202 has a higher etching selectivity than the material of the semiconductor layer 201.

[0101] In some specific examples, the method for forming a semiconductor structure further includes forming a first mask layer on the initial stacked structure, and the material of the first mask layer includes but is not limited to silicon oxide.

[0102] Reference Figure 1 , execute step S20 to form Figure 3a The plurality of first grooves 210 shown penetrating the initial stacking structure, Figure 3a 2 is a top view of the semiconductor structure. Each first groove 210 extends along the X direction, and a plurality of first grooves 210 are arranged along the Y direction; the first grooves 210 divide the initial stacking structure into a plurality of initial sub-stacked structures 220 arranged along the Y direction, and at least one of the two side walls opposite to each other along the Y direction of each initial sub-stacked structure 220 includes at least a curved surface.

[0103] In some embodiments, multiple first grooves may be formed by one etching process. It is understood that the etching pattern is the same as the shape of the first groove on the XY plane. In the embodiments of the present disclosure, the etching process includes but is not limited to wet etching and dry etching.

[0104] In some other embodiments, a plurality of first grooves may be formed by a secondary etching process. For example, the initial stacked structure may be etched along the Z direction to form a strip groove, and the strip groove extends along the X direction. Then, part of the strip groove is etched along the Y direction to form a hole groove, and the strip groove and the hole groove together form the first groove. For another example, a hole groove may be formed first, and then a strip groove that passes through the hole groove along the X direction may be formed, and finally the first groove may be formed.

[0105] The process of forming the first groove will be specifically described below by taking the secondary etching process as an example.

[0106] In some embodiments, forming a plurality of first grooves penetrating the initial stacking structure includes:

[0107] A plurality of first strip-shaped grooves penetrating the initial stacked structure may be formed by a first etching process, each of the first strip-shaped grooves extending along a first direction (eg, an X direction), and the plurality of first strip-shaped grooves are arranged along a second direction;

[0108] Then, a deposition process or a growth process may be used to fill the first strip-shaped groove with a sacrificial filling layer; the material of the sacrificial filling layer is not limited to silicon germanium and silicon nitride.

[0109] Then, a second etching process may be performed to etch a portion of the sacrificial filling layer and a portion of the initial stacking structure in contact with the portion of the sacrificial filling layer, to form a hole-shaped groove penetrating the sacrificial filling layer and the remaining initial stacking structure, the hole-shaped groove and the strip-shaped groove constitute a first groove, the size of the hole-shaped groove along the second direction is greater than the size of the strip-shaped groove along the second direction, and the hole-shaped grooves are arranged in an array along the first direction and the second direction at intervals; in the X direction, the hole-shaped grooves may be arranged at intervals, and the distance between each interval in the X direction may be the same. And / or, in the Y direction, the hole-shaped grooves may also be arranged at intervals, and the distance between each interval in the Y direction may be the same.

[0110] Then, the remaining sacrificial fill layer is removed to form Figure 3a to Figure 3b The first groove 210 is shown.

[0111] In other embodiments, the hole-shaped groove may be formed first and then the first strip-shaped groove may be formed.

[0112] In some embodiments, the initial stacked structure may be etched along the Z direction, and the substrate may be used as an etch stop layer to form a plurality of first grooves penetrating the initial stacked structure.

[0113] In some specific examples, the first groove 210 may extend into the substrate 100 .

[0114] It should be noted that Figure 3a The number of the first grooves 210 and the initial sub-stack structures 220 arranged along the Y direction is only an example, and the present disclosure does not limit the number of the first grooves 210 and the initial sub-stack structures 220.

[0115] Figure 3a A top view of a semiconductor structure including a plurality of initial sub-stack structures 220 provided for an embodiment of the present disclosure; Figure 3b for Figure 3a The semiconductor structure including the plurality of initial sub-stack structures 220 is shown as a schematic cross-sectional view along line AA′ and a schematic cross-sectional view along line BB′.

[0116] like Figure 3a As shown, the first groove 210 divides the initial stacking structure into a plurality of initial sub-stacked structures 220 arranged along the Y direction, and at least one of the two side walls opposite to each other along the Y direction of each initial sub-stacked structure 220 includes at least a curved surface.

[0117] Here, if Figure 2 as well as Figure 3a As shown, the substrate includes a first region 110 and a second region 120 arranged in parallel along the X direction, a first groove 210 extends from the first region 110 to the second region 120 , and an initial sub-stack structure 220 extends from the first region 110 to the second region 120 .

[0118] At least one sidewall of the initial sub-stack structure 220 includes at least a curved surface, which can be understood as follows: Figure 3a As shown, the two opposite side walls of the initial sub-stack structure 220 located on the first region 110 along the Y direction may both be planes. At least one of the two opposite side walls of the initial sub-stack structure 220 located on the second region 120 along the Y direction includes a curved surface.

[0119] Figures 4a to 4e Only a partial top view of the initial sub-stack structure 220 on the second region 120 is shown. For at least one of the two side walls of the initial sub-stack structure 220 on the second region 110 opposite to each other along the Y direction including a curved surface, the embodiment of the present disclosure provides a variety of situations.

[0120] Case 1: One sidewall includes a curved surface, and the other sidewall does not include a curved surface. For example, 4a shows a case where one sidewall of the initial sub-stack structure 220 is a curved surface, and the other sidewall is a flat surface. 4b shows a case where one sidewall of the initial sub-stack structure 220 includes two curved surfaces and a flat surface, and the other sidewall is a flat surface. It should be noted that Figure 4bThe figure only exemplarily shows a case where a side wall includes two curved surfaces, but is not used to limit the number of curved surfaces in the embodiments of the present disclosure.

[0121] Case 2: Both side walls include curved surfaces, and the number of curved surfaces included in the two side walls may be the same or different. For example, 4c shows the case where both side walls in the initial sub-stacked structure 220 are curved surfaces. 4d shows the case where both side walls in the initial sub-stacked structure 220 include two curved surfaces and three flat surfaces. 4e shows the case where one side wall in the initial sub-stacked structure 220 is a curved surface, and the other side wall includes two curved surfaces and three flat surfaces.

[0122] In the embodiment of the present disclosure, the curved surface may be concave toward another side wall (such as Figures 4a to 4e ), or it may protrude toward another side wall of the initial sub-stack structure opposite to the Y direction (as shown in FIG. Figure 4e As shown). The curved surface includes a spherical surface, a cylindrical surface, and a free-form surface. It can be understood that when the curved surface can be concave toward the other side wall opposite to the initial sub-stack structure along the Y direction, the distance between adjacent capacitors subsequently formed along the Y direction becomes relatively far, so that the coupling effect between adjacent capacitors can be reduced.

[0123] Reference Figure 1 , perform step S30 to remove the sacrificial layer and form a first filling area.

[0124] In some embodiments, removing the sacrificial layer to form the first filling region includes:

[0125] Reference Figures 5 to 7 , first, if Figure 5 As shown, a third dielectric layer 310 is formed in the first groove 210. The third dielectric layer 310 can not only fill the first groove, but also cover the upper surface of the plurality of initial sub-stack structures. The material of the third dielectric layer 310 includes but is not limited to silicon oxide. Figure 5 A schematic cross-sectional view of a semiconductor structure including a third dielectric layer 310 along line AA′ and a schematic cross-sectional view along line BB′ provided in an embodiment of the present disclosure.

[0126] In some embodiments, Figure 6 As shown, firstly, an etching process can be used to remove part of the third dielectric layer 310 to form a second groove 301 penetrating the stacked structure, and the second groove 301 exposes part of the sidewall of the sacrificial layer 202. Then, a wet etching process is used to remove the sacrificial layer exposed on the sidewall to form a first sub-filling region 311. The first sub-filling region 311 is located between adjacent semiconductor layers 201. Here, Figure 6 The remaining sacrificial layer 202 shown in FIG. 1 may play a supporting role for the semiconductor structure when the sacrificial layer 202 with exposed sidewalls is removed. Figure 6 A schematic cross-sectional view of a semiconductor structure including a first sub-filling region 311 along line AA′ and a schematic cross-sectional view along line BB′ provided in an embodiment of the present disclosure.

[0127] Then, a growth process or a deposition process may be used to form a Figure 7 A portion of the first dielectric layer 320 is shown; the material of the first dielectric layer 320 includes but is not limited to silicon oxide. The material of the first dielectric layer 320 and the material of the third dielectric layer may be the same or different. The portion of the first dielectric layer 320 formed in the first sub-filling region 311 may also play a supporting role for the semiconductor structure in subsequent steps. In the disclosed embodiment, the growth process includes but is not limited to In-Situ Steam Generation (ISSG). Figure 7 A schematic cross-sectional view of a semiconductor structure including a first dielectric layer 320 along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure.

[0128] The remaining third dielectric layer is removed by etching to form Figure 7 The third groove 302 is shown penetrating the stack structure, and the third groove 302 exposes the sidewall of the remaining sacrificial layer 202 .

[0129] Then, the remaining sacrificial layer 202 is removed by a wet etching process through the third groove 302 to form Figure 8 In this embodiment, the first filling region includes the first sub-filling region 311 and the second sub-filling region 312. Then, another portion of the first dielectric layer 320 may be formed in the second sub-filling region 312 using a growth process or a deposition process. Fig. 9 The semiconductor structure shown. Figure 8 A schematic cross-sectional view of a semiconductor structure including a second sub-filling region 312 along line AA′ and a schematic cross-sectional view along line BB′ provided in an embodiment of the present disclosure.

[0130] Reference Figure 1 , executing step S50: removing at least a portion of each semiconductor layer in each initial sub-stack structure to form a second filling region.

[0131] In some embodiments, Fig.10 As shown, each initial sub-stack structure 220 includes a first portion 101 located on the first area 110 and a second portion 102 extending to the second area 120, and at least one of the two side walls of the second portion 102 opposite to each other along the Y direction includes at least a curved surface; the two side walls of the first portion 101 opposite to each other along the Y direction are planes parallel to the X direction. Fig.10A top view of a semiconductor structure including a plurality of initial sub-stack structures 220 provided in accordance with an embodiment of the present disclosure.

[0132] In some embodiments, in step S50: removing at least a portion of each semiconductor layer in each initial sub-stack structure comprises: first, Fig.11 The first groove 210 in the second portion is formed by removing at least a portion of each semiconductor layer 201 in each second portion using an etching process. Fig.12 The semiconductor structure shown. Fig.11 A schematic cross-sectional view of a semiconductor structure including a first groove 210 along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure; Fig.12 A schematic cross-sectional view of a semiconductor structure along line AA′ and a schematic cross-sectional view along line BB′ provided in an embodiment of the present disclosure, wherein at least a portion of each semiconductor layer 201 in each second portion is removed.

[0133] Fig.11 as well as Fig.12 Also shown is a bit line structure 400 and a word line structure 500. The specific formation process of the bit line structure 400 and the word line structure 500 will be described in detail in the subsequent embodiments, and will not be repeated here.

[0134] In some embodiments, an etching process may be used to remove the Fig.11 At least a portion of each semiconductor layer 201 in each initial sub-stack structure shown is retained. Fig.12 The middle portion of each semiconductor layer 201 is shown. Fig.12 The semiconductor layer 201 is located between the first dielectric layers 320 adjacent to each other in the Z direction, between the first dielectric layer 320 and the substrate 100, and between the third dielectric layer 310 and the first dielectric layer 320 adjacent to each other in the Z direction. The size of the semiconductor layer 201 etched away in the X direction may be the same as or different from the size of the semiconductor layer 201 etched away in the Y direction.

[0135] In some embodiments, the first groove penetrates the stack structure and extends into the substrate; in step S50, at least a portion of each semiconductor layer in each initial sub-stack structure is removed to form a second filling region, including:

[0136] A portion of each semiconductor layer in each initial sub-stack structure and a portion of the substrate are removed to form a second filling region. Since the first groove runs through the initial stack structure and extends into the substrate, the substrate can be exposed. When at least a portion of each semiconductor layer in each initial sub-stack structure is removed through the first groove, it can be understood that a certain thickness of the exposed portion of the substrate will also be removed.

[0137] Then, the remaining semiconductor layer 201 on the second region 120 is subjected to a metallization process to form Fig.13 The first connection structure 603 is shown. The material used for the first connection structure 603 can be metal silicide, including but not limited to TiSi2 (titanium silicide), CoSi2 (cobalt silicide) and nickel alloy (for example, Ni-Pt, Ni-Al, Ni-Y) silicide and the like.

[0138] right Fig.12 The specific process of performing metallization treatment on the remaining semiconductor layer 201 on the second region 120 may be: depositing metal (including but not limited to titanium, cobalt and nickel) on the sidewall of the remaining semiconductor layer 201 on the second region 120, and then reacting the metal and the semiconductor layer 201 at a high temperature to obtain a metal semiconductor compound. When the material used for the semiconductor layer 201 is silicon and its compounds, a metal silicide may be obtained.

[0139] A vacuum hot steam method can also be used, in which a mixed powder containing metals (including but not limited to titanium, cobalt and nickel) is placed in a vacuum furnace and heated to the metal vapor temperature so that it is deposited on the side walls of the semiconductor layer 201 to form a metal semiconductor compound film. When the material used for the semiconductor layer 201 is silicon and its compounds, a metal silicide film can be obtained.

[0140] Metal silicide has good conductivity and resistivity and is suitable as an electrode material for capacitors.

[0141] In some embodiments, step S50, performing a metallization process on the remaining semiconductor layer on the second region to form a first connection structure, includes:

[0142] After removing at least a portion of each semiconductor layer in each initial sub-stack structure, Fig.12 The sidewalls of the remaining semiconductor layer 201 in the second region 120 are formed with a first metal layer (not shown).

[0143] Then, the remaining semiconductor layer 201 on the second region 120 and part of the first metal layer are subjected to a heat treatment process to form a first connection structure 603. The heat treatment process can cause the metal material used in the first metal layer and the material of the semiconductor layer (for example, silicon) to react at a high temperature to obtain a metal silicide. The metal silicide can be used as the first connection structure 603.

[0144] In some embodiments, it is also possible to Fig.12 A first metal layer (not shown) is formed on the upper surface of the substrate 100 in the second region 120 shown in the figure. Then, the substrate 100 and the first metal layer thereon are formed together by a heat treatment process. Fig.13 A connection layer 604 is shown.

[0145] In some embodiments, there is a remaining first metal layer that has not reacted with the semiconductor layer 603, and the remaining first metal layer is removed to form Fig.13 The second filling region 720 is shown. In some embodiments, there is still a first metal layer that has not reacted with the substrate 100, and the remaining first metal layer is removed. Subsequently, a conductive material can be deposited in the second filling region 720 to form a first sub-electrode layer and a second sub-electrode layer located on both sides of the first connection structure 603. Fig.13 A schematic cross-sectional view of a semiconductor structure including a second filling region along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure.

[0146] Reference Figure 1 , performing step S60: forming a first electrode layer in the second filling region to form a sub-stack structure.

[0147] In some embodiments, Fig.15 As shown, the first electrode layer 600 includes a first sub-electrode layer 601 and a second sub-electrode layer 602 arranged at intervals along the Y direction. The first electrode layer also includes a first connecting structure 603, which is located between the first sub-electrode layer 601 and the second sub-electrode layer 602. That is, the first electrode layer 600 can be a sandwich structure of the first sub-electrode layer 601, the first connecting structure 603 and the second sub-electrode layer 602.

[0148] In some embodiments, a growth process or a deposition process may be used. Fig.13 The second filling region 720 is filled with a first conductive material to form Fig.12 a and Fig.12 b shows the first electrode layer 600. The first conductive material includes but is not limited to metal ruthenium (Ru), metal tungsten (W) and metal tantalum (Ta).

[0149] The specific process of forming the first electrode layer 600 may be: first, Fig.13 The first metal material is deposited in the second filling area 720, in the first groove 210 and on the third dielectric layer 310 to form Fig.14 Then, the first metal material layer 700 deposited in the first groove 210 and on the third dielectric layer 310 is removed, and the first metal material layer 700 deposited in the second filling area 720 is retained to form Fig.15 The first sub-electrode layer 601 and the second sub-electrode layer 602 are shown. The first sub-electrode layer 601 , the first connection structure 603 and the second sub-electrode layer 602 together constitute the first electrode layer 600 . Fig.14 A schematic cross-sectional view of a semiconductor structure including a first metal material along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure; Fig.15 A schematic cross-sectional view of a semiconductor structure including a first electrode layer along line AA' and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure.

[0150] By filling and forming the first electrode layer 600 in the second filling region 720 , the stability of the semiconductor structure can be improved and short circuits between electrodes can be avoided.

[0151] In some specific examples, the semiconductor layer 603 on the second region may be completely removed, and the first metal material layer 700 may be filled in the region where the semiconductor layer 603 is removed to form the first electrode layer 600 .

[0152] In some embodiments, as shown in Figures 16a to 16d (Figures 16a to 16d are top views of a semiconductor structure provided in an embodiment of the present disclosure including alternating first sub-portions and second sub-portions), the sub-stack structure 103 includes first sub-portions 221 and second sub-portions 222 arranged alternately along the X direction; at least one of the two side walls of the first sub-portion 221 opposite to each other along the Y direction and the two side walls of the second sub-portion 222 opposite to each other along the Y direction is a curved surface.

[0153] The outer wall profile of the sub-stacked structure 103 may be the same as the outer wall profile of the initial sub-stacked structure. At least one side wall of the second portion 102 of the sub-stacked structure 103 may include at least a curved surface. Figures 4a to 4e The situation shown will not be repeated here.

[0154] For example, as shown in FIG. 16 a , two opposite side walls of the first sub-portion 221 along the Y direction are both planes, and one of two opposite side walls of the second sub-portion 222 along the Y direction is a plane and the other side wall is a curved surface.

[0155] For another example, as shown in FIG16b, one of the two side walls of the first sub-portion 221 opposite to each other along the Y direction is a plane, and the other side wall is a curved surface; one of the two side walls of the second sub-portion 222 opposite to each other along the Y direction is a plane, and the other side wall is a curved surface.

[0156] For another example, as shown in FIG. 16c , two opposite side walls of the first sub-portion 221 along the Y direction are both planes, and two opposite side walls of the second sub-portion 222 along the Y direction are both curved surfaces.

[0157] As shown in Fig. 16d, the two side walls of the first sub-portion 221 opposite to each other along the Y direction both include curved surfaces, and the two side walls of the second sub-portion 222 opposite to each other along the Y direction both include curved surfaces. It should be noted that the phrase "both include curved surfaces" does not mean that the side walls only include curved surfaces, but can also be a combination of curved surfaces and flat surfaces.

[0158] Reference Figure 1, perform step S70: use a deposition process or a growth process to form the second dielectric layer 801 that conformally covers the outer wall of the sub-stack structure and the bottom wall of the first groove as shown in FIG17 and the second electrode layer 802 that conformally covers the second dielectric layer 801. FIG17 is a schematic cross-sectional view of a semiconductor structure including a second dielectric layer 801 and a second electrode layer 802 along line AA' and along line BB' provided by an embodiment of the present disclosure;

[0159] Here, conformal covering means that the shapes of the second dielectric layer 801 and the second electrode layer 802 are the same as the outer wall shapes of the sub-stack structures 103 and the bottom wall surfaces of the first grooves 210 between the sub-stack structures 103 .

[0160] In some embodiments, the thickness of the second dielectric layer 801 and the second electrode layer 802 on the outer walls of the sub-stack structures is the same as the thickness on the bottom wall of the first groove 210 between the sub-stack structures.

[0161] The material of the second dielectric layer 801 includes but is not limited to a high dielectric constant material. A high dielectric constant material refers to a material having a dielectric constant higher than SiO 2 . Generally speaking, the dielectric constant of SiO 2 is 3.7.

[0162] The material of the second electrode layer 802 includes a conductive material, including but not limited to metal ruthenium (Ru), metal tungsten (W) and metal tantalum (Ta).

[0163] In some embodiments, the method for forming a semiconductor structure further includes forming a bit line structure and a word line structure. Figures 18 to 21 The process of forming the bit line structure and the word line structure in the embodiment of the present disclosure is specifically introduced.

[0164] In some embodiments, reference Fig.18 as well as Fig.19 ( Fig.18 A schematic cross-sectional view of a semiconductor structure including a third filling region along line AA' provided in an embodiment of the present disclosure; Fig.19 A schematic cross-sectional view of a semiconductor structure including a bit line structure along line AA' provided in an embodiment of the present disclosure) wherein the method for forming the semiconductor structure further comprises:

[0165] From one side of the two sides of the initial sub-stack structure perpendicular to the X direction and located on the first region 110, a portion of each semiconductor layer 201 of each initial sub-stack structure on the first region 110 is removed by a side etching process to form Fig.18 The third filling region 410 is shown, that is, a portion of each semiconductor layer 201 of each initial sub-stack structure located on the first region 110 is etched from the side of the initial sub-stack structure.

[0166] In some embodiments, after forming the sub-stack structure, a portion of each semiconductor layer of the stack structure located on the first region may be etched from a side of the stack structure to form a third filling region.

[0167] Then, a bit line structure 400 is formed in the third filling region 410 using a deposition process or a growth process, and the bit line structure 400 is connected to the remaining semiconductor layer 201 on the first region 110 .

[0168] The material used for the bit line structure 400 includes a conductive material, such as metal tungsten.

[0169] In some embodiments, the bit line structure may include Fig.19 The bit line 403, the adhesion layer 402 and the bit line contact structure 401 are shown. The process of forming the bit line structure 400 may include: performing metallization treatment on the remaining semiconductor layer 201 exposed from the third filling region 410 to form the bit line contact structure 401. The bit line contact structure 401 is used to reduce the contact resistance between the bit line 403 and the transistor subsequently formed in the semiconductor layer 201.

[0170] Continue to use the deposition process or the growth process to form an adhesion layer 402 on the sidewall of the third filling region 410 where the bit line contact structure 401 is formed. The material of the adhesion layer 402 includes but is not limited to titanium nitride. The adhesion layer 402 has good adhesion and can be used to adhere the bit line 403 and the bit line contact structure 401.

[0171] It should be noted that the bit line structure 400 may be formed before or after the capacitor is formed, which is not limited in the embodiments of the present disclosure.

[0172] The deposition process or the growth process is continued to be used to form the bit line 403 in the remaining third filling region 410. The material used for the bit line 403 includes a conductive material, including but not limited to tungsten.

[0173] In some embodiments, reference Fig.18 and Fig. 20 ( Fig. 20 A schematic cross-sectional view of a semiconductor structure including a word line structure along line AA' provided in an embodiment of the present disclosure) wherein the method for forming the semiconductor structure further comprises:

[0174] use Fig.18 The remaining portion of each semiconductor layer 201 on the first region 110 shown forms a plurality of transistors. Here, the remaining portion refers to the semiconductor layer 201 in the first region 110 that has not been removed.

[0175] In some embodiments, transistors may be formed first, and then the bit line structure 400 may be formed. For example, after forming the third filling region 410, doping may be performed at both ends along the X direction to form a source and a drain, thereby forming a plurality of transistors, wherein the semiconductor layer 201 between the source and the drain constitutes a channel region of the transistor, and the transistor is connected to the first electrode layer 600;

[0176] In some embodiments, the bit line structure 400 may be formed first, and then the transistor may be formed. Ion implantation may be performed along the Z direction on both ends of the remaining portion of each semiconductor layer 201 on the first region 110, where the concentration of the implanted ions in the semiconductor layers 201 at different depths may be the same.

[0177] In some embodiments, it may further include forming a plurality of word line structures 500, the plurality of word line structures 500 are arranged along the Y direction, each word line structure 500 extends along the thickness direction of the substrate, and a word line structure 500 is connected to the channel regions of the plurality of transistors in a first portion. In some specific examples, a word line structure 500 may cover two opposite side walls of the channel region of each transistor in a first portion along the Y direction.

[0178] The process of forming the word line structure 500 may be: Fig. 20 A word line contact structure 501 is formed on the upper surface of the third dielectric layer 310 and the exposed surface of the channel regions of the multiple transistors (not shown). The material of the word line contact structure 501 can be titanium nitride. Titanium nitride has good adhesion and can be used to adhere the third dielectric layer 310 and the word line 502.

[0179] Then, a word line 502 is formed on the word line contact structure 501. The material used for the word line 502 includes a conductive material, such as metal tungsten.

[0180] In some embodiments, a mask layer 503 may be formed on the word line structure 500, and then, as shown in FIG. Fig.21 As shown ( Fig.21 A schematic cross-sectional view of a semiconductor structure including a mask layer along line AA' provided in an embodiment of the present disclosure can form a plurality of first grooves by etching the mask layer 503, wherein at the junction of the first portion and the second portion, the side wall of the second portion can be covered with the third dielectric layer 310 or can be uncovered with the third dielectric layer 310.

[0181] The portion of the mask layer 503 located on the first region 110 is retained, and the retained mask layer 503 can protect the word line structure 500 in subsequent processes.

[0182] It is understandable that the order of forming the transistor, forming the bit line structure 400, forming the word line structure 500, and forming the capacitor can be adjusted according to the actual process. The order of forming the above structures is not limited here.

[0183] Based on the same concept as the method for forming the semiconductor structure in the aforementioned embodiments, the embodiments of the present disclosure further provide a semiconductor structure, which can be obtained by the method for forming the semiconductor structure in any of the aforementioned embodiments.

[0184] like Fig. 22 as well as Fig.23 As shown, the semiconductor structure comprises:

[0185] A substrate 100 and a stacking structure located on the substrate 100; the stacking structure includes a first electrode layer 600 and a first dielectric layer 320 that are alternately stacked; the stacking structure includes a plurality of sub-stacked structures 103, each of which extends along a first direction, and the plurality of sub-stacked structures 103 are arranged along a second direction; at least one of the two side walls of each sub-stacked structure 103 that are opposite to each other along the second direction includes at least a curved surface, and the two side walls of each sub-stacked structure 103 that are opposite to each other along the thickness direction of the substrate 100 are planes parallel to the substrate; the first direction intersects with the second direction and is perpendicular to the thickness direction of the substrate; in the embodiment of the present disclosure, the first direction may be an X direction, the second direction may be a Y direction, and the thickness direction of the substrate may be a Z direction.

[0186] The second dielectric layer 801 conformally covers the outer wall of each sub-stack structure 103 and the bottom surface of the first groove formed between two adjacent sub-stack structures 103;

[0187] The second electrode layer 802 conformally covers the second dielectric layer 801 .

[0188] Fig. 22 A schematic cross-sectional view of a semiconductor structure along line AA' and a schematic cross-sectional view along line BB' provided by an embodiment of the present disclosure; Fig.23 A top view of a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0189] In the technical solution provided by the present disclosure, the first electrode layer of the stacked structure can be used as the lower electrode of the capacitor, the second dielectric layer can be used as the dielectric layer of the capacitor, and the second electrode layer can be used as the upper electrode of the capacitor. In addition, at least one of the two side walls of the sub-stacked structure opposite to each other along the second direction includes at least a curved surface. In the first aspect, compared with the two side walls of the sub-stacked structure opposite to each other along the second direction being planes, the area of ​​the first electrode layer is enlarged, and the second dielectric layer is conformally covered on the outer wall of each sub-stacked structure and the bottom surface of the first groove formed between the two adjacent sub-stacked structures. The second electrode layer conformally covers the second dielectric layer, thereby correspondingly enlarging the area of ​​the second dielectric layer and the second electrode layer, thereby increasing the capacitance of the capacitor and improving the storage capacity of the capacitor; in the second aspect, since at least one of the two side walls of the sub-stacked structure opposite to each other along the second direction includes at least a curved surface, more space is left for the second electrode layer and the first dielectric layer, so that the integration of the semiconductor structure can be improved; in the third aspect, the distance between the first electrode layers of the capacitors adjacent to each other along the second direction becomes relatively far, so that the coupling effect between adjacent capacitors can be reduced.

[0190] In some embodiments, reference Fig.10 , Fig. 22 , the substrate 100 includes a first region 110 and a second region 120 arranged in parallel along the X direction; each sub-stack structure 103 includes a first portion 101 located on the first region 110 and a second portion 102 extending to the second region 120, the second portion 102 includes alternately stacked first electrode layers 600 and first dielectric layers 320, and the first portion 101 includes the first dielectric layer 320. The second dielectric layer 801 and the second electrode layer 802 are located between adjacent second portions 102;

[0191] At least one of the two side walls of the second portion 102 that are opposite to each other along the Y direction comprises at least a curved surface; and the two side walls of the first portion 101 that are opposite to each other along the Y direction are planes parallel to the X direction.

[0192] In the embodiment of the present disclosure, since the second dielectric layer 801 and the second electrode layer 802 are located between adjacent second parts 102, at least one of the two side walls of the second part 102 in the sub-stack structure that are opposite to each other along the Y direction includes at least a curved surface. This expands the area of ​​the first electrode layer relative to the two side walls of the second part 102 in the sub-stack structure that are opposite to each other along the Y direction and are both planes. The second dielectric layer conformally covers the outer wall of each sub-stack structure and the bottom surface of the first groove formed between two adjacent sub-stack structures, and the second electrode layer conformally covers the second dielectric layer, thereby correspondingly expanding the areas of the second dielectric layer and the second electrode layer, thereby increasing the capacity of the capacitor and improving the storage capacity of the capacitor.

[0193] In some embodiments, referring to Figures 16a to 16d, the sub-stack structure 103 includes a first sub-portion 221 and a second sub-portion 222 arranged alternately along the X direction; at least one of the two opposite side walls of the first sub-portion 221 along the Y direction and the two opposite side walls of the second sub-portion 222 along the Y direction is a curved surface.

[0194] 16a to 16d show four schematic diagrams of the sub-stack structure 103 including the first sub-portions 221 and the second sub-portions 222 alternately arranged along the X direction. It should be noted that the top view of the sub-stack structure 103 is not limited thereto.

[0195] In the embodiment of the present disclosure, by setting at least one of the two side walls of the first sub-part 221 opposite to each other along the Y direction and the two side walls of the second sub-part 222 opposite to each other along the Y direction as a curved surface, the area of ​​the first electrode layer is expanded compared to the two side walls of the first sub-part 221 opposite to each other along the Y direction and the two side walls of the second sub-part 222 opposite to each other along the Y direction being set as a plane, and the second dielectric layer is conformally covered on the outer wall of each sub-stack structure and the bottom surface of the first groove formed between two adjacent sub-stack structures, and the second electrode layer conformally covers the second dielectric layer, thereby correspondingly expanding the area of ​​the second dielectric layer and the second electrode layer, thereby increasing the capacitance of the capacitor and improving the storage capacity of the capacitor; on the second hand, since at least one of the two side walls of the sub-stack structure opposite to each other along the second direction includes at least a curved surface, more space is reserved for the second electrode layer and the first dielectric layer, so that the integration of the semiconductor structure can be improved; on the third hand, the distance between the first electrode layers of the capacitors adjacent to each other along the second direction becomes relatively far, so that the coupling effect between adjacent capacitors can be reduced.

[0196] In some embodiments, referring to FIGS. 16a to 16d , the curved surface is parallel to the thickness direction of the substrate 100, and the curved surface is concave toward the other side wall of the sub-stacked structure 103 along the Y direction. Compared with setting the curved surface convex toward the other side wall of the sub-stacked structure 103 along the Y direction, setting the curved surface concave toward the other side wall of the sub-stacked structure 103 along the Y direction in the embodiment of the present disclosure is easier to implement in the actual process, reducing the process difficulty. Of course, setting the curved surface convex toward the other side wall of the sub-stacked structure 103 along the Y direction is also optional.

[0197] In some embodiments, reference Fig. 22 and Fig.23 , the first part 101 further includes: a plurality of transistors 800; each transistor 800 is located between two adjacent first dielectric layers 320 in the first part 101, and each transistor 800 includes a source and a drain at two opposite ends along the X direction, and a channel region located between the source and the drain;

[0198] A plurality of word line structures 500 ; each word line structure 500 extends along the thickness direction of the substrate 100 , and one word line structure 500 is connected to the channel regions of the plurality of transistors 800 in one first portion 101 .

[0199] In some embodiments, reference Fig. 22 and Fig.23 The first part 101 also includes: a plurality of bit line structures 400, each bit line structure 400 extends along the Y direction, and each bit line structure 400 is located between two first dielectric layers 320 adjacent to each other along the Z direction, and is connected to the source or drain of a plurality of transistors 800 in one layer, and the transistor 800 is connected to the first electrode layer 600.

[0200] In the disclosed embodiment, the first region 110 further includes a plurality of word line structures 500, a plurality of bit line structures 400, and a plurality of transistors 800. A layer of a plurality of transistors 800 is connected to the same bit line structure 400. Here, a layer refers to being located on the same XY plane. A column of a plurality of transistors 800 is connected to the same word line structure 500, and here, a column refers to being located on the same XZ plane.

[0201] By applying corresponding operating voltages to the word line structure 500 and the bit line structure 400 , various operations on the transistor 800 and the capacitor, such as programming operations, read / write operations, and erase operations, can be implemented.

[0202] In some embodiments, reference Fig. 22 Each first electrode layer 600 in each sub-stack structure 103 includes a first sub-electrode layer 601 and a second sub-electrode layer 602 arranged at intervals along the Y direction, and the first electrode layer 600 also includes a first connecting structure 603 located between the first sub-electrode layer 601 and the second sub-electrode layer 602.

[0203] In the embodiment of the present disclosure, the first electrode layer 600 may be a sandwich structure of a first sub-electrode layer 601, a first connection structure 603, and a second sub-electrode layer 602. The material used for the first connection structure 603 may be a metal silicide, which is used to reduce the contact resistance between the sub-electrode layers (including the first sub-electrode layer 601 and the second sub-electrode layer 602) and the active pillars.

[0204] The above semiconductor structure has been introduced in detail in the part of the method for forming the semiconductor structure, and will not be described again here.

[0205] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0206] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include A substrate and a stacking structure located on the substrate; the stacking structure comprises a first electrode layer and a first dielectric layer alternately stacked; the stacking structure comprises a plurality of sub-stacked structures, each of the sub-stacked structures extends along a first direction, and the plurality of sub-stacked structures are arranged along a second direction; at least one of the two side walls opposite to each other along the second direction of each sub-stacked structure comprises at least a curved surface, and the two side walls opposite to each other along the thickness direction of the substrate of each sub-stacked structure are planes parallel to the substrate; the first direction intersects with the second direction and is perpendicular to the thickness direction of the substrate; A second dielectric layer conformally covers the outer wall of each of the sub-stacked structures and the bottom surface of the first groove formed between two adjacent sub-stacked structures; The second electrode layer conformally covers the second dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: The substrate comprises a first region and a second region arranged in parallel along the first direction; each of the sub-stack structures comprises a first portion located on the first region and a second portion extending to the second region, the second portion comprises first electrode layers and first dielectric layers alternately stacked, the first portion comprises the first dielectric layer, and the second dielectric layer and the second electrode layer are located between adjacent second portions; At least one of the two side walls of the second part that are opposite to each other along the second direction comprises at least a curved surface; and the two side walls of the first part that are opposite to each other along the second direction are planes parallel to the first direction.

3. The semiconductor structure according to claim 1, characterized in that: The sub-stack structure includes first sub-parts and second sub-parts alternately arranged along a first direction; at least one of two opposite side walls of the first sub-part along the second direction and two opposite side walls of the second sub-part along the second direction is a curved surface.

4. The semiconductor structure according to claim 3, characterized in that: The curved surface is parallel to the thickness direction of the substrate, and the curved surface is concave toward another side wall of the sub-stack structure opposite to the second direction.

5. The semiconductor structure according to claim 2, characterized in that: The first part further includes: a plurality of transistors; each of the transistors is located between two adjacent first dielectric layers in the first part, and each of the transistors includes a source and a drain at two opposite ends along a first direction, and a channel region located between the source and the drain; A plurality of word line structures; each of the word line structures extends along the thickness direction of the substrate, and one of the word line structures is connected to the channel regions of the plurality of transistors in the first portion.

6. The semiconductor structure according to claim 5, characterized in that: The first part also includes: multiple bit line structures, each of which extends along the second direction, and each of which is located between two adjacent first dielectric layers along the thickness direction of the substrate, and is connected to the source or drain of multiple transistors in one layer, and the transistors are connected to the first electrode layer.

7. The semiconductor structure according to claim 1, characterized in that: Each of the first electrode layers in each of the sub-stacked structures includes a first sub-electrode layer and a second sub-electrode layer arranged at intervals along the second direction, and the first electrode layer also includes a first connection structure located between the first sub-electrode layer and the second sub-electrode layer.

8. A method for forming a semiconductor structure, characterized in that: include: forming an initial stacking structure of semiconductor layers and sacrificial layers alternately stacked on a substrate; A plurality of first grooves are formed that penetrate the initial stacking structure, each of the first grooves extends along a first direction, and the plurality of first grooves are arranged along a second direction; the first grooves divide the initial stacking structure into a plurality of initial sub-stacked structures arranged along the second direction, and at least one of the two side walls of each initial sub-stacked structure that are opposite to each other along the second direction includes at least a curved surface; the first direction intersects with the second direction and is perpendicular to the thickness direction of the substrate; removing the sacrificial layer to form a first filling area; forming a first dielectric layer in the first filling region; removing at least a portion of each semiconductor layer in each of the initial sub-stack structures to form a second filling region; forming a first electrode layer in the second filling region to form a sub-stack structure; A second dielectric layer conformally covering the outer wall of the sub-stack structure and the bottom wall of the first groove and a second electrode layer conformally covering the second dielectric layer are formed.

9. The forming method according to claim 8, characterized in that: The substrate comprises a first region and a second region arranged in parallel along the first direction, the first groove extends from the first region to the second region, each of the initial sub-stack structures comprises a first portion located on the first region and a second portion extending to the second region, at least one of two side walls of the second portion opposite to each other along the second direction comprises at least a curved surface; and the two side walls of the first portion opposite to each other along the second direction are planes parallel to the first direction; The removing at least a portion of each semiconductor layer in each of the initial sub-stack structures comprises: removing at least a portion of each semiconductor layer in each of the second portions along the first groove; A metallization process is performed on the semiconductor layer remaining on the second region to form a first connection structure.

10. The forming method according to claim 9, characterized in that: The first electrode layer includes a first sub-electrode layer and a second sub-electrode layer arranged at intervals along the second direction, the first electrode layer also includes a first connection structure located between the first sub-electrode layer and the second sub-electrode layer, and the metallization treatment is performed on the semiconductor layer remaining on the second region to form the first connection structure, including: After removing at least a portion of each semiconductor layer in each of the initial sub-stack structures, forming a first metal layer on the sidewalls of the remaining semiconductor layer on the second region; Through a heat treatment process, the remaining semiconductor layer and a portion of the first metal layer on the second region form the first connection structure; The remaining first metal layer is removed to form the second filling region.

11. The forming method according to claim 9, characterized in that: The method further comprises: After forming a plurality of first grooves penetrating the stack structure, removing a portion of each semiconductor layer of each of the initial sub-stack structures on the first region from one side of the stack structure located on the first region and perpendicular to the first direction, to form a third filling region; A bit line structure is formed in the third filling region, and the bit line structure is connected to the semiconductor layer remaining on the first region.

12. The forming method according to claim 11, characterized in that: The method further comprises: Performing doping treatment on the remaining portion of each semiconductor layer on the first region at both ends along the first direction to form a source and a drain, thereby forming a plurality of transistors, wherein the semiconductor layer between the source and the drain constitutes a channel region of the transistor, and the transistor is connected to the first electrode layer; A plurality of word line structures are formed, each of the word line structures extending along the thickness direction of the substrate, and one of the word line structures is connected to the channel regions of the plurality of transistors in one first portion.

13. The forming method according to claim 8, characterized in that: The sub-stack structure comprises a first sub-section and a second sub-section arranged alternately along a first direction; at least one of two side walls of the first sub-section opposite to each other along the second direction and two side walls of the second sub-section opposite to each other along the second direction is a curved surface; The forming of a plurality of first grooves penetrating the initial stacking structure comprises: Forming a plurality of first strip-shaped grooves penetrating the initial stacking structure, each of the first strip-shaped grooves extending along a first direction, and the plurality of first strip-shaped grooves arranged along a second direction; Filling a sacrificial filling layer in the first strip-shaped groove; Forming a hole-shaped groove penetrating the sacrificial filling layer and the remaining initial stacking structure, wherein the hole-shaped groove and the strip-shaped groove constitute the first groove, the size of the hole-shaped groove along the second direction is larger than the size of the strip-shaped groove along the second direction, and the hole-shaped grooves are arranged in an array along the first direction and the second direction at intervals; The remaining sacrificial filling layer is removed.

14. The forming method according to claim 8, characterized in that: The step of removing the sacrificial layer to form a first filling region comprises: forming a third dielectric layer in the first groove; Removing a portion of the third dielectric layer to form a second groove penetrating the stacked structure, wherein the second groove exposes a portion of the sidewall of the sacrificial layer; removing the sacrificial layer with exposed sidewalls to form a first sub-filling region; forming a portion of the first dielectric layer in the first sub-filling region; removing the remaining third dielectric layer to form a third groove penetrating the stacked structure, wherein the third groove exposes the remaining sidewall of the sacrificial layer; removing the remaining sacrificial layer to form a second sub-filling area; Another portion of the first dielectric layer is formed in the second sub-filling region.

15. The forming method according to claim 8, characterized in that: The first groove penetrates the stack structure and extends into the substrate; The removing at least a portion of each semiconductor layer in each of the initial sub-stack structures to form a second filling region comprises: A portion of each semiconductor layer and a portion of the substrate in each of the initial sub-stack structures are removed to form the second filling region.

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