Semiconductor device structure and preparation method thereof

Abstract

The invention discloses a semiconductor device structure and a preparation method thereof. The method comprises the following steps: forming a shallow trench isolation piece on a semiconductor substrate; forming a plurality of bit line structures distributed in an array on the shallow trench isolation piece; the bit line structure comprises a bit line and bit line side walls positioned on opposite side walls of the bit line; depositing a semiconductor material layer on the plurality of bit line structures; partial back etching is carried out on the top of the semiconductor material layer, and then the outer layer and the middle layer of the bit line side wall and the semiconductor material layer are partially removed by using a wet etching process to form a buried contact part; and depositing a metal filling layer on the bit line structure buried contact part, and performing partial back etching on the metal filling layer. According to the invention, the LP technology is removed, and the outer layer and the middle layer of the bit line structure side wall are partially removed only through the wet etching technology after partial back etching, so that the area of the top part of the contact part is maximized, the contact area of the capacitor is ensured, the technology efficiency is improved, and the cost is saved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor device structure and a preparation method thereof. Background Art

[0002] DRAM (Dynamic Random Access Memory) is a semiconductor memory that is widely used in various electronic devices. In the DRAM manufacturing process, directly connecting the connection terminal between the capacitor (SN, storage node) and the shallow trench isolation (STI) on the storage node contact (SNC) has the defect of insufficient capacitor contact area. Therefore, the contact area of ​​the capacitor is increased by adding a landing pad (Land PAD, LP) process to connect SN and SNC.

[0003] However, the LP process is very complicated, including multiple process steps such as LP Patterning (up to 30 to 40 process steps), which will lead to greatly reduced process efficiency and high process cost. Summary of the invention

[0004] In order to solve the problems of complex process, low process efficiency and high cost in the existing technology of DRAM manufacturing using LP process, the present invention proposes a semiconductor device structure and a preparation method thereof. The present invention cancels the LP process and only adopts the method of Wet Enlarge to increase the area of ​​the Burried Contact Top part. Since the LP process is omitted, the process steps are reduced, the process efficiency is improved, and the process cost is saved.

[0005] The present invention is achieved through the following technical solutions:

[0006] A semiconductor device structure and a method for preparing the same, the method comprising the following steps:

[0007] providing a semiconductor substrate;

[0008] forming a shallow trench isolation member on the semiconductor substrate;

[0009] A plurality of bit line structures distributed in an array are formed on the shallow trench isolation member; the bit line structure comprises a bit line and a bit line sidewall located on the opposite sidewalls of the bit line; the bit line sidewall is a three-layer structure, the outer layer and the inner layer are both nitride layers, and the middle layer is an oxide layer;

[0010] depositing a semiconductor material layer on the plurality of bit line structures;

[0011] Partially etching back the top of the semiconductor material layer, and then partially removing the outer layer, the middle layer and the semiconductor material layer of the bit line sidewall by a wet etching process to form a buried contact portion; the top surface of the buried contact portion is located between the top surface of the bit line and the ground;

[0012] A metal filling layer is deposited on the buried contact portion of the bit line structure, and a portion of the metal filling layer is etched back.

[0013] In the preparation of DRAM devices, the LP process is usually used to increase the contact area of ​​the capacitor and realize the connection between the capacitor and the buried contact part. However, the LP process is complicated and includes more than 30 process steps, which leads to low preparation process efficiency and high process cost. The present application removes the LP process and only partially removes the outer layer and the middle layer of the side wall of the bit line structure by using a wet etching process after partial back etching, thereby maximizing the area of ​​the top part of the contact part and ensuring the contact area of ​​the capacitor. At the same time, due to the cancellation of the LP process, the process steps are greatly reduced, the process efficiency is improved, and the cost is saved.

[0014] In addition, the present application deposits a metal layer above the buried contact portion to reduce resistance and further improve process efficiency.

[0015] As a preferred embodiment, the step of forming a shallow trench isolation member on a semiconductor substrate of the present invention further includes:

[0016] Using a dry etching process to carve an isolation trench with a depth of 0.3 to 0.8 μm on the surface of the semiconductor substrate;

[0017] Growing a linear oxide layer on the surface of the isolation trench and filling it with CVD oxygen;

[0018] The shallow trench isolation is formed by CMP polishing.

[0019] The present application adopts the STI process to form a shallow trench isolation component, thereby improving the depth-to-width ratio of the isolation trench and ensuring the performance of the DRAM device.

[0020] As a preferred embodiment, the step of forming a plurality of bit line structures distributed in an array on the shallow trench isolation member of the present invention further includes:

[0021] sequentially depositing a metal layer and a mask layer above the shallow trench isolation member;

[0022] Sequentially etching the mask layer and the metal layer from top to bottom to form a plurality of bit lines distributed in an array;

[0023] An insulating material layer is deposited above the plurality of bit lines, and the insulating material layer is etched into bit line sidewalls located on opposite side walls of the plurality of bit lines to form a bit line structure.

[0024] As a preferred embodiment, the metal layer of the present invention is made of tungsten; and the mask layer is made of silicon nitride.

[0025] As a preferred embodiment, the top surface of the buried contact portion of the present invention is located at half the height of the bit line structure.

[0026] As a preferred embodiment, the semiconductor substrate of the present invention is a silicon wafer;

[0027] The semiconductor material layer is made of silicon;

[0028] The metal filling layer is made of tungsten.

[0029] As a preferred embodiment, the present invention adopts a partial etching back process or CMP to partially etch back the metal filling layer.

[0030] As a preferred embodiment, the wet etching process of the present invention adopts HF Based Etchant or phosphoric acid method.

[0031] In a second aspect, the present invention provides a semiconductor device structure, which is prepared using the preparation method described in the present invention.

[0032] In a third aspect, the present invention provides a DRAM device structure, which is prepared by the preparation method described in the present invention.

[0033] The present invention has the following advantages and beneficial effects:

[0034] In the preparation of DRAM devices, the LP process is usually used to increase the contact area of ​​the capacitor and realize the connection between the capacitor and the buried contact part. However, the LP process is complicated and includes more than 30 process steps, which leads to low preparation process efficiency and high process cost. Compared with using the LP process to increase the contact area of ​​the capacitor, the semiconductor preparation method provided by the present invention only partially removes the outer layer and the middle layer of the side wall of the bit line structure by a wet etching process after partial back etching, thereby maximizing the area of ​​the top part of the contact part and ensuring the contact area of ​​the capacitor. At the same time, since the LP process is cancelled, the DRAM device manufacturing process is greatly reduced, the manufacturing process efficiency is improved, and the cost is saved.

[0035] The semiconductor manufacturing method proposed by the present invention forms shallow trench isolation by using the STI process, thereby improving the depth-to-width ratio of the isolation trench and ensuring the performance of the DRAM device.

[0036] The semiconductor manufacturing method proposed in the present invention has better resistance performance and further improves process efficiency by depositing a metal layer above the contact portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0038] Figure 1 This is a flow chart of the existing LP process.

[0039] Figure 2 It is a cross-sectional diagram of the existing process implemented using LP technology.

[0040] Figure 3 The figure is a flow chart of a method according to an embodiment of the present invention.

[0041] Figure 4 It is a cross-sectional view of the implementation process of the embodiment of the present invention.

[0042] Marks and corresponding parts names in the attached drawings:

[0043] 101-semiconductor substrate, 102-shallow trench isolation (STI), 103-bit line structure (Bit Line), 110-bit line, 111-metal layer, 112-mask layer, 120-bit line sidewall (NON structure), 104-semiconductor material layer, 105-first buried contact, 106-landing pad (Landing PAD, LP), 107-second buried contact, 108-metal filling layer. DETAILED DESCRIPTION

[0044] Hereinafter, the term "include" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present invention, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0045] In various embodiments of the present invention, the expression "or" or "at least one of A or / and B" includes any combination or all combinations of the words listed at the same time. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0046] The expressions (such as "first", "second", etc.) used in various embodiments of the present invention may modify the various constituent elements in various embodiments, but may not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used for the purpose of distinguishing an element from other elements. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, without departing from the scope of various embodiments of the present invention, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0047] It should be noted that if it is described that one component element is “connected” to another component element, the first component element may be directly connected to the second component element, and a third component element may be “connected” between the first component element and the second component element. Conversely, when one component element is “directly connected” to another component element, it can be understood that there is no third component element between the first component element and the second component element.

[0048] The terms used in various embodiments of the present invention are only used for the purpose of describing specific embodiments and are not intended to limit various embodiments of the present invention. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise limited, all terms used here (including technical terms and scientific terms) have the same meaning as the meaning generally understood by those of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as the terms defined in the dictionary generally used) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in various embodiments of the present invention.

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0050] Example

[0051] In the manufacturing process of DRAM devices, the LP process is usually used to connect the capacitor and the buried contact. The process is as follows: Figure 1-2As shown, a semiconductor substrate 101 (silicon wafer) is provided. First, isolation trenches with a depth of 0.3 to 0.8 μm are etched on the surface of the semiconductor substrate 101 by dry etching. These isolation trenches have right angles and rounded corners, and the depth-to-width ratio of the isolation trenches is about 2:1 to 5:1. A linear oxide layer is grown on the surface of the isolation trench, filled with CVD oxygen, and polished by CMP to form a shallow trench isolation (STI) 102; then, a plurality of array-distributed bit line structures 103 are formed on the shallow trench isolation STI 102, wherein the bit line structure 103 includes A metal layer 111 (which may be a metal material with good thermal conductivity such as tungsten) and a mask layer 112 (which may be a nitride, such as silicon nitride) are sequentially deposited above 102, and then the mask layer 112 and the metal layer 111 are sequentially etched from top to bottom to form a plurality of array-distributed bit lines 110; finally, an insulating material layer is deposited above the plurality of bit lines 110, and then the insulating material layer is etched into a bit line sidewall 120 located on the opposite side walls of the plurality of bit lines 110 to form a bit line structure 103, wherein the bit line sidewall 120 may be a multilayer structure of nitride-oxide-nitride (i.e., a NON structure, in which the outer layer and the inner layer are both nitride, and the middle layer is oxide), and finally a semiconductor material layer 104 (silicon) is deposited on the plurality of bit line structures 103 to obtain a structure such as Figure 2 Then the semiconductor material layer 104 is partially etched to form a first buried contact portion 105, the top surface of the first buried contact portion 105 can be located between the top surface and the bottom surface of the mask layer 112, and the bottom end of the first buried contact portion 105 is connected to the STI 102, to obtain Figure 2 Finally, after forming the first buried contact 105, a landing pad 106 is formed above the bit line structure 103 and the first buried contact 105, to obtain Figure 2 The structure shown in (c); after the landing pad LP is formed, the capacitor Capacitor (CAP) is connected to the STI 102 through the landing pad LP. The existing method of connecting the capacitor to the buried contact through LP is very complicated because the LP process includes 30 to 40 process steps including the pad patterning process, resulting in low manufacturing process efficiency and high cost. Based on this, the present embodiment provides a method for preparing a semiconductor device structure, which cancels the LP process. The method deposits a polysilicon structure on the mask contact, and then removes a portion of the insulating material layer through a partial back etching process, and then removes the outer nitride and the middle oxide of the bit line side wall through a wet etching process, thereby maximizing the top area of ​​the mask contact and ensuring the contact area of ​​the capacitor. At the same time, since the LP process is not used, the process complexity is reduced, the process efficiency is improved, and the process cost is reduced.

[0052] Specific as Figure 3-4As shown, the preparation method proposed in this embodiment includes the following steps:

[0053] Step 1, providing a semiconductor substrate 101, forming a polysilicon structure on the semiconductor substrate 101, and obtaining Figure 4 The structure shown in (a).

[0054] The process is the same as the prior art, specifically including:

[0055] First, isolation trenches with a depth of 0.3 to 0.8 μm are etched on the surface of the semiconductor substrate 101 by dry etching. These isolation trenches have right angles and rounded corners. A linear oxide layer is grown on the surface of the isolation trench, filled with CVD oxygen, and smoothed by CMP to form a shallow trench isolation (STI) 102.

[0056] Then, a bit line structure 103 is formed on the shallow trench isolation STI 102, wherein the bit line structure 103 includes a metal layer 111 and a mask layer 112 sequentially deposited above the STI 102, and then the mask layer 112 and the metal layer 111 are sequentially etched from top to bottom to form a plurality of bit lines 110 distributed in an array; an insulating material layer is deposited above the plurality of bit lines 110, and then the insulating material layer is etched into a bit line sidewall 120 located on the opposite side walls of the plurality of bit lines 110 to form the bit line structure 103, and finally a semiconductor material layer 104 is deposited on the plurality of bit line structures 103; specifically, the bit line sidewall 120 adopts a multilayer structure in which both the outer layer and the inner layer are nitride layers and the middle layer is an oxide layer, i.e., a NON structure.

[0057] Step 2, partially etch back the polysilicon structure through a polysilicon partial etch back process, and then partially remove the outer nitride layer, the middle oxide layer and the contact part of the bit line structure through a wet etching process to obtain Figure 4 The structure shown in (b).

[0058] Specifically, the top of the semiconductor material layer 104 is partially etched back, and then the outer layer (nitride layer), the middle layer (oxide layer) and the semiconductor material layer 104 of the bit line spacer 120 are removed by a wet etching process, thereby forming a second buried contact 107, and the second buried contact 107 can be located between the top surface and the bottom surface of the mask layer 112. Preferably, the top surface of the second buried contact 107 is located at half the height of the bit line structure 103; then, the bit line spacer 120 is wet etched to remove the outer nitride layer and the middle oxide layer, so as to maximize the area of ​​the top of the buried contact, and obtain the following: Figure 4 Preferably, the wet etching process can adopt HF Based Etchant or phosphoric acid method.

[0059] Step 3, depositing a metal filling layer 108 on the bit line structure 103 and the second buried contact portion 107, and finally partially etching back the metal filling layer 108 by using an etching back process or CMP to obtain Figure 4 By depositing a metal layer on the bit line structure 103 and the second buried contact portion 107, the metal layer can be made of a material with good thermal conductivity such as tungsten to reduce the barrier and further improve the process efficiency.

[0060] In the preparation of DRAM devices, the LP process is usually used to increase the contact area of ​​the capacitor and realize the connection between the capacitor and the buried contact part. However, the LP process is complex and includes more than 30 process steps, which leads to low efficiency and high process cost of the preparation process. The preparation method proposed in the embodiment of the present invention only uses a wet etching process on the top of the contact part to increase the area of ​​the top part of the contact part, thereby realizing the manufacture of DRAM without the LP process. Since the preparation method proposed in the embodiment of the present invention does not use the LP process, all LP-related processes are cancelled in the DRAM manufacturing process. For example, two patterning processes are cancelled, which effectively reduces the process complexity, improves the process efficiency, and reduces the process cost.

[0061] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device structure, characterized in that: The method comprises the following steps: providing a semiconductor substrate; forming a shallow trench isolation member on the semiconductor substrate; A plurality of bit line structures distributed in an array are formed on the shallow trench isolation member; the bit line structure comprises a bit line and a bit line sidewall located on the opposite sidewalls of the bit line; the bit line sidewall is a three-layer structure, the outer layer and the inner layer are both nitride layers, and the middle layer is an oxide layer; depositing a semiconductor material layer on the plurality of bit line structures; Partially etching back the top of the semiconductor material layer, and then partially removing the outer layer, the middle layer and the semiconductor material layer of the bit line sidewall by a wet etching process to form a buried contact portion; the top surface of the buried contact portion is located between the top surface of the bit line and the ground; A metal filling layer is deposited on the buried contact portion of the bit line structure, and a portion of the metal filling layer is etched back.

2. The method for preparing a semiconductor device structure according to claim 1, characterized in that: The step of forming a shallow trench isolation member on the semiconductor substrate further includes: Using a dry etching process to carve an isolation trench with a depth of 0.3 to 0.8 μm on the surface of the semiconductor substrate; Growing a linear oxide layer on the surface of the isolation trench and filling it with CVD oxygen; The shallow trench isolation is formed by CMP polishing.

3. The method for preparing a semiconductor device structure according to claim 1, characterized in that: The step of forming a plurality of bit line structures distributed in an array on the shallow trench isolation element also includes: sequentially depositing a metal layer and a mask layer above the shallow trench isolation member; Sequentially etching the mask layer and the metal layer from top to bottom to form a plurality of bit lines distributed in an array; An insulating material layer is deposited above the plurality of bit lines, and the insulating material layer is etched into bit line sidewalls located on opposite side walls of the plurality of bit lines to form a bit line structure.

4. The method for preparing a semiconductor device structure according to claim 3, characterized in that: The metal layer is made of tungsten; the mask layer is made of silicon nitride.

5. The method for preparing a semiconductor device structure according to claim 1, characterized in that: A top surface of the buried contact is located at one-half the height of the bit line structure.

6. A method for preparing a semiconductor device structure according to any one of claims 1 to 5, characterized in that: The semiconductor substrate is a silicon wafer; The semiconductor material layer is made of silicon; The metal filling layer is made of tungsten.

7. A method for preparing a semiconductor device structure according to any one of claims 1 to 5, characterized in that: The metal filling layer is partially etched back by using a partial etch-back process or CMP.

8. A method for preparing a semiconductor device structure according to any one of claims 1 to 5, characterized in that: The wet etching process adopts HF Based Etchant or phosphoric acid method.

9. A semiconductor device structure, characterized in that: The preparation method is described in any one of claims 1 to 8.

10. A DRAM device structure, characterized in that: The preparation method is described in any one of claims 1 to 8.

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