Microelectronic device and related memory device and electronic system

Abstract

The invention relates to a microelectronic device and a related memory device and an electronic system. A microelectronic device includes: a memory array region including a vertical stack of dynamic random access memory (DRAM) cells, each of the DRAM cells including a storage device in the vertical stack of storage devices and a horizontally adjacent access device in the vertical stack of access devices; and a step region substantially horizontally adjacent to the memory array region in a first horizontal direction and comprising: a vertical stack of first conductive structures extending horizontally through the step region in the first horizontal direction, the first conductive structures in contact with the first DRAM cell and the second DRAM cell; and sub-step structures individually including a second conductive structure in contact with the first conductive structure and extending horizontally from the first conductive structure in a second horizontal direction substantially perpendicular to the first horizontal direction, each of the sub-step structures individually including at least four steps, each step is defined at a horizontal boundary of the second conductive structure defining the step.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 63 / 516,076, filed on July 27, 2023, entitled “MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS” and also claims the benefit of the filing date of U.S. patent application serial number 18 / 754,652, filed on June 26, 2024, entitled “MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS”. Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to microelectronic devices and related memory devices and electronic systems that include a staircase structure horizontally adjacent to a memory array region, the staircase structure being operably associated with vertically stacked memory cells of the memory array region. Background Art

[0004] Microelectronic device designers generally desire to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the spacing distance between adjacent features. In addition, microelectronic device designers generally seek to design architectures that are not only small but also provide performance advantages and simplified design.

[0005] One example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices, including, but not limited to: volatile memory devices, such as dynamic random access memory (DRAM) devices; and non-volatile memory devices, such as NAND flash memory devices. A typical memory cell of a DRAM device includes one access device (e.g., a transistor) and one memory storage structure (e.g., a capacitor). Modern applications of semiconductor devices may employ a significant number of memory cells arranged in a memory array that exhibits rows and columns of memory cells. The memory cells may be electrically accessed by digital lines (e.g., bit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of memory cells of the memory array. The memory array may be two-dimensional (2D) so as to exhibit a single level (e.g., a single level, a single level) of memory cells, or may be three-dimensional (3D) so as to exhibit multiple levels (e.g., multiple levels, multiple levels) of memory cells.

[0006] As the size of memory cells decreases, the density and complexity of memory arrays increase. As the density of memory cells within a memory array increases, the density of conductive interconnect structures configured to facilitate the operation of the memory cells also increases. For example, the spacing between adjacent conductive interconnect structures decreases as the density of memory cells of a memory array increases. However, the increased density of conductive interconnect structures presents difficulties in forming conductive interconnect structures that are sufficiently in electrical communication with the memory cells. In addition, as the density of memory cells increases, the amount of area occupied by the electrical interconnects between the components of the memory cells increases. Summary of the invention

[0007] In some embodiments, a microelectronic device includes: a memory array region including a vertical stack of dynamic random access memory (DRAM) cells, each of the DRAM cells including a memory device in the vertical stack of memory devices and a horizontally adjacent access device in the vertical stack of access devices; a step region substantially horizontally adjacent to the memory array region in a first horizontal direction. The step region includes: a vertical stack of first conductive structures extending horizontally through the step region in the first horizontal direction, the first conductive structures contacting the DRAM cells; and sub-step structures individually including second conductive structures contacting the first conductive structures and extending horizontally from the first conductive structures in a second horizontal direction substantially perpendicular to the first horizontal direction, each of the sub-step structures individually including at least four steps, each of the at least four steps being defined at a horizontal boundary of one of the second conductive structures defining the step.

[0008] In an additional embodiment, a memory device includes a memory array region including a vertical stack of memory cells, the vertical stack of memory cells including: a vertical stack of access devices; a vertical stack of storage devices horizontally adjacent to the vertical stack of access devices; and a portion of a vertical stack structure including a substantially linear first conductive structure extending horizontally through the vertical stack of memory cells, the substantially linear first conductive structure being adjacent to the memory cell of the vertical stack of memory cells. The memory device further includes a staircase region horizontally adjacent to the memory array region, the staircase region including a staircase structure including: an additional portion of the vertical stack structure extending horizontally from the memory array region through the staircase region in a first direction; and sub-staircase structures extending horizontally from the vertical stack structure in a second direction different from the first direction, the sub-staircase structures individually including a second conductive structure defining at least three steps of the sub-staircase structure.

[0009] In another embodiment, an electronic device includes: an input device; an output device; a processor device, which is operably coupled to the input device and the output device; and a microelectronic device, which is operably coupled to the processor device and includes: a first array area, which includes a first vertical stack of memory cells including a first vertical stack of storage devices horizontally adjacent to the first vertical stack of access devices; a second array area, which includes a second vertical stack of memory cells including a second vertical stack of storage devices horizontally adjacent to the second vertical stack of access devices; a step area, which is horizontally between the first array area and the second array area and includes a step structure. At least one of the stepped structures includes: a vertical stack including a first conductive structure extending horizontally through the stepped region and through the first array region and the second array region; a sub-step structure including a second conductive structure extending horizontally in a horizontal direction extending away from the vertical stack, the sub-step structures individually including steps that descend vertically in the horizontal direction extending away from the vertical stack and defined by an edge of the second conductive structure; and a conductive contact structure that contacts the second conductive structure in the horizontal direction extending away from the vertical stack and in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1X is a simplified partial top view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure ( Figure 1A , Figure 1D , Figure 1G , Fig. 1I , Figure 1L , Fig.1O , Figure 1S and Figure 1W ) and simplified partial cross-sectional view ( Figure 1B , Figure 1C , Figure 1E , Figure 1F , Figure 1H , Figure 1J , Figure 1K , Figure 1M , Figure 1N , Figure 1P to Figure 1R , Figure 1T to Figure 1V and Figure 1X );

[0011] Figure 2 is a block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The illustrations included with this document are not meant to be actual diagrams of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations used to describe the embodiments herein. Common elements and features between the figures may retain the same numerical designation, but only for ease of following the description, the reference number begins with the number of the figure on which the element is introduced or most completely described.

[0013] The following description provides specific details such as material type, material thickness, and processing conditions in order to provide a detailed description of the embodiments described herein. However, it should be understood by those skilled in the art that the embodiments disclosed herein can be practiced without adopting these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing microelectronic devices (e.g., semiconductor devices, memory devices, such as DRAM memory devices), equipment, memory devices, or electronic systems, or a complete microelectronic device, device, memory device, or electronic system including a conductive contact structure. The structure described below does not form a complete microelectronic device, device, memory device, or electronic system. Only those process actions and structures required to understand the embodiments described herein are described in detail below. Additional actions for forming a complete microelectronic device, device, memory device, or electronic system from a structure can be performed by conventional techniques.

[0014] The drawings presented herein are for illustration only and do not imply actual drawings of any particular material, component, structure, device, or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions described, but rather include shape deviations due to, for example, manufacturing. For example, a region described or described as a frame may have rough and / or nonlinear features, and a region described or described as a circle may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the regions described in the figures are schematic and their shapes do not wish to illustrate the precise shape of the regions and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same numerical symbols.

[0015] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) such as single chip systems (SoCs), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0016] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structure and device in a predetermined manner.

[0017] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" are referenced to a principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively larger area than other surfaces of the structure. With reference to the figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0018] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to each other mean and include features of one (or several) disclosed entities that are positioned closest (e.g., closest) to each other. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) of one (or several) disclosed entities that do not match the "adjacent" features may be disposed between the "adjacent" features.

[0019] As used herein, for ease of description, spatially relative terms (e.g., "below," "beneath," "bottom," "above," "up," "top," "front," "rear," "left," "right," and the like) may be used to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figure is reversed, an element described as being "below" or "beneath" or "under" or "on the bottom" of other elements or features would be oriented to be "above" or "on the top" of the other elements or features. Thus, one of ordinary skill in the art would understand that the term "below" may encompass both above and below orientations, depending on the context in which the term is used. The material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

[0020] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0021] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] As used herein, the phrase "coupled to" refers to structures being operatively connected to each other, such as electrically connected through a direct ohmic connection or through an indirect connection (such as through another structure).

[0023] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied within a certain degree of variation (e.g., within an acceptable tolerance) as understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, satisfied by at least 95.0%, satisfied by at least 99.0%, satisfied by at least 99.9%, or even satisfied by 100%.

[0024] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and the degree of variation of the numerical value within an acceptable tolerance for the particular parameter as understood by one of ordinary skill in the art. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0025] A chemical formula (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y ) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios rather than absolute chemical structures, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds having elemental compositions that cannot be represented by well-defined natural number ratios and that violate the law of definite proportions. In addition, an "insulating structure" means and includes a structure formed of and including an insulating material.

[0026] Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth.

[0027] According to embodiments described herein, a microelectronic device includes a microelectronic device structure including array regions, each array region including a vertical stack of memory cells and a vertical stack structure including a conductive structure extending horizontally through the vertical spacing of the array region. The vertical stack of memory cells includes a vertical stack of memory devices, each memory device being in contact with an access device in the vertical stack of access devices. The vertical stack structures extend horizontally from a first array region through a step region and to a second array region individually. The step region is horizontally interposed between the first array region and the second array region. The step region includes a step structure shared between the vertical stack of memory cells in the first array region and the vertical stack of memory cells in the second array region. Each step structure individually includes a vertical stack of first conductive structures extending horizontally through the vertical spacing of the first array region, the step region, and the second array region. In use and operation (e.g., in response to an applied voltage), the first conductive structure is configured to be electrically connected to the vertical stack of memory cells in the first array region and the vertical stack of memory cells in the second array region (e.g., the vertical stack of access devices in the first array region and the vertical stack of access devices in the second array region). Each staircase structure further includes a sub-staircase structure extending horizontally from the vertical stack of first conductive structures (e.g., substantially perpendicular to the vertical stack of first conductive structures). The sub-staircase structure includes a second conductive structure in contact with the first conductive structure (and configured to be electrically connected to the first conductive structure, for example, during use and operation). Each sub-staircase structure includes a step defined at a horizontal edge of the second conductive structure. The steps of each sub-staircase structure of the staircase structure are vertically offset from each other. In some embodiments, each sub-staircase structure individually includes at least three steps, for example, four steps. In some embodiments, a region horizontally between the staircase region and each of the first array region and the second array region includes a conductive routing region configured to route conductive interconnects between the staircase region and additional circuitry (e.g., circuitry of additional microelectronic device structures, such as sub-wordline driver circuitry).

[0028] The conductive contact structure contacts the second conductive structure at the step. The conductive contact structure contacts the second conductive structure individually along its horizontally extending surface. In some embodiments, the conductive contact structure further contacts the second conductive structure individually in the vertical direction. Contacting the second conductive structure in the horizontal direction and in the vertical direction increases the contact surface area between the conductive contact structure and the second conductive structure, thereby reducing the resistivity of the interconnection between the conductive contact structure and the second conductive structure and reducing the resistance-capacitance (RC) product (also referred to as "RC delay") of the conductive contact structure, thereby increasing the operation of the circuit system (e.g., sub-word line driver) operably connected to the conductive contact structure.

[0029] The location of the step region horizontally between the first array region and the second array region reduces the horizontal area occupied by the step structure and facilitates increasing the density of vertical stacking of memory cells within a given area. In addition, contacting the second conductive structure in the horizontal and vertical directions facilitates increasing the number of steps per sub-stair structure, increasing the step density, and not increasing the resistivity of the conductive contact structure. In addition, forming a step structure including sub-stair structures reduces the complexity of forming the steps, for example, by reducing the number of different material compositions removed during the patterning of the step structure compared to conventional microelectronic devices.

[0030] Figures 1A to 1X 1 is a diagram illustrating various views of a microelectronic device at different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a 3D DRAM memory device) according to an embodiment of the present disclosure (described in more detail below). From the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein can be used to form a variety of devices. In other words, the methods of the present disclosure can be used whenever it is desired to form a microelectronic device.

[0031] Figure 1A is a simplified partial top view of the microelectronic device 100; Figure 1B is through Figure 1A A simplified partial cross-sectional view of the microelectronic device 100 taken along section line BB; and Figure 1C is through Figure 1A 1 is a simplified partial cross-sectional view of the microelectronic device 100 taken along section line CC.

[0032] For clarity and ease of understanding, Figure 1A Some portions of the microelectronic device 100 positioned on the uppermost surface of the microelectronic device 100 are not illustrated to more clearly illustrate the relative positions of portions of the microelectronic device 100 positioned vertically below the vertical uppermost surface of the microelectronic device 100 (e.g., in the Z direction). Figure 1A , even if the first material 106 is vertically positioned below the vertical uppermost surface of the microelectronic device 100 (eg, in the Z direction), as shown in FIG. Figure 1B and Figure 1C Therefore, some top views ( Figure 1A , Figure 1G , Fig. 1I , Figure 1L , Fig.1O and Figure 1S) do not illustrate the relative vertical positions of the components of the microelectronic device 100 with respect to each other (e.g., in the Z direction); rather, the top view illustrates the relative horizontal positions of the illustrated components of the microelectronic device 100 with respect to each other (e.g., in the X direction, in the Y direction); and the relative vertical positions of the components of the microelectronic device 100 are illustrated in the cross-sectional views ( Figure 1B , Figure 1C , Figure 1E , Figure 1F , Figure 1H , Figure 1J , Figure 1K , Figure 1M , Figure 1N , Figure 1P to Figure 1R , Figure 1T to Figure 1V and Figure 1X ) is described in .

[0033] refer to Figure 1A , the microelectronic device 100 includes an array region 102 (also referred to herein as a "memory array region") horizontally adjacent (e.g., in the X direction) to a step region 104 (also referred to herein as a "peripheral region"). In some embodiments, the step region 104 is horizontally interposed between the array regions 102 (e.g., in the X direction) and may be directly horizontally between the array regions 102 (e.g., the first array region 102 and the second array region 102) (e.g., in the X direction). In some embodiments, the horizontal area of ​​the step region 104 (e.g., in the XY plane) is greater than the horizontal area of ​​the individual array regions 102. In some embodiments, the horizontal area of ​​the step region 104 is greater than the total horizontal area of ​​the array region 102 directly horizontally adjacent (e.g., in the X direction) to the step region 104.

[0034] although Figure 1A Only one step region 104 and two array regions 102 are illustrated, but the present disclosure is not limited thereto. The microelectronic device 100 may include more than one step region 104 and more than two array regions 102. In some embodiments, each step region 104 is horizontally inserted (e.g., in the X direction) between two array regions 102. In some embodiments, horizontally adjacent step regions 104 are spaced apart from each other (e.g., in the X direction) by two array regions 102 (e.g., the first array region 102) operably connected to the first step structure of the first step region 104 and the second array region 102 operably connected to the second step structure of the second step region 104. In some embodiments, the array regions 102 may be horizontally adjacent to the step region 104 and the additional array regions 102 individually (e.g., in the X direction). In other embodiments, the horizontal area of ​​the step region 104 is smaller than the horizontal area of ​​the array region 102.

[0035] refer to Figure 1B and Figure 1C, the microelectronic device 100 includes a vertical stack of memory cells (e.g., memory cell 186 ( Figure 1W , Figure 1X The stack structure 105 (also referred to as a “stack structure”) is a vertical stack of a first material 106 and a second material 108 formed therefrom. The stack structure 105 includes a vertically alternating (eg, in the Z direction) sequence of first materials 106 and second materials 108.

[0036] The base structure 110 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate including a semiconductive material. As used herein, the term "bulk substrate" means and includes not only a silicon substrate, but also a silicon-on-insulator (SOI) substrate, such as a silicon-on-sapphire (SOS) substrate and a silicon-on-glass (SOG) substrate, an epitaxial silicon layer on a base semiconductive pedestal, and other substrates formed of and including one or more semiconductive materials (e.g., one or more of the following: silicon material, such as single crystal silicon or polycrystalline silicon; silicon germanium; germanium; gallium arsenide; gallium nitride; and indium phosphide). In some embodiments, the base structure 110 includes a silicon wafer.

[0037] refer to Figure 1A In some embodiments, each of the array region 102 and the step region 104 includes a first isolation region 103 extending horizontally (e.g., in the X direction) through the array region 102 and the step region 104. Within the array region 102, the first isolation region 103 can horizontally separate (e.g., in the Y direction) horizontally adjacent (e.g., in the Y direction) active regions (e.g., access devices 130); and within the step region 104, the first isolation region 103 can horizontally separate (e.g., in the Y direction) horizontally adjacent active regions (e.g., horizontally adjacent first material 106). The first isolation region 103 can vertically extend (e.g., in the Z direction) through the stacked structure 105 ( Figure 1B , Figure 1C ) and terminates at, for example, a base structure 110.

[0038] Continue to refer Figure 1A , the second isolation region 107 may extend horizontally (e.g., in the Y direction) through the array region 102 and the step region 104. In the array region 102, the second isolation region 107 may horizontally separate (e.g., in the X direction) horizontally adjacent (e.g., in the X direction) active regions (e.g., access devices 130); and in the step region 104, the second isolation region 107 may horizontally separate (e.g., in the Y direction) horizontally adjacent active regions (e.g., horizontally adjacent first material 106).

[0039] In some embodiments, horizontally adjacent (eg, in the X direction) access devices 130 in the array region 102 may be spaced apart from each other by a horizontal pitch P1 (eg, in the X direction).

[0040] The second isolation regions 107 may be individually formed of and include a first insulating material 118. The first insulating material 118 may be formed of and include an insulating material. In some embodiments, the first insulating material 118 is formed of and includes an insulating material, such as one or more of an oxide material (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3), or a combination thereof) and amorphous carbon. In some embodiments, the first insulating material 118 includes silicon dioxide.

[0041] refer to Figure 1B , the semiconductive material 112 vertically overlies (eg, in the Z direction) the array region 102 ( Figure 1A ) within the stacked structure 105. In some embodiments, the semiconductive material 112 includes silicon, such as single crystal silicon. In some embodiments, the semiconductive material 112 includes epitaxially grown silicon. As described in more detail herein, the semiconductive material 112 may be used to form one or more control logic devices of the microelectronic device 100 to facilitate control of a memory cell (e.g., memory cell 186 ( Figure 1W , Figure 1X )) control operations.

[0042] The second insulating material 114 vertically overlies (e.g., in the Z direction) the semiconductive material 112 in the array region 102 and the stacked structure 105 in the step region 104. The second insulating material 114 may be formed of and include one or more of the materials described above with reference to the first insulating material 118. In some embodiments, the second insulating material 114 comprises substantially the same material composition as the first insulating material 118. For clarity and ease of understanding of the description, the second insulating material 114 is not shown in FIG. Figure 1A In the description.

[0043] The first material 106 may be formed of and include, for example, a semiconductive material (e.g., silicon) or an oxide material (e.g., silicon dioxide). In some embodiments, the first material 106 includes silicon, such as epitaxially grown silicon. In some embodiments, the first material 106 includes single crystal silicon.

[0044] The second material 108 may have a different material composition than the first material 106 and may have an etching selectivity with respect to the first material 106. The second material 108 may be formed of and include one or more of: silicon germanium, polysilicon, a nitride material (e.g., silicon nitride (Si3N4)), or an oxynitride material (e.g., silicon oxynitride). In some embodiments, such as when the first material 106 includes silicon, the second material 108 includes silicon germanium, such as epitaxially grown silicon germanium. In other embodiments, such as when the first material 106 includes silicon, the second material 108 includes polysilicon. In still other embodiments, such as when the first material 106 includes silicon dioxide, the second material 108 includes silicon nitride or silicon oxynitride.

[0045] refer to Figure 1A and Figure 1B , a vertical stack of access devices 130 may be formed to extend vertically (eg, in the Z direction) through the stack structure 105. The vertical stack of access devices 130 may include vertically spaced (eg, in the Z direction) access devices 130, each formed within a layer of the first material 106.

[0046] In the array region 102, the access device 130 may include a channel region 132 ( Figure 1B ). The channel region 132 may be doped with one or more of at least one N-type dopant, such as one or more of arsenic ions, phosphorus ions, and antimony ions. In other embodiments, the channel region 132 is doped with at least one P-type dopant, such as one or more of boron ions, aluminum ions, and gallium ions. In some embodiments, the channel region 132 of the access device 130 is horizontally positioned between the source region and the drain region of the access device 130 (e.g., in the X direction, in the Y direction). The access devices 130 vertically overlying each other (e.g., in the Z direction) may form a vertical stack of the access devices 130.

[0047] refer to Figure 1A and Figure 1C In the step region 104, the first material 106 may not include the access device 130 ( Figure 1B As described in more detail herein, within the step region 104, the first material 106 may be selectively removed relative to the second material 108 and replaced with a conductive material to form a step structure (eg, step structure 175 ( Figure 1W to Figure 1X )) (e.g., the second conductive structure 154 ( Figure 1G , Figure 1H )).

[0048] In some embodiments, the first conductive structure 134 vertically overlies (e.g., in the Z direction) and vertically underlies (e.g., in the Z direction) each of the access devices 130 within the array region 102 and vertically overlies (e.g., in the Z direction) and vertically underlies (e.g., in the Z direction) each of the first materials 106 within the step region 104. The first conductive structure 134 may vertically overlie and vertically underlie the channel region 132 of each of the access devices 130. In some embodiments, the channel region 132 is vertically surrounded by the first conductive structure 134. In some embodiments, vertically adjacent (e.g., in the Z direction) first conductive structures 134 between vertically adjacent (e.g., in the Z direction) access devices 130 are spaced apart from each other by the third insulating material 128. Although the first conductive structure 134 vertically underlies (e.g., in the Z direction) the vertically uppermost (e.g., in the Z direction) surface of the microelectronic device 100, the first conductive structure 134 is vertically disposed on the microelectronic device 100. Figure 1A 1 is illustrated to illustrate the relative lateral position of the first conductive structure 134 with respect to other components and structures of the microelectronic device 100 .

[0049] The first conductive structures 134 may be individually formed of and include conductive materials such as, for example, one or more of the following: metals (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), materials including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of its alloys, a conductive doped semiconductor material (such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.), polysilicon, or other materials exhibiting conductivity.

[0050] The first conductive structure 134 may extend horizontally as a line in a first horizontal direction (e.g., in the X direction) and may extend from one array region 102 through the step region 104 and to another array region 102. The first conductive structure 134 extends horizontally (e.g., in the X direction) substantially continuously through the step region 104 horizontally interposed (e.g., in the X direction) between two array regions 102. As described in more detail herein, the first conductive structures 134 may be referred to herein individually as “first conductive lines,” “access lines,” or “word lines.”

[0051] In some embodiments, the first conductive structures 134 form a vertical stacked structure 135. The vertical stacked structure 135 extends horizontally (e.g., in the X direction) through at least a portion of the two array regions 102 and substantially continuously through the step region 104 horizontally interposed (e.g., in the X direction) between the two array regions 102. The vertical stacked structure 135 includes steps of the first conductive structures 134 that are vertically (e.g., in the Z direction) spaced apart from each other. In some embodiments, the vertical stacked structure 135 terminates horizontally (e.g., in the X direction) within a horizontal boundary (e.g., in the X direction) of the array region 102 (e.g., at a horizontal boundary (e.g., in the X direction) of the array region 102). In some embodiments, the vertical stacked structure 135 does not extend horizontally (e.g., in the X direction) beyond the horizontal boundary of the array region 102 on the horizontal side of the corresponding array region 102 opposite to the step region 104.

[0052] The third insulating material 128 may be formed of and include an insulating material that is different from the first material 106 and has an etching selectivity with respect to the first material 106. In some embodiments, the third insulating material 128 is formed of and includes one or more of the materials described above with reference to the first insulating material 118. In some embodiments, the third insulating material 128 is formed of and includes an oxide material (e.g., silicon dioxide).

[0053] refer to Figure 1B , each of the access devices 130 is at least partially surrounded by a dielectric material 136 (which may also be referred to herein as a "gate dielectric material"). Figure 1C , the first material 106 in the step region 104 is at least partially surrounded by the dielectric material 136. In some embodiments, the portion of the first conductive structure 134 that is directly vertically adjacent to the dielectric material 136 (e.g., in the Z direction) and positioned within the horizontal boundary of the dielectric material 136 (e.g., in the X direction, in the Y direction) can be referred to as a "gate electrode". In some embodiments, the first conductive structure 134 is separated from the access device 130 by the dielectric material 136.

[0054] The dielectric material 136 may be formed of and include an insulating material. By way of non-limiting example, the dielectric material 136 may include one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material such as silicon nitride (Si3N4), an oxynitride such as silicon oxynitride, another gate dielectric material, a dielectric carbon nitride material such as silicon carbon nitride (SiCN), or a dielectric carbon oxynitride material such as silicon oxycarbon nitride (SiOCN).

[0055] The vertically adjacent (eg, in the Z direction) access device 130 and the first material 106 are separated by a fourth insulating material 138 ( Figure 1B , Figure 1C In some embodiments, the fourth insulating material 138 surrounds at least a portion of the dielectric material 136 and is horizontally interposed (eg, in the Y direction) between the dielectric material 136 and the second material 108.

[0056] The fourth insulating material 138 may be formed of and include an insulating material having an etching selectivity with respect to the second material 108. In some embodiments, the fourth insulating material 138 includes a nitride material (e.g., silicon nitride (Si3N4)) or an oxynitride material (e.g., silicon oxynitride). In some embodiments, the fourth insulating material 138 includes silicon nitride.

[0057] refer to Figure 1A and Figure 1B , the conductive pillar structure 140 may extend vertically (e.g., in the Z direction) through the microelectronic device 100 and be horizontally adjacent (e.g., in the Y direction) to and in contact with the channel region 132 of the access device 130. The conductive pillar structure 140 may also be referred to herein as a "digit line", "second conductive line", "digit line pillar structure", "local digit line" or "vertical digit line". Each conductive pillar structure 140 extends vertically through the microelectronic device structure 100, such as through or horizontally adjacent (e.g., in the Y direction) to a vertical stack of access devices 130. In some embodiments, the conductive pillar structure 140 is horizontally adjacent (e.g., in the Y direction) to a source region or a drain region of the access device 130. In other embodiments, such as when the access device 130 is substantially composed of the channel region 132 (and does not include, for example, a source region and a drain region), the conductive pillar structure 140 directly contacts the channel region 132 of the access device 130. The conductive pillar structures 140 are individually in contact with the vertically stacked access devices 130 of the access devices 130 .

[0058] The conductive pillar structures 140 may individually be formed of and include a conductive material, such as one or more of the materials described above with reference to the first conductive structure 134 .

[0059] refer to Figure 1A In some embodiments, the stepped region 104 does not include any of the conductive pillar structures 140 within its horizontal region.

[0060] Continue to refer Figure 1B , the conductive pillar structures 140 may individually contact the conductive material 142 extending horizontally from the conductive pillar structures 140 (e.g., in the Y direction) and vertically above the second insulating material 114 (e.g., in the Z direction). For clarity and ease of understanding of the description, the conductive material 142 is not Figure 1A The conductive material 142 may be formed of and include one or more of the materials described above with reference to the conductive pillar structure 140 .

[0061] In some embodiments, the first material 106 in the array region 102 and the step region 104 may be patterned substantially concurrently (e.g., for forming the access device 130 in the array region 102 and patterning the first material 106 in the step region 104). By way of non-limiting example, a trench may be formed in the first isolation region 103 ( Figure 1A to Figure 1C ). Portions of each of the steps of the second material 108 may be selectively removed by the trenches to form recesses within the second material 108 at each of the steps. Portions of the first insulating material 118 of the second isolation region 107 may be selectively removed (e.g., in the Y direction) with respect to the first material 106 and the second material 108 by the trenches. After portions of the first insulating material 118 are removed by the trenches, portions of the second material 108 may be selectively removed in a horizontal direction (e.g., in the Y direction) relative to the first material 106 to form recesses in the steps of the second material 108 and to form steps of the first material 106 that extend horizontally closer to the trenches (e.g., in the Y direction) than the steps of the second material 108.

[0062] After removing a portion of the layer of the second material 108 by the trench, the fourth insulating material 138 may be formed on the surface of the first material 106 and the vertically extending (e.g., in the Z direction) surface of the second material 108 within the recess. The fourth insulating material 138 may be formed, for example, as a liner material (e.g., substantially not filling the recess). After forming the fourth insulating material 138, the third insulating material 128 may be formed on the surface of the fourth insulating material 138 and within the remaining portion of the recess and the trench.

[0063] After forming the fourth insulating material 138 and the third insulating material 128, portions of the third insulating material 128 may be removed (e.g., vertical portions of the third insulating material 128 may be removed) to expose sidewalls of the fourth insulating material 138. In some embodiments, the exposed portions of the fourth insulating material 138 are selectively removed (e.g., in the Y direction) to recess the fourth insulating material 138 relative to the third insulating material 128 and expose portions of the step of the first material 106. The exposed portions of the first material 106 may be selectively removed to vertically thin (e.g., in the Z direction) the exposed portions of the first material 106. After vertically thinning the exposed portions of the first material 106, the dielectric material 136 is formed on the surface of the first material 106, the surface of the fourth insulating material 138, and the surface of the third insulating material 128.

[0064] A conductive material may be formed over the surface of the dielectric material 136 to form a first conductive structure 134. In some embodiments, the conductive material is formed by one or more of ALD, CVD, and PVD. After forming the conductive material, portions of the conductive material may be selectively removed (e.g., in the Y direction) with respect to, for example, the dielectric material 136 to form first conductive structures 134 extending horizontally (e.g., in the X direction) as lines through the array region 102 and the step region 104, each first conductive structure 134 extending horizontally as a continuous integrated structure.

[0065] After forming the first conductive structure 134, additional portions of the fourth insulating material 138 may be formed to form the access device 130. Additional portions of the fourth insulating material 138 may be formed to be horizontally adjacent to the first conductive structure 134 (e.g., in the Y direction) and may be formed on the surface of the dielectric material 136. After forming the access device 130, the conductive pillar structure 140 ( Figure 1A , Figure 1B ) and conductive material 142( Figure 1B ) may be formed in the array region 102. The conductive pillar structure 140 ( Figure 1A , Figure 1B ) and conductive material 142( Figure 1B ) may not be formed in the step region 104 (eg, may be omitted from the step region 104 ). In addition, the first isolation region 103 may be filled with the first insulating material 118 .

[0066] refer to Figure 1A, array region 102 may include a central array region 119 horizontally between edge regions 117 (e.g., in the Y direction). In some embodiments, edge regions 117 individually include a single first conductive structure 134 extending horizontally (e.g., in the X direction) therethrough. Each of edge regions 117 may be horizontally adjacent to a peripheral region of microelectronic device 100 (e.g., in the Y direction) that does not include memory cells. Although Figure 1A A specific number of access device sets 130 and first conductive structures 134 in the central array region 119 is illustrated, but the disclosure is not limited thereto, and the microelectronic device 100 may include a greater number of access devices 130 and first conductive structures 134 in the central array region 119 .

[0067] Common Reference Figure 1D and Figure 1E , a first mask material 144 may be formed over the array region 102 and over a portion of the step region 104 over the microelectronic device 100. In some embodiments, substantially all of each array region 102 is covered by the first mask material 144 and a majority of the step region 104 is covered by the first mask material 144. Within the step region 104, trenches 146 and isolation structures 148 may be formed within the first mask material. In some embodiments, trenches 146 and isolation structures 148 are horizontally disposed between the first conductive structure 134 ( Figure 1A , Figure 1E ) of the vertical stacking structure 135 ( Figure 1A , Figure 1E ), the first conductive structure 134 is horizontally between the two first isolation regions 103 (for example, in the Y direction). The isolation structure 148 is Figure 1D Illustrated by dotted lines.

[0068] The isolation structure 148 can be positioned horizontally between the array region 102 and the step region 104 (e.g., in the X direction). The horizontal width of the isolation structure 148 (e.g., in the Y direction) is greater than the horizontal width of the trench 146 (e.g., in the Y direction). As described in more detail herein, the isolation structure 148 can form a conductive routing structure area for routing conductive interconnects (e.g., electrical connections) of various components of the microelectronic device 100 to circuitry (e.g., sub-word line driver circuitry) of additional microelectronic devices (e.g., additional microelectronic device structures).

[0069] refer to Figure 1E , trench 146 and isolation structure 148 ( Figure 1D ) may extend vertically (eg, in the Z direction) through the first mask material 144, the second insulating material 114, and the stacked structure 105. In some embodiments, the trench 146 and the isolation structure 148 extend vertically (eg, in the Z direction) to the base structure 110.

[0070] Continue to refer Figure 1D and Figure 1E In the step region 104, the first isolation region 103, the second isolation region 107 and the trench 146 can horizontally separate (for example, in the X direction, in the Y direction) the horizontally adjacent (for example, in the X direction, in the Y direction) portions of the first material 106 into an isolation structure 109 ( Figure 1G ), each including a portion of the first material 106. The isolation structures 109 can be separated into rows 115 of isolation structures 109 that are horizontally separated from each other (e.g., in the Y direction) by the first isolation regions 103 and columns 113 of isolation structures 109 that are horizontally separated from each other (e.g., in the X direction) by the second isolation regions 107. In some embodiments, the microelectronic device 100 includes two rows 115 of isolation structures 109 horizontally between (e.g., in the Y direction) horizontally adjacent (e.g., in the Y direction) first isolation regions 103.

[0071] The first mask material 144 may be formed of and include one or more of the following: a photoresist material, a nitride mask (e.g., silicon nitride, titanium nitride, aluminum nitride), silicon carbide, carbon-doped hydrogenated silicon oxide (SiOCH), amorphous carbon, and a spin-on mask material. In some embodiments, the first mask material 144 includes a hard mask material. However, the present disclosure is not limited thereto and the first mask material 144 may include materials other than the above materials.

[0072] Continue to refer Figure 1E , in forming the trench 146 and the isolation structure 148 ( Figure 1D ) after that, the second material 108 ( Figure 1C ) can be selectively removed (e.g., relative to the first material 106 and the fourth insulating material 138) through the trenches 146 and the isolation structures 148. Removing the second material 108 can expose portions of the first material 106 and portions of the fourth insulating material 138. In some embodiments, removing the second material 108 can remove substantially all of the second material 108 from within the stepped region 104 and expose portions of the fourth insulating material 138.

[0073] In some embodiments, before removing the second material 108 ( Figure 1C ) portion, the first material 106 portion passes through the trench 146, the isolation structure 148 ( Figure 1D ) and the areas from which the second material 108 has been removed to vertically thin (e.g., in the Z direction).

[0074] In some embodiments, the second material 108 ( Figure 1C) is selectively removed relative to the first material 106, the second insulating material 114, the first conductive structure 134, the dielectric material 136, and the first mask material 144 by exposing the second material 108 to one or both of a dry etching process and a wet etching process. By way of non-limiting example, the second material 108 can be selectively removed relative to the first material 106 by exposing the second material 108 to a dry etch comprising one or both of hydrofluoric acid (HF) and methanol (CH3OH); followed by plasma treatment with one or more of carbon tetrafluoride (CF4), fluorine (F2), ammonia (NH3), argon, and chlorine trifluoride (ClF3). In some embodiments, a portion of the first material 106 is vertically thinned (e.g., in the Z direction) by exposing the first material 106 to an atomic layer etch (ALE) process.

[0075] Next reference Figure 1F , in which the second material 108 is selectively removed relative to the first material 106 ( Figure 1E ) and vertically thinning (eg, in the Z direction) a portion of the first material 106, a fifth insulating material 150 may be formed corresponding to the second material 108 ( Figure 1D ). The fifth insulating material 150 may be formed vertically between vertically adjacent (eg, in the Z direction) steps of the first material 106 (eg, in the Z direction).

[0076] After forming the fifth insulating material 150 , portions of the fifth insulating material 150 may be removed from over the surface of the microelectronic device 100 and from the vertical sidewalls of the trenches 146 to expose the sidewalls of the steps of the first material 106 at the trenches 146 .

[0077] The fifth insulating material 150 may be formed of and include one or more of the materials described above with reference to the second insulating material 114. In some embodiments, the fifth insulating material 150 comprises a material composition substantially the same as the second insulating material 114. In some embodiments, the fifth insulating material 150 comprises an oxide material. In some embodiments, the fifth insulating material 150 comprises silicon dioxide.

[0078] Figure 1G and Figure 1H It is in reference Figure 1F A simplified partial top view of the microelectronic device 100 at a processing stage following the processing stage described ( Figure 1G ) and simplified partial cross-sectional view ( Figure 1H ). Figure 1H is through Figure 1G A simplified cross-sectional view of the microelectronic device 100 taken along the section line HH. Figure 1G In the figure, for clarity and ease of understanding of the description, the first mask material 144 is not illustrated.

[0079] After the fifth insulating material 150 is formed, the first material 106 ( Figure 1F ) can be selectively removed through the trenches 146 and isolation structures 148 (e.g., relative to the fifth insulating material 150, the first conductive structure 134, and the fourth insulating material 138). Removing the first material 106 can expose portions of the dielectric material 136. In some embodiments, the exposed portions of the dielectric material 136 can be removed to expose portions of the first conductive structure 134. Removing the first material 106 through the trenches 146 and isolation structures 148 can remove substantially all of the first material 106 from within the step region 104. In other embodiments, portions of the first material 106 can remain, such as portions of the first material 106 away from the trenches 146 and isolation structures 148 and, for example, proximate to the first insulating material 118 of the first isolation region 103.

[0080] In some embodiments, the first material 106 is etched by exposing the first material 106 to a dry etching process (e.g., using one or more of ammonia (NH3), sulfur hexafluoride (SF6), hydrogen (H2), and carbon tetrafluoride (CF4)) or a wet etching process (e.g., using tetramethylammonium hydroxide (TMAH), deionized water (DIO3), hydrofluoric acid (HF), ethyltrimethylammonium hydroxide (ETMAH) (C5H 15 NO) and one or more amine compounds (e.g., N-methylethanolamine (NMEA) (C3H9NO), monoethanolamine (MEA) (C2H7NO), diethanolamine (DEA) (C4H 11 NO2) and triethanolamine (TEA) (C6H 15 NO3) or one or more of the first and second insulating materials 150, 134, and 138. However, the present disclosure is not limited thereto and the first material 106 may be selectively removed using materials and methods other than those described above.

[0081] After removing portions of the first material 106, the exposed portions of the dielectric material 136 can be removed selectively relative to the fourth insulating material 138. In some embodiments, the dielectric material 136 is exposed to a wet etching process, such as exposure to one or more of potassium hydroxide (KOH), hydrofluoric acid (HF), and ammonium fluoride (NH4F) to remove the dielectric material 136 selectively relative to the fourth insulating material 138.

[0082] Continue to refer Figure 1G and Figure 1H , before removing the first material 106 ( Figure 1F) and portions of the dielectric material 136, the conductive material 152 may be formed at locations corresponding to the previously removed first material 106 and dielectric material 136. In some embodiments, the conductive material 152 is formed at a step of the stacked structure 105 that is vertically between vertically adjacent (e.g., in the Z direction) steps of the fifth insulating material 150. The conductive material 152 may contact the first conductive structure 134. By way of non-limiting example, each step of the conductive material 152 may contact the first conductive structure 134 that is directly vertically above the step of the conductive material 152 (e.g., in the Z direction) and the first conductive structure 134 that is directly vertically below the step of the conductive material 152 (e.g., in the Z direction). The conductive material 152 may be formed at a location ... Figure 1F ) extends horizontally (eg, in the Y direction) to the first conductive structure 134.

[0083] In some embodiments, the conductive material 152 includes one or more of the materials described above with reference to the first conductive structure 134. In some embodiments, the conductive material 152 includes substantially the same material composition as the first conductive structure 134. In other embodiments, the conductive material 152 includes a different material composition than the first conductive structure 134.

[0084] After forming the conductive material 152, in the trench 146 ( Figure 1F ) of the vertically extending sidewalls (eg, in the Z direction) and the isolation structures 148 ( Figure 1G ) and vertically overlying (eg, in the Z direction) the microelectronic device 100 can be removed. In some embodiments, the first mask material 144 ( Figure 1F ) may be removed (e.g., thinned) from the upper surface of the microelectronic device 100 during the removal of the portion of the conductive material 152. In some embodiments, the portion of the conductive material 152 is removed by exposing the conductive material 152 to a wet etching process (e.g., one or more of ammonium hydroxide, hydrogen peroxide (H2O2), sodium hypochlorite (NaOCl), hydrogen fluoride, nitric acid (HNO3), and sulfuric acid (H2SO4)).

[0085] Common Reference Figure 1G and Figure 1H , the conductive material 152 is formed from the groove 146 ( Figure 1F) are removed, the horizontally extending (e.g., in the Y direction) portion of the conductive material 152 remains at the step of the stacked structure 105. The horizontally extending portion of the conductive material 152 may form a second conductive structure 154 that extends horizontally (e.g., in the Y direction) from at least the first conductive structure 134 and terminates horizontally at, for example, the trench 146. Thus, the second conductive structures 154 may individually contact the first conductive structures 134. In some embodiments, the second conductive structures 154 extend horizontally in a horizontal direction (e.g., in the Y direction) that is substantially perpendicular to the horizontal direction (e.g., in the X direction) that the first conductive structures 134 extend horizontally. Thus, the vertical stacked structure 135 may include a second conductive structure 154 that extends horizontally from the array region 102 in a first horizontal direction (e.g., in the X direction) (e.g., through the memory cells (e.g., the memory cells 186 ( Figure 1W , Figure 1X )) of a vertical stack) and a first conductive structure 134 (e.g., a substantially linear first conductive structure 134) passing through the step region 104 and a second conductive structure 154 extending horizontally from the first conductive structure 134 in a second horizontal direction (e.g., in the Y direction).

[0086] refer to Figure 1G , the first material 106 in the step region 104 ( Figure 1A ) of the previously described isolation structure 109 ( Figure 1A ) is illustrated as having a conductive material 152 that may be vertically interposed (eg, in the Z direction) between levels of the fifth insulating material 150.

[0087] In some embodiments, the second conductive structure 154 intersects the first conductive structure 134 and extends horizontally (eg, in the Y direction) beyond a lateral boundary (eg, in the Y direction) of the first conductive structure 134. Figure 1G , the second conductive structure 154 may be positioned on both horizontal sides (eg, in the Y direction) of the first conductive structure 134 of the vertical stacked structure 135. In some embodiments, the first conductive structure 134 may be positioned within a horizontal boundary (eg, in the Y direction) of the second conductive structure 154.

[0088] Continue to refer Figure 1G and Figure 1K , before the conductive material 152 is removed from the surface of the microelectronic device 100 and the groove 146 ( Figure 1A , Figure 1F ) are removed, trench 146 and isolation structure 148 may be filled with additional portions of first insulating material 118. Portions of first insulating material 118 may be removed, for example, by exposing microelectronic device 100 to a chemical mechanical planarization (CMP) process.

[0089] Figure 1I to Figure 1K It is in reference Figure 1G and Figure 1H A simplified partial top view of the microelectronic device 100 at a processing stage following the processing stage described ( Fig. 1I ) and simplified partial cross-sectional view ( Figure 1J , Figure 1K ). Figure 1J is through Fig. 1I 1 is a simplified cross-sectional view of the microelectronic device 100 taken along section line JJ. Figure 1K is through Fig. 1I A simplified cross-sectional view of the microelectronic device 100 is taken along the section line KK. For clarity and understanding of the description, Figure 1J and Figure 1K Description ratio Figure 1H More layers of conductive material 152 and fifth insulating material 150 are provided to more clearly illustrate the stepped structure (eg, structure 175 ( Figure 1W to Figure 1X )) of the first step (e.g., the first step 155 ( Figure 1J , Figure 1K )) is formed. It should be understood that Figure 1J and Figure 1K Not about Figure 1H Explain in proportion.

[0090] Common Reference Figure 1J and Figure 1K , portions of the array region 102 and the step region 104 may be covered with one or more mask materials, such as a first buried anti-reflective coating (BARC) material 156 and a first resist material 158. For clarity and ease of understanding of the description, the first BARC material 156 and the first resist material 158 are not shown in the drawings. Fig. 1I In the description. Figure 1J and Figure 1K The base structure 110 is not illustrated. It is understood that the microelectronic device 100 includes multiple levels of the second conductive structure 154 and the fifth insulating material 150.

[0091] Openings 160 may be formed in the first BARC material 156 and the first resist material 158 to expose the vertically uppermost (e.g., in the Z direction) level of the layers of the conductive material 152 and the fifth insulating material 150 of the portion of the isolation structure 109. In some embodiments, the openings 160 in the edge region 117 may be horizontally (e.g., in the X direction) offset (e.g., staggered) from the openings 160 in the central array region 119.

[0092] The first BARC material 156 may be formed of and include one or more of titanium, titanium dioxide, chromium oxide, magnesium fluoride (MgF2), carbon, α-silicon or an organic material (e.g., a fluoropolymer), a dielectric anti-reflective coating (DARC) material. However, the present disclosure is not limited thereto and the first BARC material 156 may include materials other than the above materials.

[0093] The first resist material 158 may be formed of and include a methacrylate copolymer having a siloxane group, methyl methacrylate, naphthoquinone diazide (DNQ), a copolymer of tert-butyl methacrylate and 3-heptaisobutyl-POSS-propyl methacrylate, and a negative photoresist such as hydrogen silsesquioxane (HSQ). However, the present disclosure is not limited thereto and the first resist material 158 may include materials other than the above materials.

[0094] refer to Figure 1J and Figure 1K , after exposing additional portions of the isolation structure 109, portions of additional steps of the conductive material 152 of the fifth insulating material 150 and the second conductive structure 154 may be removed through the opening 160. By way of non-limiting example, portions of the vertically uppermost (e.g., in the Z direction) at least three steps (e.g., four steps) of each of the fifth insulating material 150 and the second conductive structure 154 may be removed through the opening 160 to expose the vertically underlying (e.g., in the Z direction) second conductive structure 154 to form first steps 155, each of the first steps 155 being horizontally adjacent to at least another of the first steps 155 in a first horizontal direction (e.g., in the X direction) and vertically spaced apart from at least another first step 155 by at least three steps (e.g., at least three pairs), e.g., four steps of the fifth insulating material 150 and the second conductive structure 154.

[0095] In some embodiments, the steps of the conductive material 152 of the fifth insulating material 150 and the second conductive structure 154 can be removed by dry etching, such as by reactive ion etching (RIE). By way of non-limiting example, the fifth insulating material 150 can be removed by exposing the fifth insulating material 150 to one or more of hydrogen (H2), carbon tetrafluoride (CF4), fluoromethane (CH3F), hexafluoroethane (C2F6), octafluoropropane (C3F8), and octafluorocyclopentene (C5F8). Portions of the steps of the second conductive structure 154 can be removed by exposing the second conductive structure 154 to one or more of sulfur hexafluoride (SF6), oxygen (O2), ammonia (NH3), carbon tetrafluoride, fluoromethane, and bromotrifluoromethane (CBrF3). However, the present disclosure is not limited thereto and portions of each of the fifth insulating material 150 and the second conductive structure 154 can be removed by methods other than the above methods.

[0096] Figure 1L to Figure 1N It is in reference Fig. 1I and Figure 1K A simplified partial top view of the microelectronic device 100 at a processing stage following the processing stage described ( Figure 1L ) and simplified partial cross-sectional view ( Figure 1M , Figure 1N ). Figure 1M is through Figure 1L 1 is a simplified cross-sectional view of the microelectronic device 100 taken along section line MM. Figure 1N is through Figure 1L A simplified cross-sectional view of the microelectronic device 100 taken along section line NN.

[0097] Common Reference Figure 1L to Figure 1N Portions of the first BARC material 156 and the first resist material 158 in the stepped region 104 may be trimmed (e.g., removed) in a horizontal direction (e.g., in the X direction) to expose additional portions of the isolation structure 109 through the opening 160, such as one or two additional columns 113 of the isolation structure 109.

[0098] refer to Figure 1M and Figure 1N , after exposing additional portions of the isolation structure 109, additional portions of additional steps of the fifth insulating material 150 and the conductive material 152 (e.g., at least three additional steps, e.g., four additional steps of each of the fifth insulating material 150 and the conductive material 152) may be removed to form additional first steps 155 that vertically rise and fall (e.g., in the Z direction) in the first horizontal direction (e.g., in the X direction). After forming the additional first steps 155, additional portions of the first BARC material 156 and the first resist material 158 in the step region 104 may be removed (e.g., trimmed) in the first horizontal direction to expose additional portions of the isolation structure 109, e.g., one or two additional columns 113 of the isolation structure 109, through the opening 160. After exposing additional portions of the isolation structure 109, further additional first steps 155 may be formed by removing additional portions of the additional steps of the fifth insulating material 150 and the conductive material 152 of the second conductive structure 154 exposed through the opening 160. The process of trimming the first BARC material 156 and the first resist material 158 to horizontally extend the opening 160 in a first horizontal direction (e.g., in the X direction) and expose additional portions of the steps of the fifth insulating material 150 and the conductive material 152 and then removing the exposed portions of the additional steps of the fifth insulating material 150 and the conductive material 152 can be repeated a desired number of times to form a partial stepped structure 165 including a desired number of first steps 155.

[0099] In some embodiments, each of the first steps 155 is vertically spaced (e.g., in the Z direction) at least three levels of the pair of fifth insulating material 150 and conductive material 152 from the directly horizontally adjacent (e.g., in the X direction) first step 155. In some embodiments, each of the first steps 155 is vertically spaced (e.g., in the Z direction) at least four levels of the pair of fifth insulating material 150 and conductive material 152 from the directly horizontally adjacent (e.g., in the X direction) first step 155.

[0100] Continue to refer Figure 1M In some embodiments, after forming the first step 155, a mask material (eg, a trim mask) may be formed on the first region 151 of the microelectronic device 100 and on the second region 153 of the step region 104. Figure 1L , Figure 1M In some embodiments, the steps of the fifth insulating material 150 and the conductive material 152 of the exposed portion of the isolation structure 109 in the second region 153 may be removed to form a first step 155 in the second region 153 that is vertically offset (e.g., in the Z direction) from the first step 155 in the first region 151.

[0101] refer to Figure 1N In some embodiments, within the edge region 117, the partial step structures 165 including the first step 155 form stadium-type structures 167 each including two partial step structures 165, and the vertically lowest (e.g., in the Z direction) first step 155 of the stadium-type structure 167 is horizontally centered (e.g., in the X direction) within the stadium-type structure 167. In some embodiments, the first partial step structure 165 of the stadium-type structure 167 includes a first step 155 that rises vertically (e.g., in the Z direction) in a positive horizontal direction (e.g., in the positive X direction) and the second partial step structure 165 of the stadium-type structure 167 includes a first step 155 that rises vertically (e.g., in the Z direction) in a negative horizontal direction (e.g., in the negative X direction) that is substantially opposite to the positive horizontal direction. It should be understood that the stadium-type structure 167 may include a plurality of first steps 155 in addition to the first step 155. Figure 1N An additional first step 155 beyond the first step described in Figure 1N left and right in the view).

[0102] Fig.1O and Figure 1P It is in reference Figure 1L to Figure 1N A simplified partial top view of the microelectronic device 100 at a processing stage following the processing stage described ( Fig.1O ) and simplified partial cross-sectional view ( Figure 1P ). Figure 1P is through Fig.1O 1 is a simplified cross-sectional view of the microelectronic device 100 taken along section line PP.

[0103] Common Reference Fig.1O and Figure 1P , after forming the partial stepped structure 165 including the first step 155 extending in the first horizontal direction (e.g., the X direction), the first BARC material 156 and the first resist material 158 may be trimmed in the second horizontal direction (e.g., in the Y direction) to increase the horizontal dimension of the opening 160 in the second horizontal direction and expose additional portions of the steps of the fifth insulating material 150 and the conductive material 152 of the isolation structure 109. In some embodiments, after exposing the additional portions of the steps of the fifth insulating material 150 and the conductive material 152, portions of a pair of the steps of the fifth insulating material 150 and the conductive material 152 are removed to separate the first step 155 ( Figure 1M , Figure 1N ) and a step structure 175 (for example, a first step 155 vertically ascending and descending (for example, in the Z direction) in a first horizontal direction (for example, in the X direction) and a second step 162 vertically ascending and descending (for example, in the Z direction) in a second horizontal direction (for example, in the Y direction) is formed. Figure 1S ).

[0104] The process of trimming the first BARC material 156 and the first resist material 158 in the second horizontal direction to increase the horizontal size of the opening 160 in the second horizontal dimension and expose additional portions of the step of the fifth insulating material 150 and the conductive material 152 and then removing the additional exposed portions of the step of the fifth insulating material 150 and the conductive material 152 may be repeated a desired number of times to form the stepped structure 175 ( Figure 1S , four of which are in Figure 1S ), each of which individually includes a sub-stair structure 170 facing each other and individually including a second step 162 extending in a second horizontal direction (e.g., in the Y direction) substantially perpendicular to the first horizontal direction (e.g., in the X direction). In some embodiments, the second step 162 vertically rises and falls (e.g., in the Z direction) in a second horizontal direction (e.g., in the Y direction) substantially perpendicular to the first horizontal direction (e.g., in the X direction) in which the first step 155 vertically rises and falls (e.g., in the Z direction).

[0105] In some embodiments, each sub-step structure 170 is composed of a first step 155 ( Figure 1M) and individually include at least three (e.g., four) second steps 162 that vertically rise and fall (e.g., in the Z direction) in a second horizontal direction (e.g., in the Y direction). Horizontally adjacent (e.g., in the X direction) sub-step structures 170 that share the same first conductive structure 134 may be vertically offset from each other (e.g., in the Z direction) by at least three (e.g., four) pairs of steps of the fifth insulating material 150 and the second conductive structure 154. In some embodiments, within the central array region 119, the sub-step structures 170 of the step structure 175 may be vertically aligned (e.g., in the Z direction) with the sub-step structures 170 of the horizontal neighbors (e.g., in the Y direction) positioned within its horizontal boundary (e.g., in the X direction). In some embodiments, at least some (e.g., each) sub-step structures 170 within the edge region 117 may be vertically offset (e.g., in the Z direction) from sub-step structures 170 positioned within horizontal boundaries (e.g., in the X direction) of at least some sub-step structures 170 of horizontally adjacent (e.g., in the Y direction) step structures 175.

[0106] Thus, each of the stepped structures 175 may include a first portion of a vertically stacked structure 135 including a first conductive structure 134 extending horizontally from the array region 102 in a first horizontal direction and close to (e.g., passing through) the vertical stack of access devices 130 and a second conductive structure 154 extending horizontally from the first conductive structure 134 in a second horizontal direction. In some embodiments, each of the first conductive structures 134 is configured to communicate with a memory cell (e.g., structure 175) by means of a first array region 102 and a corresponding access device 130 of a second array region 102 spaced from the first array region 102 by the stepped region 104. Figure 1W to Figure 1X ))Electrically connected.

[0107] Continue to refer Figure 1P , are horizontally aligned with each other (eg, in the X direction) and are positioned at the vertically aligned (eg, in the Z direction) first steps 155 ( Figure 1M , Figure 1N ) can form an additional stadium-type structure 172 including the pair of sub-step structures 170 facing each other. Each of the sub-step structures 170 can include a first conductive structure 134 of a different vertically stacked structure 135. In some such embodiments, the additional stadium-type structure 172 can be formed by the sub-step structures 170 associated with different first conductive structures 134 and second conductive structures 154.

[0108] In some embodiments, horizontally adjacent (eg, in the X-direction) sub-stair structures 170 are separated from each other by one of the second isolation regions 107 including the first insulating material 118 .

[0109] Figure 1Q It is in reference Figure 1P 1. A simplified partial cross-sectional view of the microelectronic device 100 at a processing stage following the processing stage described. After forming the sub-step structure 170, in some embodiments, the conductive material 173 is vertically formed on the first step 155 ( Figure 1N ) and above the second step 162 (e.g., in the Z direction). A vertically extending portion (e.g., in the Z direction) of the conductive material 173 can be removed, such as a portion of the conductive material 173 that vertically extends between a horizontally adjacent (e.g., in the X direction) sub-step structure 170 and a vertically adjacent (e.g., in the Z direction) second step 162 of the sub-step structure 170. As described in more detail herein, the conductive material 173 can merge two horizontally adjacent (e.g., in the X direction) isolation structures 109 ( Fig.1O ) to form a horizontally wider (eg, in the X direction) surface for forming a conductive contact structure (eg, conductive contact structure 180 ( Figure 1S to Figure 1U In some embodiments, the conductive material 173 individually overlying each of the second steps 162 constitutes a portion of the corresponding second step 162. In other words, the second step 162 may include the conductive material 173. In some embodiments, the conductive material 173 is not vertically formed on the sub-step structure 170.

[0110] Conductive material 173 may be formed of and include one or more of the materials described above with reference to conductive material 152. In some embodiments, conductive material 173 comprises substantially the same material composition as conductive material 152. In some embodiments, conductive material 173 comprises tungsten.

[0111] Continue to refer Figure 1Q After forming the conductive material 173, a liner material 174 may be formed vertically over the microelectronic device 100 (e.g., in the Z direction), for example, over the second step 162 of the sub-step structure 170. After forming the liner material 174, a sixth insulating material 176 may be formed over the microelectronic device 100, for example, over the sub-step structure 170 and within an additional stadium-shaped structure 172 over the liner material 174. After forming the liner material 174 and the sixth insulating material 176, horizontally extending (e.g., in the X direction, in the Y direction) portions of the liner material 174 and the sixth insulating material 176 may be removed from the upper surface (e.g., in the Z direction) of the microelectronic device 100, for example, by CMP.

[0112] The liner material 174 may be formed of a dielectric material and include a dielectric material, such as one or more of aluminum oxide (e.g., Al2O3), silicon oxynitride (SiON), magnesium oxide, and cerium oxide. However, the present disclosure is not limited thereto and the liner material 174 may be formed of other materials and include other materials.

[0113] The sixth insulating material 176 may exhibit an etch selectivity with respect to the liner material 174. The sixth insulating material 176 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 118. In some embodiments, the sixth insulating material 176 includes silicon dioxide.

[0114] In some embodiments, the liner material 174 and horizontally extending portions of the sixth insulating material 176 (eg, in the X direction, in the Y direction) are removed from the uppermost surface (eg, in the Z direction) of the microelectronic device 100 , such as by CMP.

[0115] Continue to refer Figure 1Q After forming the liner material 174 and the sixth insulating material 176, an opening 178 may be formed in the sixth insulating material 176 horizontally aligned with the second step 162 (e.g., in the X direction, in the Y direction) and vertically formed above the second step 162 (e.g., in the Z direction) to expose a portion of the liner material 174 vertically overlying (e.g., in the Z direction) the second step 162. In some embodiments, the opening 178 is horizontally aligned with a horizontal edge of the second step 162 (e.g., in the X direction, in the Y direction).

[0116] Figure 1R It is in reference Figure 1Q Simplified partial cross-sectional view of microelectronic device 100 in a processing stage after the described processing stage. After forming opening 178, the portion of liner material 174 exposed by opening 178 can be removed to expose horizontally extending surfaces (e.g., in the X direction, in the Y direction) and vertically extending surfaces (e.g., in the Z direction) of second step 162 of sub-step structure 170 (e.g., horizontally extending surfaces and vertically extending surfaces of conductive material 173 and / or conductive material 152), such horizontally extending surfaces and vertically extending surfaces being substantially perpendicular to each other. In some embodiments, removing liner material 174 can expose one or both of conductive material 173 and conductive material 152 at a horizontal edge (e.g., in the Y direction) defining second step 162 of sub-step structure 170.

[0117] In some embodiments, when Figure 1RWhen viewed in the cross section illustrated in FIG. 1 , the exposed portion of the second step 162 of the sub-step structure 170 may exhibit an “L-shape.” The exposed portion of the second step 162 may include, for example, a horizontally extending surface and a vertically extending surface substantially perpendicular to the horizontally extending surface.

[0118] Portions of the liner material 174 may be removed by exposing the liner material 174 to, for example, a dry etching process, such as a reactive ion etching (RIE) process. In some embodiments, the exposed portion of the liner material 174 is exposed to a plasma, such as one or more of boron trichloride (BCl3), chlorine (Cl2), carbon tetrachloride (CCl4), silicon tetrachloride (SiCl4), ammonia (NH3), and oxygen (O2). However, the present disclosure is not limited thereto and the exposed portion of the liner material 174 may be removed with other etchants.

[0119] Figure 1S to Figure 1V It is in reference Figure 1R A simplified partial top view of the microelectronic device 100 at a processing stage following the processing stage described ( Figure 1S ) and simplified partial cross-sectional view ( Figure 1T to Figure 1V ). Figure 1T is through Figure 1S The section line TT is taken Figure 1S FIG. 1 is a simplified partial cross-sectional view of a microelectronic device 100 . Figure 1U is through Figure 1S The section line UU intercepts Figure 1S FIG. 1 is a simplified partial cross-sectional view of a microelectronic device 100 . Figure 1V is through Figure 1S The section line VV is taken Figure 1S FIG. 1 is a simplified partial cross-sectional view of a microelectronic device 100 .

[0120] refer to Figure 1S , the sub-stair structures 170 may be horizontally spaced apart by a pitch P2 (eg, in the X direction), where the pitch P2 is a horizontal spacing (eg, in the X direction) of the access devices 130 in the array region 102 formed by the access devices 130 by a pitch P1 ( Figure 1A ) (and the corresponding pitch P1 of the memory cell) (e.g., structure 175 ( Figure 1W to Figure 1X )) is about twice as large.

[0121] refer to Figure 1S to Figure 1V , through opening 178 ( Figure 1R) After removing the exposed portion of the liner material 174 by the opening 178, a conductive contact structure 180 may be formed in the opening 178 and contact the second conductive structure 154 defining the second step 162 of the sub-step structure 170, such as one or both of the conductive material 173 and the conductive material 152 of the second step 162. The conductive contact structure 180 may individually contact a horizontally extending (e.g., in the X direction, in the Y direction) surface of the second step 162 of the sub-step structure 170, such as a horizontally extending surface of the conductive material 173 or the conductive material 152; and the conductive contact structure 180 may individually contact a vertically extending (e.g., in the Z direction) surface of the second step 162 of the sub-step structure 170, such as a vertically extending surface of the conductive material 173 and the conductive material 152.

[0122] In some embodiments, each of the second steps 162 individually directly contacts one of the conductive contact structures 180 and each of the sub-step structures 170 is contacted by at least three (e.g., four) conductive contact structures 180 (e.g., different steps of the second conductive structure 154 that define the horizontal edge (e.g., in the X direction) of the second step 162 of the sub-step structure 170 are contacted by different conductive contact structures 180). In some embodiments, each of the sub-step structures 170 includes exposed portions of four steps of the second conductive structure 154. In some such embodiments, each of the sub-step structures 170 is directly contacted by four conductive contact structures 180 (e.g., one conductive contact structure 180 at each of the second steps 162 of the sub-step structure 170).

[0123] refer to Figure 1S and Figure 1V In some embodiments, forming the conductive material 173 may merge horizontally adjacent pairs (eg, in the X direction) to form the sub-staircase structure 170 and have a pitch P2 that is approximately twice the pitch P1.

[0124] In some embodiments, within the edge region 117, the sub-step structures 170 may be arranged to form a stadium-type structure 167, with the vertically lowermost (e.g., in the Z direction) first step 155 (corresponding to the vertically lowermost sub-step structure 170) being substantially horizontally centered (e.g., in the X direction) between the first array region 102 and the second array region 102 spaced apart from the first array region 102 by the step region 104. In some such embodiments, the vertically uppermost (e.g., in the Z direction) sub-step structure 170 may be positioned close to (e.g., directly horizontally adjacent (e.g., in the X direction)) the array region 102. In some embodiments, the vertical height (e.g., in the Z direction) of the sub-step structure 170 within the edge region 117 decreases as the horizontal distance (e.g., in the X direction) of the sub-step structure 170 from the array region 102 increases.

[0125] Common Reference Figure 1S to Figure 1V In some embodiments, the sub-step structures 170 of the first stepped structure 175 within the central array region 119 are vertically aligned (e.g., in the Z direction) with the sub-step structures 170 of the horizontally adjacent (e.g., in the Y direction) second stepped structures 175 positioned within the horizontal boundary (e.g., in the X direction) of the sub-step structures 170 of the first stepped structure 175. By way of non-limiting example, the first sub-step structure 170 of the first stepped structure 175 may be positioned within the horizontal boundary (e.g., in the X direction) of the second sub-step structure 170 of the second stepped structure 175 and may be vertically aligned (e.g., in the Z direction) with the second sub-step structure 170.

[0126] In some embodiments, the sub-step structures 170 of the first stepped structure 175 in the central array region 119 may be vertically offset (e.g., in the Z direction) from the sub-step structures 170 of the horizontally adjacent (e.g., in the Y direction) third stepped structures 175 located in the edge region 117 and located within the horizontal boundary (e.g., in the X direction) of the sub-step structures 170 of the first stepped structures 175. By way of non-limiting example, the first sub-step structures 170 of the first stepped structure 175 (in the central array region 119) may be located within the horizontal boundary (e.g., in the X direction) of the third sub-step structures 170 of the third stepped structure 175 (in the edge region 117) and may be vertically offset (e.g., in the Z direction) from the third sub-step structures 170.

[0127] The conductive contact structures 180 may be formed of and include a conductive material, such as one or more of the materials described above with reference to the first conductive structure 134. In some embodiments, the conductive contact structures 180 individually include substantially the same material composition as the first conductive structure 134. In some embodiments, the conductive contact structures 180 individually include tungsten.

[0128] although Figure 1W to Figure 1XThe step structures 175 are illustrated as individually including a specific number of second steps 162 (e.g., 32 second steps 162; eight (8) sub-step structures 170, each including four (4) second steps 162), but the present disclosure is not limited thereto. In other embodiments, the step structures 175 may individually include a desired number of sub-step structures 170 and a desired number of total second steps 162 (e.g., a desired number of stepped second conductive structures 154). In some embodiments, the step structures 175 individually include a number of second steps 162 within a range from approximately thirty-two (32) second steps 162 to two hundred and fifty-six (256) second steps 162. In some embodiments, the step structures 175 each individually include sixty-four (64) second steps 162. In other embodiments, the step structures 175 each individually include ninety-six (96) or more second steps 162. In other embodiments, the stepped structures 175 each individually include a different number of second steps 162, such as less than sixty-four (64) second steps 162 (e.g., less than or equal to sixty (60) second steps 162, less than or equal to fifty (50) second steps 162, less than approximately forty (40) second steps 162, less than or equal to thirty (30) second steps 162, less than or equal to twenty (20) second steps 162, less than or equal to ten (10) second steps 162) or greater than sixty-four (64) second steps 162 (e.g., greater than or equal to seventy (70) second steps 162, greater than or equal to one hundred (100) second steps 162, greater than or equal to approximately one hundred and twenty-eight (128) second steps 162, greater than two hundred and fifty-six (256) second steps 162).

[0129] Figure 1W and Figure 1X It is in reference Figure 1S to Figure 1V A simplified partial top view of the microelectronic device 100 at a processing stage following the processing stage described ( Figure 1W ) and simplified partial cross-sectional view ( Figure 1X ). Figure 1X is through Figure 1W The section line XX is intercepted Figure 1W FIG. 1 is a simplified partial cross-sectional view of a microelectronic device 100 .

[0130] Storage devices 185 (e.g., capacitors) may be formed within array region 102, each storage device 185 individually contacting access devices 130. Storage devices 185 may form a vertical stack of storage devices 185 including vertical tiers of storage devices 185 individually contacting tiers of access devices 130 in the vertical stack of access devices 130. Each access device 130 in contact with storage devices 185 may form a memory cell 186 and the vertical stack of access devices 130 coupled to the vertical stack of storage devices 185 may form a corresponding vertical stack of memory cells 186. Thus, the vertical stack of memory cells 186 may individually include vertically spaced (e.g., in the Z direction) tiers of memory cells 186, each memory cell 186 individually including a storage device 185 horizontally adjacent (e.g., in the Y direction) to an access device 130.

[0131] although Figure 1W Each of the array regions 102 is illustrated as individually including sixteen (16) vertical stacks of memory cells 186 (e.g., four (4) rows and four (4) columns of vertical stacks of memory cells 186), but the disclosure is not limited in this regard and the array regions 102 may individually include greater than 16 vertical stacks of memory cells 186.

[0132] Continue to refer Figure 1W and Figure 1X , in some embodiments, the storage device 185 is in contact with a conductive plate structure 187. By way of non-limiting example, the second electrode 184 of the storage device 185 is in contact with the conductive plate structure 187. The conductive plate structure 187 may be formed of a conductive material and include a conductive material, such as one or more of the materials of the electrodes of the storage device 185 (e.g., the second electrode 184). In some embodiments, the conductive plate structure 187 includes a material composition substantially the same as that of the electrodes of the storage device 185. In other embodiments, the conductive plate structure 187 includes a material composition different from that of the electrodes of the storage device 185. The conductive plate structure 187 may be referred to herein as a "conductive plate" or a "grounding structure." The conductive plate structure 187 extends horizontally (e.g., in the X direction) as a conductive plate. In some embodiments and with reference to Figure 1W , the conductive plate structure 187 extends horizontally in substantially the same direction and substantially parallel to the first conductive structure 134 of the vertical stacked structure 135. The conductive plate structure 187 may be horizontally between vertical stacks of memory cells 186 (e.g., in the Y direction), such as between vertical stacks of memory devices 185.

[0133] Each of the memory devices 185 individually includes a first electrode 182 (also referred to herein as an "outer electrode", "first electrode plate" or "first node structure"), a second electrode 184 (also referred to herein as an "inner electrode", "second electrode plate" or "second node structure"), and a dielectric material 183 between the first electrode 182 and the second electrode 184. In some such embodiments, the memory devices 185 individually include capacitors. However, the present disclosure is not limited thereto and in other embodiments, the memory devices 185 may each individually include other structures such as, for example, a phase change memory (PCM), a resistive random access memory (RRAM), a conductive bridging random access memory (conductive bridging RAM), or another structure for storing logic states.

[0134] At least a portion of each storage device 185 contacts a horizontally adjacent (eg, in the X direction) access device 130 . In some embodiments, the first electrode 182 of each storage device 185 contacts a horizontally adjacent access device 130 .

[0135] The first electrode 182 may be formed of a conductive material and include a conductive material such as, for example, one or more of the following: a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), a material including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of alloys thereof, a conductive doped semiconductor material (eg, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium), polysilicon, or other materials exhibiting conductivity. In some embodiments, the first electrode 182 includes titanium nitride.

[0136] The second electrode 184 may be formed of and include a conductive material. In some embodiments, the second electrode 184 includes one or more of the materials described above with reference to the first electrode 182. In some embodiments, the second electrode 184 includes substantially the same material composition as the first electrode 182.

[0137] The dielectric material 183 may be formed from and include one or more of the following: silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (such as silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (such as ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT)) and high-k dielectric materials.

[0138] The second electrode 184 can be in contact with one of the vertically stacked conductive plate structures 187 of the memory cell 186. In some embodiments, the second electrode 184 is substantially integrated with the conductive plate structure 187. Figure 1X , in some embodiments, horizontally adjacent (e.g., in the X direction) vertically stacked second electrodes 184 of the memory devices 185 contact the same conductive plate structure 187. In some embodiments, the conductive plate structures 187 are individually formed of conductive materials, such as one or more of the materials of the second electrodes 184. In some embodiments, the conductive plate structures 187 include substantially the same material composition as the second electrodes 184. In other embodiments, the conductive plate structures 187 include a different material composition than the second electrodes 184.

[0139] refer to Figure 1X , the step region 104 is horizontally between horizontally adjacent array regions 102 (e.g., in the X direction) that include vertical stacks of memory cells 186. The step structures 175 are horizontally positioned between the array regions 102 (e.g., in the X direction). The step structures 175 individually include vertical stacks of first conductive structures 134 extending horizontally (e.g., in the X direction) through the step region 104 and into each of the array regions 102.

[0140] In use and operation, the first conductive structures 134 may be individually configured to provide a sufficient voltage to a channel region 132 that is directly vertically adjacent (e.g., in the Z direction) to a respective access device 130 to electrically couple a storage device 185 that is horizontally adjacent (e.g., in the Y direction) and associated with the access device 130 to, for example, a conductive pillar structure 140 extending vertically proximate to a vertical stack of access devices 130 of a vertical stack of memory cells 186. In other words, each of the first conductive structures 134 may individually include a gate structure that is configured to provide a sufficient voltage to a channel region 132 that is vertically adjacent (e.g., in the Z direction) to the first conductive structure 134 to electrically couple the access device 130 that includes the channel region 132 to a horizontally adjacent (e.g., in the Y direction) storage device 185. Because the first conductive structure 134 is configured to provide a voltage to the memory cell 186 (e.g., by means of a voltage applied to the corresponding second conductive structure 154 through the corresponding conductive contact structure 180), the first conductive structure 134 may be referred to herein individually as a "first conductive line," "access line," or "word line."

[0141] Thus, the first conductive structures 134 of the memory cells 186 of two different array regions 102 can be driven (e.g., a voltage can be applied to the first conductive structures 134) by applying a voltage to one or more of the conductive contact structures 180 in the step structures 175 located in the step region 104. In some embodiments, each individual first conductive structure 134 is configured to provide a voltage (e.g., a drive voltage, an access voltage) to the level of the memory cells 186 in each of the two array regions 102 that are horizontally separated from each other by the step region 104.

[0142] Still refer to Figure 1W and Figure 1X , global digit lines 188 may be formed above the vertical stack of memory cells 186. Each global digit line 188 may be configured to electrically communicate with more than one conductive pillar structure 140 by means of, for example, transistors (e.g., multiplexers) of semiconductive material 112. The transistors of semiconductive material 112 may be in contact with conductive interconnect structures 189, which are in contact with global digit lines 188 and conductive pillar structures 140. Routing structures 190 provide an electrically conductive path from one of the conductive interconnect structures 189 in contact with the transistors of semiconductive material 112 to a conductive interconnect structure 189 in contact with conductive pillar structures 140.

[0143] Each of the global digit lines 188 may be in contact with more than one vertical stack of memory cells 186 , such as more than one conductive pillar structure (local digit line) 140 of a different vertical stack of memory cells 186 .

[0144] The global digit line 188 may also be referred to as a “conductive line.” The global digit line 188 may be formed vertically above the conductive pillar structure 140 (eg, in the Z direction) and electrically communicate with the conductive pillar structure 140 via a transistor within the semiconductive material 112. Figure 1W , the global digit line 188 is positioned within the array region 102 and extends in a horizontal direction (eg, Y direction) substantially perpendicular to the vertical stack structure 135 .

[0145] Continue to refer Figure 1X In some embodiments, the conductive plate structure 187 is configured to electrically communicate with the transistors of the semiconductive material 112 by way of an additional one of a conductive interconnect structure 189 and a routing structure 190 .

[0146] Each of the conductive interconnect structures 189 and routing structures 190 individually includes a conductive material, such as one or more of the materials described above with reference to the first conductive structure 134. In some embodiments, each of the conductive interconnect structures 189 and routing structures 190 individually includes tungsten.

[0147] In some embodiments, the second step 162 of the sub-step structure 170 vertically descends (e.g., in the Z direction) in a horizontal direction (e.g., in the Y direction) substantially perpendicular to the conductive plate structure 187. In some embodiments, the conductive plate structure 187 is horizontally formed in an additional stadium-shaped structure ( Figure 1T ) between horizontally adjacent (eg, in the Y direction) step structures 175 (eg, in the Y direction).

[0148] refer to Figure 1W In some embodiments, conductive routing region 192 may be defined within a horizontal boundary (e.g., in the X direction, in the Y direction) of isolation structure 148. Conductive routing region 192 may be positioned horizontally between step structure 175 and the vertical stack of memory cells 186 (e.g., in the X direction). Conductive interconnect and routing structures 194 (only one of which is shown in FIG. 1 for clarity and ease of understanding of the description) may be positioned horizontally between step structure 175 and the vertical stack of memory cells 186. Figure 1W ) can be electrically connected to the conductive contact structure 180 in the step region 104 and can be electrically connected to the additional conductive contact structure 196 in the conductive routing region 192 (for clarity and ease of understanding of the description, only one of which is shown in Figure 1W ) are electrically connected.

[0149] The additional conductive contact structure 196 can be configured to be in electrical communication with circuitry of an additional microelectronic device (e.g., a microelectronic device structure) including circuitry (e.g., one or more of a sub-word line driver, a sense amplifier device (e.g., an equalization (EQ) amplifier, an isolation (ISO) amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), a column decoder, a multiplexer control logic device, a sense amplifier driver, a main word line driver device, a row decoder device, and a row select device) that can be attached to the microelectronic device 100. In some embodiments, the additional conductive contact structure 196 is configured to be in electrical communication with a sub-word line driver of the additional microelectronic device and is configured to electrically couple the first conductive structure 134 to the sub-word line driver of the additional microelectronic device.

[0150] Therefore, according to some embodiments of the present disclosure, a microelectronic device includes: a memory array region including a vertical stack of dynamic random access memory (DRAM) cells, each of the DRAM cells including a memory device in the vertical stack of memory devices and a horizontally adjacent access device in the vertical stack of access devices; a step region substantially horizontally adjacent to the memory array region in a first horizontal direction. The step region includes: a vertical stack of first conductive structures extending horizontally through the step region in the first horizontal direction, the first conductive structures contacting the DRAM cells; and sub-step structures individually including second conductive structures contacting the first conductive structures and extending horizontally from the first conductive structures in a second horizontal direction substantially perpendicular to the first horizontal direction, each of the sub-step structures individually including at least four steps, each of the at least four steps being defined at a horizontal boundary of one of the second conductive structures defining the step.

[0151] Therefore, according to some embodiments of the present disclosure, a memory device includes a memory array region including a vertical stack of memory cells, the vertical stack of memory cells including: a vertical stack of access devices; a vertical stack of storage devices horizontally adjacent to the vertical stack of access devices; and a portion of a vertical stack structure including a substantially linear first conductive structure extending horizontally through the vertical stack of memory cells, the substantially linear first conductive structure being adjacent to the memory cell of the vertical stack of memory cells. The memory device further includes a step region horizontally adjacent to the memory array region, the step region including a step structure, the step structure including: an additional portion of the vertical stack structure extending horizontally from the memory array region through the step region in a first direction; and a sub-step structure extending horizontally from the vertical stack structure in a second direction different from the first direction, the sub-step structures individually including a second conductive structure defining at least three steps of the sub-step structure.

[0152] The microelectronic device of the present disclosure (such as microelectronic device 100) may be included in an embodiment of the electronic system of the present disclosure. For example, Figure 2 2 is a block diagram of an electronic system 200 according to an embodiment of the present disclosure. The electronic system 200 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 200 includes at least one memory device 202. For example, the memory device 202 may include a microelectronic device previously described herein (e.g., a microelectronic device previously described in reference Figures 1A to 1X An embodiment of a microelectronic device 100 is described.

[0153] The electronic system 200 may further include at least one electronic signal processor device 204 (commonly referred to as a "microprocessor"). The electronic signal processor device 204 may optionally include an embodiment of one or more of the microelectronic devices and microelectronic device structures previously described herein. The electronic system 200 may further include one or more input devices 206 for inputting information into the electronic system 200 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 200 may further include one or more output devices 208 for outputting information (e.g., visual or audio output) to the user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 206 and the output device 208 may constitute a single touch screen device that can be used both to input information to the electronic system 200 and to output visual information to the user. The input device 206 and the output device 208 may be in electrical communication with one or more of the memory device 202 and the electronic signal processor device 204.

[0154] Therefore, in at least some embodiments, an electronic device includes: an input device; an output device; a processor device, which is operably coupled to the input device and the output device; and a microelectronic device, which is operably coupled to the processor device and includes: a first array area, which includes a first vertical stack of memory cells including a first vertical stack of storage devices horizontally adjacent to the first vertical stack of access devices; a second array area, which includes a second vertical stack of memory cells including a second vertical stack of storage devices horizontally adjacent to the second vertical stack of access devices; a step area, which is horizontally between the first array area and the second array area and includes a step structure. At least one of the stepped structures includes: a vertical stack including a first conductive structure extending horizontally through the stepped region and through the first array region and the second array region; a sub-step structure including a second conductive structure extending horizontally in a horizontal direction extending away from the vertical stack, the sub-step structures individually including steps that descend vertically in the horizontal direction extending away from the vertical stack and defined by an edge of the second conductive structure; and a conductive contact structure that contacts the second conductive structure in the horizontal direction extending away from the vertical stack and in a vertical direction.

[0155] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0156] Embodiment 1: A microelectronic device, comprising: a memory array area, which includes a vertical stack of dynamic random access memory (DRAM) cells, each of the DRAM cells including a storage device in the vertical stack of storage devices and a horizontally adjacent access device in the vertical stack of access devices; a step area, which is substantially horizontally adjacent to the memory array area in a first horizontal direction, the step area comprising: a vertical stack of first conductive structures, which extend horizontally through the step area in the first horizontal direction, the first conductive structure contacting the DRAM cells; and sub-step structures, which individually include second conductive structures contacting the first conductive structure and extending horizontally from the first conductive structure in a second horizontal direction substantially perpendicular to the first horizontal direction, each of the sub-step structures individually including at least four steps, each of the at least four steps being defined at a horizontal boundary of one of the second conductive structures defining the step.

[0157] Embodiment 2: The microelectronic device according to Embodiment 1, further comprising a conductive contact structure individually contacting the second conductive structure of each step of the sub-stair structure.

[0158] Embodiment 3: The microelectronic device of Embodiment 2, wherein each electrically conductive contact structure individually contacts the second electrically conductive structure on a first surface of the electrically conductive contact structure extending horizontally in the second horizontal direction and on a second surface extending vertically.

[0159] Embodiment 4: A microelectronic device according to any one of embodiments 1 to 3, further comprising an additional sub-stair structure horizontally spaced apart from the sub-stair structure in the second horizontal direction, at least some steps of the additional sub-stair structure being vertically offset in the first horizontal direction from the corresponding steps of the sub-stair structure and within the horizontal boundary.

[0160] Embodiment 5: According to the microelectronic device described in embodiment 4, it further includes an additional sub-stair structure horizontally spaced from the sub-stair structure in the second horizontal direction, and at least some steps of the additional sub-stair structure are vertically aligned in the first horizontal direction with the corresponding steps of the sub-stair structure and within the horizontal boundary.

[0161] Embodiment 6: The microelectronic device according to any one of embodiments 1 to 5, further comprising an additional memory array region separated from the memory array region by the step region in the first horizontal direction.

[0162] Embodiment 7: A microelectronic device according to embodiment 6, wherein at least one of the second conductive structures contacts at least one of the first conductive structures, and the at least one of the first conductive structures contacts some of the DRAM cells in the memory array area and some additional DRAM cells in the additional memory array area.

[0163] Embodiment 8: The microelectronic device of any one of embodiments 1 to 7, wherein a pitch of the sub-staircase structures in the first horizontal direction is about twice a pitch of the vertical stack of DRAM cells in the first horizontal direction.

[0164] Embodiment 9: The microelectronic device of any one of Embodiments 1 to 8, further comprising a liner material overlying the at least four steps of each of the sub-step structures.

[0165] Embodiment 10: The microelectronic device of Embodiment 9, wherein the liner material comprises aluminum oxide.

[0166] Embodiment 11: The microelectronic device of any one of embodiments 1 to 10, further comprising a conductive routing region horizontally between the memory array region and the step region.

[0167] Embodiment 12: A memory device comprising: a memory array region comprising a vertical stack of memory cells, the vertical stack of memory cells comprising: a vertical stack of access devices; a vertical stack of storage devices horizontally adjacent to the vertical stack of access devices; and a portion of the vertical stack structure comprising a substantially linear first conductive structure extending horizontally through the vertical stack of memory cells, the substantially linear first conductive structure being adjacent to the memory cells of the vertical stack of memory cells; and a step region horizontally adjacent to the memory array region, the step region comprising a step structure, the step structure comprising: an additional portion of the vertical stack structure extending horizontally from the memory array region through the step region in a first direction; and a sub-step structure extending horizontally from the vertical stack structure in a second direction different from the first direction, the sub-step structures individually comprising a second conductive structure defining at least three steps of the sub-step structure.

[0168] Embodiment 13: The memory device of Embodiment 12, wherein the additional portion of the vertically stacked structure extends horizontally from the memory array region, through the staircase region, and to an additional memory array region.

[0169] Embodiment 14: The memory device according to one of embodiments 12 and 13, wherein the sub-staircase structures individually include four steps descending vertically in the second direction.

[0170] Embodiment 15: The memory device of any one of Embodiments 12 to 14, wherein the second conductive structure of the sub-staircase structure vertically descends in the first direction in a direction from the memory array region toward the staircase region.

[0171] Embodiment 16: The memory device according to embodiment 15 further comprises: an additional portion of an additional stacked structure, comprising an additional first conductive structure extending horizontally from the memory array region through the step region in the first direction; and an additional sub-step structure, comprising an additional second conductive structure extending horizontally from the additional first conductive structure in the second direction, the additional sub-step structure comprising a stadium-type structure in the first direction.

[0172] Embodiment 17: The memory device of Embodiment 16, wherein a vertically lowermost step of the additional sub-stair structure is horizontally offset from a vertically lowermost step of the sub-stair structure in the first direction.

[0173] Embodiment 18: The memory device of any one of Embodiments 12 to 17, further comprising conductive contact structures individually contacting the second conductive structures in the second direction and in a vertical direction.

[0174] Embodiment 19: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a microelectronic device coupled to the processor device and comprising: a first array region comprising a first vertical stack of memory cells including a first vertical stack of storage devices horizontally adjacent to the first vertical stack of access devices; a second array region comprising a second vertical stack of memory cells including a second vertical stack of storage devices horizontally adjacent to the second vertical stack of access devices; a stepped region horizontally between the first array region and the second array region The invention relates to a semiconductor device for transmitting the semiconductor device to the semiconductor device of claim 1 , wherein the semiconductor device comprises a semiconductor layer and a semiconductor layer connected to the semiconductor device. The semiconductor device comprises a semiconductor layer connected to the semiconductor device of claim 1 , wherein the semiconductor layer has a plurality of semiconductor layers connected to the semiconductor device. The semiconductor device comprises a semiconductor layer connected to the semiconductor device of claim 1 , wherein the semiconductor layer has a plurality of semiconductor layers connected to the semiconductor device of claim 1 .

[0175] Embodiment 20: The electronic system according to Embodiment 19, wherein each sub-stair structure is defined by four edges of the second conductive structures.

[0176] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, it will be recognized and appreciated by those of ordinary skill in the art that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Specifically, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure, such as the scope claimed in the claims, including legal equivalents. Additionally, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device comprising: a memory array region comprising a vertical stack of dynamic random access memory (DRAM) cells, each of the DRAM cells comprising a storage device in the vertical stack of storage devices and a horizontally adjacent access device in the vertical stack of access devices; a stepped region substantially horizontally adjacent to the memory array region in a first horizontal direction, the stepped region comprising: a vertical stack of first conductive structures extending horizontally through the stepped region in the first horizontal direction, the first conductive structures contacting the DRAM cells; and Sub-step structures, each of which individually includes a second conductive structure in contact with the first conductive structure and extending horizontally from the first conductive structure in a second horizontal direction substantially perpendicular to the first horizontal direction, each of the sub-step structures individually including at least four steps, each of the at least four steps being defined at a horizontal boundary of one of the second conductive structures defining the step. 2 . The microelectronic device according to claim 1 , further comprising a conductive contact structure individually contacting the second conductive structure of each step of the sub-stair structure. 3 . The microelectronic device of claim 2 , wherein each conductive contact structure individually contacts the second conductive structure on a first surface of the conductive contact structure extending horizontally in the second horizontal direction and on a second surface extending vertically.

4. The microelectronic device of any one of claims 1 to 3, further comprising an additional sub-stair structure horizontally spaced apart from the sub-stair structure in the second horizontal direction, at least some steps of the additional sub-stair structure being vertically offset in the first horizontal direction from corresponding steps of the sub-stair structure and within horizontal boundaries.

5. The microelectronic device of claim 4 , further comprising another additional sub-stair structure horizontally spaced apart from the sub-stair structure in the second horizontal direction, at least some steps of the additional sub-stair structure being vertically aligned in the first horizontal direction and within horizontal boundaries of corresponding steps of the sub-stair structure.

6. The microelectronic device of any one of claims 1 to 3, further comprising an additional memory array region spaced apart from the memory array region by the step region in the first horizontal direction.

7. A microelectronic device according to claim 6, wherein at least one of the second conductive structures contacts at least one of the first conductive structures, and the at least one of the first conductive structures contacts some of the DRAM cells of the memory array area and some additional DRAM cells of the additional memory array area.

8. The microelectronic device of any one of claims 1 to 3, wherein a pitch of the sub-staircase structures in the first horizontal direction is about twice a pitch of the vertical stack of DRAM cells in the first horizontal direction.

9. The microelectronic device of any one of claims 1 to 3, further comprising a liner material overlying the at least four steps of each of the sub-step structures.

10. The microelectronic device of claim 9, wherein the liner material comprises aluminum oxide.

11. The microelectronic device of any one of claims 1 to 3, further comprising a conductive routing region horizontally between the memory array region and the step region.

12. A memory device comprising: A memory array region comprising a vertical stack of memory cells, the vertical stack of memory cells comprising: vertical stacking of storage and access devices; a vertical stack of storage devices horizontally adjacent to the vertical stack of access devices; and a portion of a vertical stack structure comprising a substantially linear first conductive structure extending horizontally through the vertical stack of memory cells, the substantially linear first conductive structure being adjacent to the memory cell of the vertical stack of memory cells; and A step region, which is horizontally adjacent to the memory array region, the step region comprising a step structure, the step structure comprising: an additional portion of the vertical stack structure extending horizontally from the memory array region through the step region in a first direction; and Sub-stair structures extend horizontally from the vertical stack structure in a second direction different from the first direction, the sub-stair structures individually including second conductive structures defining at least three steps of the sub-stair structures.

13. The memory device of claim 12, wherein the additional portion of the vertically stacked structure extends horizontally from the memory array region, through the staircase region, and to an additional memory array region. 14 . The memory device of claim 12 , wherein the sub-stair structures individually include four steps vertically descending in the second direction.

15. The memory device of any one of claims 12 to 14, wherein the second conductive structure of the sub-staircase structure descends vertically in the first direction in a direction from the memory array region toward the staircase region.

16. The memory device of claim 15, further comprising: an additional portion of an additional stacked structure including an additional first conductive structure extending horizontally from the memory array region through the step region in the first direction; and An additional sub-step structure includes an additional second conductive structure extending horizontally from the additional first conductive structure in the second direction, the additional sub-step structure including a stadium-type structure in the first direction. 17 . The memory device of claim 16 , wherein a vertically lowermost step of the additional sub-stair structure is horizontally offset from a vertically lowermost step of the sub-stair structure in the first direction.

18. The memory device of any one of claims 12-14, further comprising conductive contact structures individually contacting the second conductive structures in the second direction and in a vertical direction.

19. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; and a microelectronic device coupled to the processor device and comprising: A first array region comprising storage devices horizontally adjacent to a first vertical stack of access devices a first vertical stack of first vertically stacked memory cells; A second array region comprising storage devices horizontally adjacent to a second vertical stack of access devices a second vertical stack of second vertically stacked memory cells; a step region horizontally between the first array region and the second array region and comprising a step structure, at least one of the step structures comprising: a vertical stack including a first conductive structure extending horizontally through the step region and through the first array region and the second array region; sub-stair structures including second conductive structures extending horizontally in a horizontal direction extending away from the vertical stack, the sub-stair structures individually including steps descending vertically in the horizontal direction extending away from the vertical stack and defined by edges of the second conductive structures; and A conductive contact structure contacts the second conductive structure in the horizontal direction extending away from the vertical stack and in the vertical direction. 20 . The electronic system of claim 19 , wherein each sub-stair structure is defined by four edges of the second conductive structures.

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