Semiconductor memory device

Abstract

A semiconductor memory device includes a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure includes: an active region; a first gate structure including a first gate insulating layer intersecting the active region and in contact with the active region; a second gate structure including a second gate insulating layer spaced apart from the first gate structure and in contact with the active region; and a source / drain region between the first gate structure and the second gate structure. The thickness of the first gate insulating layer is smaller than that of the second gate insulating layer. The source / drain region includes a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. The depth of the first region is equal to that of the second region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0096641 filed in the Korean Intellectual Property Office on July 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various example embodiments relate to a semiconductor memory device. Background Art

[0004] In order to meet or help meet consumer demand for superior performance and / or low prices, it is desirable to increase the integration density of semiconductor memory devices. In semiconductor memory devices, it is particularly necessary or desirable to increase the integration density because the integration density of semiconductor memory devices can be an important factor in determining product prices.

[0005] Meanwhile, regarding the structure of transistors controlling the operation of memory cells, research is being conducted on a process for implementing one or more transistors having gate insulating layers of different thicknesses on one active region. Summary of the invention

[0006] Various example embodiments provide a semiconductor memory device having improved performance and reliability.

[0007] However, the inventive concept is not limited to the concept set forth herein. The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept belongs by referring to the following detailed description of various exemplary embodiments.

[0008] According to some example embodiments, a semiconductor memory device is provided, including a cell structure and a peripheral circuit structure electrically connected to the cell structure. The cell structure includes: a plurality of gate electrodes extending in a first direction and spaced apart in a second direction; a channel structure penetrating the plurality of gate electrodes in a second direction; and a bit line connected to the channel structure and extending in a third direction. The peripheral circuit structure includes: an active area; a first gate structure including a first gate insulating layer intersecting with and contacting the active area; a second gate structure including a second gate insulating layer spaced apart from the first gate structure and contacting the active area; and a source / drain region located in the active area and between the first gate structure and the second gate structure. The thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer. The source / drain region includes a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. The depth of the first region is equal to the depth of the second region.

[0009] Alternatively or additionally, according to various example embodiments, there is provided a semiconductor memory device, comprising: a first active region and a second active region, defined by an element isolation layer; a first gate structure, comprising a first gate insulating layer intersecting and contacting the first active region; a second gate structure, comprising a second gate insulating layer extending parallel to the first gate structure and contacting the first active region; a first source / drain region, located in the first active region and between the first gate structure and the second gate structure; a third gate structure, comprising a third gate insulating layer intersecting and contacting the second active region; and a second source / drain region, located in the second active region and on at least one side of the third gate structure. The thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer, wherein the first source / drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. The depth of the first region is equal to the depth of the second region. The top surface of the first region is located below the top surface of the second source / drain region.

[0010] Alternatively or additionally, according to various example embodiments, a semiconductor memory device is provided, comprising a cell structure and a peripheral circuit structure electrically connected to the cell structure. The cell structure comprises: a plurality of gate electrodes extending in a first direction and spaced apart in a second direction; a channel structure penetrating the plurality of gate electrodes in a second direction; and a bit line connected to the channel structure and extending in a third direction. The peripheral circuit structure comprises: a first active region and a second active region defined by an element isolation layer; a first gate structure comprising a first gate insulating layer intersecting with and contacting the first active region; a second gate structure comprising a second gate insulating layer extending parallel to the first gate structure and contacting the first active region; a first source / drain region located in the first active region and between the first gate structure and the second gate structure; a third gate structure comprising a third gate insulating layer intersecting with and contacting the second active region; and a second source / drain region located in the second active region and on at least one side of the third gate structure. The thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer. The first source / drain region includes a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. The top surface of the first region is above the top surface of the second region, but below the top surface of the second source / drain region. The depth of the first region is equal to the depth of the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is an example block diagram illustrating a semiconductor memory device according to some example embodiments.

[0013] Figure 2 is an example circuit diagram illustrating a semiconductor memory device according to some example embodiments.

[0014] Figure 3 are example cross-sectional views of semiconductor memory devices according to some example embodiments.

[0015] Figure 4 yes Figure 3 Magnified view of region R1.

[0016] Figure 5 yes Figure 3 An enlarged view of region R2.

[0017] Figures 6 to 9 It is to illustrate that according to some other embodiments Figure 3 FIG. 1 is a graph of region R2.

[0018] Fig.10 yes Figure 3 An enlarged view of region R3.

[0019] Fig.11 and Fig.12 It is to illustrate that according to some other embodiments Figure 3 FIG. 1 is a graph of region R3.

[0020] Fig.13 yes Figure 3 An enlarged view of region R4.

[0021] Fig.14 is a cross-sectional view of a semiconductor memory device according to some other embodiments.

[0022] Figures 15 to 20 are diagrams showing intermediate steps for explaining a method for manufacturing a semiconductor memory device according to some example embodiments.

[0023] Fig.21 is an example block diagram illustrating an electronic system according to some example embodiments.

[0024] Fig. 22 is an example perspective view illustrating an electronic system according to some example embodiments.

[0025] Fig.23 is along Fig. 22 An example cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0026] Although the terms "first", "second", etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are used to distinguish one element or component from another element or component. Therefore, without departing from the teachings of the present disclosure, the first element or component discussed below may also be referred to as the second element or component.

[0027] Figure 1 is an example block diagram illustrating a semiconductor memory device according to some example embodiments.

[0028] Reference Figure 1 , a semiconductor memory device 10 according to various example embodiments includes a memory cell array 20 and a peripheral circuit 30 .

[0029] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells, for example, the same or different numbers of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through the bit lines BL, the word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

[0030] The peripheral circuit 30 may receive one or more of an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and may transmit and receive data DATA to and from an external device of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit, a voltage generating circuit for generating various voltages required or used for the operation of the semiconductor memory device 10, and an error correction circuit for detecting and / or correcting errors of the data DATA read from the memory cell array 20.

[0031] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage level supplied to the word line WL and / or the bit line BL during the execution of a storage operation such as a program operation and / or an erase operation.

[0032] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR. The row decoder 33 may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL for at least one of the selected memory cell blocks BLK1 to BLKn. The row decoder 33 may transmit a voltage for performing a storage operation to the word line WL of at least one selected one of the memory cell blocks BLK1 to BLKn.

[0033] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver and / or as a sense amplifier. For example, during a programming operation, the page buffer 35 may operate as a write driver to apply a voltage corresponding to the data DATA to be stored in the memory cell array 20 to the bit line BL. On the other hand, during a read operation, the page buffer 35 may operate as a sense amplifier to read out the data DATA stored in the memory cell array 20.

[0034] Figure 2 is an example circuit diagram illustrating a semiconductor memory device according to some example embodiments.

[0035] Reference Figure 2 , a memory cell array (e.g., Figure 1 '20' in FIG. 1 may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0036] The common source line CSL may extend along the first direction D1. In some example embodiments, a plurality of common source lines CSL may be arranged two-dimensionally. For example, a plurality of common source lines CSL may extend in the first direction D1 while being spaced apart from each other. The same voltage may be applied to the common source lines CSL. Alternatively, different voltages may be applied to the common source lines CSL for individual control.

[0037] A plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may extend along a third direction D3 intersecting the first direction D1 while being spaced apart from each other. A plurality of cell strings CSTR may be connected to each bit line BL in parallel. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

[0038] Each of the cell strings CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each of the memory cell transistors MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series in a second direction D2. In the present specification, the first direction D1, the third direction D3, and the second direction D2 may be substantially perpendicular to each other.

[0039] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL1 to WLn, and a string selection line SSL may be disposed between the common source line CSL and the bit line BL. The number of word lines WL1 to WLn may be different from the number of memory cell blocks BLK1 to BLKn. The ground selection line GSL may be used as the gate electrode of the ground selection transistor GST. The word lines WL1 to WLn may be used as the gate electrode of the memory cell transistor MCT, or may correspond to the gate electrode of the memory cell transistor MCT. The string selection line SSL may be used as the gate electrode of the string selection transistor SST, or may correspond to the gate electrode of the string selection transistor SST.

[0040] In some example embodiments, the erase control transistor ECT may be disposed between a common source line CSL and a ground selection transistor GST. The common source line CSL may be commonly connected to a source of the erase control transistor ECT. The erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistor ECT may perform an erase operation of the memory cell array by generating a gate induced drain leakage (GIDL).

[0041] Figure 3 are example cross-sectional views of semiconductor memory devices according to some example embodiments. Figure 4 yes Figure 3 Magnified view of region R1.

[0042] Reference Figure 3 and Figure 4 , a semiconductor memory device according to some example embodiments includes a cell structure CELL and a peripheral circuit structure PERI.

[0043] In some example embodiments, the cell structure CELL may include a cell substrate 100 , a mold structure MS, a cell interlayer insulating layer 120 , a channel structure CH, a word line cutting structure WLC, a bit line BL, a plurality of cell contacts 153 , and through-contacts 155 .

[0044] A semiconductor memory device according to various example embodiments may include a cell array region CAR, an extension region EXR, and a pad region PAD. Although the cell array region CAR, the extension region EXR, and the pad region PAD are illustrated as being connected to each other, the technical spirit of the present disclosure is not limited thereto.

[0045] A memory cell array including a plurality of memory cells (eg, Figure 1 '20' in ' may be formed in the cell array region CAR. For example, a channel structure CH, a bit line BL, gate electrodes ECL, GSL, WL1 to WL1n, and SSL, etc., which will be described later, may be provided in the cell array region CAR.

[0046] The extension region EXR may be disposed around the cell array region CAR. Gate electrodes ECL, GSL, WL1 to WLn, and SSL to be described later may be stacked in a step-by-step manner in the extension region EXR. In addition, a plurality of cell contacts 153 to be described later may be disposed in the extension region EXR.

[0047] The pad area PAD may be disposed inside or outside the cell array region CAR and the extension region EXR. A through-contact 155 or the like to be described later may be disposed in the pad area PAD.

[0048] The substrate may include a cell array region CAR, an extension region EXR, and a pad region PAD. The substrate may include a unit substrate 100 and an insulating pattern 101, but is not limited thereto.

[0049] The unit substrate 100 may include, for example, a semiconductor substrate, such as one or more of a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the unit substrate 100 may include a silicon-on-insulator (SOI) substrate and / or a germanium-on-insulator (GOI) substrate. In some example embodiments, the unit substrate 100 may include impurities. For example, the unit substrate 100 may include n-type impurities (e.g., phosphorus (P) and / or arsenic (As), etc.) and / or p-type impurities (e.g., boron (B), etc.).

[0050] The insulating pattern 101 may be disposed in the extension region EXR and the pad region PAD. The insulating pattern 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but is not limited thereto. Unlike the illustration, the insulating pattern 101 may be disposed in the unit substrate 100 .

[0051] The mold structure MS may be disposed on a front surface (e.g., a top surface) of the unit substrate 100. The mold structure MS may include a plurality of mold insulating layers 110 and a plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL alternately stacked on the unit substrate 100. The mold insulating layer 110 and the gate electrodes ECL, GSL, WL1 to WLn, and SSL may have a layered structure in which each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL and each of the mold insulating layer 110 extend parallel to the top surface of the unit substrate 100. The gate electrodes ECL, GSL, WL1 to WLn, and SSL may be sequentially stacked on the unit substrate 100 while being spaced apart from each other by the mold insulating layer 110.

[0052] The gate electrodes ECL, GSL, WL1 to WLn, and SSL may be stacked on the extension region EXR in a step manner (e.g., a stair manner). For example, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may extend to different lengths along the first direction D1 and have a step portion. In some example embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may have a step portion in the third direction D3. Therefore, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may be exposed from other gate electrodes. The exposed portion may refer to an area where a plurality of cell contacts 153 and the gate electrodes contact each other.

[0053] In some example embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include an erase control line ECL, a ground selection line GSL, and a plurality of word lines WL1 to WLn sequentially stacked on the unit substrate 100. In some example embodiments, the erase control line ECL may be omitted.

[0054] The mold insulation layer 110 may be stacked on the extension region EXR in a stepped manner. For example, the mold insulation layer 110 may extend to different lengths along the first direction D1 and have a stepped portion. In some example embodiments, the mold insulation layer 110 may have a stepped portion in the third direction D3.

[0055] Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include a conductive material, for example, a metal such as one or more of tungsten (W), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon, but is not limited thereto. For example, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include tungsten (W). Unlike the illustration, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may be multilayered. For example, when the gate electrodes ECL, GSL, WL1 to WLn, and SSL are multilayered, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include a gate electrode barrier layer and a gate electrode filling layer. The gate electrode barrier layer may include, for example, titanium nitride (TiN), and the gate electrode filling layer may include tungsten (W), but example embodiments are not limited thereto.

[0056] The mold insulating layer 110 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. For example, the mold insulating layer 110 may include silicon oxide.

[0057] The channel structure CH may be disposed in the mold structure MS of the cell array region CAR. The channel structure CH may extend in a vertical direction (hereinafter referred to as a second direction D2) intersecting the top surface of the cell substrate 100, and may penetrate the mold structure MS and the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the channel structure CH may have a columnar shape (e.g., a cylindrical shape or a tapered cylindrical shape) extending in the second direction D2. Therefore, the channel structure CH may intersect each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL.

[0058] The channel structure CH may include a semiconductor pattern 130 and an information storage layer 132 .

[0059] The semiconductor pattern 130 may extend along the second direction D2 to penetrate the mold structure MS. The semiconductor pattern 130 is shown only as a cup shape, but this is only an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular tube shape, a prism shape, and a solid column shape. The semiconductor pattern 130 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nanostructure, but is not limited thereto.

[0060] The information storage layer 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the information storage layer 132 may extend along the outer side surface of the semiconductor pattern 130. The information storage layer 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one selected from the group consisting of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0061] In some example embodiments, the information storage layer 132 may be formed as multiple layers. Figure 4 As shown, the information storage layer 132 may include a tunnel insulating layer 132 a , a charge storage layer 132 b , and a blocking insulating layer 132 c sequentially stacked on an outer surface of the semiconductor pattern 130 .

[0062] The tunnel insulating layer 132a may include, for example, silicon oxide and / or a high-k material with a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al 2 O 3 ) and / or hafnium oxide (HfO 2 )). The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating layer 132c may include, for example, silicon oxide and / or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al 2 O 3 ) and / or hafnium oxide (HfO 2 )).

[0063] In some example embodiments, the channel structure CH may further include a filling pattern 134. The filling pattern 134 may be formed to fill the inside of the semiconductor pattern 130 having the cup shape. The filling pattern 134 may include an insulating material (eg, silicon oxide), but is not limited thereto.

[0064] In some example embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to be connected to the semiconductor pattern 130. For example, the channel pad 136 may be formed in a cell interlayer insulating layer 120 described later and connected to an upper portion of the semiconductor pattern 130. The channel pad 136 may include, for example, polysilicon doped with impurities, but is not limited thereto.

[0065] In some example embodiments, the source layer 102 and the source support layer 104 may be sequentially formed on the unit substrate 100. The source layer 102 and the source support layer 104 may be interposed between the unit substrate 100 and the mold structure MS. For example, the source layer 102 and the source support layer 104 may extend along the top surface of the unit substrate 100.

[0066] In some example embodiments, the source layer 102 may be formed to be connected to the semiconductor pattern 130 of the channel structure CH. Figure 4 As shown, the source layer 102 may penetrate the information storage layer 132 to contact the semiconductor pattern 130. The source layer 102 may be provided as a common source line (eg, Figure 2 The source layer 102 may include, for example, doped polysilicon and / or metal, but is not limited thereto.

[0067] In some example embodiments, the channel structure CH may penetrate the source layer 102 and the source supporting layer 104. For example, a lower portion of the channel structure CH may penetrate the source layer 102 and the source supporting layer 104 and be buried in the unit substrate 100.

[0068] In some example embodiments, the source support layer 104 may be used as a support layer for preventing the mold stack from falling or collapsing in a replacement step for forming the source layer 102 .

[0069] Although not shown, a base insulating layer may be interposed between the unit substrate 100 and the source layer 102. The base insulating layer may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0070] In some example embodiments, the insulating pattern 101 may be formed in the extension region EXR and the pad region PAD. Although the top surface of the insulating pattern 101 is shown to be coplanar with the top surface of the source support layer 104, this is only an example. As another example, the top surface of the insulating pattern 101 may be higher than the top surface of the source support layer 104 or located above the top surface of the source support layer 104.

[0071] The word line cutting structure WLC may cut the mold structure MS. The mold structure MS may be cut by the word line cutting structure WLC to form a plurality of memory cell blocks (eg, Figure 1 For example, although not shown, two adjacent word line cutting structures WLC may define one memory cell block therebetween. A plurality of channel structures CH may be provided in each of the memory cell blocks defined by the word line cutting structures WLC.

[0072] In some example embodiments, the word line cutting structure WLC may cut the source layer 102 and the source support layer 104. Although the bottom surface of the word line cutting structure WLC is shown as being coplanar with the bottom surface of the source layer 102, this is only an example. As another example, the bottom surface of the word line cutting structure WLC may be lower than the bottom surface of the source layer 102.

[0073] In some example embodiments, the word line cutting structure WLC may include an insulating material. For example, the insulating material may fill the word line cutting structure WLC. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0074] Although not shown, a string isolation structure may be provided in the mold structure MS. The string isolation structure may cut the string selection line SSL. Each of the memory cell blocks defined by the word line cutting structure WLC may be divided by the string isolation structure to form a plurality of string regions. For example, the string isolation structure may define two string regions in one memory cell block.

[0075] The cell interlayer insulating layer 120 may be disposed on the mold structure MS. The cell interlayer insulating layer 120 may cover the plurality of channel structures CH, the plurality of cell contacts 153, and the through-contacts 155. The cell interlayer insulating layer 120 may include an oxide-based insulating material. The cell interlayer insulating layer 120 may include, for example, at least one of silicon oxide, silicon oxynitride, or a low-k material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0076] The bit line BL may be disposed on the substrate in the cell array region CAR. The bit line BL may be formed on the mold structure MS. The bit line BL may be or may correspond to a bit line BL of a semiconductor memory device (see Figure 2 ). The bit line BL may be disposed in the cell interlayer insulating layer 120. The bit line BL may extend along a third direction D3.

[0077] The bit line BL may be connected to a plurality of channel structures CH. As an example, a first bit line contact 151 and a second bit line contact 161 connected to the upper portion of each channel structure CH may be formed in the cell interlayer insulating layer 120. The first bit line contact 151 is disposed on the channel structure CH. The first bit line contact 151 may be connected to the channel pad 136. The second bit line contact 161 is disposed on the first bit line contact 151. The second bit line contact 161 may be connected to the bit line BL. The second bit line contact 161 may be disposed between each bit line BL and the first bit line contact 151. The bit line BL may be electrically connected to the channel structure CH through the first bit line contact 151 and the second bit line contact 161.

[0078] The bit line BL may include a conductive material. For example, the bit line BL may include tungsten (W) and / or copper (Cu), but is not limited thereto.

[0079] A plurality of cell contacts 153 may be disposed on the substrate in the extension region EXR. The plurality of cell contacts 153 may extend in the extension region EXR along the second direction D2 and penetrate the cell interlayer insulating layer 120. Each of the plurality of cell contacts 153 may be connected to one of the plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, each of the plurality of cell contacts 153 may land on a gate electrode disposed at the highest level among the plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL. In some example embodiments, each of the plurality of cell contacts 153 may be electrically connected to a gate electrode disposed at the highest level among the plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL.

[0080] Top surfaces of the plurality of cell contacts 153 may all be coplanar. In addition, bottom surfaces of the plurality of cell contacts 153 may all be coplanar. However, example embodiments are not limited thereto.

[0081] A plurality of first metal patterns 170 may be disposed on the substrate in the extension region EXR. A plurality of first metal patterns 170 may be disposed on the mold structure MS. A plurality of first metal patterns 170 may be connected to a plurality of cell contacts 153, respectively. For example, a first via contact 163 may be formed between the plurality of first metal patterns 170 and the cell contact 153. A plurality of first metal patterns 170 may be electrically connected to the cell contact 153 through the first via contact 163.

[0082] The plurality of first metal patterns 170 may include a conductive material. For example, the plurality of first metal patterns 170 may include tungsten (W) and / or copper (Cu), but is not limited thereto.

[0083] The through contact 155 may be disposed on the substrate in the pad area PAD. The through contact 155 may extend in the pad area PAD along the second direction D2 to penetrate the cell interlayer insulating layer 120. In addition, the through contact 155 may also penetrate the insulating pattern 101. The through contact 155 may penetrate the insulating pattern 101 to be connected to the peripheral circuit element PT of the peripheral circuit structure PERI to be described later. The through contact 155 may be connected to, for example, the wiring pattern 290 of the peripheral circuit structure PERI.

[0084] A plurality of second metal patterns 180 may be disposed on the substrate in the pad region PAD. A plurality of second metal patterns 180 may be disposed in the cell interlayer insulating layer 120. A plurality of second metal patterns 180 may be connected to the through-contacts 155. For example, second via contacts 165 may be formed between the plurality of second metal patterns 180 and the through-contacts 155. A plurality of second metal patterns 180 may be electrically connected to the through-contacts 155 through the second via contacts 165.

[0085] The plurality of second metal patterns 180 may include a conductive material. For example, the plurality of second metal patterns 180 may include tungsten (W) and / or copper (Cu), but is not limited thereto.

[0086] In some example embodiments, the peripheral circuit structure PERI may include a peripheral circuit substrate or a peripheral circuit board 200 and a peripheral circuit element PT.

[0087] The peripheral circuit board 200 may be disposed below the unit substrate 100. For example, the top surface of the peripheral circuit board 200 may face the bottom surface of the unit substrate 100. The peripheral circuit board 200 may include, for example, a semiconductor substrate, such as one or more of a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon-on-insulator (SOI) substrate and / or a germanium-on-insulator (GOI) substrate.

[0088] The peripheral circuit element PT may be formed on the peripheral circuit board 200. The peripheral circuit element PT may constitute or correspond to a peripheral circuit (eg, Figure 1 For example, the peripheral circuit element PT may include control logic (e.g., Figure 1 "37" in ), row decoders (e.g., Figure 1 "33" in ) and page buffers (e.g., Figure 1 As an example, the peripheral circuit element PT may be a page buffer and may control the operation of the bit line BL, but example embodiments are not limited thereto.

[0089] In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit element PT is disposed may be referred to as the front surface of the peripheral circuit board 200. Conversely, the surface of the peripheral circuit board 200 opposite to the front surface of the peripheral circuit board 200 may be referred to as the rear surface of the peripheral circuit board 200.

[0090] The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit element PT may include various active elements such as a transistor and / or a diode, and various passive elements such as one or more of a memristor, a capacitor, a resistor, and an inductor. Figure 3It is illustrated that the peripheral circuit element PT extends along the third direction D3 , but example embodiments are not limited thereto, and the peripheral circuit element PT may extend along the second direction D2 .

[0091] In some example embodiments, the rear surface of the unit substrate 100 may face the front surface of the peripheral circuit board 200. For example, a peripheral circuit interlayer insulating layer 220 covering the peripheral circuit element PT may be formed on the front surface of the peripheral circuit board 200. The unit substrate 100 and / or the insulating pattern 101 may be stacked on the top surface of the peripheral circuit interlayer insulating layer 220.

[0092] The plurality of second metal patterns 180 may be connected to the peripheral circuit element PT through the through-contacts 155. For example, a wiring pattern 290 connected to the peripheral circuit element PT may be formed in the peripheral circuit interlayer insulating layer 220. Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL, the bit line BL, and / or the source layer 102 may be electrically connected to the peripheral circuit element PT through the wiring pattern 290.

[0093] The peripheral circuit element PT may be separated by a peripheral element isolation layer 205. For example, the peripheral element isolation layer 205 may be disposed in the peripheral circuit board 200. The peripheral element isolation layer 205 may be or may include a shallow trench isolation (STI) layer. The peripheral element isolation layer 205 may define an active area of ​​the peripheral circuit element PT. The peripheral element isolation layer 205 may include an insulating material. The peripheral element isolation layer 205 may include, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0094] Will refer to Figures 5 to 14 The peripheral circuit element PT is described in more detail.

[0095] Figure 5 yes Figure 3 An enlarged view of region R2. Figure 5 , a semiconductor memory device according to various example embodiments may include an active region ACT, a first gate structure GS1 , a second gate structure GS2 , a first source / drain region 261 , a second source / drain region 262 , and a third source / drain region 263 .

[0096] The active area ACT may be disposed on the peripheral circuit board 200. The active area ACT may be used as a channel of a transistor. The first gate structure GS1 and the second gate structure GS2 may be disposed on the active area ACT. That is, the first gate structure GS1 and the second gate structure GS2 may be disposed on the same active area ACT.

[0097] The first gate structure GS1 may be disposed on the active area ACT. The first gate structure GS1 may intersect with the active area ACT. For example, assuming that the active area ACT extends along the X-axis direction, the first gate structure GS1 may extend along the Y-axis direction intersecting with the X-axis direction.

[0098] The first gate structure GS1 may include a first gate insulating layer 241 , a first lower gate pattern 242 , a first upper gate pattern 243 , a first gate capping layer 244 , and a first gate spacer 245 .

[0099] The first gate insulating layer 241, the first lower gate pattern 242, the first upper gate pattern 243, and the first gate capping layer 244 may be sequentially stacked on the active area ACT. For example, the first lower gate pattern 242 may be disposed on the first gate insulating layer 241. The first upper gate pattern 243 may be disposed on the first lower gate pattern 242. The first gate capping layer 244 may be disposed on the first upper gate pattern 243. The first gate insulating layer 241 may contact at least a portion of the active area ACT.

[0100] The first gate spacer 245 may extend along sidewalls of the first gate insulating layer 241 , the first lower gate pattern 242 , the first upper gate pattern 243 , and the first gate capping layer 244 .

[0101] The second gate insulating layer 251, the second lower gate pattern 252, the second upper gate pattern 253, and the second gate capping layer 254 may be sequentially stacked on the active area ACT. For example, the second lower gate pattern 252 may be disposed on the second gate insulating layer 251. The second upper gate pattern 253 may be disposed on the second lower gate pattern 252. The second gate capping layer 254 may be disposed on the second upper gate pattern 253. The second gate insulating layer 251 may contact at least a portion of the active area ACT. The second gate insulating layer 251 may not be disposed on the first source / drain region 261 and the third source / drain region 263.

[0102] The second gate spacer 255 may extend along sidewalls of the second gate insulating layer 251 , the second lower gate pattern 252 , the second upper gate pattern 253 , and the second gate capping layer 254 .

[0103] Each of the first gate insulating layer 241 and the second gate insulating layer 251 may simultaneously or independently include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, at least one selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. As an example, each of the first gate insulating layer 241 and the second gate insulating layer 251 may be formed of a silicon oxide layer.

[0104] Each of the first and second lower gate patterns 242 and 252 may include, for example, a polysilicon layer such as a doped polysilicon layer, but is not limited thereto.

[0105] Each of the first upper gate pattern 243 and the second upper gate pattern 253 may include a metal material. For example, each of the first upper gate pattern 243 and the second upper gate pattern 253 may include tungsten (W), but is not limited thereto.

[0106] Each of the first gate capping layer 244 and the second gate capping layer 254 may be formed of, for example, a silicon nitride layer, and in some example embodiments, the first gate capping layer 244 may be formed simultaneously with the second gate capping layer 254 and integrated with the second gate capping layer 254, but is not limited thereto.

[0107] The first gate spacer 245 and the second gate spacer 255 may be formed of, for example, a silicon oxide layer, and in some example embodiments, the first gate spacer 254 may be formed simultaneously with the second gate spacer 255 and integrated with the second gate spacer 255, but is not limited thereto. In some example embodiments, either or both of the first gate spacer 245 and the second gate spacer 255 may include a silicon oxide layer, but is not limited thereto.

[0108] In some example embodiments, a thickness 241 th of the first gate insulating layer 241 in the vertical direction is smaller than a thickness 251 th of the second gate insulating layer 251 in the vertical direction, for example, by a few angstroms (such as between 5 angstroms and 50 angstroms).

[0109] In this case, the top surface of the first gate insulating layer 241 and the top surface of the second gate insulating layer 251 may be located on the same plane. However, the bottom surface 241BS of the first gate insulating layer 241 is not located on the same plane as the bottom surface 251BS of the second gate insulating layer 251. For example, the vertical level of the bottom surface 241BS of the first gate insulating layer 241 may be higher than the vertical level of the bottom surface 251BS of the second gate insulating layer 251. In some example embodiments, the height from the top surface of the peripheral circuit board 200 to the bottom surface 241BS of the first gate insulating layer 241 is greater than the height from the top surface of the peripheral circuit board 200 to the bottom surface 251BS of the second gate insulating layer 251.

[0110] In the semiconductor memory device according to some example embodiments, since the thickness 241th of the first gate insulating layer 241 in the vertical direction is smaller than the thickness 251th of the second gate insulating layer 251 in the vertical direction, the amplitude of the voltage applied to the gate structure GS1 (e.g., the amplitude of the threshold voltage) may be smaller than the amplitude of the voltage applied to the second gate structure GS2. In some example embodiments, the length (e.g., the channel length) of the first gate structure GS1 may be the same as or different from the length or channel length of the second gate structure GS2 (e.g., greater than or less than the length or channel length of the second gate structure GS2).

[0111] In some example embodiments, a top surface 244US of the first gate capping layer 244 may be coplanar with a top surface 254US of the second gate capping layer 254. In addition, a thickness 244th of the first gate capping layer 244 in the vertical direction may be equal to a thickness 254th of the second gate capping layer 254 in the vertical direction.

[0112] In some example embodiments, the first gate structure GS1 and the second gate structure GS2 may be formed by the same process.

[0113] The first, second, and third source / drain regions 261, 262, and 263 may be disposed in the active region ACT. Each of the first, second, and third source / drain regions 261, 262, and 263 may be an impurity-doped region.

[0114] For example, when the first gate structure GS1 and the second gate structure GS2 are PMOS transistors, the first source / drain region 261, the second source / drain region 262, and the third source / drain region 263 may be doped with p-type impurities. As another example, when the first gate structure GS1 and the second gate structure GS2 are NMOS transistors, the first source / drain region 261, the second source / drain region 262, and the third source / drain region 263 may be doped with n-type impurities. In some example embodiments, the PMOS transistor may have light counter-doping of n-type impurities in the first source / drain region 261 and the second source / drain region 262; alternatively or additionally, the NMOS transistor may have light counter-doping of p-type impurities in the first source / drain region 261 and the second source / drain region 262; example embodiments are not limited thereto.

[0115] The first source / drain region 261 may be interposed between the first gate structure GS1 and the second gate structure GS2 .

[0116] In some example embodiments, the first source / drain region 261 may include a first region 261a, a second region 261b, and a third region 261c. The first region 261a of the first source / drain region 261 may be adjacent to the first gate structure GS1. The second region 261b of the first source / drain region 261 may be adjacent to the second gate structure GS2. The third region 261c of the first source / drain region 261 may be interposed between the first region 261a and the second region 261b.

[0117] As described herein, the expression "A is adjacent to B" may mean that A is arranged at a position adjacent to B or arranged beside B and in contact with B. For example, the first region 261a of the first source / drain region 261 may be disposed at a position adjacent to the first gate structure GS1. The first region 261a of the first source / drain region 261 may be in contact with the first gate structure GS1. However, the first region 261a of the first source / drain region 261 does not contact the second gate structure GS2.

[0118] In addition, the second region 261b of the first source / drain region 261 may be disposed adjacent to the second gate structure GS2. The second region 261b of the first source / drain region 261 may contact the second gate structure GS2. However, the second region 261b of the first source / drain region 261 does not contact the first gate structure GS1.

[0119] In some example embodiments, the vertical level of the top surface 261a_US of the first region 261a may be higher than the vertical level of the top surface 261b_US of the second region 261b or located above the vertical level of the top surface 261b_US of the second region 261b. For example, based on the top surface of the peripheral circuit board 200, the height of the top surface 261a_US of the first region 261a may be higher than the height of the top surface 261b_US of the second region 261b. The top surface of the third region 261c may have an inclination relative to the top surface of the peripheral circuit board 200. However, example embodiments are not limited thereto.

[0120] In some example embodiments, the depth 261a_D of the first region 261a in the vertical direction may be equal to the depth 261b_D of the second region 261b. The depth 261a_D of the first region 261a in the vertical direction may represent the maximum value among the depths of the first region 261a in the vertical direction. Similarly, the depth 261b_D of the second region 261b in the vertical direction may represent the maximum value among the depths of the second region 261b in the vertical direction.

[0121] As described herein, the depth of the source / drain region may correspond to a depth at which the concentration of impurities is low or reduced to a level close to zero. In some example embodiments, the depth of the source / drain region may be determined by an analytical method, such as but not limited to a secondary ion mass spectrometry (SIMS) method; however, example embodiments are not limited thereto.

[0122] As described above, in the semiconductor memory device according to various example embodiments, even if gate structures having gate insulating layers of different thicknesses are formed on the same active region ACT, the depth of the source / drain region can be kept constant. Therefore, a semiconductor memory device with improved reliability can be manufactured.

[0123] In some example embodiments, the horizontal plane of the bottom surface 241BS of the first gate insulating layer 241 may be different from the horizontal plane of the top surface 261a_US of the first region 261a of the first source / drain region 261. For example, the vertical level of the bottom surface 241BS of the first gate insulating layer 241 may be higher than the vertical level of the top surface 261a_US of the first region 261a. In some example embodiments, the height from the top surface of the peripheral circuit board 200 to the bottom surface 241BS of the first gate insulating layer 241 may be greater than the height of the top surface 261a_US of the first region 261a.

[0124] In the process of removing the oxide layer formed on both sides of the second gate structure GS2, a portion of the active area ACT adjacent to the first gate structure GS1 may be removed. Therefore, a stepped portion may be formed between the first gate insulating layer 241 and the first source / drain region 261. Similarly, a stepped portion may be formed between the first gate insulating layer 241 and the second source / drain region 262. Also in this case, the vertical level of the bottom surface 241BS of the first gate insulating layer 241 may be higher than the vertical level of the top surface of the second source / drain region 262.

[0125] The second source / drain region 262 may be disposed on one side of the first gate structure GS1. The second source / drain region 262 and the first source / drain region 261 may be the source / drain region of the first gate structure GS1. The third source / drain region 263 may be disposed on one side of the second gate structure GS2. The third source / drain region 263 and the first source / drain region 261 may be the source / drain region of the second gate structure GS2.

[0126] The semiconductor memory device according to various example embodiments may further include a first insulating layer 230. The first insulating layer 230 may extend along the top surfaces of the first to third source / drain regions 261, 262, and 263, the outline of the first gate structure GS1, and the outline of the second gate structure GS2. The first insulating layer 230 may also serve as an etching stop layer. For example, the first insulating layer 230 may be formed of a silicon nitride layer, but example embodiments are not limited thereto.

[0127] Figures 6 to 9 is an illustration of some example embodiments Figure 3 In the following, reference will be made to Figures 6 to 9 To simplify the description, references may be repeated or omitted. Figure 5 Redundant parts of the description.

[0128] First, refer to Figure 6 , the horizontal plane of the bottom surface 241BS of the first gate insulating layer 241 may be the same as or coplanar with the horizontal plane of the top surface 261a_US of the first region 261a of the first source / drain region 261. For example, the vertical level of the bottom surface 241BS of the first gate insulating layer 241 may be equal to the vertical level of the top surface 261a_US of the first region 261a. In some example embodiments, the height from the top surface of the peripheral circuit board 200 to the bottom surface 241BS of the first gate insulating layer 241 may be equal to the height of the top surface 261a_US of the first region 261a.

[0129] Reference Figure 7, the horizontal plane of the bottom surface 251BS of the second gate insulating layer 251 may be different from the horizontal plane of the top surface 261b_US of the second region 261b of the first source / drain region 261. For example, the vertical level of the bottom surface 251BS of the second gate insulating layer 251 may be higher than the vertical level of the top surface 261b_US of the second region 261b. In some example embodiments, the height from the top surface of the peripheral circuit board 200 to the bottom surface 251BS of the second gate insulating layer 251 may be greater than the height of the top surface 261b_US of the second region 261b.

[0130] In the process of removing the oxide layer formed on both sides of the second gate structure GS2, a portion of the active area ACT adjacent to the second gate structure GS2 may be removed. Therefore, a stepped portion may be formed between the second gate insulating layer 251 and the first source / drain region 261. Similarly, a stepped portion may be formed between the second gate insulating layer 251 and the third source / drain region 263. Also in this case, the vertical level of the bottom surface 251BS of the second gate insulating layer 251 may be higher than the vertical level of the top surface of the third source / drain region 263.

[0131] exist Figure 7 , a first vertical distance th1 from the bottom surface 241BS of the first gate insulating layer 241 to the top surface 261a_US of the first region 261a may be different from a second vertical distance th2 from the bottom surface 251BS of the second gate insulating layer 251 to the top surface 261b_US of the second region 261b. For example, the first vertical distance th1 may be greater than the second vertical distance th2. However, the technical spirit of the present disclosure is not limited thereto.

[0132] Reference Figure 8 When the top surface 261_US of the first source / drain region 261 extends from the first gate structure GS1 to the second gate structure GS2 , the level of the top surface 261_US of the first source / drain region 261 may not change.

[0133] In this case, the horizontal plane of the bottom surface 241BS of the first gate insulating layer 241 may be different from the horizontal plane of the top surface 261_US of the first source / drain region 261. For example, the vertical level of the bottom surface 241BS of the first gate insulating layer 241 may be higher than the vertical level of the top surface 261_US of the first source / drain region 261. In other words, the height from the top surface of the peripheral circuit board 200 to the bottom surface 241BS of the first gate insulating layer 241 may be greater than the height of the top surface 261_US of the first source / drain region 261.

[0134] A stepped portion may be formed between the bottom surface 241BS of the first gate insulating layer 241 and the top surface 261_US of the first source / drain region 261. Also, a stepped portion may be formed between the bottom surface 241BS of the first gate insulating layer 241 and the top surface of the second source / drain region 262.

[0135] Reference Fig. 9 , the semiconductor memory device according to some example embodiments may further include a second insulating layer 235 .

[0136] The second insulating layer 235 may be disposed below the first insulating layer 230. For example, the second insulating layer 235 may extend along the outline of the first gate structure GS1, the outline of the second gate structure GS2, the top surface of the first source / drain region 261, the top surface of the second source / drain region 262, and the top surface of the third source / drain region 263. The first insulating layer 230 may be disposed on the second insulating layer 235. As an example, the second insulating layer 235 may be formed of a silicon oxide layer, but the technical spirit of the present disclosure is not limited thereto.

[0137] Fig.10 yes Figure 3 In order to simplify the description, reference may be omitted. Figure 5 Redundant parts of the description.

[0138] Reference Fig.10 , a semiconductor memory device according to various example embodiments may include a first active region ACT1, a second active region ACT2, an element isolation layer 205, and first to third gate structures GS1, GS2, and GS3.

[0139] The element isolation layer 205 may be disposed on the peripheral circuit board 200. The element isolation layer 205 may define a first active region ACT1 and a second active region ACT2. For example, one side of the element isolation layer 205 may be the first active region ACT1, and the other side of the element isolation layer 205 may be the second active region ACT2.

[0140] The first gate structure GS1 and the second gate structure GS2 may be disposed on the first active region ACT1. The first gate structure GS1 and the second gate structure GS2 may be respectively connected to the reference Figure 5 The first gate structure GS1 and the second gate structure GS2 described are the same.

[0141] The third gate structure GS3 may be disposed on the second active region ACT2. The third gate structure GS3 may intersect the second active region ACT2. The third gate structure GS3 may include a third gate insulating layer 271, a third lower gate pattern 272, a third upper gate pattern 273, a third gate capping layer 274, and a third gate spacer 275.

[0142] The third gate insulating layer 271, the third lower gate pattern 272, the third upper gate pattern 273, and the third gate capping layer 274 may be sequentially stacked on the second active region ACT2. For example, the third lower gate pattern 272 may be disposed on the third gate insulating layer 271. The third upper gate pattern 273 may be disposed on the third lower gate pattern 272. The third gate capping layer 274 may be disposed on the third upper gate pattern 273. The third gate insulating layer 271 may contact at least a portion of the second active region ACT2.

[0143] The third gate spacer 275 may extend along sidewalls of the third gate insulating layer 271 , the third lower gate pattern 272 , the third upper gate pattern 273 , and the third gate capping layer 274 .

[0144] The third gate insulating layer 271 may be formed of the same material as the first gate insulating layer 241. The third lower gate pattern 272 may be formed of the same material as the first lower gate pattern 242. The third upper gate pattern 273 may be formed of the same material as the first upper gate pattern 243. The third gate capping layer 274 may be formed of the same material as the first gate capping layer 244. The third gate spacer 275 may be formed of the same material as the first gate spacer 245.

[0145] In some example embodiments, a thickness 271th of the third gate insulating layer 271 in the vertical direction may be the same as a thickness 241th of the first gate insulating layer 241 in the vertical direction. In addition, a thickness 271th of the third gate insulating layer 271 in the vertical direction may be less than a thickness 251th of the second gate insulating layer 251 in the vertical direction. In some example embodiments, the magnitude of a voltage applied to the second gate structure GS2 or an absolute value of a threshold voltage of the second gate structure GS2 may be higher than the magnitude of a voltage applied to the third gate structure GS1.

[0146] In some example embodiments, a top surface of the third gate insulating layer 271 may be coplanar with a top surface of the first gate insulating layer 241 and a top surface of the second gate insulating layer 251. In addition, a bottom surface 241BS of the first gate insulating layer 241 may be coplanar with a bottom surface 271BS of the third gate insulating layer 271. However, a horizontal plane of the bottom surface 271BS of the third gate insulating layer 271 may be different from a horizontal plane of the bottom surface 251BS of the second gate insulating layer 251. A vertical level of the bottom surface 251BS of the second gate insulating layer 251 may be lower than a vertical level of the bottom surface 271BS of the third gate insulating layer 271.

[0147] In some example embodiments, the top surface 274US of the third gate capping layer 274 may not be coplanar with the top surface 244US of the first gate capping layer 244 and the top surface 254US of the second gate capping layer 254. For example, the vertical level of the top surface 274US of the third gate capping layer 274 may be higher than the vertical level of the top surface 244US of the first gate capping layer 244 and the vertical level of the top surface 254US of the second gate capping layer 254.

[0148] In various example embodiments, the height of the top surface 274US of the third gate capping layer 274 may be greater than the height of the top surface 244US of the first gate capping layer 244 and the height of the top surface 254US of the second gate capping layer 254 relative to the top surface of the peripheral circuit board 200. In this case, the bottom surface of the first gate capping layer 244, the bottom surface of the second gate capping layer 254, and the bottom surface of the third gate capping layer 274 may be coplanar with each other. This may be because, in the process of removing the oxide layer formed on both sides of the second gate structure GS2, a portion of the first gate capping layer 244 and a portion of the second gate capping layer 254 are removed.

[0149] In some example embodiments, a thickness 244th of the first gate capping layer 244 may be smaller than a thickness 274th of the third gate capping layer 274. A thickness 254th of the second gate capping layer 254 may be smaller than a thickness 274th of the third gate capping layer 274.

[0150] In some example embodiments, a top surface 261a_US of the first region 261a of the first source / drain region 261 may be coplanar with a top surface 264US of the fourth source / drain region 264. A top surface 261b_US of the second region 261b of the first source / drain region 261 may be disposed at a lower level than a top surface 264US of the fourth source / drain region 264.

[0151] The semiconductor memory device according to some example embodiments may further include a fourth source / drain region 264. The fourth source / drain region 264 may be disposed at least one side of the third gate structure GS3.

[0152] As shown in the figure, the fourth source / drain region 264 can be arranged on both sides of the third gate structure GS3. The fourth source / drain region 264 can be a region doped with impurities. As an example, when the third gate structure GS3 is a PMOS transistor, the fourth source / drain region 264 can be doped with p-type impurities. As another example, when the third gate structure GS3 is an NMOS transistor, the fourth source / drain region 264 can be doped with n-type impurities.

[0153] Fig.11 and Fig.12 It is to illustrate that according to some other embodiments Figure 3 In the following, reference will be made to Fig.11 and Fig.12 Some other embodiments of the present disclosure are described. To simplify the description, references may be repeated or omitted. Fig.10 Redundant parts of the description.

[0154] First, refer to Fig.11 , the top surface 261a_US of the first region 261a of the first source / drain region 261 may be at a different level from the bottom surface 241BS of the first gate insulating layer 241. For example, the vertical level of the top surface 261a_US of the first region 261a may be higher than the bottom surface 241BS of the first gate insulating layer 241. In other words, relative to the top surface of the peripheral circuit board 200, the height of the bottom surface 241BS of the first gate insulating layer 241 may be greater than the height of the top surface 261a_US of the first region 261a.

[0155] The top surface 261a_US of the first region 261a of the first source / drain region 261 may be at a different level from the top surface 264US of the fourth source / drain region 264. The vertical level of the top surface 261a_US of the first region 261a of the first source / drain region 261 may be lower than the vertical level of the top surface 264US of the fourth source / drain region 264. For example, the height of the top surface 261a_US of the first region 261a may be smaller than the top surface 264US of the fourth source / drain region 264 relative to the top surface of the peripheral circuit board 200.

[0156] In the process of removing the oxide layer formed on both sides of the second gate structure GS2, the active area ACT adjacent to the first gate structure GS1 may be partially removed. Therefore, a stepped portion may appear between the first gate insulating layer 241 and the first source / drain region 261. Similarly, a stepped portion may also appear between the first gate insulating layer 241 and the second source / drain region 262. In this case, the vertical level of the bottom surface 241BS of the first gate insulating layer 241 may also be higher than the vertical level of the top surface of the second source / drain region 262.

[0157] Reference Fig.12 , a portion of the third gate insulating layer 271 may extend along the top surface 264US of the fourth source / drain region 264 .

[0158] For example, the third gate insulating layer 271 may include a first portion 271_1 and a second portion 271_2. The first portion 271_1 of the third gate insulating layer 271 may completely overlap the third lower gate pattern 272 in the vertical direction. The second portion 271_2 of the third gate insulating layer 271 may be a portion other than the first portion 271_1. A portion of the second portion 271_2 of the third gate insulating layer 271 may extend along the top surface 264US of the fourth source / drain region 264.

[0159] The thickness 271_1th of the first portion 271_1 of the third gate insulating layer 271 in the vertical direction is greater than the thickness of the second portion 271_2 of the third gate insulating layer 271 in the vertical direction. In addition, the thickness 271_1th of the first portion 271_1 of the third gate insulating layer 271 in the vertical direction is greater than the thickness 241th of the first gate insulating layer 241 in the vertical direction. The thickness 271_1th of the first portion 271_1 of the third gate insulating layer 271 in the vertical direction may be the same as the thickness 251th of the second gate insulating layer 251 in the vertical direction.

[0160] The second portion 271_2 of the third gate insulating layer 271 may extend along the top surface 264US of the fourth source / drain region 264. In some example embodiments, the second portion 271_2 of the third gate insulating layer 271 may extend along the top surface of the element isolation layer 205, but is not limited thereto. The second portion 271_2 of the third gate insulating layer 271 may contact a portion of the top surface 264US of the fourth source / drain region 264.

[0161] Fig.13 yes Figure 3 In order to simplify the description, reference may be omitted. Figure 5 and Fig.10 Redundant parts of the description.

[0162] Reference Fig.13 , a semiconductor memory device according to some example embodiments may include a first element isolation layer 205_1, a second element isolation layer 205_2, first to third active regions ACT1, ACT2, and ACT3, and first to fourth gate structures GS1, GS2, GS3, and GS4.

[0163] The first to third active regions ACT1, ACT2, and ACT3 may be disposed on the peripheral circuit board 200. The first to third active regions ACT1, ACT2, and ACT3 may be defined by the first element isolation layer 205_1 and the second element isolation layer 205_2. For example, the first element isolation layer 205_1 may define the first active region ACT1 and the second active region ACT2, and the second element isolation layer 205_2 may define the second active region ACT2 and the third active region ACT3.

[0164] The first gate structure GS1 and the second gate structure GS2 may be disposed on the first active region ACT1. Figure 5 The descriptions are the same, and thus a detailed description will be omitted.

[0165] The third gate structure GS3 may be disposed on the second active region ACT2. Fig.10 The descriptions are the same, and thus a detailed description will be omitted.

[0166] The fourth gate structure GS4 may be disposed on the third active region ACT3. The fourth gate structure GS4 may intersect the third active region ACT3. The fourth gate structure GS4 may include a fourth gate insulating layer 281, a fourth lower gate pattern 282, a fourth upper gate pattern 283, a fourth gate capping layer 284, and a fourth gate spacer 285.

[0167] A fourth gate insulating layer 281, a fourth lower gate pattern 282, a fourth upper gate pattern 283, and a fourth gate capping layer 284 may be sequentially stacked on the third active region ACT3. The fourth gate insulating layer 281 may contact at least a portion of the third active region ACT3.

[0168] The fourth gate spacer 285 may extend along sidewalls of the fourth gate insulating layer 281 , the fourth lower gate pattern 282 , the fourth upper gate pattern 283 , and the fourth gate capping layer 284 .

[0169] The fourth gate insulating layer 281 may be formed of the same material as the first gate insulating layer 241. The fourth lower gate pattern 282 may be formed of the same material as the first lower gate pattern 242. The fourth upper gate pattern 283 may be formed of the same material as the first upper gate pattern 243. The fourth gate capping layer 284 may be formed of the same material as the first gate capping layer 244. The fourth gate spacer 285 may be formed of the same material as the first gate spacer 245.

[0170] In various example embodiments, the fourth gate insulating layer 281 may include a first portion 281_1 and a second portion 281_2 .

[0171] The first portion 281_1 of the fourth gate insulating layer 281 may completely overlap the fourth lower gate pattern 282 in a vertical direction. The second portion 281_2 of the fourth gate insulating layer 281 may be a portion other than the first portion 281_1.

[0172] The thickness 281_1th of the first portion 281_1 of the fourth gate insulating layer 281 in the vertical direction is greater than the thickness of the second portion 281_2 of the fourth gate insulating layer 281 in the vertical direction. In addition, the thickness 281_1th of the first portion 281_1 of the fourth gate insulating layer 281 in the vertical direction is greater than the thickness 241th of the first gate insulating layer 241 in the vertical direction. The thickness 281_1th of the first portion 281_1 of the fourth gate insulating layer 281 in the vertical direction may be the same as the thickness 251th of the second gate insulating layer 251 in the vertical direction.

[0173] The second portion 281_2 of the fourth gate insulating layer 281 may extend along the top surface 265US of the fifth source / drain region 265 . The second portion 281_2 of the fourth gate insulating layer 281 may contact a portion of the top surface 265US of the fifth source / drain region 265 .

[0174] In some example embodiments, a top surface of the fourth gate insulating layer 281 may be coplanar with top surfaces of the first gate insulating layer 241 , the second gate insulating layer 251 , and the third gate insulating layer 271 .

[0175] The bottom surface 281BS of the fourth gate insulating layer 281 may be coplanar with the bottom surface 251BS of the second gate insulating layer 251. However, the level of the bottom surface 281BS of the fourth gate insulating layer 281 may be different from the level of the bottom surface 241BS of the first gate insulating layer 241 and the bottom surface 271BS of the third gate insulating layer 271.

[0176] In some example embodiments, the top surface 284US of the fourth gate capping layer 284 may not be coplanar with the top surface 244US of the first gate capping layer 244 and the top surface 254US of the second gate capping layer 254. For example, the vertical level of the top surface 284US of the fourth gate capping layer 284 may be higher than or located above the vertical level of the top surface 244US of the first gate capping layer 244 and the vertical level of the top surface 254US of the second gate capping layer 254. For example, the height of the top surface 284US of the fourth gate capping layer 284 may be greater than the height of the top surface 244US of the first gate capping layer 244 and the height of the top surface 254US of the second gate capping layer 254 relative to the top surface of the peripheral circuit board 200.

[0177] In this case, the bottom surfaces of the first gate capping layer 244, the second gate capping layer 254, and the fourth gate capping layer 284 may be coplanar with each other. This may be because, in the process of removing the oxide layer formed on both sides of the second gate structure GS2, a portion of the first gate capping layer 244 and a portion of the second gate capping layer 254 are removed.

[0178] In some example embodiments, the thickness 244th of the first gate capping layer 244 in the vertical direction may be less than the thickness 284th of the fourth gate capping layer 284 in the vertical direction. The thickness 254th of the second gate capping layer 254 in the vertical direction may be less than the thickness 284th of the fourth gate capping layer 284 in the vertical direction. However, the thickness 284th of the fourth gate capping layer 284 in the vertical direction may be the same as the thickness 274th of the third gate capping layer 274 in the vertical direction. The top surface 284US of the fourth gate capping layer 284 may be coplanar with the top surface 274US of the third gate capping layer 274.

[0179] In some example embodiments, a top surface 261b_US of the second region 261b of the first source / drain region 261 may be coplanar with a top surface 265US of the fifth source / drain region 265. A top surface 261a_US of the first region 261a of the first source / drain region 261 may be disposed at a lower level than a top surface 265US of the fifth source / drain region 265.

[0180] The semiconductor memory device according to various example embodiments may further include a fifth source / drain region 265. The fifth source / drain region 265 may be disposed on at least one side of the fourth gate structure GS4. As shown, the fifth source / drain region 265 may be disposed on both sides of the fourth gate structure GS4. The fifth source / drain region 265 may be a region doped with impurities, such as but not limited to the same impurities in the first source / drain region 261 and / or the second source / drain region 262. As an example, when the fourth gate structure GS4 is a PMOS transistor, the fifth source / drain region 265 may be doped with p-type impurities. As another example, when the fourth gate structure GS4 is an NMOS transistor, the fifth source / drain region 265 may be doped with n-type impurities.

[0181] Fig.14 is a cross-sectional view of a semiconductor memory device according to various other embodiments. Fig.14 Semiconductor memory devices according to some other embodiments are described.

[0182] Reference Fig.14 , in the semiconductor memory device according to some example embodiments, the front surface of the unit substrate 100 faces the front surface of the peripheral circuit board 200 .

[0183] For example, a semiconductor memory device according to some example embodiments may have a chip-to-chip (C2C) structure. The C2C structure may be formed by manufacturing an upper chip including a cell structure CELL on a first wafer (e.g., a unit substrate 100), manufacturing a lower chip including a peripheral circuit structure PERI on a second wafer (e.g., a peripheral circuit board 200) different from the first wafer, and then connecting the upper chip to the lower chip by a bonding method. In some example embodiments, before the bonding method, the chips in the first wafer may be singulated, and the chips in the second wafer may be singulated. Example embodiments are not limited thereto.

[0184] For example, the bonding method may refer to electrically connecting the bit line BL, the plurality of first metal patterns 170, and the second metal pattern 180 formed in the uppermost metal layer of the upper chip to the first bonding metal to the third bonding metal 292, 293, and 294 formed in the uppermost metal layer of the lower chip. For example, when the bit line BL, the plurality of first metal patterns 170, the second metal pattern 180, and the first bonding metal to the third bonding metal 292, 293, and 294 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only an example, and the bit line BL, the plurality of first metal patterns 170, the second metal pattern 180, and the first bonding metal to the third bonding metal 292, 293, and 294 may be formed of a variety of other metals, such as one or more of aluminum (Al), tungsten (W), and the like.

[0185] Since the bit line BL is connected to the first bonding metal 292, the plurality of first metal patterns 170 are connected to the second bonding metal 293, and the second metal pattern 180 is connected to the third bonding metal 294, the cell structure CELL may be connected to the peripheral circuit structure PERI. For example, the bit line BL, the plurality of first metal patterns 170 and the second metal pattern 180 may be electrically connected to the wiring pattern 290 via the respective first to third bonding metals 292, 293, and 294 and the through-hole contact 291. This may allow each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL and / or the source layer 102 to be electrically connected to the peripheral circuit element PT. Fig.14 It is illustrated that the wiring pattern 290 includes one layer; however, example embodiments are not limited thereto, and the number of layers in the wiring pattern 290 may be more than one layer.

[0186] Figures 15 to 20 FIG. 1 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to some example embodiments. Figures 15 to 20 Methods for manufacturing a semiconductor memory device according to some example embodiments are described. For reference, Figures 15 to 20 Can be shown to make Fig.13Figure 5. Cross-sectional method of the method.

[0187] First, refer to Fig.15 , a peripheral circuit board 200 may be provided. A first element isolation layer 205_1 and a second element isolation layer 205_2 may be formed in the peripheral circuit board 200 .

[0188] The first element isolation layer 205_1 may be formed to form the first active region ACT1 and the second active region ACT2. The second element isolation layer 205_2 may be formed to form the second active region ACT2 and the third active region ACT3.

[0189] Then, a groove may be formed on one side of the first element isolation layer 205_1 in the first active region ACT1. Then, a groove may be formed on one side of the second element isolation layer 205_2 in the third active region ACT3. The groove may then be used to form a gate insulating layer having a greater thickness. The groove may be formed by a wet etching process and / or a dry etching process; example embodiments are not limited thereto.

[0190] Reference Fig.16 , a pre-gate insulating layer 310, a pre-lower gate pattern 320, a pre-upper gate pattern 330, and a pre-gate capping layer 340 may be sequentially stacked. The pre-lower gate pattern 320, the pre-upper gate pattern 330, and the pre-gate capping layer 340 may be deposited, for example, using a chemical vapor deposition (CVD) process and / or an atomic layer deposition (ALD) process; example embodiments are not limited thereto.

[0191] Reference Fig.17 , the pre-gate insulating layer 310 is patterned so that the first gate insulating layer 241, the pre-second gate insulating layer 251p, the third gate insulating layer 271 and the fourth gate insulating layer 281 can be formed. The pre-lower gate pattern 320 is patterned so that the first lower gate pattern 242, the second lower gate pattern 252, the third lower gate pattern 272 and the fourth lower gate pattern 282 can be formed. The pre-upper gate pattern 330 is patterned so that the first upper gate pattern 243, the second upper gate pattern 253, the third upper gate pattern 273 and the fourth upper gate pattern 283 can be formed. In addition, the pre-gate capping layer 340 is patterned so that the pre-first gate capping layer 244p, the pre-second gate capping layer 254p, the third gate capping layer 274 and the fourth gate capping layer 284 can be formed.

[0192] The thickness of the first gate insulating layer 241 may be the same as that of the third gate insulating layer 271. The pre-first gate capping layer 244p, the pre-second gate capping layer 254p, the third gate capping layer 274, and the fourth gate capping layer 284 may have the same thickness.

[0193] Reference Fig.18A photoresist layer PR may be formed on the second active region ACT2. The photoresist layer PR may be formed of at least one of a photoresist layer, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), or a silicon nitride layer.

[0194] The photoresist layer PR may completely cover the third gate capping layer 274 and the fourth gate capping layer 284 .

[0195] Reference Fig.19 , the pre-second gate insulating layer 251p may be etched, for example, using a dry etching process. The pre-second gate insulating layer 251p may be etched to form the second gate insulating layer 251. In the process of etching the pre-second gate insulating layer 251p, a portion of the pre-first gate capping layer 244p and a portion of the pre-second gate capping layer 254p may be removed. A portion of the pre-first gate capping layer 244p and a portion of the pre-second gate capping layer 254p may be removed to form the first gate capping layer 244 and the second gate capping layer 254.

[0196] Therefore, the thickness 244th of the first gate capping layer 244 and the thickness 254th of the second gate capping layer 254 in the vertical direction may be smaller than the thickness 274th of the third gate capping layer 274 and the thickness 284th of the fourth gate capping layer 284 in the vertical direction, respectively.

[0197] Reference Fig. 20 , the photoresist layer PR may be removed. Next, the first to fifth source / drain regions 261, 262, 263, 264, and 265 may be formed. The first to third source / drain regions 261, 262, and 263 may be formed by doping impurities (e.g., by implanting impurities) into the first active region ACT1. The fourth source / drain region 264 may be formed by doping impurities into the second active region ACT2. The fifth source / drain region 265 may be formed by doping impurities into the third active region ACT3. In some example embodiments, after doping the first to fifth source / drain regions 261, 262, 263, 264, and 265, the impurities may be activated, for example, using an annealing process such as, but not limited to, a rapid thermal annealing (RTA) process.

[0198] The first source / drain region 261 may be formed between the first gate insulating layer 241 and the second gate insulating layer 251. Since the thickness of the first gate insulating layer 241 is different from the thickness of the second gate insulating layer 251, the top surface of the first source / drain region 261 may have a stepped portion. However, a depth 261a_D of a first region 261a adjacent to the first gate insulating layer 241 may be the same as a depth 261b_D of a second region 261b adjacent to the second gate insulating layer 251. Therefore, a semiconductor memory device with improved reliability may be manufactured.

[0199] In the following, reference will be made to Figures 1 to 5 and Figure 21 to Figure 23 An electronic system including a semiconductor memory device according to example embodiments is described.

[0200] Fig.21 is an example block diagram illustrating an electronic system according to various example embodiments. Fig. 22 is an example perspective view illustrating an electronic system according to various example embodiments. Fig.23 is along Fig. 22 An example cross-sectional view taken along line II'.

[0201] Reference Fig.21 , the electronic system 1000 according to some example embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100, or an electronic device including a storage device. For example, the electronic system 1000 may be or may include or be included in at least one of the following: a solid state drive (SSD) device including one or more semiconductor memory devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0202] The semiconductor memory device 1100 may be, include, or be included in, for example, a NAND flash memory device, for example, Figures 1 to 5 The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0203] The first structure 1100F may include a decoder circuit 1110 (eg, Figure 1 , a row decoder 33 in the page buffer 1120 (eg, Figure 1 , and logic circuits 1130 (eg, Figure 1 The peripheral circuit structure of the control logic 37).

[0204] The second structure 1100S may include the above reference Figure 2 The common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR are described. The cell strings CSTR may be connected to the decoder circuit 1110 via word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell strings CSTR may be connected to the page buffer 1120 via the bit lines BL.

[0205] In some example embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S.

[0206] In some example embodiments, the bit line BL may be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S. The page buffer 1120 may be a reference Figures 1 to 5 Describe the peripheral circuit components PT.

[0207] The semiconductor memory device 1100 may be electrically connected to a logic circuit 1130 (eg, Figure 1 The input / output pads 1101 of the control logic 37 in the first structure 1100F) communicate with the controller 1200. The input / output pads 1101 may be electrically connected to the logic circuit 1130 through the input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0208] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100. In this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0209] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor memory device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 for communicating with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be written into the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0210] Reference Figure 21 to Figure 23 , an electronic system according to some example embodiments may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed on the main substrate 2001.

[0211] The main substrate 2001 may include a connector 2006 having a plurality of pins connected to an external host. In the connector 2006, the number and arrangement of the pins may vary according to the communication interface between the electronic system 2000 and the external host. In various example embodiments, the electronic system 2000 may communicate with the external host through any of the interfaces such as a universal serial bus (USB), a peripheral component interconnect (PCIe), a serial advanced technology attachment (SATA), and an M-PHY for universal flash storage (UFS). In some example embodiments, the electronic system 2000 may be operated by power provided from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power provided from the external host to the main controller 2002 and the semiconductor package 2003.

[0212] The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0213] The DRAM 2004 may be a buffer memory for reducing a speed difference between an external host and the semiconductor package 2003 as a data storage space. The DRAM 2004 included in the electronic system 2000 may also operate as a high-speed cache memory and may also provide a space for temporarily storing data when controlling the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the main controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0214] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 respectively disposed on the bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 above the package substrate 2100.

[0215] The package substrate 2100 may be a printed circuit board including an upper package pad 2130. Each of the semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may be connected to a Fig.21 Corresponding to the input / output pad 1101.

[0216] In various example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the upper package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a wire bonding method and may be electrically connected to the upper package pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the wire bonding type connection structure 2400.

[0217] In various example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in one package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 may be connected to the semiconductor chip 2200 through wiring formed on the interposer substrate.

[0218] In some example embodiments, the package substrate 2100 may be or may include or be included in a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, an upper package pad 2130 disposed on a top surface of the package substrate body portion 2120, a lower pad 2125 disposed on a bottom surface of the package substrate body portion 2120 or exposed through the bottom surface of the package substrate body portion 2120, and an internal wiring 2135 electrically connecting the upper pad 2130 to the lower pad 2125 in the package substrate body portion 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main substrate 2001 of the electronic system 2000 through a conductive connector 2800, such as Fig.21 shown.

[0219] Reference Fig. 22 and Fig.23 In an electronic system according to some example embodiments, each of the semiconductor chips 2200 may include the above-referenced Figures 1 to 5 For example, each of the semiconductor chips 2200 may include a peripheral circuit structure PERI and a cell structure CELL stacked on the peripheral circuit structure PERI. For example, the peripheral circuit structure PERI may include the above-mentioned Figures 3 to 5 The peripheral circuit board 200 and the peripheral circuit element PT described above. In addition, for example, the cell structure CELL may include a cell substrate 100, a molding structure MS, a channel structure CH, a word line cutting structure WLC and a bit line BL, as described above with reference to Figures 3 to 5 described.

[0220] Any of the elements and / or functional blocks disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include electronic components such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include electronic components such as a logic gate including at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0221] In summarizing the detailed description, it will be appreciated by those of ordinary skill in the art that many changes and modifications may be made to the preferred embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed example embodiments of the present disclosure are intended only in a general and descriptive sense, and not for purposes of limitation. Additionally, the example embodiments are not necessarily mutually exclusive of one another. For example, some example embodiments may include one or more features described with reference to one or more of the accompanying drawings, and may also include one or more other features described with reference to one or more of the other accompanying drawings.

Claims

1. A semiconductor memory device, comprising: Unit structure; as well as a peripheral circuit structure electrically connected to the cell structure, Wherein, the unit structure comprises: a plurality of gate electrodes extending along a first direction and spaced apart in a second direction, a channel structure penetrating the plurality of gate electrodes in the second direction, and A bit line is connected to the channel structure and extends along a third direction, and the peripheral circuit structure includes: Active area, a first gate structure, comprising a first gate insulating layer intersecting with and contacting the active region, a second gate structure including a second gate insulating layer spaced apart from the first gate structure and contacting the active region, and A source / drain region is located in the active region and between the first gate structure and the second gate structure, wherein: The thickness of the first gate insulating layer is smaller than the thickness of the second gate insulating layer, The source / drain region includes a first region adjacent to the first gate structure and a second region adjacent to the second gate structure, and The depth of the first region is equal to the depth of the second region.

2. The semiconductor memory device according to claim 1, wherein: The first gate structure includes a first gate capping layer on the first gate insulating layer, The second gate structure includes a second gate capping layer on the second gate insulating layer, and A top surface of the second gate capping layer is coplanar with a top surface of the first gate capping layer.

3. The semiconductor memory device according to claim 2, wherein: The thickness of the first gate capping layer is equal to the thickness of the second gate capping layer.

4. The semiconductor memory device according to claim 1, wherein: The second gate insulating layer is not on the second region of the source / drain region.

5. The semiconductor memory device according to claim 1, wherein A bottom surface of the first gate insulating layer is located above a top surface of the first region of the source / drain region.

6. The semiconductor memory device according to claim 1, wherein A bottom surface of the second gate insulating layer is coplanar with a top surface of the second region of the source / drain region or is located above a top surface of the second region of the source / drain region.

7. The semiconductor memory device according to claim 1, wherein: The source / drain region is connected to the bit line of the cell structure.

8. The semiconductor memory device according to claim 1, wherein: A top surface of the first region is located above a top surface of the second region.

9. A semiconductor memory device comprising: A first active region and a second active region are defined by an element isolation layer; A first gate structure comprising a first gate insulating layer intersecting with and contacting the first active region; a second gate structure, comprising a second gate insulating layer extending parallel to the first gate structure and contacting the first active region; a first source / drain region located in the first active region and between the first gate structure and the second gate structure; a third gate structure, comprising a third gate insulating layer intersecting with and contacting the second active region; as well as a second source / drain region, located in the second active region and on at least one side of the third gate structure, wherein: The thickness of the first gate insulating layer is smaller than the thickness of the second gate insulating layer, The first source / drain region includes a first region adjacent to the first gate structure and a second region adjacent to the second gate structure, The depth of the first region is equal to the depth of the second region, and Wherein, a top surface of the first region is located below a top surface of the second source / drain region.

10. The semiconductor memory device according to claim 9, wherein: The thickness of the second gate insulating layer is greater than the thickness of the third gate insulating layer.

11. The semiconductor memory device according to claim 9, wherein: Each of the first source / drain region and the second source / drain region is connected to the same or different bit lines of the cell structure.

12. The semiconductor memory device according to claim 9, wherein: The second gate insulating layer is not on the second region of the first source / drain region.

13. The semiconductor memory device according to claim 9, wherein: The first gate structure includes a first gate capping layer on the first gate insulating layer, The second gate structure includes a second gate capping layer on the second gate insulating layer, and A top surface of the second gate capping layer is coplanar with a top surface of the first gate capping layer.

14. The semiconductor memory device according to claim 13, wherein: The third gate structure includes a third gate capping layer on the third gate insulating layer, and A top surface of the third gate capping layer is below a top surface of the first gate capping layer.

15. The semiconductor memory device according to claim 14, wherein: The thickness of the third gate capping layer is smaller than the thickness of the first gate capping layer.

16. The semiconductor memory device according to claim 9, wherein: The top surface of the first region is coplanar with or located above the top surface of the second region.

17. The semiconductor memory device according to claim 9, wherein: A bottom surface of the first gate insulating layer is located above the top surface of the first region of the first source / drain region.

18. A semiconductor memory device comprising: Unit structure; as well as a peripheral circuit structure electrically connected to the cell structure, Wherein, the unit structure comprises: a plurality of gate electrodes extending along a first direction and spaced apart in a second direction, a channel structure penetrating the plurality of gate electrodes in the second direction, and A bit line is connected to the channel structure and extends along a third direction, and the peripheral circuit structure includes: A first active region and a second active region are defined by an element isolation layer; A first gate structure comprising a first gate insulating layer intersecting with and contacting the first active region; a second gate structure, comprising a second gate insulating layer extending parallel to the first gate structure and contacting the first active region; a first source / drain region located in the first active region and between the first gate structure and the second gate structure; a third gate structure comprising a third gate insulating layer intersecting with and contacting the second active region; and a second source / drain region, located in the second active region and on at least one side of the third gate structure, wherein: The thickness of the first gate insulating layer is smaller than the thickness of the second gate insulating layer, The first source / drain region includes a first region adjacent to the first gate structure and a second region adjacent to the second gate structure, A top surface of the first region is above a top surface of the second region but below a top surface of the second source / drain region, and The depth of the first region is equal to the depth of the second region.

19. The semiconductor memory device according to claim 18, wherein: The first gate structure includes a first gate capping layer on the first gate insulating layer, The second gate structure includes a second gate capping layer on the second gate insulating layer, The third gate structure includes a third gate capping layer on the third gate insulating layer, A top surface of the second gate capping layer is coplanar with a top surface of the first gate capping layer, and A top surface of the third gate capping layer is below a top surface of the first gate capping layer.

20. The semiconductor memory device according to claim 19, wherein The thickness of the third gate capping layer is smaller than the thickness of the first gate capping layer.

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