LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. According to the preparation method, the groove is formed in the substrate, and the gate structure is arranged in the groove of the substrate, so that the field plate structure can be formed in the groove and upwards extends out of the groove from the groove, the longitudinal size of the field plate structure can be increased, the breakdown voltage of the device can be improved, and the device reliability is improved. The voltage withstanding performance of the device is improved under the conditions that the on-resistance of the device is not influenced and the overall area of the device is not increased. Moreover, after the gate structure is formed, the groove is filled with the insulating dielectric layer, so that the plane where the top of the gate structure is located is flat, the preparation difficulty of the field plate structure is reduced, the field plate structure can be allowed to further extend out of the groove from the interior of the groove, and the effect that the longitudinal size and the transverse size of the field plate structure are increased at the same time is achieved. And the voltage withstanding performance of the device is further optimized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] Laterally diffused metal oxide semiconductor (LDMOS) devices are commonly used semiconductor high voltage devices, which are widely used in power amplifiers in radio frequency fields such as wireless base stations and broadcasting stations.

[0003] Figure 1 is a schematic diagram of the structure of an existing LDMOS device, such as Figure 1 As shown, the LDMOS device generally includes: a substrate 10 having a drift region, a source region 20S and a drain region 20D formed in the substrate 10, and a gate structure 20G formed between the source region 20S and the drain region 20D. In order to ensure that the device has sufficient withstand voltage performance, a field plate design is generally adopted to utilize the coupling effect of the field plate structure to increase the device's breakdown voltage BV (Breakdown Voltage), reduce the on-resistance Rdson, and suppress the hot carrier injection effect HCI (Hot Carrier Injection).

[0004] For example Figure 1 As shown, a field plate structure 40 in an LDMOS device adopts a contact hole field plate (CFP), that is, the field plate structure 40 penetrates the interlayer dielectric layer (not shown in the figure) above the substrate 10, so that the contact hole field plate can achieve the electric field modulation effect in the drift region. However, the size of the field plate structure 40 is limited by the thickness of the interlayer dielectric layer, so that the effect of the field plate structure 40 on the drift region is also limited, which easily causes the on-resistance Rdson of the device to be too high, the breakdown voltage BV is insufficient, and other problems. Among them, in order to increase the breakdown voltage BV of the device, it can be achieved by reducing the ion concentration of the drift region or increasing the length of the drift region, but this will cause the on-resistance Rdson of the device to increase, and also increase the area of ​​the device. Therefore, it is difficult to improve the withstand voltage performance of the device while ensuring the on-resistance of the device in the prior art. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing an LDMOS device, so that the prepared LDMOS device can improve the withstand voltage performance of the device without affecting the on-resistance of the device.

[0006] The present invention provides a method for preparing an LDMOS device, comprising: providing a substrate, wherein a groove is formed in the substrate; forming a gate structure on the bottom surface of the groove, wherein the top of the gate structure is lower than the top of the groove; forming an insulating dielectric layer in the groove, wherein the insulating dielectric layer fills the peripheral area of ​​the gate structure and makes the top surface of the insulating dielectric layer flush with the top surface of the gate structure; forming a field dielectric layer on the substrate, wherein the field dielectric layer partially covers the gate structure and extends to cover the top surface of the insulating dielectric layer; and forming a field plate structure on the field dielectric layer, wherein the top of the field plate structure is higher than the top of the groove and extends out of the groove.

[0007] Optionally, the method for preparing the insulating dielectric layer includes: forming an insulating dielectric material layer on the substrate, the insulating dielectric material layer filling the groove and covering the top surface of the substrate; performing a grinding process on the insulating dielectric material layer until the top surface of the substrate is exposed, so that the remaining insulating dielectric material layer fills the groove; and performing an etching process on the insulating dielectric material layer in the groove until the top surface of the gate structure is exposed.

[0008] Optionally, the field dielectric layer further extends laterally to the outside of the groove to extend and cover the top surface of the substrate; the field plate structure further extends laterally to the outside of the groove to be partially formed on the top surface of the substrate.

[0009] Optionally, the method for preparing the field dielectric layer includes: forming a field dielectric material layer, the field dielectric material layer covering the top surface of the gate structure, the top surface of the insulating dielectric layer, the exposed groove sidewalls and the top surface of the substrate; and etching the field dielectric material layer to form the field dielectric layer.

[0010] Optionally, the method for preparing the gate structure includes: sequentially forming a gate dielectric material layer and a gate conductive material layer on the substrate, the gate dielectric material layer and the gate conductive material layer conformally covering the bottom surface and side walls of the groove and covering the top surface of the substrate; and, performing an etching process on the gate conductive material layer and the gate dielectric material layer, and using the remaining dielectric material and conductive material in the groove to form a stacked gate dielectric layer and a gate conductive layer.

[0011] Optionally, the field plate structure includes a contact hole field plate.

[0012] Optionally, before forming the contact hole field plate, it also includes: forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer filling the groove and covering the top surface of the substrate, and making the top surface of the interlayer dielectric layer higher than the top of the groove; forming a field plate contact hole in the interlayer dielectric layer, the field plate contact hole penetrating the interlayer dielectric layer to the field dielectric layer, and the field plate contact hole is used to accommodate the contact hole field plate.

[0013] Optionally, after forming the gate structure, it also includes: forming a source region and a drain region, the source region is at least partially formed below the groove and extends downward from the bottom surface of the groove, and the drain region is located on the side of the field plate structure away from the source region and extends downward from the top surface of the substrate.

[0014] Optionally, the depth of the groove is less than or equal to 1 μm.

[0015] Optionally, after forming the groove, an annular gate structure is formed in the groove, and an insulating dielectric layer is filled on the inner and outer sides of the gate structure to make the plane where the top of the gate structure is located flat, and then an annular field dielectric layer and an annular field plate structure are formed, and the field dielectric layer and the field plate structure are at least partially formed in the groove; wherein the gate structure surrounds the center of the groove, and the field plate structure is arranged in an annular shape at a position farther away from the center of the groove relative to the gate structure.

[0016] The present invention also provides an LDMOS device, comprising: a substrate, a groove formed in the substrate; a gate structure, located on the bottom surface of the groove, and the top of the gate structure is lower than the top of the groove; an insulating dielectric layer, located in the groove and filling the peripheral area of ​​the gate structure, and the top surface of the insulating dielectric layer is flush with the top surface of the gate structure; a field dielectric layer, partially covering the gate structure and extending to cover the top surface of the insulating dielectric layer; and a field plate structure, the field plate structure is formed on the field dielectric layer, and the top of the field plate structure is higher than the top of the groove and extends out of the groove.

[0017] Optionally, the field dielectric layer further extends laterally to the outside of the groove to extend and cover the top surface of the substrate; the field plate structure further extends laterally to the outside of the groove to be partially formed on the top surface of the substrate.

[0018] Optionally, the LDMOS device further includes: a source region and a drain region, wherein the source region is at least partially formed below the groove and extends downward from the bottom surface of the groove, and the drain region is located on a side of the field plate structure away from the source region and extends downward from the top surface of the substrate.

[0019] Optionally, the gate structure is arranged in a ring shape around the center of the groove, and the field plate structure is arranged in a ring shape at a position farther away from the center of the groove relative to the gate structure.

[0020] In the preparation method of the LDMOS device provided by the present invention, a groove is formed in the substrate to set the gate structure in the groove of the substrate, so that the field plate structure can be at least partially formed in the groove and extend upward from the groove, which is beneficial to increase the longitudinal dimension of the field plate structure, thereby improving the breakdown voltage of the device, and achieving the improvement of the voltage resistance performance of the device without affecting the on-resistance of the device and increasing the overall area of ​​the device.

[0021] In addition, in the preparation method provided by the present invention, after the gate structure is formed, an insulating dielectric layer is also filled in the groove to make the plane where the top of the gate structure is located flat, which facilitates the subsequent formation of the field dielectric layer and the field plate structure, reduces the difficulty of preparing the field plate structure, and allows the field plate structure to be further extended from the groove to the outside of the groove, thereby achieving the effect of simultaneously increasing the longitudinal and lateral dimensions of the field plate structure, and further optimizing the voltage resistance performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of an existing LDMOS device.

[0023] Figure 2 It is a schematic flow chart of a method for manufacturing an LDMOS device in one embodiment of the present invention.

[0024] Figure 3-Figure 10 The figure is a schematic structural diagram of an LDMOS device provided in an embodiment of the present invention during its preparation process.

[0025] Fig.11 FIG. 4 is a top view of an LDMOS device according to an embodiment of the present invention.

[0026] Fig.12 for Fig.11 The cross-sectional view of the LDMOS device shown is along the aa' direction.

[0027] The reference numerals are as follows:

[0028] 10 / 100-substrate;

[0029] 100a-groove;

[0030] 110 - base;

[0031] 120P-well region;

[0032] 120N-drift zone;

[0033] 20G / 200G-gate structure;

[0034] 20S / 200S-source region;

[0035] 20D / 200D-drain area;

[0036] 300-field dielectric layer;

[0037] 310-first dielectric layer;

[0038] 320- second dielectric layer;

[0039] 40 / 400-field plate structure;

[0040] 500S-source metal;

[0041] 500D-drain metal;

[0042] 610-insulating dielectric layer;

[0043] 620-interlayer dielectric layer. DETAILED DESCRIPTION

[0044] The core idea of ​​the present invention is to provide a novel method for preparing a LDMOS device, which is used to form a LDMOS device with low on-resistance and high withstand voltage performance. Figure 2 As shown, the method for preparing the LDMOS device provided by the present invention includes the following steps.

[0045] Step S100, providing a substrate, wherein a groove is formed in the substrate.

[0046] Step S200 , forming a gate structure on the bottom surface of the groove, wherein the top of the gate structure is lower than the top of the groove.

[0047] Step S300 , forming an insulating dielectric layer in the groove, wherein the insulating dielectric layer fills the peripheral region of the gate structure and makes the top surface of the insulating dielectric layer flush with the top surface of the gate structure.

[0048] Step S400 , forming a field dielectric layer on the substrate, wherein the field dielectric layer partially covers the gate structure and extends to cover the top surface of the insulating dielectric layer.

[0049] Step S500 , forming a field plate structure on the field dielectric layer, and making the top of the field plate structure higher than the top of the groove and extending out of the groove.

[0050] In the preparation method provided by the present invention, the gate structure is formed in the groove of the substrate, so that the field plate structure can be extended longitudinally into the groove, which is conducive to increasing the longitudinal dimension of the field plate structure, improving the voltage resistance of the device, and achieving the improvement of the breakdown voltage without affecting the on-resistance of the device and increasing the overall area of ​​the device. In addition, precisely because the field plate structure can be extended longitudinally into the groove, the thickness of the interlayer dielectric layer on the top surface of the substrate can be correspondingly reduced while keeping the longitudinal dimension of the field plate structure unchanged, thereby reducing the size of the device.

[0051] The following combination Figure 3-Figure 10 The LDMOS device and the method for manufacturing the same are further described in detail with specific embodiments. Figure 3-Figure 10 It is a schematic diagram of the structure of the LDMOS device provided in one embodiment of the present invention during its preparation process. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element will now be below the element.

[0052] In step S100, refer to Figure 3 As shown, a substrate 100 is provided. The substrate 100 may include a second doping type base 110N and a first doping type epitaxial layer formed on the base 110. The base 110 may be a silicon base, and the LDMOS device will be formed on the epitaxial layer.

[0053] In one example, before etching the substrate 100 to form the groove 100a, it also includes: forming a well region 120P of the second doping type in the substrate, that is, forming the well region 120P in the epitaxial layer. Specifically, the well region 120P of the second doping type can be formed in the device region of the substrate 100 through an ion implantation process, and the portion of the device region where the well region 120P is not formed can constitute a drift region 120N of the first doping type, and the drift region 120N and the well region 120P are laterally adjacent. The first doping type and the second doping type are opposite doping types, for example, if the first doping type is N-type, the second doping type is P-type; or, if the first doping type is P-type, the second doping type is N-type. In this embodiment, the first doping type is N-type and the second doping type is P-type for explanation.

[0054] Continue to refer Figure 3 As shown, the substrate 100 is etched to form a groove 100a, and a gate structure will be formed in the groove 100a in a subsequent step, and the field plate structure can be longitudinally extended into the groove 100a. Specifically, the bottom surface of the groove 100a exposes the well region 120P and a portion of the drift region 120N near the well region 120P.

[0055] In addition, the depth and shape of the groove 100a can be adjusted according to actual needs, for example, the groove 100a can be a circular groove, an elliptical groove or a rectangular groove, etc. Also, in this embodiment, the depth of the groove 100a can be controlled within a smaller depth range, for example, the depth of the groove 100a can be made less than or equal to 1 μm, so as to avoid the groove 100a being too deep and causing the well region 120P and the drift region 120N in the corresponding area to be consumed in large quantities, thereby ensuring the performance stability of the prepared LDMOS device.

[0056] In step S200, refer to Figure 4 and Figure 5 As shown, a gate structure 200G is formed on the bottom surface of the groove 100a, and the top of the gate structure 200G is lower than the top of the groove 100a. Specifically, the gate structure 200G is arranged at the junction of the well region 120P and the drift region 120N to simultaneously cover a portion of the well region 120P and a portion of the drift region 120N.

[0057] Furthermore, not only is the height of the gate structure 200G smaller than the depth of the groove 100a, so that the top of the gate structure 200G does not exceed the top of the groove 100a, but the width of the gate structure 200G is also smaller than the width of the groove 100a, so that the gate structure 200G does not completely cover the bottom surface of the groove 100a.

[0058] Continue to refer Figure 4 As shown, the gate structure 200G may include a gate dielectric layer 210 and a gate conductive layer 220 stacked sequentially from bottom to top, and its preparation method may include: sequentially forming a gate dielectric material layer and a gate conductive material layer on the substrate 100, the gate dielectric material layer and the gate conductive material layer conformally cover the bottom surface and sidewall of the groove 100a, and cover the top surface of the substrate 100; then, performing an etching process to remove the dielectric material and conductive material on the top surface of the substrate, part of the dielectric material and part of the conductive material in the groove 100, and using the remaining dielectric material and conductive material in the groove 100a to form a stacked gate dielectric layer 210 and a gate conductive layer 220. The gate dielectric layer 210 may be formed, for example, by an oxidation process, and its material may include silicon oxide; and the gate conductive layer 220 may be formed, for example, by a deposition process, and its material may include polysilicon.

[0059] In further plans, focus on Figure 5 As shown, the gate structure 200G may further include a sidewall structure 230 covering the sidewalls of the gate dielectric layer 210 and the gate conductive layer 220. In a specific example, the sidewall structure 230 may be a composite film layer structure, which may include an oxide layer and a nitride layer sequentially covering the sidewalls, wherein the material of the oxide layer includes, for example, silicon oxide, and the material of the nitride layer includes, for example, silicon nitride. More specifically, the sidewall structure 230 may also be an ONO composite structure including an oxide layer, a nitride layer, and an oxide layer.

[0060] In this embodiment, after forming the gate structure 200G, a source region 200S of the first doping type and a drain region 200D of the first doping type may be formed in the substrate 100 .

[0061] Specific reference Figure 6 As shown, the source region 200S and the drain region 200D are respectively located on both sides of the gate structure 200G, wherein the source region 200S is specifically formed in the well region 120P, and the drain region 200D is formed in the drift region 120N. When a turn-on voltage is applied to the gate structure 200G of the LDMOS device, the well region 120P covered by the gate structure 200G is inverted to form a conductive channel, so that the source region 200S can be connected to the drift region 120N through the conductive channel, and further electrically connected to the drain region 200D, so that current flows between the source region 200S, the conductive channel, the drift region 120N and the drain region 200D.

[0062] like Figure 6 As shown, the source region 200S is at least partially formed below the groove 100a, so that the end of the source region 200S can reach below the gate structure 200G, that is, the source region 200S has a portion extending downward from the bottom surface of the groove 100a; and the drain region 200D is formed outside the groove 100a and extends inward from the top surface of the substrate. In this embodiment, the source region 200S is completely formed within the region below the groove 100a and extends downward from the bottom surface of the groove 100a. It should be recognized that in other embodiments, the source region 200S may also be partially located within the region below the groove 100a, and the portion extends downward from the bottom surface of the groove 100a; and another portion of the source region 200S extends laterally to the outside of the groove 100a in a direction away from the gate structure 200G, and extends to the top surface of the substrate outside the groove.

[0063] In step S300, refer to Figure 7 and Figure 8As shown, an insulating dielectric layer 610 is formed in the groove 100a, and the insulating dielectric layer 610 fills the peripheral area of ​​the gate structure 200G, and the top surface of the insulating dielectric layer 610 is flush with the top surface of the gate structure 200G. The material of the insulating dielectric layer 610 includes, for example, silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

[0064] That is, the insulating dielectric layer 610 is used to fill the peripheral space of the gate structure 200G in the groove 100a, so that the plane where the top of the gate structure 200G is located is overall flat in the groove, which is conducive to reducing the difficulty of preparing the subsequent field dielectric layer and field plate structure and improving the quality of the formed field plate structure.

[0065] In a specific example, the preparation method of the insulating dielectric layer 610 includes, for example, first, forming an insulating dielectric material layer on the substrate 100, the insulating dielectric material layer filling the groove 100a and covering the top surface of the substrate 100; then, performing a grinding process on the insulating dielectric material layer until the top surface of the substrate 100 is exposed, at which time the dielectric material outside the groove 100a can be removed, and the dielectric material in the groove 100a is retained, that is, Figure 7 As shown, the remaining insulating dielectric material layer 610a is filled in the groove 100a; Figure 8 As shown, an etching process is performed on the insulating dielectric material layer 610a in the groove 100a. At this time, the insulating dielectric material layer 610a in the groove 100a is uniformly etched from top to bottom until the top surface of the gate structure 200G is exposed. At this point, the top surface of the remaining dielectric material layer can be flush with the top surface of the gate structure 200G, forming an insulating dielectric layer 610.

[0066] In step S400, refer to Fig. 9 As shown, a field dielectric layer 300 is formed on the substrate 100 , and the field dielectric layer 300 partially covers the gate structure 200G and extends to cover the top surface of the insulating dielectric layer 610 .

[0067] Specifically, the field dielectric layer 300 covers the top surface of the gate structure 200G near the drain region 200D, and extends in the direction of the drain region 200D to cover the top surface of the insulating dielectric layer 610. In this embodiment, the field dielectric layer 300 further extends from the groove 100a in a direction toward the drain region 200D to cover the top surface of the substrate 100, that is, the field dielectric layer 300 covers part of the top surface of the gate structure 200G, the top surface of the insulating dielectric layer 610, the exposed groove sidewalls and the top surface of the substrate 100. At this time, the field plate structure formed subsequently can be extended laterally from the groove 100a to the outside of the groove 100a, which is conducive to increasing the lateral size of the field plate structure.

[0068] In one example, the field dielectric layer 300 may include a first dielectric layer 310 and a second dielectric layer 320 which are stacked, the first dielectric layer 310 may include an oxide layer (e.g., a silicon oxide layer), and the second dielectric layer 320 may include a nitride layer (e.g., a silicon nitride layer). The method for preparing the field dielectric layer 300 in this example specifically includes: first, sequentially depositing a first dielectric material layer and a second dielectric material layer, the first dielectric material layer and the second dielectric material layer both covering the top surface of the gate structure 200G in the groove 100a, the top surface of the insulating dielectric layer 610 and the exposed groove sidewalls, and also covering the top surface of the substrate outside the groove 100a; then, performing an etching process on the first dielectric material layer and the second dielectric material layer to form a stacked first dielectric layer 310 and a second dielectric layer 320.

[0069] In step S500, refer to Fig.10 As shown, a field plate structure 400 is formed on the field dielectric layer 300 , and the top of the field plate structure 400 is higher than the top of the groove 100 a and extends out of the groove 100 a .

[0070] As described above, since the top surface of the gate structure 200G is lower than the top position of the groove 100a, a space for the field plate structure 400 to extend longitudinally is reserved above the gate structure 200G, that is, the field plate structure 400 extends longitudinally from the groove 100a to the top of the groove 100a, thereby increasing the longitudinal dimension of the field plate structure 400. Alternatively, it can be considered that, without changing the overall longitudinal dimension of the field plate structure 400, since the field plate structure 400 can be partially disposed in the groove 100a, the height of the field plate structure 400 protruding from the top surface of the substrate can be reduced, which is beneficial to reducing the overall size of the device.

[0071] In a specific example, the field plate structure 300 is partially formed in the groove 100a, and extends laterally from the groove 100a to the outside of the groove 100a and covers the top surface of the substrate 100, thereby increasing the lateral size of the field plate structure, improving the field plate capacitance, and further optimizing the voltage resistance performance of the device.

[0072] It should be appreciated that in conventional LDMOS devices, the field plate structure only covers the top surface of the drift region (see, for example, Figure 1 As shown in the figure, however, the field plate structure 300 in this embodiment not only covers the top surface of the drift region 120N (corresponding to the top surface of the substrate), but also covers the side walls of the drift region 120N (corresponding to the side walls of the groove 100a), thereby increasing the coverage area of ​​the drift region 120N, so that the electric field modulation range of the drift region 120N is extended from the top surface to the side walls, and the average surface electric field is better, thereby effectively improving the breakdown voltage of the device.

[0073] In this embodiment, the field plate structure 400 including the contact hole field plate is taken as an example to explain the preparation process. Figure 8 As shown, after forming the field dielectric layer 300, an interlayer dielectric layer 620 is formed on the substrate 100, the interlayer dielectric layer 620 fills the groove 100a and covers the top surface of the substrate 100, and the interlayer dielectric layer 620 has a planarized top surface higher than the top of the groove; then, a field plate contact hole is formed in the interlayer dielectric layer 620, the field plate contact hole is at least partially located within the area of ​​the groove 100a and exposes the field dielectric layer 300; thereafter, a conductive material can be filled in the field plate contact hole to form a field plate structure 400.

[0074] In a specific example, a source contact hole and a drain contact hole are formed in the interlayer dielectric layer 620, wherein the source contact hole is located within the region of the groove 100a and extends downward to the bottom surface of the groove 100a to expose a portion of the source region 200S, and the drain contact hole penetrates the interlayer dielectric layer 620 to the top surface of the substrate to expose a portion of the drain region 200D; thereafter, a conductive material can be filled in each contact hole to respectively form a contact hole field plate (i.e., the field plate structure 400), a source metal 500S and a drain metal 500D.

[0075] As described above, the source region 200S in this embodiment is completely formed in the area below the groove 100a, so the source metal 500S correspondingly extends to the bottom surface of the groove 100a to electrically connect to the source region 200S. However, in other examples, a portion of the source region 200S can be formed in the area below the groove 100a, and another portion can be laterally extended to the outside of the groove 100a and to the top surface of the substrate outside the groove. In this case, the source metal 500S can be formed on the top surface of the substrate 100 to be electrically connected to the portion of the source region 200S that extends to the top surface of the substrate.

[0076] The present disclosure also provides an LDMOS device, which can be prepared by the method described above. Fig.10 As shown, the LDMOS device includes: a substrate 100 , a gate structure 200G formed on the substrate 100 , a field dielectric layer 300 and a field plate structure 400 .

[0077] Furthermore, a drift region 120N of a first doping type and a well region 120P of a second doping type are formed in the substrate 100, and the drift region 120N and the well region 120P have a laterally adjacent boundary. Also, a groove 100a formed in the substrate 100 is sunken from the top surface of the substrate 100 to a predetermined depth at least at a position where the well region 120P and the drift region 120N are adjacent to each other, wherein the depth of the groove 100a can be adjusted accordingly according to actual needs, for example, the depth of the groove 100a can be no greater than 1 μm.

[0078] Continue to refer Fig.10 As shown, the gate structure 200G is formed on the bottom surface of the groove 100a, and the gate structure 200G partially covers the well region 120P and crosses the boundary so that another part of the gate structure 200G extends to the drift region 120N. In a specific example, the gate structure 200G includes a gate dielectric layer 210 and a gate conductive layer 220 that are stacked, and a spacer structure 230 can also be formed on the sidewall of the gate conductive layer 220.

[0079] The LDMOS device further includes a source region 200S of the first doping type and a drain region 200D of the first doping type, the source region 200S and the drain region 200D are respectively located on both sides of the gate structure 200G, wherein the source region 200S is specifically formed in the well region 120P, and the drain region 200D is formed in the drift region 120N. Specifically, the source region 200S can at least partially extend to the bottom of the groove 100a, so that the end of the source region 200S can reach the bottom of the gate structure 200G. In this embodiment, the source region 200S is completely formed in the area below the groove 100a and extends downward from the bottom surface of the groove 100a.

[0080] Further, the field dielectric layer 300 is at least formed in the groove 100a, partially covering the top surface of the gate structure 200G and further extending to cover the top surface of the insulating dielectric layer 610. The field dielectric layer 300 specifically covers the surface of the gate structure 200G close to the drain region 200D and extends toward the drain region 200D to cover the top surface of the insulating dielectric layer 610. Also, the field plate structure 400 is formed on the field dielectric layer 300, and the field plate structure 400 is at least partially located in the groove 100a and extends upward from the groove 100a in the height direction. Therefore, the longitudinal dimension of the field plate structure 400 can be effectively increased, thereby improving the withstand voltage performance of the device. In this embodiment, the field dielectric layer 300 further covers the side wall of the groove 100a to the top surface of the substrate 100. At this time, the field plate structure 400 can also be further extended laterally from the inside of the groove 100a to the top surface of the substrate outside the groove, so as to increase the lateral size of the field plate structure 400, improve the field plate capacitance, and further optimize the voltage resistance performance of the device.

[0081] In a specific example, the field plate structure 400 used may be, for example, a contact hole field plate (CFP), which specifically includes a contact hole penetrating the interlayer dielectric layer 620 and an electrode material formed in the contact hole. In this example, the contact hole field plate (CFP) may be formed simultaneously with the source metal 500S and the drain metal 500D, and may be made of the same metal material.

[0082] The above example only illustrates the cross-sectional structure of the prepared LDMOS device, but in a specific application, the LDMOS device can be arranged in a ring structure. Fig.11 and Fig.12 As shown, the gate structure 200G in the LDMOS device may be disposed in a ring shape around the center of the groove 100 a , and the field plate structure 400 is disposed in a ring shape at a position farther from the center of the groove relative to the gate structure 200G.

[0083] In a specific example, the source region 200S, the gate structure 200G, the field plate structure 400 and the drain region 200D are specifically arranged in sequence from the inner ring to the outer ring, that is, the source region 200S is arranged in the inner ring, the gate structure 200G surrounds the periphery of the source region 200S, the field plate structure 400 surrounds the periphery of the gate structure 200G, and the inner ring portion of the field plate structure 300 close to the gate structure 200G is also formed on the gate structure 200G. In this embodiment, the field plate structure 400 is partially located within the region of the groove 100a and further extends out of the groove 100a, that is, the outer ring portion of the field plate structure 400 is located outside the groove 100a and is formed on the top surface of the substrate. And, the drain region 200D is located outside the groove 100a and surrounds the periphery of the field plate structure 400.

[0084] Furthermore, the groove 100a in the substrate 100 may be a circular groove, an elliptical groove, a rectangular groove, etc., for example Fig.11 In the example, a circular groove is used as an example for explanation. In a specific example, the source region 200S can be formed at the center of the groove 100a, and the shape of the source region 200S matches the shape of the groove 100a, that is, the source region 200S can correspond to a circle, an ellipse or a rectangle. Alternatively, in another example, the source region 200S is an annular structure surrounding the center of the groove, and its shape can be, for example, a circular ring, an elliptical ring or an annular rectangle, and a well lead-out region of the second doping type can be formed at the center of the groove 100a.

[0085] In the preparation of Fig.11 and Fig.12 When the LDMOS device is shown, a ring-shaped gate structure 200G can be formed in the groove 100a; then, an insulating dielectric layer 610 is filled on the inner and outer sides of the gate structure 200G to make the plane where the top of the gate structure 200G is located flat; then, a ring-shaped field dielectric layer 300 and a ring-shaped field plate structure 400 are formed, and the field dielectric layer 300 and the field plate structure 400 are at least partially formed in the groove 100a. For example, in this example, the inner ring part of the field dielectric layer 300 and the field plate structure 400 is formed in the groove 100a, and the outer ring part extends out of the groove 100a and is formed on the top surface of the substrate 100.

[0086] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0087] It must be noted that as used herein and in the appended claims, the singular forms "a," "an," and "an" include plural references unless the context clearly indicates otherwise. For example, reference to "a step" or "a device" means reference to one or more steps or devices and may include secondary steps as well as secondary devices. All conjunctions used should be interpreted in the broadest sense. Also, the word "or" should be interpreted as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise.

Claims

1. A method for preparing an LDMOS device, characterized in that: include: Providing a substrate, wherein a groove is formed in the substrate; forming a gate structure on the bottom surface of the groove, wherein a top of the gate structure is lower than a top of the groove; forming an insulating dielectric layer in the groove, wherein the insulating dielectric layer fills the peripheral area of ​​the gate structure and makes the top surface of the insulating dielectric layer flush with the top surface of the gate structure; forming a field dielectric layer on the substrate, wherein the field dielectric layer partially covers the gate structure and extends to cover the top surface of the insulating dielectric layer; as well as, A field plate structure is formed on the field dielectric layer, and the top of the field plate structure is higher than the top of the groove and extends out of the groove.

2. The method for preparing an LDMOS device according to claim 1, wherein: The method for preparing the insulating dielectric layer comprises: forming an insulating dielectric material layer on the substrate, wherein the insulating dielectric material layer fills the groove and covers the top surface of the substrate; performing a grinding process on the insulating dielectric material layer until the top surface of the substrate is exposed so that the remaining insulating dielectric material layer fills the groove; and, An etching process is performed on the insulating dielectric material layer in the groove until the top surface of the gate structure is exposed.

3. The method for preparing an LDMOS device according to claim 1, wherein: The field dielectric layer also extends laterally to the outside of the groove to extend and cover the top surface of the substrate; the field plate structure also extends laterally to the outside of the groove to be partially formed on the top surface of the substrate.

4. The method for preparing an LDMOS device according to claim 1, wherein: The method for preparing the field dielectric layer comprises: forming a field dielectric material layer, the field dielectric material layer covering the top surface of the gate structure, the top surface of the insulating dielectric layer, the exposed sidewalls of the groove and the top surface of the substrate; and, The field dielectric material layer is etched to form the field dielectric layer.

5. The method for preparing an LDMOS device according to claim 1, wherein: The method for preparing the gate structure comprises: forming a gate dielectric material layer and a gate conductive material layer on the substrate in sequence, wherein the gate dielectric material layer and the gate conductive material layer conformally cover the bottom surface and sidewalls of the groove and cover the top surface of the substrate; and An etching process is performed on the gate conductive material layer and the gate dielectric material layer, and the dielectric material and conductive material remaining in the groove are used to form a stacked gate dielectric layer and a gate conductive layer.

6. The method for preparing an LDMOS device according to claim 1, wherein: The field plate structure includes a contact hole field plate.

7. The method for preparing an LDMOS device according to claim 6, wherein: Before forming the contact hole field plate, the method further includes: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer fills the groove and covers the top surface of the substrate, and the top surface of the interlayer dielectric layer is higher than the top of the groove; A field plate contact hole is formed in the interlayer dielectric layer, the field plate contact hole penetrates the interlayer dielectric layer to the field dielectric layer, and the field plate contact hole is used to accommodate the contact hole field plate.

8. The method for preparing an LDMOS device according to claim 1, wherein: After forming the gate structure, the method further includes: A source region and a drain region are formed, wherein the source region is at least partially formed below the groove and extends downward from the bottom surface of the groove, and the drain region is located on a side of the field plate structure away from the source region and extends downward from the top surface of the substrate.

9. The method for preparing an LDMOS device according to claim 1, wherein: The depth of the groove is less than or equal to 1 μm.

10. The method for preparing an LDMOS device according to any one of claims 1 to 9, characterized in that: After forming the groove, forming an annular gate structure in the groove, and filling the inner and outer sides of the gate structure with insulating dielectric layers to make the plane where the top of the gate structure is located flat, and then forming an annular field dielectric layer and an annular field plate structure, wherein the field dielectric layer and the field plate structure are at least partially formed in the groove; The gate structure surrounds the center of the groove, and the field plate structure is arranged in a ring shape at a position farther away from the center of the groove relative to the gate structure.

11. An LDMOS device, characterized in that: include: A substrate having a groove formed therein; a gate structure located on the bottom surface of the groove, and a top of the gate structure is lower than a top of the groove; an insulating dielectric layer, located in the groove and filling a peripheral area of ​​the gate structure, wherein a top surface of the insulating dielectric layer is flush with a top surface of the gate structure; a field dielectric layer, partially covering the gate structure and extending to cover a top surface of the insulating dielectric layer; as well as, A field plate structure is formed on the field dielectric layer, and a top of the field plate structure is higher than a top of the groove and extends out of the groove.

12. The LDMOS device according to claim 11, characterized in that: The field dielectric layer also extends laterally to the outside of the groove to extend and cover the top surface of the substrate; the field plate structure also extends laterally to the outside of the groove to be partially formed on the top surface of the substrate.

13. The LDMOS device according to claim 11, wherein: Also includes: A source region and a drain region, wherein the source region is at least partially formed below the groove and extends downward from the bottom surface of the groove, and the drain region is located on a side of the field plate structure away from the source region and extends downward from the top surface of the substrate.

14. The LDMOS device according to any one of claims 11 to 13, characterized in that: The gate structure is disposed in a ring shape around the center of the groove, and the field plate structure is disposed in a ring shape at a position farther away from the center of the groove relative to the gate structure.

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