LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. In the preparation method, a first light absorption layer is arranged below an interlayer dielectric layer, so that a large number of photons generated by etching the interlayer dielectric layer can be absorbed by the exposed first light absorption layer, and then the exposed first light absorption layer absorbing the large number of photons is removed. The formation of the field plate structure within the first contact hole having a large number of photons is avoided. Therefore, the problem that charges at the bottom of the field plate structure are easy to migrate after absorbing a large number of photons can be improved, and the breakdown voltage of the device is improved; meanwhile, the risk that energy overflows due to the fact that the film layer absorbing a large number of photons is still reserved in the device is avoided, and the performance stability of the device is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] LDMOS devices are a type of MOS devices that are formed using a double-diffused process and have a channel consisting of a double concentration difference. Compared with traditional CMOS devices, LDMOS devices have a longer low-doped drift region to bear the source-drain voltage, which is also the reason why LDMOS devices have a high withstand voltage. Due to the advantages of LDMOS devices such as high voltage resistance and good compatibility with CMOS devices, they are widely used in the BCD process to prepare power management chips.

[0003] Therefore, high withstand voltage is a major purpose of LDMOS device design. In order to improve the withstand voltage of LDMOS devices, field plate design is usually used to utilize the coupling effect of the field plate structure to increase the device's breakdown voltage BV (Breakdown Voltage), reduce the on-resistance Rdson, and suppress the hot carrier injection effect HCI (Hot Carrier Injection). However, the withstand voltage performance of existing LDMOS devices still needs to be improved. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing an LDMOS device, so as to improve the electric field modulation effect of the field plate structure of the prepared LDMOS device and enhance the breakdown voltage of the device.

[0005] To this end, the present invention provides a method for preparing an LDMOS device, comprising: providing a substrate, forming a gate structure, a source region and a drain region in a device region of the substrate, wherein the source region and the drain region are respectively located on both sides of the gate structure; forming a field dielectric layer, wherein the field dielectric layer covers a portion of the gate structure and extends toward the drain region to cover the top surface of the substrate; forming a first light absorption layer, wherein the first light absorption layer at least covers the top of the field dielectric layer; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the device region; etching the interlayer dielectric layer, and further etching the first light absorption layer to form a first contact hole that at least penetrates the interlayer dielectric layer and the first light absorption layer; and forming a field plate structure in the first contact hole.

[0006] Optionally, the method for forming the first contact hole includes: performing a first etching step to etch the interlayer dielectric layer and stopping the etching at the first light absorbing layer; and performing a second etching process to etch the exposed first light absorbing layer to form the first contact hole.

[0007] Optionally, a blocking layer is formed between the field dielectric layer and the first light absorbing layer, the blocking layer at least covers the field dielectric layer, and the bottom of the first contact hole stops at the blocking layer, so that the blocking layer is still spaced between the bottom of the field plate structure and the substrate.

[0008] Optionally, an etch stop layer is further formed below the first light absorbing layer, and the etch stop layer is between the field dielectric layer and the first light absorbing layer. When etching the first light absorbing layer, the etching is stopped at the etch stop layer to form a first contact hole that sequentially penetrates the interlayer dielectric layer, the first light absorbing layer, and the etch stop layer.

[0009] Optionally, a second light absorbing layer is further formed between the field dielectric layer and the etch stop layer. The method for forming the first contact hole comprises: performing a first etching step to etch the interlayer dielectric layer and stop etching at the first light absorbing layer; performing a second etching step to etch the first light absorbing layer and stop etching at the etch stop layer; and performing a third etching step to etch the etch stop layer and stop etching at the second light absorbing layer to form a first contact hole whose bottom stops at the second light absorbing layer.

[0010] Optionally, after forming the field dielectric layer and before forming the first light absorbing layer, the method further includes: forming a second light absorbing layer and / or a blocking layer at least on the field dielectric layer; and forming an etching stop layer in the device region. The method for forming the first contact hole includes: performing a first etching step to etch the interlayer dielectric layer and stop etching at the first light absorbing layer; performing a second etching step to etch the first light absorbing layer and the etching stop layer to form the first contact hole, and at least one of the second light absorbing layer and the blocking layer is still retained at the bottom of the first contact hole.

[0011] Optionally, the thickness of the blocking layer is smaller than the thickness of the first light absorbing layer. Also, the material of the blocking layer includes silicon oxynitride, for example.

[0012] Optionally, the thickness of the second light absorbing layer is smaller than the thickness of the first light absorbing layer. Also, the material of the first light absorbing layer includes silicon, for example.

[0013] The present invention also provides an LDMOS device, comprising: a substrate having a device region for setting up the LDMOS device; a gate structure formed on the substrate in the device region; a source region and a drain region formed in the substrate in the device region and respectively located on both sides of the gate structure; a field dielectric layer covering a portion of the gate structure and extending toward the drain region to cover the top surface of the substrate; a first light absorption layer at least covering the top of the field dielectric layer; an interlayer dielectric layer covering the device region; and a field plate structure formed above the field dielectric layer and at least penetrating the interlayer dielectric layer and the first light absorption layer.

[0014] Optionally, at least one of the second light absorbing layer and the blocking layer is spaced between the field plate structure and the substrate.

[0015] In the preparation method of the LDMOS device provided by the present invention, a first light absorption layer is arranged below the interlayer dielectric layer, so that a large number of photons generated when etching the interlayer dielectric layer can be absorbed by the exposed first light absorption layer, and then the first light absorption layer that absorbs a large number of photons and is exposed is removed, thereby avoiding the formation of a field plate structure in the first contact hole with a large number of photons. In this way, the problem that the charges at the bottom of the field plate structure are prone to migration after absorbing a large number of photons can be improved, thereby improving the breakdown voltage of the device; at the same time, it also avoids the risk of energy overflow caused by the film layer that absorbs a large number of photons being retained in the device, thereby ensuring the performance stability of the device.

[0016] Furthermore, a blocking layer may be formed between the field dielectric layer and the first light absorbing layer, and the blocking layer is retained at the bottom of the first contact hole, so that the blocking layer may be spaced between the field plate structure and the substrate to block the charge from migrating downward, thereby optimizing the voltage resistance of the device to a greater extent under the joint action of the first light absorbing layer and the blocking layer. Alternatively, a second light absorbing layer may be formed between the field dielectric layer and the first light absorbing layer, and the second light absorbing layer may be retained at the bottom of the first contact hole to absorb a small amount of photons that may be generated in the etching step of the previous layer (for example, a small amount of photons that may be generated in the etching step for the first light absorbing layer), thereby reducing the risk of charge migration at the bottom of the field plate structure.

[0017] Furthermore, an etch stop layer may be formed below the first light absorbing layer. In this case, the etch stop layer is provided between the field dielectric layer and the first light absorbing layer, so as to utilize the etch stop layer to improve the etching accuracy of the contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The included drawings are used to provide a further understanding of the embodiments of the present invention, which constitute a part of the specification, are used to illustrate the implementation of the present invention, and together with the text description, explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention.

[0019] Figure 1 A schematic diagram of the structure of an LDMOS device.

[0020] Figure 2 It is a schematic diagram of the process of the method for preparing the LDMOS device in the first embodiment of the present invention.

[0021] Figure 3-Figure 10 FIG. 1 is a schematic diagram of the structure of the LDMOS device in the first embodiment of the present invention during its preparation process.

[0022] Figure 11-13 It is a schematic diagram of the structure of the LDMOS device in the second embodiment of the present invention during its preparation process.

[0023] Figure 14-15 It is a schematic diagram of the structure of the LDMOS device in the third embodiment of the present invention during its preparation process.

[0024] The reference numerals are as follows:

[0025] 10 / 100-substrate;

[0026] 10N / 100N-drift zone;

[0027] 10P / 100P-well area;

[0028] 20G / 200G-gate structure;

[0029] 20S / 200S-source region;

[0030] 20D / 200D-drain area;

[0031] 30 / 300-field plate structure;

[0032] 310-first contact hole;

[0033] 400-field dielectric layer;

[0034] 510-first light absorbing layer;

[0035] 520- second light absorbing layer;

[0036] 600-etching stop layer;

[0037] 700-barrier layer;

[0038] 800S-source metal;

[0039] 800D-drain metal;

[0040] 800G-gate metal;

[0041] 810S-second contact hole;

[0042] 810D-third contact hole;

[0043] 810G-fourth contact hole;

[0044] 90 / 900-interlayer dielectric layer. DETAILED DESCRIPTION

[0045] As described in the background art, although the existing LDMOS device is provided with a field plate structure, it is still necessary to further optimize the withstand voltage performance of the device. Figure 1 Schematic diagram of the structure of an LDMOS device shown, the LDMOS device generally includes: a substrate 10 formed with a drift region 10N, a source region 20S and a drain region 20D formed in the substrate 10, and a gate structure 20G formed between the source region 20S and the drain region 20D. In addition, the LDMOS device also includes a field plate structure 30 formed on the substrate 10, the field plate structure 30 partially covers the gate structure 20G and extends to cover the top surface of the substrate 10.

[0046] When the device is forward-conducting, current flows between the source region 20S and the drain region 20D through the conductive channel under the gate structure 20G. At this time, charges of the first conductive type are gathered in the drift region 10N under the field plate structure 30, and charges of the second conductive type are generated at the bottom of the field plate structure 30 under the action of the electric field between the drain region 20D and the gate structure 20G. Figure 1 As shown, taking an N-type LDMOS device as an example, when the device is working, positive charges will be accumulated in the drift region 10N below the field plate structure 30 , and negative charges will be generated at the bottom of the field plate structure 30 .

[0047] However, when the device withstands reverse voltage, the second conductivity type charges at the bottom of the field plate structure 30 easily migrate to the drift region 10N thereunder, thereby adversely affecting the depletion region in the drift region 10N, resulting in a reduction in the breakdown voltage of the LDMOS device.

[0048] Specifically, an interlayer dielectric layer 90 with a large thickness is formed on the top surface of the substrate 10, and the field plate structure 30 is specifically formed in a contact hole of the interlayer dielectric layer 90, that is, the method for preparing the field plate structure 30 generally includes: etching the interlayer dielectric layer 90 to form a contact hole, and then filling the contact hole with an electrode material to form the field plate structure 30. However, a large number of photons are generally generated in the process of etching the interlayer dielectric layer 90, and at this time, the second conductive type of charges at the bottom of the field plate structure 30 will absorb the photon energy and easily pass through the field dielectric layer below the field plate structure 30, thereby entering the drift region 10N below it. For example, for an N-type LDMOS device, the negative charges at the bottom of the field plate structure 30 will absorb photons and have sufficient energy to migrate to the drift region 10N, thereby suppressing the aggregation of positive charges in the drift region 10N, affecting the depletion width in the drift region 10N, and thereby reducing the breakdown voltage of the LDMOS device.

[0049] To this end, the present invention provides a method for preparing an LDMOS device, wherein the LDMOS device prepared thereby has a field plate structure and can improve the electric field modulation effect of the field plate structure, so as to facilitate improving the breakdown voltage of the device. Specifically, the preparation method includes: providing a substrate, forming a gate structure, a source region and a drain region in the device region of the substrate, wherein the source region and the drain region are respectively located on both sides of the gate structure; forming a field dielectric layer, wherein the field dielectric layer partially covers the gate structure and extends in the direction of the drain region to cover the top surface of the substrate; forming a first light absorption layer, wherein the first light absorption layer at least covers the top of the field dielectric layer; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the device region; etching the interlayer dielectric layer, and further etching the first light absorption layer to form a first contact hole that at least penetrates the interlayer dielectric layer and the first light absorption layer; and forming a field plate structure in the first contact hole.

[0050] That is, in the preparation method of the LDMOS device provided by the present invention, a first light absorption layer is arranged at the bottom of the interlayer dielectric layer, so that a large number of photons generated when etching the interlayer dielectric layer can be absorbed by the exposed first light absorption layer, and then the first light absorption layer that absorbs a large number of photons is removed, thereby avoiding the formation of a field plate structure in the first contact hole with a large number of photons. In this way, on the one hand, the problem that the charges at the bottom of the field plate structure are prone to migration after absorbing a large number of photons can be improved, thereby improving the breakdown voltage of the device; on the other hand, it also avoids the risk of energy overflow caused by the film layer that absorbs a large number of photons being retained in the device, thereby ensuring the performance stability of the device.

[0051] In the first example, a blocking layer may be formed between the field dielectric layer and the first light absorbing layer, and the blocking layer is retained at the bottom of the first contact hole, so that the blocking layer may be spaced between the field plate structure and the substrate to block the downward migration of charges. In this example, the blocking layer may be further used to indicate the end point of etching, that is, when etching the film layer above the blocking layer, the etching is stopped at the blocking layer. For example, the first light absorbing layer may be etched until the etching stops at the blocking layer; or, an etching stop layer may be further provided between the blocking layer and the first light absorbing layer, and at this time, the first light absorbing layer and the etching stop layer may be etched in sequence until the etching stops at the blocking layer.

[0052] In the example where a blocking layer is provided, a second light absorbing layer may be provided below the blocking layer, and when the first light absorbing layer above the blocking layer is etched, the second light absorbing layer below the blocking layer will not be exposed but may be retained. In this way, when the field plate structure is finally formed, the blocking layer and the second light absorbing layer may be spaced between the bottom of the field plate structure and the substrate, thereby avoiding the problem of charge migration to a greater extent.

[0053] In the second example, an etch stop layer is further formed below the first light absorbing layer. In this case, the etch stop layer is provided between the field dielectric layer and the first light absorbing layer, and the etch stop layer covers the device region, so as to utilize the etch stop layer to improve the etching accuracy for the contact hole. Specifically, the etching may be stopped at the etch stop layer when etching the first light absorbing layer, and then the etch stop layer may be further etched. In this example, a second light absorbing layer and / or a blocking layer may be further provided between the etch stop layer and the field dielectric layer (for example, only a second light absorbing layer may be provided; or only a blocking layer may be provided; or a stacked structure of a second light absorbing layer and a blocking layer may be provided). In this case, when the etch stop layer is further etched, the etching stops on the second light absorbing layer (or on the blocking layer), so that at least one of the second light absorbing layer and the blocking layer is still retained at the bottom of the formed first contact hole.

[0054] In the third example, a second light absorption layer is further formed between the field dielectric layer and the first light absorption layer. At this time, an etch stop layer may be further provided between the first light absorption layer and the second light absorption layer, so that when etching the first light absorption layer, the etching may stop at the etch stop layer, and then the etch stop layer is etched to the second light absorption layer, so that the second light absorption layer can be retained at the bottom of the first contact hole to absorb a small amount of photons that may be generated in the etching step of the previous layer (for example, a small amount of photons that may be generated in the etching step for the first light absorption layer), thereby reducing the risk of charge migration at the bottom of the field plate structure.

[0055] The LDMOS device and the method for preparing the same proposed by the present invention are further described in detail below in conjunction with specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element will now be below the element.

[0056] <Example 1>

[0057] In this embodiment, an example is taken in which a blocking layer and an etching stop layer are sequentially arranged between the field dielectric layer and the first light absorbing layer for description.

[0058] Figure 2 FIG. 1 is a flow chart of a method for preparing an LDMOS device in Embodiment 1 of the present invention, as shown in FIG. Figure 2 As shown, the etching process for the first contact hole in this embodiment specifically includes: executing a first etching step to etch the interlayer dielectric layer, and the etching stops at the first light absorbing layer; executing a second etching step to etch the first light absorbing layer and the etching stop layer, and the etching stops at the blocking layer.

[0059] Combine the following Figure 3-Figure 10 , each step in the preparation method provided in this embodiment is described in detail. Figure 3-Figure 10 FIG. 1 is a schematic diagram of the structure of the LDMOS device in the first embodiment of the present invention during its preparation process.

[0060] First, execute step S100. Figure 3 As shown, a substrate 100 is provided, and a gate structure 200G, a source region 200S and a drain region 200D are formed in a device region of the substrate 100 . The source region 200S and the drain region 200D are respectively located on both sides of the gate structure 200G.

[0061] In a specific example, the substrate 100 may include a substrate of a second doping type and an epitaxial layer of a first conductivity type formed on the substrate. Also, before forming the gate structure 200G, the source region 200S and the drain region 200D, a well region 100P of a second conductivity type and a drift region 100N of a first conductivity type are formed in the substrate 100. In this embodiment, the well region 100P is formed in the epitaxial layer, and the portion of the device region where the well region 100P is not formed may constitute the drift region 100N, and the drift region 100N and the well region 100P have a laterally adjacent interface.

[0062] The first doping type and the second doping type are opposite doping types, for example, if the first doping type is N-type, the second doping type is P-type; or, if the first doping type is P-type, the second doping type is N-type. In this embodiment, the first doping type is N-type and the second doping type is P-type for explanation.

[0063] Furthermore, the gate structure 200G is located between the source region 200S and the drain region 200D, and the gate structure 200G partially covers the well region 100P and the drift region 100N at the junction of the well region 100P and the drift region 100N. The portion of the well region 100P covered by the gate structure 200G constitutes the channel region of the device, which is used to form a conductive channel in an inverted manner when the device is turned on. In addition, the source region 200S is formed in the well region 100P and is located on one side of the gate structure 200G, and the drain region 200D is formed in the drift region 100N and is located on the other side of the gate structure 200G. In addition,

[0064] Exemplarily, the gate structure 200G specifically includes a gate dielectric layer and a gate conductive layer formed on the gate dielectric layer. Further, the gate structure 200G also includes a sidewall structure covering the sidewall of the gate conductive layer.

[0065] Then, step S200 is performed. For details, refer to Figure 4 As shown, a field dielectric layer 400 is formed. The field dielectric layer 400 partially covers the gate structure 200G and extends toward the drain region 200D to cover the top surface of the substrate between the gate structure 200G and the drain region 200D.

[0066] In one example, the field dielectric layer 400 may include a silicide blocking layer (SAB), which may be used to cover the area of ​​the substrate where metal silicide is not desired to be formed, and expose the area where metal silicide is desired to be formed, so that metal silicide can be formed in a self-aligned manner at the target position. Specifically, the silicide blocking layer (SAB) may cover a portion of the gate structure and the substrate top surface between the gate structure and the drain region 200D, so as to expose the top surface of the source region 200S, a portion of the top surface of the gate structure 200G, and the top surface of the drain region 200D, and then a metal layer is formed on the top surface of the substrate 100, and the metal in the metal layer reacts with the exposed area to form a metal silicide layer (not shown in the figure), that is, a metal silicide layer is formed on the top surface of the source region 200S, a portion of the top surface of the gate structure 200G, and the top surface of the drain region 200D, so as to reduce the contact resistance of the conductive plug formed subsequently in the corresponding area through the metal silicide layer.

[0067] In this example, after the metal silicide layer is formed, a silicide blocking layer (SAB) is still retained to form the field dielectric layer 400. The material of the silicide blocking layer (SAB) includes, for example, one of strontium oxide (SRO), silicon oxide or silicon nitride or a combination thereof. That is, the field dielectric layer 400 may include, for example, a layer of a strontium oxide layer, a silicon oxide layer and a silicon nitride layer or a stacked structure formed by a combination thereof.

[0068] Then, step S300 is performed. For details, refer to Figure 5 As shown, a barrier layer 700 is formed, and the barrier layer 700 at least covers the field dielectric layer 400 .

[0069] That is, the blocking layer 700 is formed at least in the field plate region of the field plate structure, so that the blocking layer 700 can be interposed between the subsequently formed field plate structure and the substrate 100, and is used to block the charges at the bottom of the field plate structure from migrating downward. The blocking layer 700 can be formed of any material that can block charge migration, for example, the material of the blocking layer 700 can include silicon oxynitride (SION).

[0070] Then, step S400 is performed. For details, refer to Figure 6 As shown, an etch stop layer 600 is formed, and the etch stop layer 600 covers the device area. Specifically, the etch stop layer 600 at least covers the source region 200S, the drain region 200D, and the region between the source region 200S and the drain region 200D. The material of the etch stop layer 600 is different from the material of the light blocking layer 700, for example, the material of the etch stop layer 600 may include silicon nitride.

[0071] Then execute step S500, and continue to refer to Figure 6 As shown, a first light absorbing layer 510 is formed, and the first light absorbing layer 510 at least covers the field dielectric layer 410. The material of the first light absorbing layer 510 includes silicon (Si), and further can be a doped silicon material layer.

[0072] In a specific example, the first light absorbing layer 510 may cover the entire device region. In this case, the first light absorbing layer 510 may absorb photons not only in the field plate region, but also in the source region, the drain region, and the gate region.

[0073] Then, step S600 is performed. For details, refer to Figure 7 As shown, an interlayer dielectric layer 900 is formed, and the interlayer dielectric layer 900 covers the device region. The material of the interlayer dielectric layer 900 includes, for example, borosilicate glass, phosphosilicate glass, borophosphosilicate glass or silicon oxide.

[0074] It should be noted that the interlayer dielectric layer 900 is used to cover the device structure below it, so that the device structure below it can have good electrical isolation from other metal wiring layers. Therefore, the interlayer dielectric layer 900 formed in this step is usually thicker, and its thickness can be greater than or equal to 1000 Å. Even reach Due to the large thickness of the interlayer dielectric layer 900 , a large number of photons will be generated in the subsequent etching process of the interlayer dielectric layer 900 , and details may refer to step S700 .

[0075] In step S700, refer to Figure 8 As shown, a first etching step is performed to etch the interlayer dielectric layer 900, and the etching stops at the first light absorbing layer 510. As described above, a large number of photons will be generated during the etching process of the interlayer dielectric layer 900, and the generated photons can be absorbed by the exposed first light absorbing layer 510.

[0076] In this embodiment, the first etching step is performed to form an initial contact hole in the field plate region of the interlayer dielectric layer 900, and the bottom of the initial contact hole exposes the first light absorbing layer 510. Furthermore, the first etching step can also be performed to form initial contact holes in the source region, the drain region, and the gate region of the interlayer dielectric layer 900 at the same time.

[0077] Then, step S800 is executed. For details, refer to Fig. 9 As shown, a second etching step is performed to etch the first light absorbing layer 510 and the etching stop layer 600, and the etching stops at the barrier layer 700 in the field plate region. In this way, the exposed first light absorbing layer 510 that absorbs photons can be removed to avoid the risk of energy overflow due to the retention of the first light absorbing layer 510 in the device.

[0078] Specifically, the second etching step is used to further form a first contact hole 310 that sequentially penetrates the interlayer dielectric layer 900, the first light absorbing layer 510, and the etching stop layer 600. The first contact hole 310 is used to accommodate the field plate structure. In this embodiment, the second etching step can also form a second contact hole 810S for accommodating a source metal in the source terminal region, a third contact hole 810D for accommodating a drain metal in the drain terminal region, and a fourth contact hole 810G for accommodating a gate metal in the gate region.

[0079] Then, step S900 is executed. For details, refer to Fig.10As shown, a field plate structure 300 is formed in the first contact hole. In this example, the bottom of the field plate structure 300 contacts the barrier layer 700, so that the barrier layer 700 is still spaced between the field plate structure 300 and the substrate 100. In this step, metal materials are also filled in the second contact hole 810S, the third contact hole 810D, and the fourth contact hole 810G at the same time to form a source metal 800S electrically connected to the source region 200S, a drain metal 800D electrically connected to the drain region 200D, and a gate metal 800G electrically connected to the gate structure 200G.

[0080] It should be noted that the first light absorbing layer 510 in this embodiment is used to be removed after absorbing photons, so the thickness of the first light absorbing layer 510 will not affect the electric field modulation performance of the field plate structure 300. On this basis, it is allowed to set a first light absorbing layer 510 with a relatively large thickness, so as to fully absorb the photons generated by the film layer above it during the etching process. And it is precisely because the first light absorbing layer 510 is provided and the first light absorbing layer 510 can be set to a relatively large thickness that most of the photons generated during the etching process of the contact hole can be absorbed and removed. At this time, the barrier layer 700 below the field plate structure 300 can be set to a relatively small thickness to ensure the electric field modulation effect of the field plate structure 300 on the substrate 100. Therefore, the thickness of the first light absorbing layer 510 can be much greater than the thickness of the barrier layer 700.

[0081] In addition, in this embodiment, the etching process of the first contact hole includes a first etching step and a second etching step, and the first light absorbing layer 510 and the etching stop layer 600 are sequentially etched in the second etching step. However, in other examples, when the second etching step is performed, the etching may stop at the etching stop layer 600 when etching the first light absorbing layer 510, and then the etching stop layer 600 is etched. It should also be recognized that the photons generated in the first etching step are much larger than the photons generated in the second etching step, and the first light absorbing layer that absorbs the photons in the first etching step can be removed by the second etching step, thereby preventing the photons generated in the first etching step from affecting the charges at the bottom of the field plate structure.

[0082] <Example 2>

[0083] In this embodiment, an example is taken in which a second light absorbing layer and an etching stop layer are sequentially disposed between the field dielectric layer and the first light absorbing layer for description.

[0084] Combine the following Figure 11-13 , the preparation method provided in this embodiment is described. Fig.11As shown, a second light absorbing layer 520 and an etching stop layer 600 are sequentially disposed between the field dielectric layer 400 and the first light absorbing layer 510. The first light absorbing layer 510 and the second light absorbing layer 520 may be formed of the same material, for example, both include silicon.

[0085] Continue to refer Fig.11 As shown, after forming the interlayer dielectric layer 900, a first etching step is performed to etch the interlayer dielectric layer 900, and the etching stops at the first light absorbing layer 510. The photons generated during the etching process of the interlayer dielectric layer 900 can be absorbed by the exposed first light absorbing layer 510.

[0086] Next reference Fig.12 As shown, a second etching step is performed to etch the first light absorbing layer 510 and the etching stops at the etching stop layer 600 , so as to remove the exposed portion of the first light absorbing layer 510 that absorbs photons. At the same time, the second light absorbing layer 520 can be prevented from being etched under the blocking of the etching stop layer 600 .

[0087] Next reference Fig.13 As shown, a third etching step is performed to etch the exposed etch stop layer 600, and the etching can stop at the second light absorption layer 520 in the field plate region, thereby forming a first contact hole 310 that sequentially penetrates the interlayer dielectric layer 900, the first light absorption layer 510 and the etch stop layer 600, and the second light absorption layer 520 is exposed at the bottom of the first contact hole 310.

[0088] In a specific example, through the first etching step, the second etching step and the third etching step, a second contact hole 810S, a third contact hole 810D, and a fourth contact hole 810G can be formed in the source region, the drain region, and the gate region at the same time.

[0089] Afterwards, metal materials can be filled in each contact hole to form a field plate structure, source metal, drain metal and gate metal. In this embodiment, the bottom of the field plate structure is formed on the second light absorbing layer 520, so that the second light absorbing layer 520 is still spaced between the field plate structure and the substrate 100.

[0090] In the present embodiment, most of the photons generated during the etching process of the thicker interlayer dielectric layer 900 are absorbed by the first light absorption layer 510. Subsequently, a large number of photons are not generated during the etching process of the first light absorption layer 510. Therefore, a thinner second light absorption layer 520 is sufficient to avoid the second light absorption layer 520 being too thick and affecting the electric field modulation capability of the field plate structure.

[0091] <Example 3>

[0092] In this embodiment, an example in which an etching stop layer is provided between the field dielectric layer and the first light absorbing layer is taken for description.

[0093] Specific reference Fig.14 As shown, after forming the field dielectric layer 400, an etching stop layer 600 is formed in the device region, and then the first light absorption layer 510 and the interlayer dielectric layer 900 are sequentially formed. Afterwards, a first etching step is performed to etch the interlayer dielectric layer 900, and the etching stops at the first light absorption layer 510, and the photons generated in this process can be absorbed by the exposed first light absorption layer 510.

[0094] Next reference Fig.15 As shown, a second etching step is performed to etch the exposed etching stop layer 600, and then a first contact hole 310 can be formed in the field plate region, which sequentially penetrates the interlayer dielectric layer 900, the first light absorbing layer 510 and the etching stop layer 600. At the same time, a second contact hole is formed in the source terminal region, a third contact hole is formed in the drain terminal region, and a fourth contact hole is formed in the gate region. Afterwards, metal materials can be filled in each contact hole to form a field plate structure, a source metal, a drain metal, and a gate metal.

[0095] The present disclosure also provides an LDMOS device, which is formed by the method described above. Fig.10 As shown, the LDMOS device is specifically formed in a device region of a substrate, wherein a drift region 100N of a first conductivity type and a well region 100P of a second conductivity type are formed in the substrate 100 .

[0096] Furthermore, the LDMOS device further includes: a gate structure 200G, a source region 200S and a drain region 200D. The gate structure 200G is formed on the substrate 100, and partially covers the well region 100P and extends to cover the adjacent drift region 100N. Furthermore, the source region 200S is formed in the well region 100P and is located on one side of the gate structure 200G, and the drain region 200D is formed in the drift region 100N and is located on the other side of the gate structure 200G.

[0097] Furthermore, the LDMOS device further includes a field dielectric layer 400, which is formed in the field plate region, covers a portion of the gate structure 200G and extends toward the drain region 200D to cover the top surface of the substrate. A field plate structure 300 is also provided in the field plate region, and the field plate structure 300 is formed above the field dielectric layer 400.

[0098] Continue to refer Fig.10As shown, a first light absorbing layer 510 and an interlayer dielectric layer 900 are sequentially formed in the device region. The first light absorbing layer 510 at least covers the field dielectric layer 400, that is, the first light absorbing layer 510 is at least formed in the field plate region. And, the interlayer dielectric layer 900 can cover the entire device region. Further, the field plate structure 300 at least penetrates the interlayer dielectric layer 900 and the first light absorbing layer 510 in the field plate region.

[0099] In a specific example, at least one of a second light absorbing layer and a blocking layer is further spaced between the field plate structure 300 and the substrate 100. Fig.10 In the example of FIG. 1 , a barrier layer 700 is further spaced between the field plate structure 300 and the substrate 100; and Fig.13 In the example of , a second light absorbing layer 520 is further spaced between the field plate structure 300 and the substrate 100. Of course, in other examples, a stacked structure of the second light absorbing layer 520 and the blocking layer 700 may be spaced between the field plate structure 300 and the substrate 100.

[0100] The thickness of the second light absorbing layer 520 and the blocking layer 700 are both less than the thickness of the first light absorbing layer 510 . As for the stacked structure of the second light absorbing layer 520 and the blocking layer 700 , the total thickness of the stacked structure is still less than the thickness of the first light absorbing layer 510 .

[0101] The LDMOS device provided in this embodiment can be specifically prepared by the method as described above, wherein in the process of preparing the first contact hole for accommodating the field plate structure 300, a large number of photons generated when etching the interlayer dielectric layer can be absorbed by the first light absorption layer, and the first light absorption layer that absorbs a large number of photons and corresponds to the contact hole area is removed, so that there are no large number of photons in the first contact hole, thereby avoiding the problem that the charges at the bottom of the field plate structure absorb a large amount of photon energy and are prone to migration.

[0102] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. Although the present invention has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified to equivalent embodiments of equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0103] It must be noted that as used herein and in the appended claims, the singular forms "a," "an," and "an" include plural references unless the context clearly indicates otherwise. For example, reference to "a step" or "a device" means reference to one or more steps or devices and may include secondary steps as well as secondary devices. All conjunctions used should be interpreted in the broadest sense. Also, the word "or" should be interpreted as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise.

Claims

1. A method for preparing an LDMOS device, characterized in that: include: Providing a substrate, and forming a gate structure, a source region, and a drain region in a device region of the substrate, wherein the source region and the drain region are respectively located on two sides of the gate structure; forming a field dielectric layer, wherein the field dielectric layer covers a portion of the gate structure and extends toward the drain region to cover the top surface of the substrate; forming a first light absorbing layer, wherein the first light absorbing layer at least covers the field dielectric layer; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the device region; Etching the interlayer dielectric layer, and further etching the first light absorbing layer to form a first contact hole at least penetrating the interlayer dielectric layer and the first light absorbing layer; as well as, A field plate structure is formed in the first contact hole.

2. The method for preparing an LDMOS device according to claim 1, wherein: The method of forming the first contact hole includes: performing a first etching step to etch the interlayer dielectric layer and stop the etching at the first light absorbing layer; and, A second etching process is performed to etch the exposed first light absorbing layer to form the first contact hole.

3. The method for preparing an LDMOS device according to claim 1, wherein: A blocking layer is also formed between the field dielectric layer and the first light absorbing layer, the blocking layer at least covers the field dielectric layer, and the bottom of the first contact hole stops at the blocking layer, so that the blocking layer is still spaced between the bottom of the field plate structure and the substrate.

4. The method for preparing an LDMOS device according to claim 1, wherein: An etch stop layer is also formed below the first light absorbing layer, and the etch stop layer is between the field dielectric layer and the first light absorbing layer; When etching the first light absorbing layer, the etching is stopped at the etch stop layer to form a first contact hole that sequentially penetrates the interlayer dielectric layer, the first light absorbing layer and the etch stop layer.

5. The method for preparing an LDMOS device according to claim 4, characterized in that: A second light absorbing layer is also formed between the field dielectric layer and the etch stop layer; Wherein, the method of forming the first contact hole comprises: Performing a first etching step to etch the interlayer dielectric layer, and stopping the etching at the first light absorbing layer; performing a second etching step to etch the first light absorbing layer, and stopping the etching at the etching stop layer; and, A third etching step is performed to etch the etch stop layer, and the etching stops at the second light absorbing layer to form a first contact hole whose bottom stops at the second light absorbing layer.

6. The method for preparing an LDMOS device according to claim 1, wherein: After forming the field dielectric layer and before forming the first light absorbing layer, the method further includes: forming a second light absorbing layer and / or a blocking layer at least on the field dielectric layer; and forming an etching stop layer in the device region; Wherein, the method of forming the first contact hole comprises: Performing a first etching step to etch the interlayer dielectric layer, and stopping the etching at the first light absorbing layer; A second etching step is performed to etch the first light absorbing layer and the etching stop layer to form the first contact hole, wherein at least one of the second light absorbing layer and the blocking layer is still retained at the bottom of the first contact hole.

7. The method for preparing an LDMOS device according to claim 3 or 6, characterized in that: The thickness of the blocking layer is smaller than the thickness of the first light absorbing layer.

8. The method for preparing an LDMOS device according to claim 3 or 6, characterized in that: The material of the barrier layer includes silicon oxynitride.

9. The method for preparing an LDMOS device according to claim 5 or 6, characterized in that: The thickness of the second light absorbing layer is smaller than the thickness of the first light absorbing layer.

10. The method for preparing an LDMOS device according to claim 1, wherein: The material of the first light absorbing layer includes silicon.

11. An LDMOS device, characterized in that: include: A substrate having a device region for arranging an LDMOS device; A gate structure formed on the substrate in the device region; A source region and a drain region are formed in the substrate of the device region and are respectively located on both sides of the gate structure; A field dielectric layer, covering a portion of the gate structure and extending toward the drain region to cover the top surface of the substrate; A first light absorbing layer at least covers the field medium layer; An interlayer dielectric layer, covering the device region; as well as, A field plate structure is formed above the field dielectric layer and at least penetrates the interlayer dielectric layer and the first light absorbing layer.

12. The LDMOS device according to claim 11, characterized in that: At least one of a second light absorbing layer and a blocking layer is spaced between the field plate structure and the substrate.

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