Planar MOSFET device

Abstract

The planar MOSFET device provided by the embodiment of the invention has the advantages of breakdown resistance, low resistance, reduced gate-drain capacitance and the like. The device comprises a substrate; the epitaxial layer is arranged on the substrate layer; the epitaxial layer includes a drift layer, a first sub-region, a well region, and a source region. A channel region located between the source region and the first sub-region is arranged in the well region; the gate oxide layer is arranged on the top surface, far away from the substrate, of the epitaxial layer and is connected with the first sub-region, the channel region and the source region respectively; the gate electrode is arranged on the side, away from the epitaxial layer, of the gate oxide layer, and the gate electrode comprises two main body parts which are arranged at intervals in the first direction; orthographic projections of the two main body parts on the epitaxial layer are respectively positioned on the channel region; the source electrode metal is arranged on one side, far away from the epitaxial layer, of the gate electrode and is respectively connected with the well region and the source region; the isolation oxide layer is arranged between the gate electrode and the source electrode metal; a contact hole is formed in the isolation oxide layer; and the first metal layer is embedded in the isolation oxide layer and penetrates through the contact hole to be electrically connected with the gate electrode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a planar MOSFET device. Background Art

[0002] MOSFET (Metal-Oxide-SemiconductorField-EffectTransistor) is a metal-oxide-semiconductor field-effect transistor, which has a higher input impedance than a junction field-effect transistor, and the manufacturing process is relatively simple, flexible and convenient to use, which is very conducive to high integration and has therefore received extensive attention and research. Silicon carbide materials have outstanding characteristics such as wide bandgap width, high critical breakdown electric field strength, high saturated electron drift velocity and high thermal conductivity, which make them more capable of playing a role in high temperature, high pressure and high frequency fields compared with silicon materials. Silicon carbide MOSFET is more widely used than silicon-based devices with the same withstand voltage level because of its high withstand voltage and low on-resistance. Compared with silicon, silicon carbide MOSFET has a higher critical breakdown electric field, so the electric field strength of the gate oxide layer in silicon carbide is also high, which leads to an increase in the reliability problem of the device gate oxide layer. When the gate oxide layer is set thin, it will be easily broken down; and thickening the gate oxide layer will cause a decrease in carrier mobility, thereby increasing the on-resistance. Therefore, existing traditional silicon carbide MOSFETs cannot improve performance while maintaining reliability. Summary of the invention

[0003] Therefore, in order to overcome at least some of the defects and shortcomings in the prior art, an embodiment of the present invention provides a planar MOSFET device, which can have the advantages of anti-breakdown, low resistance, and reduced gate-drain capacitance through the design of the gate electrode and the first metal layer.

[0004] An embodiment of the present invention provides a planar MOSFET device, comprising: a substrate; an epitaxial layer, arranged on the substrate layer; the epitaxial layer comprising: a drift layer; a first sub-region, arranged on a side of the drift layer away from the substrate; a well region, arranged on two opposite sides of the first sub-region along a first direction; a source region, the source region being embedded in the well region and the source region being away from the upper surface of the substrate and exposed outside the well region; a channel region located between the source region and the first sub-region in the well region; a gate oxide layer, arranged on a top surface of the epitaxial layer away from the substrate and respectively contacting the first sub-region, the well region and the gate oxide layer; The channel region is connected to the source region; a gate electrode is arranged on a side of the gate oxide layer away from the epitaxial layer, and the gate electrode includes two main parts arranged at intervals along the first direction; the orthographic projections of the two main parts on the epitaxial layer are respectively located on the channel region; a source metal is arranged on a side of the gate electrode away from the epitaxial layer and is respectively connected to the well region and the source region; an isolation oxide layer is arranged between the gate electrode and the source metal; a contact hole is opened in the isolation oxide layer; a first metal layer is embedded in the isolation oxide layer and is electrically connected to the gate electrode through the contact hole.

[0005] In some embodiments, the gate electrode also includes a connecting portion, which is connected between the two main body portions; the length of the connecting portion along the second direction is less than the length of the two main body portions along the second direction; the second direction is perpendicular to the first direction; and the orthographic projection of the contact hole on the gate electrode is at least partially located on the connecting portion.

[0006] In some embodiments, a width of the first metal layer along the first direction is smaller than a width of the gate electrode along the first direction.

[0007] In some embodiments, the connecting portion is disposed close to ends of the two main body portions along the second direction.

[0008] In some embodiments, the thickness of the first metal layer is 0.2-4 micrometers.

[0009] In some embodiments, the spacing distance between the two main body parts is 0.2-4 micrometers.

[0010] In some embodiments, the isolation oxide layer includes a first sublayer located between the first metal layer and the gate electrode, and the thickness of the first sublayer is 0.1-1 micrometer.

[0011] In some embodiments, the first metal layer is made of aluminum or aluminum alloy.

[0012] In some embodiments, a width of the first metal layer along the first direction is smaller than a width of the gate electrode along the first direction.

[0013] In some embodiments, a width of each of the two main body portions along the first direction is 0.2-4 micrometers.

[0014] The above-mentioned embodiments of the present invention have at least one or more of the following beneficial effects: by designing the structure of the gate electrode in the planar MOSFET device, the two main parts are separated from each other to improve the electric field at the first sub-region and enhance the anti-breakthrough capability, and the addition of a second metal layer connected to the gate electrode can achieve a lower gate resistance, so that the planar MOSFET device can have the advantages of anti-breakthrough, low resistance, and reduced gate-drain capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A schematic diagram of the three-dimensional structure of a planar MOSFET device provided in an embodiment of the present invention.

[0017] Figure 2 for Figure 1 The cross-sectional structure diagram of the planar MOSFET device taken along line L1 is shown.

[0018] Figure 3 for Figure 1 The schematic structural diagram of the cross section of the planar MOSFET device taken along the L2 line is shown.

[0019] Figure 4 A schematic diagram of the three-dimensional structure of a step in the preparation process of a planar MOSFET device provided by an embodiment of the present invention.

[0020] Figure 5 In the process of preparing the planar MOSFET device provided by the embodiment of the present invention Figure 4 A schematic diagram of the three-dimensional structure at a step after the step shown.

[0021] Figure 6 In the process of preparing the planar MOSFET device provided by the embodiment of the present invention, Figure 5 A schematic diagram of the three-dimensional structure at a step after the step shown.

[0022] Figure 7 In the process of preparing the planar MOSFET device provided by the embodiment of the present invention, Figure 6 A schematic diagram of the three-dimensional structure at a step after the step shown.

[0023] Figure 8In the process of preparing the planar MOSFET device provided by the embodiment of the present invention, Figure 7 A schematic diagram of the three-dimensional structure at a step after the step shown.

[0024] [Description of Reference Numerals]

[0025] 10. Substrate; 20. Epitaxial layer; 21. Drift layer; 22. First sub-region; 23. Well region; 231. Channel region; 24. Source region; 30. Gate oxide layer; 40. Gate electrode; 41. Main body; 42. Connecting portion; 50. Isolation oxide layer; 51. First sub-layer; 511. Contact hole; 52. Second sub-layer; 60. First metal layer; 70. Source metal; 51a. First isolation material layer; 52a. Second isolation material layer. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0030] like Figure 1 , Figure 2 and Figure 3As shown, an embodiment of the present invention provides a planar MOSFET device, comprising a substrate 10, an epitaxial layer 20, a gate oxide layer 30, a gate electrode 40, an isolation oxide layer 50, a first metal layer 60 and a source metal 70 stacked in sequence along the thickness direction. Among them, the epitaxial layer 20 is arranged on the substrate 10 layer. The epitaxial layer 20 includes a drift layer 21, a first sub-region 22, a well region 23 and a source region 24. The first sub-region 22 is arranged on a side of the drift layer 21 away from the substrate 10. The well region 23 is arranged on two opposite sides of the first sub-region 22 along the first direction. The source region 24 is embedded in the well region 23 and the upper surface of the source region 24 away from the substrate 10 is exposed outside the well region 23. The well region 23 has a channel region 231 located between the source region 24 and the first sub-region 22. The gate oxide layer 30 is arranged on the top surface of the epitaxial layer 20 away from the substrate 10 and is connected to the first sub-region 22, the channel region 231 and the source region 24 respectively. The gate electrode 40 is disposed on a side of the gate oxide layer 30 away from the epitaxial layer 20, and the gate electrode 40 includes two main body portions 41 spaced apart along a first direction. The orthographic projections of the two main body portions 41 on the epitaxial layer 20 are respectively located on the channel region 231. The source metal 70 is disposed on a side of the gate electrode 40 away from the epitaxial layer 20, and is respectively connected to the well region 23 and the source region 24. The isolation oxide layer 50 is disposed between the gate electrode 40 and the source metal 70. A contact hole 511 is opened in the isolation oxide layer 50 (refer to Figure 5 ). Reference Figure 3 The first metal layer 60 is embedded in the isolation oxide layer 50 and is electrically connected to the gate electrode 40 through the contact hole 511 .

[0031] Wherein, the substrate 10 is, for example, a silicon carbide substrate. Since the first sub-region 22 and the drift layer 21 have the same material and doping type, the first sub-region 22 can also be called a JFET region, that is, a region in the epitaxial layer 20 located between the two well regions 23. The two source regions 24 are arranged in a one-to-one correspondence with the two well regions 23, and the upper surfaces of the two source regions 24 facing away from the substrate 10 are also a part of the top surface of the epitaxial layer 20 facing away from the substrate 10. Whether the doping type of the drift layer 21 is N-type doping or P-type doping can classify the planar MOSFET device as an N-type field effect transistor or a P-type field effect transistor. For example, if the drift layer 21 is N-type doped, the planar MOSFET device is an N-type field effect transistor. When the drift layer 21 is N-type doped, the source region 24 is also N-type doped, and the well region 23 is P-type doped. When the drift layer 21 is P-type doped, the source region 24 is also P-type doped, and the well region 23 is N-type doped.

[0032] The gate oxide layer 30 may be made of silicon oxide material, such as Figure 2 As shown, the gate oxide layer 30 covers the first sub-region 22 and extends toward both sides of the first sub-region 22 to above the channel region 231 and contacts portions of the upper surfaces of the source regions 24 on both sides.

[0033] The isolation oxide layer 50 is used to isolate the gate electrode 40 from the source metal 70. The source metal 70 covers the isolation oxide layer 50 and extends to the top surface of the epitaxial layer 20 to form an ohmic contact with the source region 24 and a part of the well region 23. The source metal 70 is, for example, a single layer of aluminum alloy.

[0034] The gate electrode 40 is, for example, a polysilicon (poly) layer. A drain layer is provided on the bottom surface side of the substrate 10 away from the epitaxial layer 20, for example. The electrical property of the drain layer corresponds to the electrical property of the drift layer 21. When the drift layer 21 is N-type doped, the drain is an N electrode.

[0035] In the gate electrode 40, the two main bodies 41 are specifically located above the two channel regions 231 so that when a voltage is applied between the gate electrode 40 and the source metal 70, an inversion layer can be formed in the two channel regions 231 to achieve a switching function. The spacing distance between the two main bodies 41 ( Figure 4 The distance S) is, for example, 0.2 to 4 micrometers. The distance between the two main body portions 41 is smaller than the width of the first sub-region 22 along the first direction. The width of a single main body portion 41 along the first direction (refer to Figure 4 The middle distance W2) is, for example, 0.2 to 4 microns, and the width of a single main body 41 along the first direction can be designed according to the width of the channel region 231 along the first direction. In this embodiment, the electric field distribution of the first sub-region 22 (i.e., the JFET region) can be changed by setting the two main bodies 41 at intervals, reducing the peak value of the electric field intensity of the first sub-region 22 while ensuring normal working performance, so that the reliability of the device is guaranteed. And the two main bodies 41 are arranged at intervals to reduce the gate-drain capacitance of the first sub-region 22. The two main bodies 41 are arranged at intervals to form a partial hollow area in the gate electrode 40. The planar MOSFET device provided in this embodiment is also provided with a first metal layer 60, and the first metal layer 60 and the gate electrode 40 together constitute the gate of the planar MOSFET device. Since the first metal layer 60 is embedded in the isolation oxide layer 50 and is electrically connected to the gate electrode 40 through the contact hole 511, the gate resistance can be optimized, and the increase in gate resistance caused by the formation of the hollow area can be improved. Due to the reduction of gate resistance, the EAS capability of the device can be improved, and the turn-on / off switching time can be optimized. In one embodiment of the present invention, the gate resistance can reach less than 0.5Ω. The first metal layer 60 is made of aluminum or alloy, for example, and has a low resistance. The thickness of the first metal layer 60 is 0.2 to 4 microns. Therefore, the planar MOSFET device provided in the embodiment of the present invention can have the advantages of anti-breakthrough, low resistance, and reduced gate-drain capacitance by designing the structure of the gate electrode 40 and adding the first metal layer 60.

[0036] The planar MOSFET device provided in the above embodiment of the present invention can be manufactured through the following steps.

[0037] S1 : forming an epitaxial layer material on a substrate 10 , and doping corresponding regions of the epitaxial layer material to form an epitaxial layer 20 including a drift layer 21 , a first sub-region 22 , a well region 23 and a source region 24 .

[0038] S2 : growing a gate oxide material on the top surface of the epitaxial layer 20 away from the substrate 10 , and performing patterning to obtain a gate oxide layer 30 .

[0039] S3: depositing a gate electrode material on the gate oxide layer 30, and performing patterning, etching away the portion of the gate electrode material outside the gate oxide layer 30, and at least the portion above the first sub-region 22, to obtain a gate electrode 40. The structure obtained after step S3 is completed can refer to Figure 4 , Figure 4 Midline L3 and Figure 1 The positions of the midlines L2 correspond, and the two are in the same vertical plane.

[0040] Step S4: depositing a first isolation material layer 51a so that the first isolation material layer 51a covers the gate electrode 40 and the top surface of the epitaxial layer 20, and opening the first isolation material layer 51a to obtain a contact hole 511. The structure obtained after step S4 can refer to Figure 5 shown.

[0041] Step S5: depositing a first metal material layer on the first isolation material layer 51a, so that part of the first metal material layer is connected to the gate electrode 40 through the contact hole 511, and removing the excess part of the first metal material layer to obtain the first metal layer 60. The structure after step S5 is completed can refer to Figure 6 shown.

[0042] Step S6: Deposit the second isolation material layer 52a so that the second isolation material layer 52a covers the first metal layer 60 and covers the portion of the first isolation oxygen material layer 51a exposed outside the first metal layer 60. The structure after step S6 is completed can refer to Figure 7 shown.

[0043] Step S7: Remove the redundant parts of the first isolation material layer 51a and the second isolation material layer 52a to obtain the first sublayer 51 and the second sublayer 52. The first sublayer 51 and the second sublayer 52 together constitute the isolation oxide layer 50. The thickness of the first sublayer 51 is 0.1 to 1 micron, and the thickness of the second sublayer is, for example, 0.1 to 1 micron. The structure obtained after step S7 can refer to Figure 8 shown.

[0044] Step S8 : depositing a source metal material on the isolation oxide layer 50 to obtain a source metal 70 .

[0045] The above preparation steps are highly compatible with the traditional MOSFET device preparation process and are easy to implement.

[0046] In some embodiments, reference Figure 4 The gate electrode 40 further includes a connecting portion 42, the connecting portion 42 is connected between the two main portions 41, the length L2 of the connecting portion 42 along the second direction is less than the length L1 of the two main portions 41 along the second direction, and the second direction is perpendicular to the first direction. The orthographic projection of the contact hole 511 on the gate electrode 40 is at least partially located on the connecting portion 42. Figure 1 The first direction of the orientation shown is the left-right direction on the horizontal plane, and the second direction is the front-back direction on the horizontal plane. The second direction is perpendicular to the first direction and perpendicular to the thickness direction of the planar MOSFET device.

[0047] In some embodiments, the width D1 of the contact hole 511 along the first direction is 0.2 to 5 microns, and the width D2 of the contact hole 511 along the first direction is 0.2 to 5 microns. Through the above configuration, the first metal layer 60 is at least partially connected to the connecting portion 42 through the portion of the contact hole 511, and then the first metal layer 60 is connected to the gate electrode 40 through the connection with the connecting portion 42, which can increase the contactable area between the first metal layer 60 and the gate electrode 40, and achieve a more stable electrical connection. In a specific embodiment, the width D1 of the contact hole 511 along the first direction is greater than or equal to the spacing distance between the two main bodies 41, and the length D2 of the contact hole 511 (i.e., the width along the second direction) is, for example, equal to the length of the connecting portion 42 along the second direction.

[0048] In some embodiments, reference Figure 4 The connecting portion 42 is disposed near the ends of the two main portions 41 along the second direction so that the orthographic projection of the gate electrode 40 on the top surface of the epitaxial layer 20 is a U-shaped structure, which can better improve the electric field of the first sub-region.

[0049] In some embodiments, the width of the first metal layer 60 along the first direction is smaller than the width of the gate electrode 40 along the first direction, so as to prevent the problem of the gate-drain capacitance being increased due to the excessive width of the first metal layer 60. In some embodiments, the width of the first metal layer 60 along the first direction is larger than the width of the contact hole 511 along the first direction and smaller than the width of the gate electrode 40 along the first direction, so as to reduce the gate-drain capacitance while ensuring good contact between the first metal layer 60 and the gate electrode 40. The length of the first metal layer 60 along the second direction is larger than the length of the contact hole 511 along the second direction to ensure good contact with the gate electrode 40.

[0050] The planar MOSFET device provided in the above embodiment of the present invention can improve the electric field in the JFET region, reduce the peak value of the electric field strength in the JFET region, improve the device's breakdown resistance, and has the advantages of low resistance and reduced gate-drain capacitance.

[0051] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A planar MOSFET device, characterized in that: include: A substrate (10); An epitaxial layer (20) is disposed on the substrate (10); The epitaxial layer (20) comprises: a drift layer (21); a first sub-region (22) arranged on a side of the drift layer (21) away from the substrate (10); a well region (23) arranged on two opposite sides of the first sub-region (22) along a first direction; a source region (24), the source region (24) being embedded in the well region (23) and the upper surface of the source region (24) away from the substrate (10) being exposed outside the well region (23); the well region (23) having a channel region (231) located between the source region (24) and the first sub-region (22); A gate oxide layer (30) is arranged on a top surface of the epitaxial layer (20) away from the substrate (10) and is respectively connected to the first sub-region (22), the channel region (231) and the source region (24); A gate electrode (40) is arranged on a side of the gate oxide layer (30) away from the epitaxial layer (20), the gate electrode (40) comprising two main body portions (41) arranged at intervals along the first direction; orthographic projections of the two main body portions (41) on the epitaxial layer (20) are respectively located on the channel region (231); A source metal (70) is arranged on a side of the gate electrode (40) away from the epitaxial layer (20) and is respectively connected to the well region (23) and the source region (24); An isolation oxide layer (50) is disposed between the gate electrode (40) and the source metal (70); a contact hole (511) is provided in the isolation oxide layer (50); The first metal layer (60) is embedded in the isolation oxide layer (50) and is electrically connected to the gate electrode (40) through the contact hole (511).

2. The planar MOSFET device according to claim 1, characterized in that: The gate electrode (40) further comprises a connecting portion (42), wherein the connecting portion (42) is connected between the two main body portions (41); the length of the connecting portion (42) along a second direction is shorter than the length of the two main body portions (41) along the second direction; and the second direction is perpendicular to the first direction; An orthographic projection of the contact hole (511) on the gate electrode (40) is at least partially located on the connecting portion (42).

3. The planar MOSFET device according to claim 2, characterized in that: The width of the contact hole (511) along the first direction is 0.2 to 5 microns, and the width of the contact hole (511) along the second direction is 0.2 to 5 microns.

4. The planar MOSFET device according to claim 2, characterized in that: The connecting portion (42) is arranged close to the ends of the two main body portions (41) along the second direction.

5. The planar MOSFET device according to claim 1, characterized in that: The thickness of the first metal layer (60) is 0.2-4 micrometers.

6. The planar MOSFET device according to claim 1, characterized in that: The spacing distance between the two main body parts (41) is 0.2 to 4 micrometers.

7. The planar MOSFET device according to claim 1, characterized in that: The isolation oxide layer (50) comprises a first sublayer (51) located between the first metal layer (60) and the gate electrode (40), and the thickness of the first sublayer (51) is 0.1 to 1 micrometer.

8. The planar MOSFET device according to claim 1, characterized in that: The first metal layer (60) is made of aluminum or aluminum alloy.

9. The planar MOSFET device according to claim 1, characterized in that: The width of the first metal layer (60) along the first direction is smaller than the width of the gate electrode (40) along the first direction.

10. The planar MOSFET device according to claim 1, characterized in that: The width of each of the two main body parts (41) along the first direction is 0.2 to 4 micrometers.

Images