FinFET structure and manufacturing method and application thereof

Abstract

The invention discloses a FinFET structure and a manufacturing method and application thereof. The FinFET structure comprises a heterojunction which comprises a channel layer and a barrier layer, the surface of the channel layer is provided with a source region, a gate region and a drain region which are sequentially distributed along a first direction, the gate region comprises a plurality of selected regions which are distributed at intervals along a second direction, and the barrier layer is stacked on the plurality of selected regions to form a plurality of fin-shaped structures; the first ohmic contact layer is stacked on the source region on the surface of the channel layer; the second ohmic contact layer is stacked on the drain region on the surface of the channel layer; and a source electrode, a drain electrode and a grid electrode, and the grid electrode is at least continuously stacked on the top end surface and the side wall of the plurality of fin-shaped structures. The source electrode is arranged on the first ohmic contact layer, and the drain electrode is arranged on the second ohmic contact layer. According to the invention, a thin barrier heterojunction epitaxial structure is adopted, an ohmic contact layer is grown by means of secondary epitaxy, a near-full-grid-control short-channel device is prepared, and low knee-point voltage and an enhanced working mode can be realized at the same time, so that a radio frequency front-end PA application scene is met.

Description

Technical Field

[0001] The present invention particularly relates to a FinFET structure and a manufacturing method and application thereof, belonging to the field of micro-nano manufacturing / semiconductor technology. Background Art

[0002] The third-generation semiconductor material gallium nitride (GaN) has advantages such as wide bandgap (3.4eV), high breakdown electric field (3.1MV / cm) and high electron saturation velocity, making GaN devices very suitable for making high-temperature electronic devices and have broad application prospects in the high-frequency and microwave fields. Under the action of polarization effect, a strong built-in electric field can be formed in GaN-based heterostructures (such as AlGaN / GaN, AlInGaN / GaN, AlN / GaN, etc.), which modulates the band structure of the nitride heterojunction, forms a deep quantum well on the GaN side, attracts free electrons to gather in the well to form a high-density 2DEG (Two-dimensional electron gas), and becomes an ideal choice for the new generation of electronic devices - lateral HEMT (High-electron-mobility transistor). GaN HEMT has shown excellent performance in high-frequency, high-power and high-temperature applications, and has been successfully used as a radio frequency power amplifier (PA) in 5G core infrastructure such as base stations. For 5G and highly integrated large-scale MIMO (Multiple-input Multiple-output) applications in communication systems, the high power handling capability of GaN devices has a stronger advantage than that of GaAs, and is expected to improve overall efficiency and reduce the size of RF chips, and is superior to GaAs in terms of power output capability and heat dissipation performance.

[0003] Silicon-based GaN HEMTs for RF (Radio Frequency) / MM Wave (Millimeter Wave) applications with low cost advantages are also very competitive, but there is still no GaN RF HEMT for mobile terminal applications in the true sense. The main reason is some inherent defects in the structure of conventional GaN HEMT devices: along the channel direction, there is an access region between the gate-source and gate-drain of the device, which introduces a large proportion of series resistance, which greatly reduces the voltage effectively applied to both sides of the channel under the gate, and fundamentally limits the saturation behavior of the device output current, causing pinch-off saturation to appear earlier than speed saturation, and failing to reduce the device V knee (Knee Voltage, knee voltage), such as Figure 1As shown in the figure. Since the operating voltage of mobile smart terminals is relatively low (generally 3-5V), the higher V knee (usually 2-3V) severely limits its low-voltage application and cannot give full play to its high output power density advantage. On the other hand, the conventional GaN HEMT structure inevitably has a channel resistance R between the gate and the source. GS Under the action of high electric field, this resistor will produce nonlinear effects closely related to the degradation of electron mobility, deteriorating the output current and linearity, and seriously restricting the device's PA application in mobile smart terminals. On the other hand, in order to simplify the system and reduce the chip area, the enhanced working mode of PA is necessary for the RF front end of mobile smart terminals. However, only Intel has used the barrier layer slow etching technology to prepare the enhanced GaN RF HEMT. The current device structure and process technology make it extremely difficult to prepare GaN HEMT for RF applications.

[0004] In order to solve the above problems, under the conditions allowed by semiconductor process technology, shortening the source-drain spacing as much as possible is a feasible solution. First, this solution can construct a high electric field between the source and drain under the condition of small source-drain voltage, so that the speed saturation appears earlier than the pinch-off saturation, effectively reducing the knee voltage. At present, the HRL laboratory in the United States uses the sidewall process technology to prepare GaN HEMTs with a source-drain spacing of 130nm; Intel and OMMIC in France use conventional photolithography and electron beam exposure processes to prepare short-channel (<500nm) GaN HEMTs. Secondly, compared with traditional planar devices, the FinFET structure has better channel control capabilities and has more advantages in suppressing short channel effects and improving electron mobility; combined with the shortening of the source-drain spacing, the access area resistance is suppressed, which can make the device more linear. And by adjusting the effective gate width, the threshold voltage can be shifted positively, thereby realizing an enhanced device.

[0005] The general process flow of GaN HEMT devices in the prior art is: ohmic contact preparation-table isolation-surface passivation-gate groove etching-gate metal preparation. The device prepared by the above scheme cannot avoid the access area between the gate-source and the gate-drain, so the linearity degradation of the device is more serious when outputting high current. Another technical challenge is that it is extremely difficult to prepare enhanced GaN HEMTs for RF (and millimeter wave) applications by conventional schemes, and due to the practical requirements of simplifying the system and reducing the chip area, the enhanced working mode of PA is necessary for the RF front end of mobile smart terminals. In fact, as mentioned above, only a few companies in the world have achieved the preparation of enhanced GaN RF HEMTs. For example, Intel uses barrier layer slow etching technology to prepare enhanced GaN RF HEMTs. However, this technology puts forward extremely high requirements on etching accuracy and controllability, and is difficult to achieve. In addition, Panasonic of Japan has also developed technical reserves for the development of enhanced GaN RF HEMTs and developed p-NiO gate technology. However, there are certain difficulties in the growth of p-type NiO and its thermal stability is poor. Summary of the invention

[0006] The main purpose of the present invention is to provide a FinFET structure and a manufacturing method and application thereof, so as to overcome the deficiencies in the prior art.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0008] In one aspect, the present invention provides a FinFET structure, comprising:

[0009] A heterojunction, comprising a channel layer and a barrier layer, wherein a surface of the channel layer has a source region, a gate region and a drain region sequentially distributed along a first direction, the gate region comprises a plurality of selected regions spaced apart and distributed along a second direction, the barrier layer is stacked on the plurality of selected regions to form a plurality of fin-shaped structures, and the first direction is perpendicular to the second direction;

[0010] A first ohmic contact layer, which is at least stacked on the source region on the surface of the channel layer;

[0011] A second ohmic contact layer, which is at least stacked on the drain region on the surface of the channel layer;

[0012] A gate extending along the second direction and continuously stacked on at least the top surfaces and side walls of the plurality of fin-shaped structures;

[0013] a source electrode, which is disposed on the first ohmic contact layer and forms an ohmic contact with the first ohmic contact layer;

[0014] The drain electrode is disposed on the second ohmic contact layer and forms an ohmic contact with the second ohmic contact layer.

[0015] Furthermore, the distances between the gate and the source and drain should be as small as possible, but the three should not be in direct contact with each other.

[0016] In a more specific embodiment, the surface of the channel layer has a plurality of first regions and a plurality of second regions alternately distributed along a second direction, and the barrier layer is stacked on the plurality of the first regions to form a plurality of the fin-like structures; the fin structure and the second region both have a source region, a gate region and a drain region; and, in the first direction, the source region, the gate region and the drain region of the fin-like structure and the second region are respectively arranged corresponding to the source region, the gate region and the drain region on the surface of the channel layer; the gate continuously covers the gate regions of the plurality of the second regions and the top surfaces and side walls of the gate regions of the plurality of the fin-like structures along the second direction; a first ohmic contact layer and a source electrode are sequentially stacked on at least the source region of the fin structure, and a second ohmic contact layer and a drain electrode are sequentially stacked on at least the drain region of the fin structure.

[0017] Furthermore, a first ohmic contact layer is stacked on the source region of the second region, and the source electrode extends continuously along the second direction and is stacked on the multiple fin-like structures and the multiple source regions of the second region; and / or a second ohmic contact layer is stacked on the drain region of the second region, and the drain electrode extends continuously along the second direction and is stacked on the multiple fin-like structures and the multiple drain regions of the second region.

[0018] Furthermore, the FinFET structure includes a groove structure formed between the first ohmic contact layer and the second ohmic contact layer; the groove bottom surface of the groove structure is distributed on the gate region of the second region and the top surface and side wall of the gate region of the fin structure, and extends continuously along the second direction; the gate foot of the gate is filled in the groove structure, and the gate cap of the gate has an extension part, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and a gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

[0019] In a more specific embodiment, a first ohmic contact layer and a second ohmic contact layer are directly stacked on the source region and the drain region on the surface of the channel layer, respectively, and the source, the first ohmic contact layer, the drain and the second ohmic contact layer all extend continuously along the second direction; the gate region on the surface of the channel layer also includes a third region distributed between adjacent selected regions, and the gate extends along the second direction and continuously covers the third region and the top surfaces and side walls of the plurality of fin-like structures.

[0020] Furthermore, the FinFET structure includes a groove structure formed between the first ohmic contact layer and the second ohmic contact layer; the groove bottom surface of the groove structure is distributed on the third area of ​​the channel layer surface and the top surface and side wall of the fin structure, and extends continuously along the second direction; the gate foot of the gate is filled in the groove structure, and the gate cap of the gate has an extension part, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and a gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

[0021] Furthermore, the sidewalls of the fin-shaped structure are electrically connected to the sidewalls of the first ohmic contact layer and the second ohmic contact layer respectively.

[0022] Furthermore, a cross section of the gate in the first direction is T-shaped.

[0023] Furthermore, a size of the gate foot of the gate in the first direction is 50-250 nm.

[0024] Furthermore, the FinFET structure includes at least three fin structures.

[0025] Furthermore, the fin-shaped structure further includes an insertion layer and / or a cap layer, wherein the insertion layer is distributed between the barrier layer and the channel layer, and the cap layer is stacked on the barrier layer.

[0026] Furthermore, a gate dielectric layer is distributed between the gate and the heterojunction, and the material of the gate dielectric layer includes one or more combinations of Al2O3, SiO2, HfO2, AlON, and silicon nitride, but is not limited thereto. Furthermore, the gate dielectric layer can be a single dielectric layer or a composite dielectric layer. Exemplarily, the composite dielectric layer can be a composite dielectric layer such as Al2O3 / AlN or Al2O3 / HfO2.

[0027] Furthermore, the FinFET structure also includes a substrate, on which a buffer layer, a channel layer and a barrier layer are stacked in sequence.

[0028] Furthermore, the material of the substrate includes one or more combinations of silicon, sapphire, silicon carbide, gallium nitride, and aluminum nitride, but is not limited thereto.

[0029] Furthermore, the FinFET structure includes a GaN-based FinFET structure, a GaAs-based FinFET structure or a GaO-based FinFET structure.

[0030] Furthermore, the heterojunction includes a single heterojunction or a multiple heterojunction.

[0031] Furthermore, the heterojunction includes one or more combinations of single-channel or multi-channel AlGaN / GaN heterojunction, AlN / GaN heterojunction, AlInN / GaN heterojunction, AlInGaN / GaN heterojunction, AlGaN / GaN / AlGaN double heterojunction, and AlGaN / GaN / InGaN double heterojunction, but is not limited thereto.

[0032] Furthermore, the material of the first ohmic contact layer and the second ohmic contact layer includes one or more combinations of n++GaN, n++InGaN, and n++InN, but is not limited thereto.

[0033] Another aspect of the present invention further provides a method for manufacturing a FinFET structure, comprising:

[0034] Providing an epitaxial layer, wherein the epitaxial layer includes a channel layer and a barrier layer stacked on the channel layer, wherein the channel layer and the barrier layer cooperate to form a heterojunction;

[0035] A first graphic mask is arranged on a surface of the epitaxial layer away from the channel layer, and the epitaxial layer is etched using the first graphic mask until the surface or the inside of the channel layer is reached, so that a plurality of second regions on the surface of the channel layer are exposed, and the barrier layer on the plurality of first regions on the surface of the channel layer is retained, so as to form a plurality of fin-shaped structures, wherein the fin-shaped structures and the second regions both have a source region, a gate region and a drain region sequentially distributed along a first direction, and the plurality of the first regions and the plurality of the second regions are alternately distributed along a second direction, and the second direction is perpendicular to the first direction;

[0036] Removing the first graphic mask, and then setting a second graphic mask on a surface of the epitaxial layer away from the channel layer, wherein the second graphic mask continuously extends along a second direction and covers the plurality of fin structures and the plurality of gate regions of the second region;

[0037] Growing an ohmic contact layer on the surface of the channel layer, the ohmic contact layer comprising a first ohmic contact layer and a second ohmic contact layer, the first ohmic contact layer being stacked on the plurality of fin-shaped structures and the source regions of the plurality of second regions, the second ohmic contact layer being stacked on the plurality of fin-shaped structures and the drain regions of the plurality of second regions, then removing the second graphic mask, and performing active region isolation on the obtained device structure;

[0038] forming a continuous gate dielectric layer at least on the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures and the gate regions of the plurality of second regions, and then manufacturing a gate on the gate dielectric layer, and making the gate continuously cover at least the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures and the gate regions of the plurality of second regions;

[0039] A source electrode and a drain electrode are respectively formed on the first ohmic contact layer and the second ohmic contact layer, and the source electrode and the drain electrode are respectively in ohmic contact with the first ohmic contact layer and the second ohmic contact layer.

[0040] Furthermore, the manufacturing method specifically includes: continuously covering the gate dielectric layer at least on the surface of the ohmic contact layer, the fin-shaped structure and the channel layer, and then respectively processing a source window and a drain window on the gate dielectric layer to expose at least a partial surface of the first ohmic contact layer and the second ohmic contact layer, and then respectively manufacturing the source and drain at the source window and the drain window.

[0041] Furthermore, the source electrode extends continuously along the second direction and is stacked on the source regions of the plurality of fin-shaped structures and the plurality of second regions; and the drain electrode extends continuously along the second direction and is stacked on the drain regions of the plurality of fin-shaped structures and the plurality of second regions.

[0042] Furthermore, the gate foot of the gate is filled in a groove structure formed between the first ohmic contact layer and the second ohmic contact layer, and the gate cap of the gate has an extension portion, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and the gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

[0043] Furthermore, the manufacturing method specifically includes: sequentially growing a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on a substrate to form the epitaxial layer.

[0044] Another aspect of the present invention further provides a method for manufacturing a FinFET structure, comprising:

[0045] Providing an epitaxial layer, wherein the epitaxial layer includes a channel layer and a barrier layer stacked on the channel layer, wherein the channel layer and the barrier layer cooperate to form a heterojunction;

[0046] A third graphic mask is provided on a surface of the epitaxial layer away from the channel layer, and the epitaxial layer is etched using the third graphic mask until the surface or the inside of the channel layer is reached, so that the source region and the drain region on the surface of the channel layer are exposed, and the barrier layer on the gate region on the surface of the channel layer is retained to form a ridge structure, and the source region, the gate region and the drain region on the surface of the channel layer are distributed in sequence along the first direction;

[0047] Growing a first ohmic contact layer and a second ohmic contact layer on the source region and the drain region on the surface of the channel layer respectively, and then removing the third pattern mask;

[0048] A fourth pattern mask is arranged on the ridge structure, the first ohmic contact layer and the second ohmic contact layer, and then a partial area of ​​the surface of the ridge structure exposed from the fourth pattern mask is etched until reaching the surface or the inside of the channel layer, so that the barrier layer on multiple selected areas on the surface of the channel layer is retained to form multiple fin structures, and the multiple selected areas are spaced apart and distributed along a second direction, and the second direction is perpendicular to the first direction;

[0049] The fourth pattern mask is removed, and then a continuous gate dielectric layer is formed at least on the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures, and then a gate is formed on the gate dielectric layer, and the gate is made to continuously cover at least the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures;

[0050] A source electrode and a drain electrode are respectively formed on the first ohmic contact layer and the second ohmic contact layer, and the source electrode and the drain electrode are respectively in ohmic contact with the first ohmic contact layer and the second ohmic contact layer.

[0051] Furthermore, the manufacturing method specifically includes: continuously covering the gate dielectric layer on at least the surface of the first ohmic contact layer, the second ohmic contact layer, the fin-shaped structure and the channel layer, and then respectively processing a source window and a drain window on the gate dielectric layer to expose at least a partial surface of the first ohmic contact layer and the second ohmic contact layer, and then respectively manufacturing the source and drain at the source window and the drain window.

[0052] Furthermore, the gate foot of the gate is filled in a groove structure formed between the first ohmic contact layer and the second ohmic contact layer, and the gate cap of the gate has an extension portion, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and the gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

[0053] Furthermore, the manufacturing method specifically includes: sequentially growing a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on a substrate to form the epitaxial layer.

[0054] Another aspect of the present invention provides a microwave radio frequency device, comprising the FinFET structure.

[0055] Furthermore, the microwave radio frequency device includes a radio frequency power amplifier.

[0056] Furthermore, the RF power amplifier may be a power amplifier for the sub-6G band, or a power amplifier for the millimeter wave or terahertz band.

[0057] Compared with the prior art, the advantages of the present invention include:

[0058] The present invention provides a new FinFET structure for mobile smart terminal applications and a manufacturing method thereof, which adopts a thin barrier heterojunction epitaxial structure and uses a secondary epitaxial growth ohmic contact layer to prepare a nearly fully gated short channel device, which can simultaneously achieve low knee voltage and enhanced operating mode, thereby meeting the application scenarios of RF front-end PA.

[0059] The present invention provides a new FinFET structure for mobile intelligent terminal applications. There is no access area between the gate-source and the gate-drain. The introduction of the Tri-Gate structure enables the entire short channel to be effectively regulated by the gate, which can eliminate the nonlinear effect induced by RGS resistance degradation on the basis of achieving speed saturation.

[0060] In terms of the realization of the enhanced working mode, the present invention provides a new FinFET structure for mobile smart terminal applications, which adopts a thin barrier plus Fin structure. The thin barrier means a large gate capacitance, which helps to improve the transconductance of the device, thereby ultimately improving the PA power gain. The Fin structure can further increase the depletion effect of the sidewall gate on the 2DEG, and by reducing the gate length, the threshold voltage is increased, thereby realizing the preparation of an enhanced device. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a schematic diagram of the structure of a conventional GaN HEMT in the prior art;

[0062] Figure 2 is a schematic structural diagram of a nearly fully gated FinFET structure provided in Example 1 of the present invention;

[0063] Figure 3 is a schematic structural diagram of a nearly fully gated FinFET structure provided in Example 2 of the present invention;

[0064] Figure 4-Figure 47 It is a schematic diagram of an epitaxial structure obtained corresponding to each step in a manufacturing process of a nearly fully gated FinFET structure provided in Example 1 of the present invention;

[0065] Figure 48 to Figure 82 It is a schematic diagram of the epitaxial structure obtained corresponding to each step in the manufacturing process of a nearly fully gated FinFET structure provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0066] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle, etc. will be further explained in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial growth, photolithography, metal deposition, annealing and other processes and their equipment, reagents used in the embodiments of the present invention are all known to those skilled in the art and are not specifically limited or explained here.

[0067] The present invention provides a new nearly fully gated Tri-Gate FinFET structure, such as Figure 2 or Figure 3 As shown, the nearly fully gated Tri-Gate FinFET structure is based on a heterojunction GaN HEMT epitaxial structure and uses a secondary epitaxial growth ohmic technology to obtain a PA for mobile smart terminal applications. On the one hand, the present invention provides a new nearly fully gated Tri-Gate FinFET structure that can be used to prepare short channel devices, and the entire channel is almost completely effectively controlled by the gate (i.e., the gate length L G ≈ Source-Drain Distance L DS ), since there is no access region between the gate-source and gate-drain, it can effectively suppress R GS The device linearity degradation problem caused by high-field nonlinear behavior is solved, and the device heat dissipation capacity is enhanced; secondly, the Fin structure also increases the sidewall heat dissipation path, reduces the device thermal resistance, and reduces the self-heating effect. On the other hand, due to the use of the Fin structure, the top gate and the side gate have a depletion effect on the channel electrons. The smaller the Fin width, the stronger the depletion effect, and the threshold voltage increases accordingly, which is conducive to the preparation of enhanced devices.

[0068] The FinFET structure and the manufacturing method thereof provided by the present invention are based on a secondary epitaxial source-drain ohmic contact layer, and a Tri-Gate is directly constructed between the source and the drain, thereby obtaining a GaN FinFET structure with a short channel, full gate control, and nearly no access region series resistance, thereby effectively reducing the knee voltage of the device and improving the device linearity.

[0069] The FinFET structure provided by the present invention is a nearly fully gated Tri-Gate FinFET structure, which is not only suitable for enhancement-mode devices based on thin-barrier heterojunctions, but also suitable for conventional thick-barrier heterojunction epitaxial structures and enhancement-mode devices prepared by other schemes, such as p-type layer gate enhancement-mode devices, and of course also suitable for depletion-mode devices.

[0070] The FinFET structure provided by the present invention is not only applicable to Ga-polar GaN FinFET devices, but also applicable to GaN FinFET devices of various polarities, such as N-polar GaN FinFET devices, etc. The FinFET structure provided by the present invention is not limited to the GaN material system, but can also be GaAs, GaO and other material systems.

[0071] The present invention is based on a thin barrier heteroepitaxial structure, and utilizes secondary epitaxial ohmic contact, ICP etching and oxygen plasma bombardment, etc. to prepare a Tri-gate structure between the source and the drain that can regulate the entire channel, thereby realizing a short channel, full gate control, no access area series resistance, and enhanced GaN FinFET structure. The core full channel control Tri-gate in the present invention directly uses the secondary epitaxial ohmic contact as the supporting layer.

[0072] In Example 1, the Fin is first defined using a positive resist, and then the Tri-Gate is defined using a negative resist.

[0073] A FinFET structure such as Figure 2 As shown, the method for manufacturing the FinFET structure includes the following steps:

[0074] 1) Growth of a FinFET epitaxial structure (also referred to as an epitaxial layer, the same below) based on a thin barrier heterojunction, such as Figure 4 , Figure 5 As shown, Figure 4 This is a three-dimensional diagram of the FinFET epitaxial structure. Figure 5 yes Figure 4 Cross-sectional structure diagram at the cross section in .

[0075] Specifically, a FinFET epitaxial structure based on a thin barrier heterojunction can be epitaxially grown by MOCVD or other methods. The FinFET epitaxial structure includes a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a GaN cap layer stacked in sequence on a substrate. The AlGaN barrier layer is specifically AlGaN. 0.2 Ga 0.8 The thickness of the N barrier layer is about 5 nm; the thickness of the GaN cap layer is about 2 nm; the thickness of the AlN insertion layer is about 1 nm; and the thickness of the GaN channel layer is 5 to 200 nm.

[0076] 2) Using a first pattern mask to define a Fin structure (fin-shaped structure, the same below) on the surface of the FinFET epitaxial structure, such as Figure 6-Figure 8 As shown, Figure 6 It is a three-dimensional image after the first pattern mask is formed on the surface of the FinFET epitaxial structure. Figure 7 yes Figure 6 The cross-sectional structure diagram in Figure 8 yes Figure 6Longitudinal section structure diagram.

[0077] Specifically, a plurality of PMMA (PolyMethylMethacrylate) electron beam photoresists spaced along a second direction are arranged on a surface of the GaN cap layer away from the GaN channel layer to form a first graphic mask, each PMMA electron beam photoresist extends along the first direction, the width of each PMMA electron beam photoresist is equal to the width of a Fin structure, and the first direction is perpendicular to the second direction.

[0078] 3) etching the source-drain ohmic contact region of the FinFET epitaxial structure using a first graphic mask, thereby exposing a plurality of second regions on the surface of the GaN channel layer, and retaining the AlGaN barrier layer on the plurality of first regions on the surface of the GaN channel layer, to form a plurality of fin-shaped structures, wherein the fin-shaped structures and the second regions both have a source region, a gate region, and a drain region sequentially distributed along a first direction, and the plurality of the first regions and the plurality of the second regions are alternately distributed along a second direction, such as Figure 9-11 As shown, Fig. 9 This is a three-dimensional image of the source and drain ohmic contact area of ​​the FinFET epitaxial structure after etching. Fig.10 yes Fig. 9 The cross-sectional structure diagram in Fig.11 yes Fig. 9 Longitudinal section structure diagram.

[0079] Specifically, the source-drain ohmic contact region of the FinFET epitaxial structure may be etched by using a chlorine-based ICP (Inductive Coupled Plasma) etching method or the like.

[0080] It should be noted that the source region can also be referred to as the source region, source ohmic contact region, etc., which can be understood as the orthographic projection area formed by the source on the surface of the selected structural layer; the drain region can also be referred to as the drain region, drain ohmic contact region, etc., which can be understood as the orthographic projection area formed by the drain on the surface of the selected structural layer, etc.; the gate region can also be referred to as the gate region, gate ohmic contact region, etc., which can be understood as the orthographic projection area formed by the gate on the surface of the selected structural layer, etc., the same below.

[0081] 4) removing the first pattern mask and exposing the formed multiple fin structures, such as Figure 12-14 As shown, Fig.12 is a three-dimensional diagram of the FinFET epitaxial structure after removing the first pattern mask. Fig.13 yes Fig.12 The cross-sectional structure diagram in Fig.14 yes Fig.12 Longitudinal section structure diagram.

[0082] Specifically, PMMA can be removed using an acetone solution.

[0083] 5) a second graphic mask is arranged on a surface of the FinFET epitaxial structure away from the GaN channel layer, wherein the second graphic mask continuously extends along a second direction and covers the plurality of fin structures and the plurality of gate regions of the second region, such as Figure 15-Figure 20 shown.

[0084] Specifically, HSQ (Hydrogen Silsesquioxane) electron beam photoresist (hereinafter referred to as HSQ glue) is used, such as Figure 15-17 As shown, Fig.15 This is a three-dimensional image of the FinFET epitaxial structure formed with HSQ electron beam photoresist. Fig.16 yes Fig.15 A schematic diagram of the cross-section structure of Fig.17 yes Fig.25 The schematic diagram of the longitudinal section structure is a schematic diagram of the longitudinal section structure of the T-type gate, and the gate foot size of the T-type gate is defined by HSQ electron beam photoresist. Specifically, the gate foot has a gate length LG≈50-250nm in the first direction; the HSQ electron beam photoresist is cured by an annealing process at a temperature of about 400° C., thereby forming a second pattern mask, such as Figure 18-Figure 20 As shown, Fig.18 This is a three-dimensional image of the FinFET epitaxial structure formed with HSQ electron beam photoresist. Fig.19 yes Fig.18 A schematic diagram of the cross-section structure of Fig. 20 yes Fig.18 Schematic diagram of the longitudinal section structure.

[0085] It should be noted that the material of the second pattern mask is not limited to negative photoresist HSQ, and can also be other electron beam negative photoresist. Secondly, the second pattern mask can also be formed by other mask technologies that can achieve secondary epitaxy.

[0086] 6) Secondary epitaxial ohmic contact layer: an ohmic contact layer is grown on a surface of the FinFET epitaxial structure away from the GaN channel layer, wherein the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer, wherein the first ohmic contact layer is stacked on the source regions of the plurality of fin-shaped structures and the plurality of second regions, and the second ohmic contact layer is stacked on the drain regions of the plurality of fin-shaped structures and the plurality of second regions, such as Figure 21-Figure 25 As shown, Fig.21 This is a three-dimensional diagram of the FinFET epitaxial structure with secondary epitaxy to form an ohmic contact layer. Fig. 22 yes Fig.21 A schematic diagram of the structure of a cross section 1, Fig.23 yes Fig.21 A schematic diagram of the structure of the cross section 2, Fig.24yes Fig.21 A schematic diagram of the structure of a longitudinal section 1, Fig.25 yes Fig.21 Schematic diagram of the structure of the longitudinal section 2.

[0087] Specifically, MOCVD (Metal-organic Vapor Deposition) is adopted, with cured HSQ as the first pattern mask, to epitaxially grow an n-type heavily doped layer (e.g. n++GaN) as an ohmic contact layer on the surface of the FinFET epitaxial structure away from the GaN channel layer. The doping concentration and thickness of the layer need to ensure good ohmic contact with the channel electrons. The ohmic contact layer can also be called an n-type layer.

[0088] 7) Remove the second graphic mask, Figure 26-Figure 30 As shown, Fig.26 is a three-dimensional diagram of the FinFET epitaxial structure after removing the second pattern mask. Fig. 27 yes Fig.26 A schematic diagram of the structure of a cross section 1, Fig.28 yes Fig.26 A schematic diagram of the structure of the cross section 2, Fig.29 yes Fig.26 A schematic diagram of the structure of a longitudinal section 1, Fig.30 yes Fig.26 Schematic diagram of the structure of the longitudinal section 2.

[0089] Specifically, BOE solution (or HF solution) may be used to remove HSQ.

[0090] 8) Isolate the active area of ​​the FinFET epitaxial structure, such as Figure 31-Figure 32 As shown, Fig.31 is a schematic diagram of the structure of the cross section 1 after the active area isolation is performed. Fig.32 It is a schematic structural diagram of the cross section 2 after active area isolation.

[0091] Specifically, the FinFET epitaxial structure is isolated by N ion implantation, the energy of the ion implantation is 150-400 KeV, and the dose of the implanted ions is 10 12 ~10 14 / cm 2 The injection depth is about 50 to 250 nm beyond the buffer layer.

[0092] It should be noted that the ions injected in the active area isolation are not limited to N ions, but can also be F ions and other ions that can achieve high-resistance isolation. The isolation process is not limited to ion implantation, and of course it can also be achieved by etching away the epitaxial structure outside the active area.

[0093] 9) forming a gate dielectric layer on the surface of the FinFET epitaxial structure away from the GaN channel layer, such as Figure 33-Figure 37 As shown, Fig.33 It is a three-dimensional diagram of the FinFET epitaxial structure forming the gate dielectric layer. Fig.34 yes Fig.33 A schematic diagram of the structure of a cross section 1, Fig.35 yes Fig.33 A schematic diagram of the structure of the cross section 2, Fig.36 yes Fig.33 A schematic diagram of the structure of a longitudinal section 1, Fig.37 yes Fig.33 Schematic diagram of the structure of the longitudinal section 2.

[0094] Specifically, ALD (Atom Layer Deposition) technology is used (of course other processes can also be used) to deposit Al2O3 on the surface of the FinFET epitaxial structure away from the GaN channel layer. The Al2O3 at least covers the top surfaces and side walls of the gate regions of the multiple fin-shaped structures and the gate regions of the multiple second regions. The thickness of Al2O3 is 1 to 5 nm.

[0095] 10) forming a Tri-Gate on the gate dielectric layer, so that the gate at least continuously covers the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures and the gate regions of the plurality of second regions, such as Figure 38-Figure 42 As shown, Fig.38 This is a three-dimensional diagram of the epitaxial structure of the FinFET that forms the Tri-Gate. Fig.39 yes Fig.38 A schematic diagram of the structure of a cross section 1, Fig.40 yes Fig.38 A schematic diagram of the structure of the cross section 2, Fig.41 yes Fig.38 A schematic diagram of the structure of a longitudinal section 1, Fig.42 yes Fig.38 Schematic diagram of the structure of the longitudinal section 2.

[0096] Specifically, the secondary epitaxial ohmic contact layer is used as the Tri-Gate support layer, and the Ni / Au Tri-Gate is prepared by photolithography and electron beam evaporation technology (of course, it can also be Ni / Pt / Au, Ni / Pt, p-GaN or other p-type materials that can form a Schottky contact with the barrier layer). The thickness of the Ni / Au Tri-Gate is 50nm / 250nm.

[0097] 11) forming a source electrode and a drain electrode, and making the source electrode and the drain electrode form ohmic contacts with the first ohmic contact layer and the second ohmic contact layer respectively, such as Figure 43-Figure 47 As shown, Fig.43This is a three-dimensional diagram of the FinFET epitaxial structure that forms the source and drain. Fig.44 yes Fig.43 A schematic diagram of the structure of a cross section 1, Fig.45 yes Fig.43 A schematic diagram of the structure of the cross section 2, Fig.46 yes Fig.43 A schematic diagram of the structure of a longitudinal section 1, Fig.47 yes Fig.43 Schematic diagram of the structure of the longitudinal section 2.

[0098] Specifically, after the source and drain ohmic contact window opening process, the electron beam evaporation technology is used to prepare the Ti / Al / Ni / Au ohmic contact electrode, and the thickness of the Ti / Al / Ni / Au ohmic contact electrode is 50nm / 250nm.

[0099] It should be noted that the source and drain can also be other metal systems that form ohmic contact with high-concentration n+ / p+ type materials. The source can also be called a source electrode or a source ohmic contact electrode, and the drain can also be called a drain electrode or a drain ohmic contact electrode.

[0100] Example 2: First use negative resist to define Tri-Gate, and then use positive resist to define Fin.

[0101] A FinFET structure, such as Figure 3 As shown, the method for manufacturing the FinFET structure includes the following steps:

[0102] 1) Growth of a FinFET epitaxial structure (also referred to as an epitaxial layer, the same below) based on a thin barrier heterojunction, such as Figure 4-Figure 5 As shown, the specific method is the same as step 1) of Example 1.

[0103] 2) forming a third pattern mask on a surface of the FinFET epitaxial structure away from the GaN channel layer (i.e., the surface of the GaN cap layer), such as Figure 48-Figure 51 shown.

[0104] Specifically, HSQ (Hydrogen Silsesquioxane) electron beam photoresist is used to define the gate foot size of the device Tri-Gate on the surface of the FinFET epitaxial structure away from the GaN channel layer (i.e., the surface of the GaN cap layer), that is, the gate length LG≈50-250nm, such as Figure 48-Figure 49 As shown, Fig.48 This is a three-dimensional image of the FinFET epitaxial structure with HSQ glue formed on the surface. Fig.49 yes Fig.48 HSQ is cured by annealing process at a temperature of about 400° C., thereby forming a third pattern mask, such as Figure 50-Figure 51 As shown, Fig.50 This is a three-dimensional image of the FinFET epitaxial structure after the HSQ glue is cured. Fig.51 yes Fig.50 Schematic diagram of the cross-section structure.

[0105] 3) etching the source and drain ohmic contact regions to expose the source and drain regions on the surface of the channel layer, while retaining the barrier layer on the gate region on the surface of the channel layer to form a ridge structure, such as Figure 52-Figure 53 As shown, Fig.52 This is a three-dimensional image of the FinFET epitaxial structure after etching the source and drain ohmic contact areas. Fig.53 yes Fig.52 Schematic diagram of the cross-section structure.

[0106] Specifically, a chlorine-based ICP (Inductive Coupled Plasma) etching technique can be used, with a solidified HSQ glue as a mask (i.e., a third pattern mask), to etch the source and drain ohmic contact regions from the surface of the FinFET epitaxial structure away from the GaN channel layer until the surface or the interior of the GaN channel layer is reached, so that the source region and the drain region on the surface of the GaN channel layer are exposed, and the barrier layer on the gate region on the surface of the GaN channel layer is retained to form a ridge structure, and the source region, the gate region, and the drain region on the surface of the GaN channel layer are distributed in sequence along the first direction.

[0107] 4) Secondary epitaxial ohmic contact layer: grow the first ohmic contact layer and the second ohmic contact layer on the source region and the drain region on the surface of the GaN channel layer respectively, such as Figure 54-Figure 55 As shown, Fig.54 This is a three-dimensional diagram of the FinFET epitaxial structure after the secondary epitaxial ohmic contact layer. Fig.55 yes Fig.54 Schematic diagram of the cross-section structure.

[0108] Specifically, an MOCVD (Metal-organic Vapor Deposition) process is adopted, and the cured HSQ is used as a mask (i.e., the third pattern mask) to epitaxially grow n-type heavily doped n++GaN on the source region and the drain region on the surface of the GaN channel layer, and the n-type heavily doped n++GaN is used as the first ohmic contact layer and the second ohmic contact layer. The doping concentration and thickness of the n-type heavily doped n++GaN ensure good ohmic contact with the channel electrons.

[0109] 5) Remove HSQ, such as Figure 56-Figure 57 As shown, Fig.56 This is a three-dimensional diagram of the FinFET epitaxial structure after removing HSQ. Fig.57 yes Fig.56 Schematic diagram of the cross-section structure.

[0110] Specifically, BOE solution (or HF solution) may be used to remove HSQ.

[0111] 6) Isolate the active area of ​​the FinFET epitaxial structure, such as Fig.58 As shown, Fig.58 It is a structural schematic diagram of the cross section of the FinFET epitaxial structure after active area isolation.

[0112] Specifically, the FinFET epitaxial structure can be isolated by N ion implantation, the energy of the ion implantation is 150-400 KeV, and the dose of the implanted ions is 10 12 ~10 14 / cm 2 The injection depth is about 50 to 250 nm beyond the buffer layer.

[0113] 7) Using a fourth pattern mask to define a Fin structure (fin-shaped structure, the same below) on the surface of the FinFET epitaxial structure, such as Figure 59-Figure 62 As shown, Fig.59 is a three-dimensional diagram of a FinFET epitaxial structure forming a fourth pattern mask, Fig.60 yes Fig.59 A schematic diagram of the structure of a cross section 1, Fig.61 yes Fig.59 A schematic diagram of the structure of the cross section 2, Fig.62 yes Fig.59 Schematic diagram of the longitudinal section structure.

[0114] Specifically, a patterned PMMA (PolyMethylMethacrylate) electron beam photoresist is disposed on the ridge structure, the first ohmic contact layer and the second ohmic contact layer as a fourth pattern mask, and in the second direction, the width of each PMMA electron beam photoresist is equal to the width of a Fin structure.

[0115] 8) Using the fourth pattern mask, the FinFET epitaxial structure is etched to form a Fin groove, such as Figure 63-Figure 66 As shown, Fig.63 is a three-dimensional diagram of a FinFET epitaxial structure forming a fourth pattern mask, Fig.64 yes Fig.63 A schematic diagram of the structure of a cross section 1, Fig.65 yes Fig.63 A schematic diagram of the structure of the cross section 2, Fig.66 yes Fig.63 Schematic diagram of the longitudinal section structure.

[0116] Specifically, a chlorine-based ICP (Inductive Coupled Plasma) etching process is adopted, and a patterned PMMA glue is used as a fourth pattern mask to etch a partial area (i.e., the Fin groove area) of the surface of the ridge structure exposed from the fourth pattern mask, and the etching rate is controlled at 1 to 20 nm / min until the surface or the interior of the GaN channel layer is reached, so that the barrier layer on multiple selected areas on the surface of the GaN channel layer is retained to form multiple fin structures, and the multiple selected areas are spaced apart along the second direction.

[0117] 9) Remove PMMA glue, such as Figure 67-Figure 70 As shown, Fig.67 This is a three-dimensional image of the FinFET epitaxial structure after removing the PMMA glue. Fig.68 yes Fig.67 A schematic diagram of the structure of a cross section 1, Fig.69 yes Fig.67 A schematic diagram of the structure of the cross section 2, Fig.70 yes Fig.67 Schematic diagram of the longitudinal section structure.

[0118] Specifically, acetone solution may be used to remove PMMA.

[0119] 10) forming a continuous gate dielectric layer at least on the top surface and sidewall of the gate region of the plurality of fin-shaped structures, such as Figure 71-Figure 74 As shown, Fig.71 is a three-dimensional diagram of a FinFET epitaxial structure with a gate dielectric layer formed therein. Fig.72 yes Fig.71 A schematic diagram of the structure of a cross section 1, Fig.73 yes Fig.71 A schematic diagram of the structure of the cross section 2, Fig.74 yes Fig.71 Schematic diagram of the longitudinal section structure.

[0120] Specifically, a continuous Al2O3 layer may be deposited on at least the top surface and sidewalls of the gate regions of the plurality of fin-shaped structures by using ALD (Atom Layer Deposition) or other processes to form a gate dielectric, and the thickness of the Al2O3 layer is 1-5 nm.

[0121] 11) Prepare Tri-Gate, such as Figure 75-Figure 78 As shown, Fig.75 This is a three-dimensional diagram of the epitaxial structure of the FinFET that forms the Tri-Gate. Fig.76 yes Fig.75 A schematic diagram of the structure of a cross section 1, Fig.77 yes Fig.75 A schematic diagram of the structure of the cross section 2, Fig.78 yes Fig.75 Schematic diagram of the longitudinal section structure.

[0122] Specifically, the secondary epitaxial ohmic contact layer is used as the Tri-Gate support layer, and a Ni / Au Tri-Gate gate is formed on the gate dielectric layer by using a photolithography process and an electron beam evaporation process. The Ni / Au Tri-Gate gate at least continuously covers the top surface and side wall of the gate region of multiple fin-shaped structures, and the thickness of Ni / Au is 50nm / 250nm.

[0123] 12) Prepare source and drain ohmic contact electrodes, such as Figure 79-Figure 82 As shown, Fig.79 This is a three-dimensional diagram of the FinFET epitaxial structure that forms the source and drain ohmic contact electrodes. Fig.80 yes Fig.79 A schematic diagram of the structure of a cross section 1, Fig.81 yes Fig.79 A schematic diagram of the structure of the cross section 2, Fig.82 yes Fig.79 Schematic diagram of the longitudinal section structure.

[0124] After the source and drain ohmic contact window opening process, electron beam evaporation technology is used to prepare Ti / Al / Ni / Au ohmic contact electrodes (i.e., source and drain), so that the ohmic contact electrodes form ohmic contacts with the first ohmic contact layer and the second ohmic contact layer respectively, and the thickness of the Ti / Al / Ni / Au ohmic contact electrodes is 50nm / 250nm.

[0125] The present invention certainly includes not only the method in the embodiment, but also any preparation method that can realize the whole structure and partial structure of the present invention. The cross section in the embodiment of the present invention is formed by cutting along the first direction, and the longitudinal section is formed by cutting along the second direction.

[0126] It should be noted that the FinFET structure and manufacturing method provided by the present invention are also fully applicable to depletion-mode devices. Based on adjustments to the heterojunction in the active area of ​​the epitaxial structure, the corresponding implementation scheme is exactly the same as that of Example 1 and Example 2.

[0127] The present invention proposes a new FinFET structure and a manufacturing method thereof for mobile intelligent terminal applications. A thin barrier heterojunction epitaxial structure is adopted, and an ohmic contact layer is grown by secondary epitaxial growth to prepare a nearly fully gated short channel device, which can simultaneously achieve low knee voltage and enhanced working mode, thereby meeting the RF front-end PA application scenario. Compared with conventional GaN RFHEMT, the device prepared by the present invention does not have an access area between the gate-source and the gate-drain. The introduction of the Tri-Gate structure enables the entire short channel to be effectively regulated by the gate, and the nonlinear effect induced by the degradation of RGS resistance can be eliminated on the basis of achieving speed saturation. In terms of the realization of the enhanced working mode, since the epitaxial structure adopts a thin barrier plus Fin structure, the thin barrier means a large gate capacitance, which helps to improve the transconductance of the device, thereby ultimately improving the PA power gain. The Fin structure can further increase the depletion effect of the sidewall gate on the 2DEG, and by reducing the gate length, the threshold voltage is increased, thereby realizing the preparation of an enhanced device.

[0128] It should be noted that the FinFET structure provided by the present invention is completely applicable to depletion-mode and enhancement-mode devices. When a heterojunction epitaxial structure based on a thin barrier and a Fin structure are used, the preparation of an enhancement-mode device can be realized, and the material structure based on the thin barrier enables the device to have a larger transconductance, and the suppression of the access region resistance is conducive to improving the device linearity, thereby improving the device PA power gain.

[0129] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A FinFET structure, characterized in that: include: A heterojunction, comprising a channel layer and a barrier layer, wherein a surface of the channel layer has a source region, a gate region and a drain region sequentially distributed along a first direction, the gate region comprises a plurality of selected regions spaced apart and distributed along a second direction, the barrier layer is stacked on the plurality of selected regions to form a plurality of fin-shaped structures, and the first direction is perpendicular to the second direction; A first ohmic contact layer, which is at least stacked on the source region on the surface of the channel layer; A second ohmic contact layer, which is at least stacked on the drain region on the surface of the channel layer; A gate extending along the second direction and continuously stacked on at least the top surfaces and side walls of the plurality of fin-shaped structures; a source electrode, which is disposed on the first ohmic contact layer and forms an ohmic contact with the first ohmic contact layer; The drain electrode is disposed on the second ohmic contact layer and forms an ohmic contact with the second ohmic contact layer.

2. The FinFET structure according to claim 1, characterized in that: The surface of the channel layer has a plurality of first regions and a plurality of second regions alternately distributed along a second direction, and the barrier layer is stacked on the plurality of the first regions to form a plurality of the fin-shaped structures; the fin-shaped structures and the second regions both have a source region, a gate region and a drain region; Furthermore, in the first direction, the source region, the gate region, and the drain region of the fin-shaped structure and the second region are respectively arranged corresponding to the source region, the gate region, and the drain region on the surface of the channel layer; The gate continuously covers multiple gate regions of the second areas and top surfaces and side walls of multiple gate regions of the fin-like structures along the second direction; a first ohmic contact layer and a source electrode are sequentially stacked on at least the source region of the fin-like structure, and a second ohmic contact layer and a drain electrode are sequentially stacked on at least the drain region of the fin-like structure.

3. The FinFET structure according to claim 2, characterized in that: A first ohmic contact layer is stacked on the source region of the second region, and the source electrode extends continuously along the second direction and is stacked on the multiple fin-like structures and the multiple source regions of the second region; and / or a second ohmic contact layer is stacked on the drain region of the second region, and the drain electrode extends continuously along the second direction and is stacked on the multiple fin-like structures and the multiple drain regions of the second region.

4. The FinFET structure according to claim 2, wherein: The FinFET structure includes a groove structure formed between the first ohmic contact layer and the second ohmic contact layer; the groove bottom surface of the groove structure is distributed on the gate region of the second region and the top surface and side wall of the gate region of the fin structure, and extends continuously along the second direction; the gate foot of the gate is filled in the groove structure, and the gate cap of the gate has an extension part, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and a gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

5. The FinFET structure according to claim 1, wherein: A first ohmic contact layer and a second ohmic contact layer are directly stacked on the source region and the drain region on the surface of the channel layer, respectively, and the source, the first ohmic contact layer, the drain and the second ohmic contact layer all extend continuously along the second direction; the gate region on the surface of the channel layer also includes a third region distributed between adjacent selected regions, and the gate extends along the second direction and continuously covers the third region and the top surfaces and side walls of the plurality of fin-like structures.

6. The FinFET structure according to claim 5, characterized in that: The FinFET structure includes a groove structure formed between the first ohmic contact layer and the second ohmic contact layer; the groove bottom surface of the groove structure is distributed in the third area of ​​the channel layer surface and on the top surface and side wall of the fin structure, and extends continuously along the second direction; the gate foot of the gate is filled in the groove structure, and the gate cap of the gate has an extension part, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and a gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

7. The FinFET structure according to any one of claims 1 to 6, characterized in that: The sidewalls of the fin structure are electrically connected to the sidewalls of the first ohmic contact layer and the second ohmic contact layer respectively.

8. The FinFET structure according to any one of claims 1 to 6, characterized in that: The cross section of the gate in the first direction is T-shaped; and / or the size of the gate foot of the gate in the first direction is 50-250 nm.

9. The FinFET structure according to any one of claims 1 to 6, characterized in that: The FinFET structure includes at least three fin structures.

10. The FinFET structure according to any one of claims 1 to 6, characterized in that: The fin structure further includes an insertion layer and / or a cap layer, wherein the insertion layer is distributed between the barrier layer and the channel layer, and the cap layer is stacked on the barrier layer.

11. The FinFET structure according to any one of claims 1 to 6, characterized in that: A gate dielectric layer is distributed between the gate and the heterojunction, and a material of the gate dielectric layer includes a combination of one or more of Al2O3, SiO2, HfO2, AlON, and silicon nitride.

12. The FinFET structure according to any one of claims 1 to 6, characterized in that: The FinFET structure also includes a substrate, on which a buffer layer, a channel layer and a barrier layer are stacked in sequence, and the material of the substrate includes a combination of one or more of silicon, sapphire, silicon carbide, gallium nitride, and aluminum nitride.

13. The FinFET structure according to any one of claims 1 to 6, characterized in that: The FinFET structure includes a GaN-based FinFET structure, a GaAs-based FinFET structure or a GaO-based FinFET structure; And / or, the heterojunction includes a single heterojunction or a multiple heterojunction; And / or, the heterojunction includes a combination of one or more of a single-channel or multi-channel AlGaN / GaN heterojunction, an AlN / GaN heterojunction, an AlInN / GaN heterojunction, an AlInGaN / GaN heterojunction, an AlGaN / GaN / AlGaN double heterojunction, and an AlGaN / GaN / InGaN double heterojunction; And / or, the material of the first ohmic contact layer and the second ohmic contact layer includes one or more combinations of n++GaN, n++InGaN, and n++InN.

14. A method for manufacturing a FinFET structure, characterized in that: include: Providing an epitaxial layer, wherein the epitaxial layer includes a channel layer and a barrier layer stacked on the channel layer, wherein the channel layer and the barrier layer cooperate to form a heterojunction; A first graphic mask is arranged on a surface of the epitaxial layer away from the channel layer, and the epitaxial layer is etched using the first graphic mask until the surface or the inside of the channel layer is reached, so that a plurality of second regions on the surface of the channel layer are exposed, and the barrier layer on the plurality of first regions on the surface of the channel layer is retained, so as to form a plurality of fin-shaped structures, wherein the fin-shaped structures and the second regions both have a source region, a gate region and a drain region sequentially distributed along a first direction, and the plurality of the first regions and the plurality of the second regions are alternately distributed along a second direction, and the second direction is perpendicular to the first direction; Removing the first graphic mask, and then setting a second graphic mask on a surface of the epitaxial layer away from the channel layer, wherein the second graphic mask continuously extends along a second direction and covers the plurality of fin structures and the plurality of gate regions of the second region; Growing an ohmic contact layer on the surface of the channel layer, the ohmic contact layer comprising a first ohmic contact layer and a second ohmic contact layer, the first ohmic contact layer being stacked on the plurality of fin-shaped structures and the source regions of the plurality of second regions, the second ohmic contact layer being stacked on the plurality of fin-shaped structures and the drain regions of the plurality of second regions, then removing the second graphic mask, and performing active region isolation on the obtained device structure; forming a continuous gate dielectric layer at least on the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures and the gate regions of the plurality of second regions, and then manufacturing a gate on the gate dielectric layer, and making the gate continuously cover at least the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures and the gate regions of the plurality of second regions; A source electrode and a drain electrode are respectively formed on the first ohmic contact layer and the second ohmic contact layer, and the source electrode and the drain electrode are respectively in ohmic contact with the first ohmic contact layer and the second ohmic contact layer.

15. The manufacturing method according to claim 14, characterized in that: Specifically include: The gate dielectric layer is continuously covered on at least the surfaces of the ohmic contact layer, the fin-shaped structure and the channel layer, and then a source window and a drain window are respectively processed on the gate dielectric layer to expose at least a portion of the surfaces of the first ohmic contact layer and the second ohmic contact layer, and then the source and drain are respectively made at the source window and the drain window.

16. The method according to any one of claims 14 to 15, characterized in that: The source electrode extends continuously along the second direction and is stacked on the source regions of the plurality of fin-shaped structures and the plurality of second regions; and the drain electrode extends continuously along the second direction and is stacked on the drain regions of the plurality of fin-shaped structures and the plurality of second regions.

17. The method according to any one of claims 14 to 15, characterized in that: The gate foot of the gate is filled in a groove structure formed between the first ohmic contact layer and the second ohmic contact layer, and the gate cap of the gate has an extension portion, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and the gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

18. The manufacturing method according to claim 14, characterized in that: Specifically include: A buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer are sequentially grown on a substrate to form the epitaxial layer.

19. A method for manufacturing a FinFET structure, characterized in that: include: Providing an epitaxial layer, wherein the epitaxial layer includes a channel layer and a barrier layer stacked on the channel layer, wherein the channel layer and the barrier layer cooperate to form a heterojunction; A third graphic mask is provided on a surface of the epitaxial layer away from the channel layer, and the epitaxial layer is etched using the third graphic mask until the surface or the inside of the channel layer is reached, so that the source region and the drain region on the surface of the channel layer are exposed, and the barrier layer on the gate region on the surface of the channel layer is retained to form a ridge structure, and the source region, the gate region and the drain region on the surface of the channel layer are distributed in sequence along the first direction; Growing a first ohmic contact layer and a second ohmic contact layer on the source region and the drain region on the surface of the channel layer respectively, and then removing the third pattern mask; A fourth pattern mask is arranged on the ridge structure, the first ohmic contact layer and the second ohmic contact layer, and then a partial area of ​​the surface of the ridge structure exposed from the fourth pattern mask is etched until reaching the surface or the inside of the channel layer, so that the barrier layer on multiple selected areas on the surface of the channel layer is retained to form multiple fin structures, and the multiple selected areas are spaced apart and distributed along a second direction, and the second direction is perpendicular to the first direction; The fourth pattern mask is removed, and then a continuous gate dielectric layer is formed at least on the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures, and then a gate is formed on the gate dielectric layer, and the gate is made to continuously cover at least the top surfaces and side walls of the gate regions of the plurality of fin-shaped structures; A source electrode and a drain electrode are respectively formed on the first ohmic contact layer and the second ohmic contact layer, and the source electrode and the drain electrode are respectively in ohmic contact with the first ohmic contact layer and the second ohmic contact layer.

20. The manufacturing method according to claim 19, characterized in that: Specifically include: The gate dielectric layer is continuously covered on at least the surfaces of the first ohmic contact layer, the second ohmic contact layer, the fin-shaped structure and the channel layer, and then a source window and a drain window are respectively processed on the gate dielectric layer to expose at least a portion of the surfaces of the first ohmic contact layer and the second ohmic contact layer, and then the source and drain are respectively made at the source window and the drain window.

21. The method according to any one of claims 19-20, characterized in that: The gate foot of the gate is filled in a groove structure formed between the first ohmic contact layer and the second ohmic contact layer, and the gate cap of the gate has an extension portion, which is distributed outside the groove structure and extends along the first direction to be respectively stacked on the first ohmic contact layer and the second ohmic contact layer, and the gate dielectric layer is distributed between the gate and the first ohmic contact layer and the second ohmic contact layer.

22. The manufacturing method according to claim 19, characterized in that: Specifically include: A buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer are sequentially grown on a substrate to form the epitaxial layer.

23. A microwave radio frequency device, characterized in that: The FinFET structure comprises the FinFET structure as claimed in any one of claims 1 to 14.

24. The microwave radio frequency device according to claim 23, characterized in that: The microwave radio frequency device includes a radio frequency power amplifier.

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