Nitride semiconductor transistor structure

Abstract

The invention discloses a nitride semiconductor transistor structure, an epitaxial structure of which comprises a conductive substrate, a nucleating layer on the substrate, a buffer layer arranged above the nucleating layer, a p-type nitride buried layer arranged above the buffer layer, a channel layer arranged above the p-type nitride buried layer, and a barrier layer arranged above the channel layer, the epitaxial structure surface fabrication transistor structure comprises a source electrode, a grid electrode and a drain electrode. A pn junction space charge region is formed at the interface of a p-type nitride buried layer and a channel layer, so that electrons generated by avalanche ionization at the edge of a grid electrode are prevented from entering a carbon-doped buffer layer through the channel layer under the condition that the device is in an off state and high drain electrode voltage is applied. The vertical withstand voltage of the epitaxial layer is improved by arranging a high-withstand-voltage buffer layer structure below the p-type buried layer.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a nitride semiconductor transistor structure. Background Art

[0002] Compared with traditional silicon material devices, nitride semiconductor power devices have high breakdown electric field, more energy saving, more stable physical and chemical properties, can work at higher ambient temperature, have higher switching speed and other advantages, and can be applied to various consumer electronic products, electric vehicles, solar wind energy and other new energy generation, electric vehicles, robots and intelligent manufacturing industry, large data processing centers and other fields. Although gallium nitride devices have excellent performance and broad application prospects, large-scale commercialization still needs to overcome some technical difficulties, one of which is the current collapse effect. The material growth of gallium nitride power devices generally adopts the heteroepitaxial technology route, that is, growing nitride materials on large-sized silicon substrates. Compared with other substrate materials, using large-sized and cheap silicon materials as substrates can achieve the best cost performance. In order to improve the withstand voltage of silicon-based nitride epitaxial materials, carbon doping is generally used. Carbon elements are doped into the buffer layer below the channel layer that conducts current, and the deep energy level recombination center formed by carbon elements in gallium nitride materials is used to reduce the carrier concentration of the material, thereby obtaining a nitride buffer layer with high resistance and high withstand voltage. However, high carbon doping concentration will lead to the so-called current collapse effect. When the device is turned off, a high voltage is applied to the drain. The electrons generated by avalanche ionization at the gate edge pass through the channel layer into the carbon-doped buffer layer, and are captured by the deep energy levels introduced by carbon doping and become negatively charged. The formed electric field hinders the flow of electrons in the channel layer, causing the resistance of the device to gradually increase when it is working, affecting the reliability of the device.

[0003] S. Karmalkar et al. mentioned in the non-patent document “RESURF AlGaN / GaN HFET for High Voltage Power Switching”, IEEE Electron Device Letters, Vol. 22, No. 8, p. 373375 (2001) and the patent document CN102820325B that a p-type buffer layer is used in the GaN high electron mobility transistor structure to improve the horizontal electric field distribution of the channel layer when the device is turned off, so as to improve the withstand voltage of the device. However, the above scheme does not take into account the optimization of the dynamic characteristics of the device, nor does it fully consider the withstand voltage of the device in the vertical direction, and does not design a high withstand voltage buffer layer other than the p-type buffer layer. In both designs, the p-type buffer layer bears the vertical withstand voltage, so the doping concentration of the p-type buffer layer needs to be limited to an extremely low level (~10 16 / cm 3), resulting in extremely limited electric field strength and barrier height of the pn junction formed at the interface between the channel layer and the p-type buffer layer, affecting its ability to restrict channel electrons from entering the buffer layer. Summary of the invention

[0004] In response to the problems in the background technology, the present invention provides a nitride semiconductor transistor structure, whose epitaxial structure includes a substrate, a nucleation layer on the substrate, a high-voltage buffer layer is arranged above the nucleation layer, a p-type nitride buried layer is arranged above the buffer layer, and also includes a channel layer above the p-type nitride buried layer, a barrier layer above the channel layer, and a transistor structure manufactured on the surface of the epitaxial structure includes a source, a gate, and a drain.

[0005] By forming a pn junction space charge region at the interface between the p-type nitride buried layer and the channel layer, the electrons generated by avalanche ionization at the gate edge are prevented from entering the carbon-doped buffer layer through the channel layer when the device is turned off and a high drain voltage is applied. A high-voltage buffer layer structure is set below the p-type buried layer, generally using a high Al component gradient AlGaN, or AlGaN / AlN, GaN / AlN or GaN / AlGaN superlattice structure, and high carbon doping is used to introduce deep energy levels to improve the vertical voltage resistance of the epitaxial layer. Therefore, the doping concentration of the p-type buried layer is not limited by the voltage resistance requirements, and a higher doping concentration can be set.

[0006] As an optional solution of the present invention, the substrate is selected from: a conductive silicon carbide substrate, a conductive gallium nitride substrate, a conductive silicon substrate, and a composite substrate comprising any of the above substrates.

[0007] As an optional solution of the present invention, the substrate is a non-conductive substrate, and the back side of the non-conductive substrate is etched to expose the epitaxial layer.

[0008] As an optional solution of the present invention, the substrate is a non-conductive substrate, the back side of the non-conductive substrate is etched to expose the epitaxial layer, and a conductive material is deposited in the exposed epitaxial layer region.

[0009] As an optional solution of the present invention, the high voltage buffer layer adopts a multilayer Al composition gradient AlGaN structure, or adopts one of the AlGaN / AlN, GaN / AlN, GaN / AlGaN superlattice structures, or a combination of the above structures, and is doped with carbon elements.

[0010] As a further preferred solution of the present invention, the buffer layer is doped with carbon in whole or in part, and the maximum carbon concentration of the doped part is not less than 1×10 17 / cm 3 .

[0011] As a further preferred solution of the present invention, the p-type nitride layer is an alloy of p-type AlInGaN in any proportion, or a multilayer composite structure of alloy layers of the above p-type nitride in different proportions.

[0012] As a further preferred solution of the present invention, the p-type nitride layer is a continuous epitaxial thin film, or a discontinuous p-type nitride layer formed by etching after the entire p-type nitride layer is grown.

[0013] As an optional solution of the present invention, a back electrode is provided on the back of the conductive substrate, the back electrode forms an ohmic contact with the substrate, and the back electrode is electrically connected to the source or gate to maintain the same potential. This reduces the electric field strength at the edge of the gate and reduces the generation of ionized electrons. This transistor structure can effectively reduce the current collapse effect.

[0014] As an optional solution of the present invention, the transistor structure includes: an insulating dielectric layer deposited above the barrier layer, and a depletion-type transistor device formed by manufacturing a gate above the insulating dielectric layer.

[0015] As an optional solution of the present invention, the transistor structure includes: a p-type nitride layer deposited above the barrier layer, and an ohmic contact or Schottky contact gate made above the insulating dielectric layer to form an enhancement mode transistor device.

[0016] As an optional solution of the present invention, the transistor structure is prepared by the following steps: etching away part or all of the barrier layer corresponding to the gate area, depositing an insulating dielectric layer, and then making the gate to form an enhancement transistor device with a recessed gate structure.

[0017] Compared with the prior art, the present invention provides a nitride semiconductor transistor structure, which has the following beneficial effects:

[0018] The present invention forms a pn junction space charge region at the interface between the p-type nitride buried layer and the channel layer, thereby preventing the electrons generated by avalanche ionization at the gate edge from entering the carbon-doped buffer layer through the channel layer when the device is in the off state and a high drain voltage is applied. A high-voltage buffer layer structure is provided below the p-type buried layer, generally using a high Al component gradient AlGaN, or an AlGaN / AlN superlattice structure, and high carbon doping is used to introduce a deep energy level to improve the vertical voltage resistance of the buffer layer. Therefore, the doping concentration of the p-type buried layer is not limited by the voltage resistance requirement, and a higher doping concentration can be set. At the same time, a back electrode is made on the back of the conductive substrate to form an ohmic contact with the substrate, and is electrically connected to the source or the gate to maintain the same potential, thereby reducing the electric field strength at the gate edge and reducing the generation of ionized electrons. The transistor structure can effectively reduce the current collapse effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the transistor structure of Example 1 of the present invention.

[0020] Figure 2a to Figure 2d A flow chart for transistor production of Example 1.

[0021] Figure 3 Schematic diagram of the transistor structure of embodiment 2 of the present invention.

[0022] Figures 4a to 4d A flow chart for transistor production of Example 2.

[0023] Figure 5 Schematic diagram of the transistor structure of embodiment 3 of the present invention.

[0024] Figure 6 Schematic diagram of the transistor structure of embodiment 4 of the present invention.

[0025] Figure 7a to Figure 7h A flow chart for transistor production of Example 4.

[0026] Wherein: 10-conductive substrate; 11-nucleation layer; 12-buffer layer; 13-p-type nitride layer; 14-channel layer; 15-barrier layer; 16-in-situ SiN layer; 171-source; 172-gate electrode; 173-drain; 171'-back electrode; 20-conductive substrate; 21-nucleation layer; 22-buffer layer; 23-p-type nitride layer; 24-channel layer; 25-barrier layer; 26-p-type GaN cap layer; 271-source; 272-gate electrode; 273-drain; 271'-back electrode; 30-conductive substrate; 31-nucleation layer; 32-buffer layer; 33-p-type nitride layer; 34-channel layer; 35-barrier layer; 36-gate dielectric layer; 371-source; 372-gate electrode; 373-drain; 372'-back electrode. DETAILED DESCRIPTION

[0027] The present disclosure will now be described more fully below with reference to the accompanying drawings, however, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments herein will make the present disclosure more detailed and complete, and fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals throughout the text represent the same objects.

[0028] Example 1

[0029] In the first exemplary embodiment, referring to Figure 1The epitaxial growth of this embodiment is prepared by metal organic chemical vapor deposition (MOCVD) method. A nitride semiconductor transistor structure provided includes: a conductive substrate 10, the conductive substrate 10 includes a silicon carbide substrate, a gallium nitride substrate, or a composite substrate formed by the above substrate and other conductive materials.

[0030] The nucleation layer 11 on the substrate 10 is an AlN layer with a thickness of 100 nm.

[0031] The buffer layer 12 on the nucleation layer 11 includes: AlN / AlGaN / superlattice structure grown from bottom to top, wherein AlN is 100nm, AlGaN can be a single layer or a multilayer with different components, and in this embodiment, it is a 100nm AlGaN single layer structure with an Al component of 50%. The superlattice structure can be AlN / GaN, AlN / AlGaN, AlGaN / GaN superlattice structure, or a combination of the above structures. In this embodiment, an AlN / GaN superlattice structure is used, and each period includes AlN 4nm, GaN 20nm, a total thickness of about 3 microns, and a carbon doping concentration of about 1×10 19 / cm 3 .

[0032] A p-type nitride layer 13 is grown on the buffer layer. In this embodiment, 100 nm p-type GaN is used, and the Mg doping concentration is about 2×10 19 / cm 3 .

[0033] The channel layer 14 on the p-type nitride layer 13 is a 300nm GaN layer with unintentional doping, and the background electron concentration is about 4×10 16 / cm 3 However, the embodiments of the present disclosure are not limited thereto, and the channel layer 14 may also be an alloy of AlInGaN in any other proportion.

[0034] The barrier layer 15 on the channel layer 14 is a 20 nm AlGaN layer with an Al content of 25%.

[0035] In an optional embodiment, the conductive substrate 10 can use a non-conductive substrate to etch the exposed epitaxial layer as a non-insulating substrate material; the conductive substrate 10 can also use a non-conductive substrate to etch the exposed epitaxial layer and deposit a conductive material in the epitaxial layer region as a non-insulating substrate material; the barrier layer 15 can also be an AlN layer, an AlInN layer, an AlInGaN layer, or a multiple superposition of the above material layers.

[0036] An in-situ SiN layer 16 is continuously grown on the barrier layer 15 as a gate dielectric layer with a thickness of 50 nm. Electrodes are fabricated on the barrier layer, including a source 171 and a drain 173. A gate electrode 172 is fabricated on the gate dielectric layer. A back electrode 171' is fabricated on the back side of the substrate 10, and is electrically connected to the source 171 at the same potential. However, the embodiments of the present disclosure are not limited thereto. After the MOCVD epitaxial growth is completed, the gate dielectric layer may also be fabricated by other dielectric layer growth processes such as PECVD, ALD, or LPCVD to deposit an insulating dielectric layer such as SiN, Al2O3, AlN, AlON, etc.

[0037] Reference Figure 2a-2d As shown, this embodiment provides a process flow for preparing the nitride transistor structure.

[0038] Step 1, such as Figure 2a As shown, a conductive silicon substrate 10 is provided, on which a nucleation layer 11, a buffer layer 12, a p-type nitride buried layer 13, a channel layer 14, a barrier layer 15, and an in-situ SiN layer 16 are sequentially grown by MOCVD. The nucleation layer 11 is an AlN layer with a thickness of 100 nm; the buffer layer 12 includes an AlN / AlGaN / superlattice structure grown sequentially from bottom to top, wherein AlN is 100 nm, AlGaN can be a single layer or a multilayer with different components, in this embodiment, it is a 100 nm AlGaN single layer with an Al component of 50%, the superlattice structure can be AlN / GaN, AlN / AlGaN, AlGaN / GaN superlattice structure, or a combination of the above structures, in this embodiment, an AlN / GaN superlattice structure is used, each period includes AlN 4 nm, GaN 20 nm, the total thickness is about 3 microns, and the carbon doping concentration is about 1×10 19 / cm 3 ; The p-type nitride buried layer 13, in this embodiment, uses 100nm p-type GaN, and the Mg doping concentration is about 2×10 19 / cm 3 ; The channel layer 14 is unintentionally doped GaN 300nm, and the background electron concentration is about 4×10 16 / cm 3 ; The barrier layer 15 is a 20nm AlGaN layer with an Al content of 25%; an in-situ SiN layer 16 is grown on the barrier layer 15 as a gate dielectric layer with a thickness of 50nm. After growth, the Mg doping is activated by annealing at 650℃ for 30min in a nitrogen atmosphere in the growth chamber, or by taking out the epitaxial wafer and annealing at 650℃ for 30min in an oxygen atmosphere outside the growth chamber to form a higher hole concentration.

[0039] Step 2, such as Figure 2bAs shown, the dielectric layer 16 corresponding to the source and drain positions is etched away by photolithography to expose the source and drain windows.

[0040] Step 3, such as Figure 2c As shown, the electrode materials for depositing the source 171, the drain 173 and the back electrode 171' can be metal or non-metallic materials. In this embodiment, the source and drain electrodes are deposited by a Ti / Al / Ti / Au metal composite layer, and an ohmic electrode is made by a rapid thermal annealing process, and the back electrode is deposited by an Al metal layer on the back.

[0041] Step 4, such as Figure 2d As shown, a gate electrode 172 is formed on the gate dielectric layer 16. The back electrode 171' and the source electrode 171 are electrically connected during chip packaging, and can also be interconnected by metal through-hole chip processing.

[0042] Example 2

[0043] In the second exemplary embodiment, referring to Figure 3 , the nitride transistor structure of embodiment 2 includes:

[0044] The conductive substrate 20 includes a silicon carbide substrate, a gallium nitride substrate, or a composite substrate formed by the above substrates and other conductive materials.

[0045] The nucleation layer 21 on the substrate 20 is an AlN layer with a thickness of 100 nm.

[0046] The buffer layer 22 on the nucleation layer 21 includes an AlN / AlGaN / superlattice structure grown sequentially from bottom to top, wherein AlN is 100nm, and AlGaN can be a single layer or a multilayer with different components. In this embodiment, it is a 50nm AlGaN single layer structure with an Al component of 50%. The superlattice structure can be AlN / GaN, AlN / AlGaN, AlGaN / GaN superlattice structure, or a combination of the above structures. In this embodiment, an AlN / AlGaN superlattice structure is used, and each period includes AlN 4nm, AlGaN 20nm, a total thickness of about 2.5 microns, and a carbon doping concentration of about 1×10 19 / cm 3 .

[0047] A p-type nitride layer 23 is grown on the buffer layer. In this embodiment, 200 nm p-type GaN is used, and the Mg doping concentration is about 1×10 19 / cm 3 .

[0048] The channel layer 24 on the p-type nitride layer 23 is a 300nm GaN layer with unintentional doping, and the background electron concentration is about 4×10 16 / cm3 .

[0049] The barrier layer 25 on the channel layer 24 is a 10 nm AlGaN layer with an Al composition of 20%.

[0050] A p-type GaN cap layer 26 with a thickness of 80 nm is continuously grown on the barrier layer 25. Electrodes are fabricated on the barrier layer 25, including a source electrode 271 and a drain electrode 273, and a gate electrode 272 is fabricated on the p-type GaN cap layer 26. A back electrode 271' is fabricated on the back side of the substrate 20, and is electrically connected to the source electrode 271 at the same potential.

[0051] The embodiments of the present disclosure are not limited to this. In an optional embodiment, the conductive substrate 20 can use a non-conductive substrate to etch the exposed epitaxial layer as a non-insulating substrate material; or use a non-conductive substrate to etch the exposed epitaxial layer and deposit a conductive material in the epitaxial layer region as a non-insulating substrate material; the barrier layer 25 can also be an AlN layer, an AlInN layer, an AlInGaN layer, or a multiple superposition of the above material layers; the channel layer 24 can also be any other alloy of AlInGaN in any proportion.

[0052] Reference Figure 4a-4d As shown, this embodiment provides a process flow for preparing the nitride transistor structure.

[0053] Step 1, such as Figure 4a As shown, a conductive silicon substrate 20 is provided, on which a nucleation layer 21, a buffer layer 22, a p-type nitride buried layer 23, a channel layer 24, a barrier layer 25, and a p-type GaN cap layer 26 are sequentially grown by MOCVD. The nucleation layer 21 is an AlN layer with a thickness of 100 nm; the buffer layer 22 includes an AlN / AlGaN / superlattice structure grown sequentially from bottom to top, wherein the AlN is 100 nm, the AlGaN can be a single layer or a multilayer with different components, in this embodiment, it is a 50 nm AlGaN single layer with an Al component of 50%, the superlattice structure can be an AlN / GaN, AlN / AlGaN, AlGaN / GaN superlattice structure, or a combination of the above structures, in this embodiment, an AlN / AlGaN superlattice structure is used, each period includes AlN 4 nm, AlGaN 20 nm, the total thickness is about 2.5 microns, and the carbon doping concentration is about 1×10 19 / cm 3 ; The p-type nitride buried layer 23, in this embodiment, uses 200nm p-type GaN, and the Mg doping concentration is about 1×10 19 / cm 3 ; The channel layer 24 is unintentionally doped GaN 300nm, and the background electron concentration is about 4×10 16 / cm 3The barrier layer 25 is a 10nm AlGaN layer with an Al content of 20%; a p-type GaN cap layer 26 with a thickness of 80nm is grown on the barrier layer 25. After growth, the Mg doping is activated by annealing at 650℃ for 30min in a nitrogen atmosphere in the growth chamber, or by taking out the epitaxial wafer and annealing at 650℃ for 30min in an oxygen atmosphere outside the growth chamber to form a higher hole concentration.

[0054] Step 2, such as Figure 4b As shown, the p-type GaN cap layer 26 outside the gate electrode region is etched away by a photolithography process, and the thickness of the p-type cap layer is completely etched away to expose the barrier layer 25 .

[0055] Step 3, such as Figure 4c As shown, the electrode materials for depositing the source 271, the drain 273 and the back electrode 271' can be metal or non-metallic materials. In this embodiment, the source and drain electrodes are deposited by depositing Ti / Al / Ti / Au metal composite layers, and the ohmic electrodes are made by rapid thermal annealing process, and the back electrode is deposited by depositing an Al metal layer on the back.

[0056] Step 4, such as Figure 4d As shown, a gate electrode 272 is formed on the p-type GaN cap layer 26. A Ni / Au composite metal layer can be used to form an ohmic contact or a Ti / Al composite metal layer can be used to form a Schottky contact electrode. The back electrode 271' is electrically connected to the source electrode 271 during chip packaging, and can also be interconnected by metal through the chip perforation process.

[0057] Example 3

[0058] Reference Figure 5 , the nitride transistor structure of Example 3 is Figure 3 The structure of the embodiment 2 is similar to that of the embodiment 2, except that the back electrode 272' is electrically connected to the gate electrode 272 and is at the same potential, forming a structure similar to a junction field effect transistor (J-FET).

[0059] Example 4

[0060] In the fourth exemplary embodiment, referring to Figure 6 , the nitride transistor structure of embodiment 4 includes:

[0061] The conductive substrate 30 is a conductive silicon substrate in this embodiment.

[0062] The nucleation layer 31 on the substrate 30 is an AlN layer with a thickness of 150 nm.

[0063] The buffer layer 32 on the nucleation layer 31 includes an AlGaN / superlattice structure grown sequentially from bottom to top, wherein the Al component in AlGaN is 50% and the thickness is 100nm. The superlattice structure can be an AlN / GaN, AlN / AlGaN, AlGaN / GaN superlattice structure, or a combination of the above structures. In this embodiment, an AlN / GaN superlattice structure is used, wherein each period includes AlN 4nm, GaN 20nm, the total thickness is about 3 microns, and the carbon doping concentration is about 1×10 19 / cm 3 .

[0064] A p-type nitride layer 33 is grown on the buffer layer 32. The p-type nitride layer 33 of this embodiment is made of 200nm p-type GaN, and the Mg doping concentration is about 1×10 19 / cm 3 .

[0065] The channel layer 34 on the p-type nitride layer 33 is a 300nm unintentionally doped GaN layer with a background electron concentration of about 4×10 16 / cm 3 .

[0066] The barrier layer 35 on the channel layer 34 is made of a 20 nm AlGaN layer with an Al composition of 25%.

[0067] The barrier layer 35 corresponding to the gate electrode 372 region is etched away. A gate dielectric layer 36 is grown continuously with a thickness of 50 nm. After the MOCVD epitaxial growth is completed, the gate dielectric layer can be deposited with an insulating dielectric layer such as SiN, Al2O3, AlN, AlON, etc. by other dielectric layer growth processes such as PECVD, ALD, or LPCVD. Electrodes are made on the barrier layer, including a source 371 and a drain 373, and a gate electrode 372 is made on the gate dielectric. A back electrode 372' is made on the back side of the substrate 30, which is electrically connected to the gate 372 and is at the same potential.

[0068] The embodiments of the present disclosure are not limited to this. In optional embodiments, the conductive substrate 30 may also be a silicon carbide substrate, a gallium nitride substrate, or a composite substrate formed by the above substrates and other conductive materials; the conductive substrate 30 may use a non-conductive substrate to etch the exposed epitaxial layer as a non-insulating substrate material; a non-conductive substrate may be used to etch the exposed epitaxial layer and deposit a conductive material in the epitaxial layer region as a non-insulating substrate material; the barrier layer 35 may also be an AlN layer, an AlInN layer, an AlInGaN layer, or a multiple superposition of the above material layers; the channel layer 34 may also be any other alloy of AlInGaN in any proportion.

[0069] Reference Figure 7a-7hAs shown, this embodiment provides a process flow for preparing the nitride transistor structure.

[0070] Step 1, such as Figure 7a As shown, a conductive silicon substrate 30 is provided, on which a nucleation layer 31, a buffer layer 32, a p-type nitride buried layer 33, a channel layer 34, and a barrier layer 35 are sequentially grown by MOCVD. The nucleation layer 31 is an AlN layer with a thickness of 150nm; the buffer layer 32 includes an AlGaN / superlattice structure grown sequentially from bottom to top, with an Al component of 50% in AlGaN and a thickness of 100nm. The superlattice structure can be an AlN / GaN, AlN / AlGaN, AlGaN / GaN superlattice structure, or a combination of the above structures. In this embodiment, an AlN / GaN superlattice structure is used, and each period includes AlN 4nm, GaN 20nm, a total thickness of about 3 microns, and a carbon doping concentration of about 1×10 19 / cm 3 ; The p-type nitride buried layer 33, in this embodiment, uses 200nm p-type GaN, and the Mg doping concentration is about 1×10 19 / cm 3 ; The channel layer 34 is unintentionally doped GaN 300nm, and the background electron concentration is about 4×10 16 / cm 3 The barrier layer 35 is a 20nm AlGaN layer with an Al content of 25%. After growth, the Mg doping is activated by annealing at 650°C for 30 minutes in a nitrogen atmosphere in the growth chamber, or by taking out the epitaxial wafer and annealing at 650°C for 30 minutes in an oxygen atmosphere outside the growth chamber to form a higher hole concentration.

[0071] Step 2, such as Figure 7b As shown, the dielectric layer 16 corresponding to the source and drain positions is etched away by photolithography to expose the source and drain windows.

[0072] Step 3, such as Figure 7c As shown, the electrode materials for depositing the source 371, the drain 373 and the back electrode 371' can be metal or non-metallic materials. In this embodiment, the source and drain electrodes are deposited by a Ti / Al / Ti / Au metal composite layer, and an ohmic electrode is made by a rapid thermal annealing process, and the back electrode is deposited by an Al metal layer on the back.

[0073] Step 4, such as Figure 7d As shown, a gate electrode 372 is formed on the gate dielectric layer 36. The back electrode 371' and the source electrode 371 are electrically connected during chip packaging, and can also be metal interconnected through a chip through-hole process.

[0074] The above is only a specific implementation of the embodiment of the present invention, but the protection scope of the embodiment of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiment of the present invention, which should be included in the protection scope of the embodiment of the present invention. Therefore, the protection scope of the embodiment of the present invention should be based on the protection scope of the claims.

Claims

1. A nitride semiconductor transistor structure, wherein the epitaxial structure comprises a substrate, a nucleation layer is provided on the substrate, wherein: A buffer layer is arranged above the nucleation layer, a p-type nitride buried layer is arranged above the buffer layer, a channel layer is arranged above the p-type nitride buried layer, a barrier layer is arranged above the channel layer, and a transistor structure including a source, a gate, and a drain is manufactured on the surface of the epitaxial structure.

2. A nitride semiconductor transistor structure according to claim 1, characterized in that: The substrate is selected from: a conductive silicon carbide substrate, a conductive gallium nitride substrate, a conductive silicon substrate, or a composite substrate comprising any of the above substrates.

3. The nitride semiconductor transistor structure according to claim 1, characterized in that: The substrate is a non-conductive substrate, and the back side of the non-conductive substrate is etched to expose the epitaxial layer.

4. A nitride semiconductor transistor structure according to claim 3, characterized in that: A conductive material is deposited in the epitaxial layer region exposed by the etching process.

5. The nitride semiconductor transistor structure according to claim 1, characterized in that: The high withstand voltage buffer layer adopts a multi-layer Al composition gradient AlGaN structure, or adopts one of AlGaN / AlN, GaN / AlN, GaN / AlGaN super lattice structures, or a combination of the above structures, and is doped with carbon elements.

6. A nitride semiconductor transistor structure according to claim 5, characterized in that: The buffer layer is doped with carbon element in whole or in part, and the maximum carbon concentration of the doped part is not less than 1×10 17 / cm 3 .

7. The nitride semiconductor transistor structure according to claim 1, characterized in that: The p-type nitride layer is an alloy of p-type AlInGaN in any proportion, or a multilayer composite structure of the above-mentioned p-type nitride alloy layers in different component proportions.

8. The nitride semiconductor transistor structure according to claim 1, characterized in that: The p-type nitride layer is a continuous epitaxial thin film, or a discontinuous p-type nitride layer formed by etching after the entire p-type nitride layer is grown.

9. The nitride semiconductor transistor structure according to claim 1, characterized in that: A back electrode is provided on the back of the conductive substrate, the back electrode forms an ohmic contact with the substrate, and the back electrode is electrically connected to the source electrode or the gate electrode to maintain the same potential.

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