Anti-radiation SiC MOSFET structure and preparation method thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses an anti-radiation SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer positioned on the surface of the grid electrode, a P well layer, a heavily-doped P well I and a heavily-doped N well layer are formed in the N diffusion layer of each MOS cell through ion implantation, the heavily-doped P well I further comprises a heavily-doped P well II, and the height of the cross section of the heavily-doped P well II is the same as that of the cross section of the heavily-doped N well layer; the N diffusion layer further comprises a carrier storage layer. According to the method, the trench is introduced into the device JFET, P-type impurities are injected into the side wall and the bottom of the trench to form the P-type doped region, the trench is filled with dielectric materials such as SiO2 and the like, and the trench structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, so that the electric field intensity in thin gate oxide is greatly reduced, and the single-particle gate penetration resistance of the SiC MOSFET device is improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a radiation-resistant SiC MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon carbide high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more demanding environments. Therefore, they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace, etc. For the aerospace field, power devices must not only meet the requirements of high voltage, high power, high frequency and low loss, but also have good radiation resistance.

[0003] The existing patent discloses a new structure of SiC MOSFET device with high radiation resistance (publication number CN114388621A). The SiC power device in the patent often suffers single-particle burnout when the blocking voltage is less than 1 / 3 and the LET is not higher than 10MeV.cm2 / mg, which is far lower than theoretical expectations. Single-particle radiation usually involves a very complex electrothermal coupling response inside the device. When heavy ions bombard the power device, a large number of electron-hole pairs are generated along the motion trajectory. These electron-hole pairs drift under the action of the electric field, forming a large instantaneous current inside the device. Some electrons and holes will also accumulate at both ends of the device, thereby reconstructing the electric field inside the device, resulting in strong electric field breakdown in the device, such as single-particle gate breakdown. In addition, the instantaneous large current and instantaneous temperature rise formed by the large number of electron-hole movements and strong electric field coupling inside the device may trigger the conduction of the parasitic NPN transistor inside the device, resulting in local single-particle burnout of the device under low bias voltage conditions. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a radiation-resistant SiC MOSFET structure and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a radiation-resistant SiC MOSFET structure includes a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer located on the surface of the gate, wherein the semiconductor epitaxial layer also includes an N substrate layer and an N diffusion layer, and a P well layer, a heavily doped P well 1, and a heavily doped N well layer are formed inside the N diffusion layer of a single MOS cell by ion implantation.

[0006] Furthermore, the heavily doped P well 1 also includes a heavily doped P well 2, and the cross-sectional height of the heavily doped P well 2 is the same as the cross-sectional height of the heavily doped N well layer; The N diffusion layer also includes a carrier storage layer; A P-type doping region is formed in the N diffusion layer of a single MOS cell and between two adjacent P well layers by ion implantation.

[0007] Furthermore, the interior of the P-type doped region is also filled with a silicon dioxide dielectric layer.

[0008] Furthermore, the interior of the P-type doped region is also filled with P-type polysilicon.

[0009] Furthermore, the interior of the P-type doped region is also filled with N-type polysilicon.

[0010] Furthermore, the connection layer between the N-type polysilicon and the P-type doped region is formed with P-type polysilicon II by ion implantation.

[0011] A method for preparing a radiation-resistant SiC MOSFET structure comprises the following steps: S1, pre-treating the semiconductor epitaxial layer; S2, using ion implantation to implant boron into the N diffusion layer to form a P well layer, a heavily doped P well 1 and a P-type doped region, and then adjusting the conductivity and threshold voltage of the source and drain regions by controlling the energy and concentration of the implant; S3, injecting phosphorus into the P-well layer to form a heavily doped N-well layer, and injecting boron or phosphorus into the P-type doping region to form P-type polysilicon or N-type polysilicon; S4, using evaporation technology to deposit metal tungsten as a gate material, and patterning it through photolithography technology to form a required gate; S5. Evaluate whether the basic electrical performance of SiC MOSFET meets the usage standards through IV characteristic test and gate current test.

[0012] Furthermore, the test of the basic electrical performance of SiC MOSFET in step S is to determine whether the SiC MOSFET structure with added P-type doping region is qualified based on the absolute value of the difference in on-current, on-resistance, leakage current and breakdown voltage between the SiC MOSFET structure with added P-type doping region and the SiC MOSFET structure without added P-type doping region, and: In the formula, Represents the pass coefficient of the SiC MOSFET structure, It represents the absolute value of the conduction current difference between the structure with P-type doping region and the structure without P-type doping region. It represents the absolute value of the on-resistance difference between the structure with P-type doping region and the structure without P-type doping region. It represents the absolute value of the leakage current difference between the structure with P-type doping region and the structure without P-type doping region. It represents the absolute value of the breakdown voltage difference between the structure with P-type doping region and the structure without P-type doping region.

[0013] Furthermore, when When , it means that the electrical performance of the SiC MOSFET structure meets the use requirements; when When , it means that the electrical performance of the SiC MOSFET structure does not meet the use requirements. Beneficial effects: 1. The present invention adjusts the layout of the P+ injection window by optimizing the layout design of the P+ layer, and adjusts the N-well injection and P+ injection sequence at the same time, so that the bottom of the N-well is completely surrounded by the P+. A larger area of ​​P+ is used to completely surround the bottom of the N-well, which can effectively reduce the base region transport coefficient of the NPN transistor to suppress the NPN amplification effect, thereby achieving the purpose of improving the single particle burnout threshold voltage of the SiC MOSFET device.

[0014] 2. The present invention introduces a trench into the device JFET, and injects P-type impurities into the sidewalls and bottom of the trench to form a P-type doped region, and fills the trench with dielectric materials such as SiO2. The trench structure transfers the strong electric field at the gate oxide interface to the bottom of the JFET region, greatly reducing the electric field strength in the thin gate oxide, thereby improving the SiC MOSFET device's ability to resist single-particle gate penetration.

[0015] 3. The present invention fills high-concentration N-type polysilicon, so that the pinch-off effect of JFET at high blocking voltage is enhanced, and the doping concentration of the carrier storage layer is increased without affecting the voltage blocking capability of the device. The higher doping concentration of the carrier storage layer and the N-type polysilicon short-circuited to the source in the trench can greatly improve the recombination efficiency of holes and electrons at the moment of single-particle radiation, further improve the excess carrier extraction speed, and effectively improve the single-particle radiation resistance of the silicon carbide diode.

[0016] 4. The present invention can determine whether a SiC MOSFET structure with a P-type doped region is qualified by measuring the absolute value of the on-current, on-resistance, leakage current and breakdown voltage difference between a SiC MOSFET structure with a P-type doped region and a SiC MOSFET structure without a P-type doped region. This inspection method can not only reduce the inspection steps, but also ensure the accuracy of the inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a schematic diagram of the second embodiment of the present invention; Figure 3 This is a schematic diagram of Embodiment 3 of the present invention; Figure 4 is a schematic diagram of a fourth embodiment of the present invention; Figure 5 This is a schematic diagram of Embodiment 5 of the present invention.

[0018] In the figure: 1, drain; 2, N substrate layer; 3, N diffusion layer; 4, source; 5, gate oxide layer; 6, gate; 7, P well layer; 8, heavily doped P well 1; 9, heavily doped N well layer; 10, P-type doped region; 111, silicon dioxide dielectric layer; 112, P-type polysilicon 1; 113, N-type polysilicon; 1121, P-type polysilicon 2; 81, heavily doped P well 2. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] A method for preparing a radiation-resistant SiC MOSFET structure comprises the following steps: Step 1: pre-treating the semiconductor epitaxial layer; Step 2: Use ion implantation to implant boron into the N diffusion layer 3 to form a P well layer 7, a heavily doped P well 8 and a P-type doped region 10, and then adjust the conductivity and threshold voltage of the source and drain regions by controlling the energy and concentration of the implanted agent; Step 3: inject phosphorus into the P-well layer 7 to form a heavily doped N-well layer 9, and inject boron or phosphorus into the P-type doping region 10 to form a P-type polysilicon 112 or an N-type polysilicon 113; Step 4: Use evaporation technology to deposit metal tungsten as a gate material, and use photolithography technology to pattern it to form the required gate 6; Step 5: Evaluate whether the basic electrical performance of SiC MOSFET meets the usage standards through IV characteristic test and gate current test.

[0021] The test of the basic electrical performance of SiC MOSFET in step 5 is based on the absolute value of the difference in on-current, on-resistance, leakage current and breakdown voltage between the SiC MOSFET structure with the P-type doping region 10 added and the SiC MOSFET structure without the P-type doping region 10 added (the device without the P-type doping region 10 is a standard qualified device), to determine whether the SiC MOSFET structure with the P-type doping region 10 is qualified, and there are: In the formula, Represents the pass coefficient of the SiC MOSFET structure, represents the absolute value of the conduction current difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10, represents the absolute value of the on-resistance difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10, represents the absolute value of the leakage current difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10, It represents the absolute value of the breakdown voltage difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10 .

[0022] when When , it means that the electrical performance of the SiC MOSFET structure meets the use requirements; when When , it means that the electrical performance of the SiC MOSFET structure does not meet the use requirements.

[0023] The data of the medium power device X is monitored. The absolute value of the conduction current difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10 is taken as (A).

[0024] The absolute value of the on-resistance difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10 is (mΩ).

[0025] The absolute value of the leakage current difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10 is (nA).

[0026] The absolute value of the breakdown voltage difference between the structure with the P-type doping region 10 and the structure without the P-type doping region 10 is (V), then we have: From the above calculation, we can know that the qualified coefficient of medium power device X is , then it means that the electrical performance of the SiCMOSFET structure meets the use requirements.

[0027] Example 1 like Figure 1As shown, a radiation-resistant SiC MOSFET structure includes a drain 1, a semiconductor epitaxial layer, a source 4, a gate 6, and a gate oxide layer 5 located on the surface of the gate 6. The semiconductor epitaxial layer also includes an N substrate layer 2 and an N diffusion layer 3. The N diffusion layer 3 of a single MOS cell is formed with a P well layer 7, a heavily doped P well-8, and a heavily doped N well layer 9 by ion implantation. The layout of the P+ injection window is adjusted by optimizing the layout design of the P+ layer (heavily doped P well-8), and the sequence of N well injection and P+ injection is adjusted at the same time, so that the bottom of the N well is completely surrounded by the P+ (heavily doped P well-8). In addition, a larger area of ​​P+ (heavily doped P well-8) is used to completely surround the bottom of the N well, which can effectively reduce the base transport coefficient of the NPN triode to suppress the NPN amplification effect, thereby achieving the purpose of improving the single particle burnout threshold voltage of the SiC MOSFET device.

[0028] Example 2 like Figure 2 As shown, the heavily doped P well 1 8 also includes a heavily doped P well 2 81, and the cross-sectional height of the heavily doped P well 2 81 is the same as the cross-sectional height of the heavily doped N well layer 9; the N diffusion layer 3 also includes a carrier storage layer; a P-type doping region 10 is formed by ion implantation in the N diffusion layer 3 of a single MOS cell and between two adjacent P well layers 7, and the interior of the P-type doping region 10 is also filled with a silicon dioxide dielectric layer 111. The P-type doping region 10 is formed by introducing a trench in the device JFET, and injecting P-type impurities into the sidewalls and bottom of the trench, and the trench is filled with dielectric materials such as SiO2 (silicon dioxide dielectric layer 111). The trench structure transfers the strong electric field at the gate oxide interface to the bottom of the JFET region, greatly reducing the electric field strength in the thin gate oxide, thereby improving the single-particle gate penetration resistance of the SiC MOSFET device; at the same time, the P-type doping area at the bottom and sidewalls of the trench increases the hole extraction path area in the active region, which can enhance the hole extraction efficiency in the body at the moment of heavy ion bombardment; in addition, due to the introduction of the trench structure, the pinch-off effect of the JFET at high blocking voltage is enhanced, and the doping concentration of the carrier storage layer is increased without affecting the voltage blocking capability of the device, thereby improving the recombination efficiency of holes and electrons at the moment of single-particle radiation. Therefore, the present invention can effectively improve the radiation resistance of SiC MOSFET devices.

[0029] Example 3 like Figure 3As shown, the heavily doped P well 1 8 also includes a heavily doped P well 2 81, and the cross-sectional height of the heavily doped P well 2 81 is the same as the cross-sectional height of the heavily doped N well layer 9; the N diffusion layer 3 also includes a carrier storage layer; a P-type doping region 10 is formed by ion implantation in the N diffusion layer 3 of a single MOS cell and between two adjacent P well layers 7, and the interior of the P-type doping region 10 is also filled with P-type polysilicon 112. The P-type doping region 10 is formed by introducing a trench in the device JFET, and injecting P-type impurities into the sidewalls and bottom of the trench, and the trench is filled with P-type polysilicon (P-type polysilicon 112). The trench structure transfers the strong electric field at the gate oxide interface to the bottom of the JFET region, greatly reducing the electric field strength in the thin gate oxide, thereby improving the SiC MOSFET device's ability to resist single-particle gate penetration; at the same time, the P-type doped regions at the bottom and side walls of the trench and the P-type polysilicon in the trench that is short-circuited to the source increase the hole extraction path area in the active region, which can enhance the hole extraction efficiency in the body at the moment of heavy ion bombardment.

[0030] Example 4 like Figure 4 As shown, the heavily doped P-well 1 8 also includes a heavily doped P-well 2 81, and the cross-sectional height of the heavily doped P-well 2 81 is the same as the cross-sectional height of the heavily doped N-well layer 9; the N-diffusion layer 3 also includes a carrier storage layer; a P-type doping region 10 is formed by ion implantation in the N-diffusion layer 3 of a single MOS cell and between two adjacent P-well layers 7, and the interior of the P-type doping region 10 is also filled with N-type polysilicon 113. By filling with high-concentration N-type polysilicon (N-type polysilicon 113), the pinch-off effect of the JFET at high blocking voltage is enhanced, and the doping concentration of the carrier storage layer is increased without affecting the voltage blocking capability of the device. The higher doping concentration of the carrier storage layer and the N-type polysilicon (N-type polysilicon 113) short-circuited with the source in the trench can greatly improve the recombination efficiency of holes and electrons at the moment of single-particle radiation, further improve the excess carrier extraction speed, and effectively improve the single-particle radiation resistance of the silicon carbide diode.

[0031] Example 5 like Figure 5As shown, the heavily doped P well 1 8 also includes a heavily doped P well 2 81, and the cross-sectional height of the heavily doped P well 2 81 is the same as the cross-sectional height of the heavily doped N well layer 9; the N diffusion layer 3 also includes a carrier storage layer; a P-type doping region 10 is formed by ion implantation in the N diffusion layer 3 of a single MOS cell and between two adjacent P well layers 7, and a connection layer between the N-type polysilicon 113 and the P-type doping region 10 is formed by ion implantation with a P-type polysilicon 2 1121. By filling high-concentration P-type (P-type polysilicon 2 1121) and N-type polysilicon 113, and the N-type polysilicon is surrounded by the P-type polysilicon, the doping concentration of the carrier storage layer is increased without affecting the voltage blocking capability of the device. The higher doping concentration of the carrier storage layer and the N-type polysilicon short-circuited with the source in the trench can greatly improve the recombination efficiency of holes and electrons at the moment of single particle radiation, and further improve the excess carrier extraction speed. Therefore, the present invention can effectively improve the radiation resistance of SiC MOSFET devices.

[0032] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A radiation-resistant SiC MOSFET structure, comprising a drain (1), a semiconductor epitaxial layer, a source (4), a gate (6), and a gate oxide layer (5) located on the surface of the gate (6), characterized in that: The semiconductor epitaxial layer also includes an N substrate layer (2) and an N diffusion layer (3); a P well layer (7), a heavily doped P well 1 (8) and a heavily doped N well layer (9) are formed inside the N diffusion layer (3) of a single MOS cell by ion implantation.

2. The radiation-resistant SiC MOSFET structure according to claim 1, characterized in that: The heavily doped P well 1 (8) further comprises a heavily doped P well 2 (81), and the cross-sectional height of the heavily doped P well 2 (81) is the same as the cross-sectional height of the heavily doped N well layer (9); The N diffusion layer (3) also includes a carrier storage layer; A P-type doping region (10) is formed by ion implantation in the N diffusion layer (3) of a single MOS cell and between two adjacent P well layers (7).

3. The radiation-resistant SiC MOSFET structure according to claim 2, characterized in that: The interior of the P-type doped region (10) is also filled with a silicon dioxide dielectric layer (111).

4. The radiation-resistant SiC MOSFET structure according to claim 2, characterized in that: The interior of the P-type doped region (10) is also filled with P-type polysilicon 1 (112).

5. The radiation-resistant SiC MOSFET structure according to claim 2, characterized in that: The interior of the P-type doped region (10) is also filled with N-type polysilicon (113).

6. The radiation-resistant SiC MOSFET structure according to claim 5, characterized in that: The connection layer between the N-type polysilicon (113) and the P-type doped region (10) is formed with P-type polysilicon 2 (1121) by ion implantation.

7. A method for preparing a radiation-resistant SiC MOSFET structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1, pre-treating the semiconductor epitaxial layer; S2, using an ion implantation method to implant boron elements into the N diffusion layer (3) to form a P well layer (7), a heavily doped P well 1 (8) and a P-type doped region (10), and then adjusting the conductivity and threshold voltage of the source and drain regions by controlling the energy and concentration of the implanted agent; S3, injecting phosphorus into the P-well layer (7) to form a heavily doped N-well layer (9), and injecting boron or phosphorus into the P-type doping region (10) to form P-type polysilicon (112) or N-type polysilicon (113); S4, using evaporation technology to deposit metal tungsten as a gate material, and patterning it using photolithography technology to form a desired gate (6); S5. Evaluate whether the basic electrical performance of SiC MOSFET meets the usage standards through IV characteristic test and gate current test.

8. The method for preparing a radiation-resistant SiC MOSFET structure according to claim 7, characterized in that: The test of the basic electrical performance of the SiC MOSFET in step S5 is to determine whether the SiC MOSFET structure with the P-type doped region (10) is qualified based on the absolute value of the difference in on-current, on-resistance, leakage current and breakdown voltage between the SiC MOSFET structure with the P-type doped region (10) and the SiC MOSFET structure without the P-type doped region (10), and the following are performed: In the formula, Represents the pass factor of the SiC MOSFET structure, represents the absolute value of the conduction current difference between a structure with a P-type doping region (10) and a structure without a P-type doping region (10), represents the absolute value of the on-resistance difference between a structure with a P-type doping region (10) and a structure without a P-type doping region (10), represents the absolute value of the difference in leakage current between a structure with a P-type doping region (10) and a structure without a P-type doping region (10), Indicates the absolute value of the breakdown voltage difference between a structure with a P-type doping region (10) and a structure without a P-type doping region (10).

9. The method for preparing a radiation-resistant SiC MOSFET structure according to claim 8, characterized in that: when When , it means that the electrical performance of the SiC MOSFET structure meets the use requirements; when When , it means that the electrical performance of the SiC MOSFET structure does not meet the use requirements.

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