LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. According to the LDMOS device, the gate structure is arranged in the groove of the substrate, and the bottom of the field plate structure can further extend downwards into the groove, so that the longitudinal size of the field plate structure can be increased, the breakdown voltage of the device can be improved, and the field plate structure can be manufactured under the conditions that the on-resistance of the device is not influenced and the overall area of the device is not increased. And the voltage withstanding performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] Laterally diffused metal oxide semiconductor (LDMOS) devices are commonly used semiconductor high voltage devices, which are widely used in power amplifiers in radio frequency fields such as wireless base stations and broadcasting stations.

[0003] Figure 1 is a schematic diagram of the structure of an existing LDMOS device, such as Figure 1 As shown, the LDMOS device generally includes: a substrate 10 having a drift region, a source region 20S and a drain region 20D formed in the substrate 10, and a gate structure 20G formed between the source region 20S and the drain region 20D. In order to ensure that the device has sufficient withstand voltage performance, a field plate design is generally adopted to utilize the coupling effect of the field plate structure to increase the device's breakdown voltage BV (Breakdown Voltage), reduce the on-resistance Rdson, and suppress the hot carrier injection effect HCI (Hot Carrier Injection).

[0004] For example Figure 1 As shown, a field plate structure 30 in an LDMOS device adopts a contact hole field plate (CFP), that is, the field plate structure 30 penetrates the interlayer dielectric layer (not shown in the figure) above the substrate 10, so that the contact hole field plate can achieve the electric field modulation effect in the drift region. However, the size of the field plate structure 30 is limited by the thickness of the interlayer dielectric layer, so that the effect of the field plate structure 30 on the drift region is also limited, which easily causes the on-resistance Rdson of the device to be too high, the breakdown voltage BV is insufficient, and other problems. Among them, in order to increase the breakdown voltage BV of the device, it can be achieved by reducing the ion concentration of the drift region or increasing the length of the drift region, but this will cause the on-resistance Rdson of the device to increase, and also increase the area of ​​the device. Therefore, it is difficult to improve the withstand voltage performance of the device while ensuring the on-resistance of the device in the prior art. Summary of the invention

[0005] The object of the present invention is to provide an LDMOS device to solve the problem in the prior art that it is difficult to achieve both high withstand voltage performance and low on-resistance of the LDMOS device.

[0006] In this regard, the present invention provides an LDMOS device, comprising: a substrate having a groove formed therein; a gate structure, the gate structure being formed on the bottom surface of the groove, and the top surface of the gate structure being lower than the top position of the groove; and a field plate structure, the field plate structure being at least partially located within the region of the groove and extending downward into the groove, and the portion of the field plate structure located in the groove being at least formed above the gate structure.

[0007] Optionally, the field plate structure is disposed close to a side wall of the groove and covers the side wall of the groove.

[0008] Optionally, the field plate structure further extends to the outside of the groove in a direction toward the drain region to extend and cover the top surface of the substrate.

[0009] Optionally, the gate structure is arranged at a position closer to the drain region than the center position of the groove.

[0010] Optionally, the LDMOS device further includes: an insulating dielectric layer, at least covering the gate structure, and allowing the field plate structure to be formed on the insulating dielectric layer.

[0011] Optionally, the LDMOS device further includes: a source region and a drain region, wherein the source region is at least partially formed below the groove and extends downward from the bottom surface of the groove, and the drain region is located on a side of the field plate structure away from the source region and extends downward from the top surface of the substrate.

[0012] Optionally, the field plate structure includes a contact hole field plate.

[0013] Optionally, the gate structure is arranged in a ring shape around the center of the groove, and the field plate structure is arranged in a ring shape at a position farther away from the center of the groove relative to the gate structure.

[0014] Optionally, the LDMOS device further includes a source region and a drain region, and the source region, the gate structure, the field plate structure and the drain region are arranged in sequence from an inner ring to an outer ring, wherein the source region is formed in a central area of ​​the groove, and the drain region surrounds the outer side of the groove.

[0015] The present invention also provides a method for preparing an LDMOS device, comprising: providing a substrate and forming a groove in the substrate; forming a gate structure on the bottom surface of the groove, wherein the top surface of the gate structure is lower than the top position of the groove; and forming a field plate structure on the substrate, wherein the field plate structure is at least partially located within the area of ​​the groove and extends downward into the groove, and the portion of the field plate structure located in the groove is at least formed above the gate structure.

[0016] In the LDMOS device provided by the present invention, by setting the gate structure in the groove of the substrate and allowing the bottom of the field plate structure to further extend downward into the groove, it is beneficial to increase the longitudinal dimension of the field plate structure, thereby improving the breakdown voltage of the device, thereby achieving the improvement of the voltage resistance performance of the device without affecting the on-resistance of the device and without increasing the overall area of ​​the device.

[0017] Furthermore, the field plate structure can be extended laterally from the groove to the top surface of the substrate outside the groove, thereby increasing the lateral size of the field plate structure, so that the field plate structure can cover the side wall and top surface of the drift region at the same time, thereby increasing the coverage area of ​​the drift region, achieving a better average surface electric field, effectively improving the breakdown voltage of the device, and further optimizing the voltage resistance performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of an existing LDMOS device.

[0019] Figure 2 It is a schematic diagram of the structure of the LDMOS device in the first embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of the structure of the LDMOS device in the second embodiment of the present invention.

[0021] Figure 4 It is a top view of the LDMOS device in the third embodiment of the present invention.

[0022] Figure 5 It is a schematic cross-sectional view of the LDMOS device along the aa' direction in the third embodiment of the present invention.

[0023] Figure 6 The figure is a comparison diagram of the results obtained when a conventional LDMOS device and an LDMOS device provided by the present invention are subjected to a breakdown voltage simulation experiment.

[0024] Figure 7-Figure 10 This is a schematic structural diagram of an LDMOS device provided in Embodiment 4 of the present invention during its preparation process.

[0025] The reference numerals are as follows:

[0026] 10 / 100-substrate;

[0027] 100a-groove;

[0028] 110 - base;

[0029] 120P-well region;

[0030] 120N-drift zone;

[0031] 20G / 200G-gate structure;

[0032] 20S / 200S-source region;

[0033] 20D / 200D-drain area;

[0034] 30 / 300-field plate structure;

[0035] 400S-source metal;

[0036] 400D-drain metal;

[0037] 500-insulating dielectric layer;

[0038] 600-interlayer dielectric layer;

[0039] 710-source contact hole;

[0040] 720-field plate contact hole;

[0041] 730-Drain contact hole. DETAILED DESCRIPTION

[0042] The core idea of ​​the present invention is to provide a novel LDMOS device, which can improve the breakdown voltage of the device without sacrificing the on-resistance of the device.

[0043] Specifically, the LDMOS device provided by the present invention includes: a substrate having a groove, a gate structure formed in the groove, and a field plate structure at least partially formed in the groove. That is, the LDMOS device in the present invention specifically sets the gate structure in the groove of the substrate, so that the bottom of the field plate structure can be further extended downward into the groove, which is conducive to increasing the longitudinal dimension of the field plate structure, improving the withstand voltage performance of the device, and achieving the improvement of the breakdown voltage without affecting the on-resistance of the device and increasing the overall area of ​​the device.

[0044] In addition, since the field plate structure of the LDMOS device in the present invention can be extended longitudinally into the groove, the thickness of the interlayer dielectric layer on the top surface of the substrate can be correspondingly reduced while keeping the longitudinal dimension of the field plate structure unchanged, thereby reducing the size of the device and improving the cost performance.

[0045] The LDMOS device and the method for preparing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element will now be below the element.

[0046] <Example 1>

[0047] Figure 2 FIG. 1 is a schematic diagram of the structure of the LDMOS device in the first embodiment of the present invention. Figure 2 As shown, the LDMOS device includes: a substrate 100 , a gate structure 200G formed on the substrate 100 , and a field plate structure 300 .

[0048] Furthermore, a drift region 120N of a first doping type and a well region 120P of a second doping type are formed in the substrate 100, and the drift region 120N and the well region 120P have a laterally adjacent boundary. Also, the gate structure 200G partially covers the well region 120P and crosses the boundary so that another part thereof extends to the drift region 120N. The first doping type and the second doping type are opposite doping types, for example, if the first doping type is N-type, the second doping type is P-type; or, if the first doping type is P-type, the second doping type is N-type. In this embodiment, the first doping type is N-type and the second doping type is P-type as an example for explanation.

[0049] In a specific example, the substrate 100 includes a second doping type base 110 and an epitaxial layer formed on the base 110 . The base 110 may be a silicon base, and the well region 120P and the drift region 120N as described above are formed in the epitaxial layer.

[0050] Continue to refer Figure 2 As shown, a groove 100a is further formed in the substrate 100, and the groove 100a is at least used to accommodate the gate structure 200G and at least a part of the field plate structure 300. Specifically, the groove 100a is formed by being sunken from the top surface of the substrate 100 to a predetermined depth at least at a position where the well region 120P and the drift region 120N are adjacent to each other, wherein the depth of the groove 100a can be adjusted accordingly according to actual needs, for example, the depth of the groove 100a can be no greater than 5 μm.

[0051] Further, the gate structure 200G is formed on the bottom surface of the groove 100a, and the gate structure 200G partially covers the well region 120P and also covers the adjacent drift region 120N. In a specific example, the gate structure 200G includes a gate dielectric layer and a gate conductive layer formed on the gate dielectric layer. The gate dielectric layer is formed on the bottom surface of the groove 100a, and the gate conductive layer is stacked on the gate dielectric layer. Further, a sidewall may be formed on the sidewall of the gate conductive layer.

[0052] Continue to refer Figure 2 As shown, the LDMOS device further includes a source region 200S of the first doping type and a drain region 200D of the first doping type, the source region 200S and the drain region 200D are respectively located on both sides of the gate structure 200G, wherein the source region 200S is specifically formed in the well region 120P, and the drain region 200D is formed in the drift region 120N. When a turn-on voltage is applied to the gate structure 200G of the LDMOS device, the well region 120P covered by the gate structure 200G is inverted to form a conductive channel, so that the source region 200S can be connected to the drift region 120N through the conductive channel, and further electrically connected to the drain region 200D, so as to realize the current flow between the source region 200S, the conductive channel, the drift region 120N and the drain region 200D.

[0053] In a specific example, the source region 200S may at least partially extend to the bottom of the groove 100a, so that the end of the source region 200S may reach the bottom of the gate structure 200G. In this embodiment, the source region 200S is completely formed within the region below the groove 100a and extends downward from the bottom surface of the groove 100a. Based on this, the source metal 400S in this embodiment can be formed in the groove 100a and extend downward to the bottom surface of the groove 100a to be electrically connected to the source region 200S. It should be recognized that in other embodiments, the source region 200S may also be partially located within the region below the groove 100a, and the portion extends downward from the bottom surface of the groove 100a; and another portion of the source region 200S extends to the outside of the groove 100a in a direction away from the gate structure 200G, and extends to the top surface of the substrate outside the groove. At this time, the source metal 400S can be formed on the top surface of the substrate 100 to be connected to the source region 200S. Also, the drain region 200D is extended inward from the top surface of the substrate 100 , and the bottom of the drain metal 400D is abutted against the top surface of the substrate to be connected to the drain region 200D.

[0054] Continue to refer Figure 2As shown, the field plate structure 300 is formed on one side of the gate structure 200G close to the drain region 200D. Specifically, the field plate structure 300 is at least partially located within the region of the groove 100a, and the field plate structure 300 is at least partially located above the gate structure 200G, that is, there is a spatial overlap between the field plate structure 300 and the gate structure 200G. In addition, the top surface of the gate structure 200G is lower than the top position of the groove 100a, so that a space for the field plate structure 300 to extend longitudinally is reserved above the gate structure 200G, so that the bottom of the field plate structure 300 can be further extended downward into the groove 100a, so as to increase the longitudinal size of the field plate structure 300. Alternatively, it can also be considered that, without changing the overall longitudinal size of the field plate structure 300, since the field plate structure 300 can extend downward into the groove 100a, the height of the field plate structure 300 protruding from the top surface of the substrate can be reduced, which is beneficial to reducing the overall size of the device.

[0055] In a further solution, the field plate structure 300 is arranged close to the side wall of the groove 100a, so that the field plate structure 300 can cover the side wall of the groove 100a, so as to facilitate the electric field modulation of the drift region 120N. In a specific example, the gate structure 200G is arranged at a position closer to the drain region 200D relative to the center position of the groove 100a, and the field plate structure 300 extends laterally from the top of the gate structure 200G in a direction toward the drain region 200D, so as to cover the side wall of the groove 100a.

[0056] Continue to refer Figure 2 As shown, the LDMOS device further includes an insulating dielectric layer 500, which at least partially covers the gate structure 200G and extends in a direction toward the drain region 200D, and a field plate structure 300 is formed on the insulating dielectric layer 500. Therefore, when the field plate structure 300 also covers the sidewall of the groove 100a, the insulating dielectric layer 500 also covers the sidewall of the groove in the corresponding area. In this embodiment, the insulating dielectric layer 500 covers the top surface of the gate structure 200G close to the drain region 200D and extends in a direction toward the drain region 200D, so as to sequentially cover the sidewall of the groove 100a and the top surface of the substrate 100.

[0057] In addition, for medium and low voltage LDMOS devices, the field plate structure 300 used may be, for example, a contact hole field plate (CFP), which specifically includes a contact hole penetrating the interlayer dielectric layer 600 and an electrode material formed in the contact hole. In this example, the contact hole field plate (CFP) may be formed simultaneously with the source metal 400S and the drain metal 400D, and may be made of the same metal material.

[0058] The LDMOS device in this embodiment, by disposing the gate structure 200G in the groove 100a and allowing the bottom of the field plate structure 300 to further extend downward to the groove 100a, can improve the breakdown voltage of the device while maintaining the overall size of the device unchanged, thereby optimizing the withstand voltage performance of the device without affecting the on-resistance of the device. Figure 6 FIG. 2 schematically shows a comparison diagram of the withstand voltage performance of a conventional LDMOS device (having a planar gate with a gate structure disposed on the top surface of a substrate) and an LDMOS device provided by the present invention (having a recessed gate with a gate structure disposed in a recess), when performing a simulation experiment on breakdown voltage. Figure 6 The breakdown voltage of the conventional LDMOS device is 30V, while the breakdown voltage of the LDMOS device provided by the present invention can be increased to 42V.

[0059] <Example 2>

[0060] Different from the first embodiment, the field plate structure in this embodiment further extends laterally to the top surface of the substrate outside the groove in the direction toward the drain region, thereby increasing the lateral size of the field plate structure, improving the field plate capacitance, and further optimizing the voltage resistance performance of the device.

[0061] Figure 3 FIG. 1 is a schematic diagram of the structure of the LDMOS device in the second embodiment of the present invention. Figure 3 As shown, the field plate structure 300 covers the side of the gate structure 200G close to the drain region, and also covers the sidewall of the groove 100a, and further extends laterally to the top surface of the substrate outside the groove in a direction toward the drain region 200D. In this embodiment, the insulating dielectric layer 500 also sequentially covers the gate structure 200G, the sidewall of the groove 100a and the top surface of the substrate 100, and the field plate structure 300 is formed on the insulating dielectric layer 500.

[0062] It should be appreciated that in conventional LDMOS devices, the field plate structure only covers the top surface of the drift region (see, for example, Figure 1 As shown in the figure, however, the field plate structure 300 in this embodiment not only covers the top surface of the drift region 120N (corresponding to the top surface of the substrate), but also covers the side walls of the drift region 120N (corresponding to the side walls of the groove 100a), thereby increasing the coverage area of ​​the drift region 120N, so that the electric field modulation range of the drift region 120N is extended from the top surface to the side walls, and the average surface electric field is better, thereby effectively improving the breakdown voltage of the device.

[0063] <Example 3>

[0064] In this embodiment, the gate structure in the LDMOS device is arranged in a ring shape around the center of the groove, and the field plate structure is arranged in a ring shape at a position farther away from the center of the groove relative to the gate structure. In the specific example, the source region, the gate structure, the field plate structure and the drain region are arranged in sequence from the inner ring to the outer ring.

[0065] Figure 4 is a top view of the LDMOS device in the third embodiment of the present invention, Figure 5 FIG. 1 is a schematic cross-sectional view of the LDMOS device along the aa' direction in the third embodiment of the present invention. Figure 4 and Figure 5 As shown, the source region 200S is arranged in an inner ring, the gate structure 200G surrounds the periphery of the source region 200S, the field plate structure 300 surrounds the periphery of the gate structure 200G, and the inner ring portion of the field plate structure 300 close to the gate structure 200G is also formed on the gate structure 200G, and the drain region 200D surrounds the periphery of the field plate structure 300.

[0066] Furthermore, the groove 100a in the substrate 100 is formed in the central area of ​​the device. The groove 100a may be a circular groove, an elliptical groove, or a rectangular groove, for example. Figure 4 In the example, a circular groove is used as an example for explanation. In a specific example, the source region 200S can be formed at the center of the groove 100a, and the shape of the source region 200S matches the shape of the groove 100a, that is, the source region 200S can correspond to a circle, an ellipse or a rectangle. Alternatively, in another example, the source region 200S is an annular structure surrounding the center of the groove, and its shape can be, for example, a circular ring, an elliptical ring or an annular rectangle, and a well lead-out region of the second doping type can be formed at the center of the groove 100a.

[0067] Continue to refer Figure 4 and Figure 5 As shown, the gate structure 200G surrounds the periphery of the source region 200S. In a specific example, the gate structure 200G can be arranged on the inner side of the groove 100a along the sidewall of the groove 100a. And, the field plate structure 300 is located on the side of the gate structure 200G away from the center of the groove, and the field plate structure 300 is at least partially located within the area of ​​the groove 100a, and the portion can extend downward into the groove 100a. For example, the field plate structure 300 in the first embodiment is completely located within the area of ​​the groove 100a, while the field plate structure in the second embodiment is only partially located within the area of ​​the groove. In a specific example, the field plate structure 300 is arranged along the sidewall of the groove 100a so that a portion of the field plate structure 300 is located within the area of ​​the groove and extends downward and covers the sidewall of the groove 100a, and another portion of the field plate structure 300 is located outside the groove and covers the top surface of the substrate 100.

[0068] Similarly, the insulating dielectric layer 500 in this embodiment may also be a ring-shaped structure, which also covers the gate structure 200G and the sidewall of the groove 100a, and further extends to the top surface of the substrate.

[0069] Continue to refer Figure 4 and Figure 5 As shown, the drain region 200D surrounds the periphery of the field plate structure 300. In this embodiment, the insulating dielectric layer 500 extends in a direction toward the drain region and is closer to the drain region 200D than the field plate structure 300. Therefore, the drain region 200D in this embodiment surrounds the periphery of the insulating dielectric layer 500.

[0070] <Example 4>

[0071] In this embodiment, a method for preparing the LDMOS device as described above is described. Figure 7-Figure 10 A schematic structural diagram of an LDMOS device during its preparation process is shown in FIG.

[0072] First reference Figure 7 As shown, a substrate 100 is provided, in which a drift region 120N of a first doping type and a well region 120P of a second doping type are formed.

[0073] Furthermore, a groove 100a is formed in the substrate 100, and the bottom surface of the groove 100a exposes the well region 120P and a portion of the drift region 120N near the well region 120P. Also, the depth of the groove 100a can be adjusted according to actual needs, for example, the depth of the groove 100a can be less than or equal to 5 μm. In a specific example, the groove 100a can be a circular groove, an elliptical groove, a rectangular groove, etc.

[0074] Next reference Figure 8 As shown, a gate structure 200G is formed on the substrate 100 and is formed on the bottom surface of the groove 100a. Specifically, the gate structure 200G is disposed at the junction of the well region 120P and the drift region 120N to cover a portion of the well region 120P and a portion of the drift region 120N.

[0075] In a specific example, after forming the gate structure 200G, an insulating dielectric layer 500 is further formed, and the insulating dielectric layer 500 partially covers the gate structure 200G and extends the groove 100a laterally to cover the top surface of the substrate 100. In addition, a source region 200S and a drain region 200D are formed in the substrate 100, wherein the source region 200S is specifically formed in the well region 200P and is located at the side of the gate structure 200G. In this embodiment, the source region 200S is at least formed below the groove 100a so that it extends to the end of the gate structure 200G; the drain region 200D is formed outside the groove 100a and extends inward from the top surface of the substrate.

[0076] After the gate structure 200G is formed, a field plate structure 300 may be formed on the substrate 100. In this embodiment, the process of preparing the field plate structure is explained by taking the contact hole field plate as an example.

[0077] Specific reference Fig. 9 As shown, after forming the gate structure 200G, an interlayer dielectric layer 600 may be formed on the substrate 100, and the interlayer dielectric layer 600 covers the device region of the LDMOS device. When forming the interlayer dielectric layer 600, the material of the interlayer dielectric layer 600 may simultaneously fill the groove 100a; or, before forming the interlayer dielectric layer 600, the insulating material may be preferentially filled in the groove 100a.

[0078] Next reference Fig.10 As shown, a plurality of contact holes are formed in the interlayer dielectric layer 600, at least one of which is used to prepare a contact hole field plate, wherein the field plate contact hole 720 for preparing the field plate structure is at least partially located within the region of the groove 100a, and further extends downward into the groove after penetrating the interlayer dielectric layer 600. In this embodiment, the plurality of contact holes also include a source contact hole 710 and a drain contact hole 730, wherein the source contact hole 710 penetrates the interlayer dielectric layer 600 and extends downward to the bottom surface of the groove to expose a portion of the source region 200S; and the drain contact hole 730 penetrates the interlayer dielectric layer 600 to the top surface of the substrate to expose a portion of the drain region 200D.

[0079] Afterwards, each contact hole may be filled with a conductive material to form a contact hole field plate (ie, field plate structure 300 ), a source metal 400S, and a drain metal 400D, respectively.

[0080] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0081] It must be noted that as used herein and in the appended claims, the singular forms "a," "an," and "an" include plural references unless the context clearly indicates otherwise. For example, reference to "a step" or "a device" means reference to one or more steps or devices and may include secondary steps as well as secondary devices. All conjunctions used should be interpreted in the broadest sense. Also, the word "or" should be interpreted as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise.

Claims

1. An LDMOS device, characterized in that: include: A substrate having a groove formed therein; A gate structure, wherein the gate structure is formed on a bottom surface of the groove, and a top surface of the gate structure is lower than a top position of the groove; as well as, A field plate structure is at least partially located within the region of the groove and extends downward into the groove, and a portion of the field plate structure located within the groove is at least formed above the gate structure.

2. The LDMOS device according to claim 1, characterized in that The field plate structure is disposed at a position close to a side wall of the groove and covers the side wall of the groove.

3. The LDMOS device according to claim 2, characterized in that: The field plate structure further extends to the outside of the groove in a direction toward the drain region to extend onto the top surface of the substrate.

4. The LDMOS device according to claim 1, wherein: The gate structure is disposed at a position closer to the drain region than a central position of the groove.

5. The LDMOS device according to claim 1, wherein: Also includes: The insulating dielectric layer at least covers the gate structure and forms the field plate structure on the insulating dielectric layer.

6. The LDMOS device according to claim 1, wherein: Also includes: A source region and a drain region, wherein the source region is at least partially formed below the groove and extends downward from the bottom surface of the groove, and the drain region is located on a side of the field plate structure away from the source region and extends downward from the top surface of the substrate.

7. The LDMOS device according to claim 1, characterized in that: The field plate structure includes a contact hole field plate.

8. The LDMOS device according to any one of claims 1 to 7, characterized in that: The gate structure is disposed in a ring shape around the center of the groove, and the field plate structure is disposed in a ring shape at a position farther away from the center of the groove relative to the gate structure.

9. The LDMOS device according to any one of claims 8, characterized in that: The LDMOS device also includes a source region and a drain region, wherein the source region, the gate structure, the field plate structure and the drain region are arranged in sequence from an inner ring to an outer ring, wherein the source region is formed in a central area of ​​the groove, and the drain region surrounds the outer side of the groove.

10. A method for preparing the LDMOS device according to any one of claims 1 to 9, characterized in that: include: Providing a substrate and forming a groove in the substrate; forming a gate structure on the bottom surface of the groove, wherein the top surface of the gate structure is lower than the top position of the groove; as well as, A field plate structure is formed on the substrate, wherein the field plate structure is at least partially located within the region of the groove and extends downward into the groove, and a portion of the field plate structure located within the groove is at least formed above the gate structure.

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