Semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor structure and a method for manufacturing the same. The method sequentially forms a shielding layer and a photoresist layer, patterns the photoresist layer through a single exposure and development process, and etches to obtain a shielding layer opening located below the photoresist layer opening. Based on the photoresist layer opening and the shielding layer opening, a first ion implantation is performed on the semiconductor layer to obtain a first doped region. The photoresist layer and the shielding layer are then trimmed to expand the photoresist layer opening and the shielding layer opening. Based on the expanded photoresist layer opening and the shielding layer opening, a second ion implantation is performed on the semiconductor layer to obtain a second doped region. The photoresist layer and the shielding layer are then removed. The present invention improves the manufacturing process steps by introducing a shielding layer before the photoresist layer to achieve the effect of shielding the ion implantation, thereby reducing the thickness of the photoresist layer. Patterning is achieved using a thin photoresist thickness, enabling low-end products to produce photoresist patterns using Canon lithography equipment with a single low-energy exposure. This allows for better utilization of the equipment and addresses the problem of insufficient production capacity of ASML lithography equipment.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The BCD process combines bipolar, CMOS, and DMOS power devices on the same chip, leveraging the high transconductance and strong load-driving capability of bipolar devices with the high integration and low power consumption of CMOS, leveraging their respective strengths. Furthermore, DMOS can operate in switching mode, consuming extremely low power. Typical BCD process devices include low-voltage CMOS, high-voltage MOS transistors, LDMOS with various breakdown voltages, vertical NPN / PNP, and Schottky diodes. Some processes also integrate devices such as JFETs and EEPROMs.

[0003] In some high-voltage devices using the BCD process, the high-voltage P-type body (HVPB) has a T-shaped longitudinal cross-section. Forming this body requires trimming the photoresist and performing two ion implantations, one before and one after. Therefore, a thicker photoresist (PR) is needed to block the ion implantation. Currently, due to the thickness of the photoresist layer, Canon lithography equipment cannot fully expose the photoresist layer in a single exposure, necessitating a double exposure. However, this double exposure process not only poses issues with photoresist residue, but also presents issues such as pattern shift and a smaller process window. Therefore, high-end ASML lithography equipment is required, resulting in wasted equipment.

[0004] Therefore, how to improve the process steps so that low-end products can be exposed in one time using Canon equipment to obtain a doped region with a T-shaped longitudinal cross-section has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the problems of insufficient exposure equipment production capacity and small process window when forming a doped region with a T-shaped longitudinal cross-section in the prior art.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0008] forming a shielding layer on the semiconductor layer, wherein a plurality of gate structures spaced apart are formed on the semiconductor layer, and the shielding layer covers the gate structures;

[0009] forming a photoresist layer on the shielding layer, and making the photoresist layer developable in a predetermined area by a single exposure;

[0010] Patterning the photoresist layer by development to obtain a photoresist layer opening located in the predetermined area, wherein at least one of the photoresist layer openings is located between two adjacent gate structures, and a width of the photoresist layer opening is smaller than a distance between the two adjacent gate structures;

[0011] Etching the shielding layer based on the patterned photoresist layer to obtain a shielding layer opening located below the photoresist layer opening;

[0012] Performing a first ion implantation on the semiconductor layer based on the photoresist layer opening and the shielding layer opening to obtain a first doped region, wherein the first doped region extends downward from the top surface of the semiconductor layer by a first distance;

[0013] trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening, wherein the enlarged shielding layer opening exposes the sidewall of the gate structure;

[0014] performing a second ion implantation on the semiconductor layer based on the enlarged opening of the photoresist layer and the opening of the shielding layer to obtain a second doped region, wherein the second doped region extends downward from the top surface of the semiconductor layer by a second distance, the width of the second doped region is greater than the width of the first doped region, and the bottom surface of the second doped region is higher than the bottom surface of the first doped region;

[0015] The photoresist layer and the shielding layer are removed.

[0016] Optionally, the shielding layer comprises a carbon layer.

[0017] Optionally, the method of etching the shielding layer based on the patterned photoresist layer includes anisotropic dry etching.

[0018] Optionally, the method of trimming the photoresist layer and the shielding layer to expand the photoresist layer opening and the shielding layer opening comprises isotropic dry etching.

[0019] Optionally, the method of removing the photoresist layer and the shielding layer includes an ashing process, and both the photoresist layer and the shielding layer are removed during the ashing process.

[0020] Optionally, removing the photoresist layer and the shielding layer comprises the following steps:

[0021] removing the photoresist layer by ashing;

[0022] The shielding layer is removed by dry etching.

[0023] Optionally, the shielding layer includes an aluminum layer, a copper layer or an aluminum-copper alloy layer.

[0024] Optionally, the method of etching the shielding layer based on the patterned photoresist layer includes dry etching or wet etching.

[0025] Optionally, trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening comprises the following steps:

[0026] trimming the photoresist layer by isotropic dry etching;

[0027] The shielding layer is trimmed by dry etching or wet etching.

[0028] Optionally, removing the photoresist layer and the shielding layer comprises the following steps:

[0029] removing the photoresist layer by ashing;

[0030] The shielding layer is removed by dry etching or wet etching.

[0031] The present invention also provides a semiconductor structure, comprising:

[0032] semiconductor layer;

[0033] A plurality of gate structures are located on the semiconductor layer and spaced apart;

[0034] a P-type body region located in the semiconductor layer and between two adjacent gate structures, the P-type body region comprising a first doped region and a second doped region, the first doped region and the second doped region both extending downward from a top surface of the semiconductor layer, the second doped region having a width greater than a width of the first doped region, and a bottom surface of the second doped region being higher than a bottom surface of the first doped region;

[0035] The semiconductor structure is formed by any one of the above methods for manufacturing a semiconductor structure.

[0036] As described above, the present invention provides a semiconductor structure and a method for manufacturing the same, comprising the following steps: sequentially forming a shielding layer and a photoresist layer, developing the photoresist layer in a predetermined area through a single exposure, developing to obtain a photoresist layer opening, etching to obtain a shielding layer opening located below the photoresist layer opening, performing a first ion implantation on the semiconductor layer based on the photoresist layer opening and the shielding layer opening to obtain a first doped region, trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening, performing a second ion implantation on the semiconductor layer based on the enlarged photoresist layer opening and the shielding layer opening to obtain a second doped region, and then removing the photoresist layer and the shielding layer. The method of the present invention improves the manufacturing process steps by forming a shielding layer before the photoresist layer to shield the ion implantation, thereby reducing the thickness of the photoresist layer and achieving patterning with a thin photoresist thickness. This allows low-end products to use Canon lithography equipment to produce photoresist patterns using a single low-energy exposure, and then complete the shielding layer patterning through etching. This not only expands the process window and improves lithography issues, but also allows for better utilization of equipment, solving the problem of insufficient production capacity of ASML lithography equipment. Compared with the double-exposure solution, the semiconductor structure manufactured by the method of the present invention has fewer defects and a higher yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a process flow chart of a method for manufacturing a semiconductor structure of the present invention.

[0038] Figure 2 Schematic diagram showing a structure obtained after forming a shielding layer on a semiconductor layer in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0039] Figure 3 FIG2 is a schematic diagram showing the exposure of a photoresist layer in an embodiment of a method for manufacturing a semiconductor structure according to the present invention.

[0040] Figure 4 FIG2 is a schematic diagram showing a structure obtained after patterning a photoresist layer by development in an embodiment of a method for manufacturing a semiconductor structure according to the present invention.

[0041] Figure 5 Schematic diagram showing a structure obtained after etching to obtain an opening in the shielding layer in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0042] Figure 6 Schematic diagram showing a structure obtained after a first ion implantation is performed to obtain a first doped region in an embodiment of a method for fabricating a semiconductor structure according to the present invention.

[0043] Figure 7 Schematic diagram showing a structure obtained after trimming the photoresist layer and the shielding layer in one embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0044] Figure 8 Schematic diagram showing a structure obtained after a second ion implantation is performed to obtain a second doped region in an embodiment of a method for fabricating a semiconductor structure according to the present invention.

[0045] Figure 9 Schematic diagram showing a structure obtained after removing the photoresist layer and the shielding layer in one embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0046] Description of Reference Numerals

[0047] Steps S1 to S8

[0048] 1 shielding layer

[0049] 2 Semiconductor layer

[0050] 3 Gate structure

[0051] 4 Photoresist layer

[0052] 5 Photomask

[0053] 6 Photoresist layer opening

[0054] 7 Shelter opening

[0055] 8 First doping region

[0056] 9 Second doping region DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] See also Figures 1 to 9 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0059] The present invention provides a method for manufacturing a semiconductor structure. Figure 1 , shown as a process flow diagram of the method, comprising the following steps:

[0060] S1: forming a shielding layer on a semiconductor layer, wherein a plurality of gate structures spaced apart are formed on the semiconductor layer, and the shielding layer covers the gate structures;

[0061] S2: forming a photoresist layer on the shielding layer, and making the photoresist layer developable in a predetermined area by a single exposure;

[0062] S3: patterning the photoresist layer by development to obtain photoresist layer openings located in the predetermined area, wherein at least one photoresist layer opening is located between two adjacent gate structures, and a width of the photoresist layer opening is smaller than a distance between the two adjacent gate structures;

[0063] S4: etching the shielding layer based on the patterned photoresist layer to obtain a shielding layer opening located below the photoresist layer opening;

[0064] S5: performing a first ion implantation on the semiconductor layer based on the openings in the photoresist layer and the openings in the shielding layer to obtain a first doped region, wherein the first doped region extends downward from a top surface of the semiconductor layer by a first distance;

[0065] S6: trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening, wherein the enlarged shielding layer opening exposes the sidewall of the gate structure;

[0066] S7: performing a second ion implantation on the semiconductor layer based on the enlarged opening of the photoresist layer and the opening of the shielding layer to obtain a second doped region, wherein the second doped region extends downward from the top surface of the semiconductor layer by a second distance, the width of the second doped region is greater than the width of the first doped region, and the bottom surface of the second doped region is higher than the bottom surface of the first doped region;

[0067] S8: removing the photoresist layer and the shielding layer, and then removing dirt by wet cleaning.

[0068] Specifically, the present invention introduces a shielding layer that can block ion injection before the photoresist layer, which can effectively reduce the thickness of the subsequent photoresist layer and achieve the effect of using a photoresist layer with a thinner thickness to achieve patterning. In this way, the exposure process can be completed through a single exposure using Canon lithography equipment (with relatively low exposure energy), and then the photoresist layer is patterned through development, and the shielding layer is patterned through etching. This can not only expand the process window and improve lithography problems, but also make better use of the equipment and solve the problem of insufficient production capacity of ASML lithography equipment.

[0069] Specifically, the shielding layer is preferably made of a material that is easily ashed and has a high shielding effect on ion implantation, such as carbon (C), so as to avoid contaminating the previous layer structure and achieve the purpose of easy removal.

[0070] The specific execution process of the above steps when the shielding layer is a carbon layer will be described in detail below with reference to the structural diagram.

[0071] First see Figure 2 , performing the step S1: forming a shielding layer 1 on the semiconductor layer 2 , a plurality of gate structures 3 spaced apart are formed on the semiconductor layer 2 , and the shielding layer 1 covers the gate structures 3 .

[0072] Specifically, the semiconductor structure to be manufactured by the present invention can be a BCD semiconductor device or other types of devices. In actual implementation, depending on the specific device type, the semiconductor layer 2 can include silicon, silicon carbide or other suitable semiconductor substrates, or can include a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. Other required doping regions, components, etc. can be pre-formed in the semiconductor layer 2.

[0073] Specifically, the shielding layer 1, which is a carbon layer, can be deposited on the semiconductor layer 2 by chemical vapor deposition or other suitable methods. The shielding layer 1 covers the gate structure 3 and fills the gap between adjacent gate structures. The thickness of the carbon layer used as the shielding layer can be set according to the ions to be subsequently implanted. For example, the heavier the implanted ions, the thicker the carbon layer required to achieve a better shielding effect.

[0074] By way of example, the chemical vapor deposition method may be, but is not limited to, low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or plasma-enhanced chemical vapor deposition (PECVD). These methods differ in the density of the carbon layer produced. In a preferred embodiment of the present invention, atmospheric pressure chemical vapor deposition is preferably used based on the requirements for the shielding layer and the difficulty of ashing.

[0075] See also Figure 3 , executing step S2: forming a photoresist layer 4 on the shielding layer 1 by spin coating or other suitable methods, and making the photoresist layer 4 in a predetermined area developable by one exposure based on the mask 5.

[0076] As an example, the photoresist layer 4 is made of positive photoresist, and the exposed area can be removed during the development process.

[0077] Specifically, the thickness of the photoresist layer 4 can be adjusted as needed, as long as the existing Canon exposure equipment can complete the exposure process in one exposure. In one embodiment, the thickness ratio of the carbon layer as the shielding layer 1 to the thickness of the photoresist layer 4 is 10:1-2.

[0078] See also Figure 4 , performing step S3: patterning the photoresist layer 4 by development to obtain a photoresist layer opening 6 located in the preset area, at least one photoresist layer opening 6 is located between two adjacent gate structures 3, and the width of the photoresist layer opening 6 is smaller than the distance between the two adjacent gate structures 3.

[0079] See also Figure 5 , executing step S4: etching the shielding layer 1 based on the patterned photoresist layer 4 to obtain a shielding layer opening 7 located below the photoresist layer opening 6.

[0080] As an example, a method for etching the shielding layer 1 based on the patterned photoresist layer 4 includes anisotropic dry etching.

[0081] As an example, the gas used in the anisotropic dry etching includes oxygen, nitrogen, argon or other non-oxidizing gases. By adjusting the proportion of each gas and other related parameters, the pattern of the photoresist layer 4 does not change too much while the shielding layer 1 is etched and patterned.

[0082] In one embodiment, the etching gas selected for anisotropic dry etching of the shielding layer 1 includes Ar as a physical etching gas, and includes O2, N2 and N2H2 as chemical etching gases. The flow rate is controlled so that the molar ratio of the gas in the etching chamber satisfies O2:N2:N2H2=100:1:(3~5), wherein the etching rate can be increased by adjusting the volume ratio of Ar (for example, adjusting within the volume ratio range of 40%~70%). During the etching process, high pressure conditions (greater than atmospheric pressure, for example, 1~3 times atmospheric pressure) and relatively high energy (bias) are adopted, so that the final etching process is mainly physical etching, supplemented by chemical etching, to achieve anisotropic etching.

[0083] See also Figure 6 , executing step S5: performing a first ion implantation on the semiconductor layer 2 based on the photoresist layer opening 6 and the shielding layer opening 7 to obtain a first doped region 8, wherein the first doped region 8 extends downward from the top surface of the semiconductor layer 2 by a first distance.

[0084] Specifically, the depth of the first ion implantation can be controlled by adjusting the energy of the ion implantation. The specific value of the first distance can be set according to the required device performance, and is not specifically limited in the present invention.

[0085] See also Figure 7 , executing step S6 : trimming the photoresist layer 4 and the shielding layer 1 to enlarge the photoresist layer opening 6 and the shielding layer opening 7 , wherein the enlarged shielding layer opening 7 exposes the sidewall of the gate structure 3 .

[0086] As an example, a method of trimming the photoresist layer 4 and the shielding layer 1 to enlarge the photoresist layer opening 6 and the shielding layer opening 7 includes isotropic dry etching.

[0087] As an example, the gas used in the isotropic dry etching includes oxygen.

[0088] In one embodiment, isotropic dry etching is used to expand the photoresist layer opening 6 and the shielding layer opening 7. The etching gases selected include O2 and N2, and include Ar as a physical etching gas (the volume ratio range is 40% to 70%). By controlling the flow rate, the molar ratio of the gas in the etching chamber satisfies O2:N2=100:(1~5). Normal pressure conditions are used during the etching process, and relatively low energy (bias voltage) is used to weaken the overall plasma directionality. Therefore, the etching process is mainly chemical etching, supplemented by physical etching, to achieve isotropic etching.

[0089] It should be noted that dry etching is generally based on anisotropic etching, but in the manufacturing process, the directionality of the etching plasma can be weakened by weakening the bias voltage and increasing the radio frequency (RF) voltage range, so that the etching process is finally transformed from physical etching to chemical etching, achieving the effect of isotropic etching.

[0090] See also Figure 8 , executing step S7: performing a second ion implantation on the semiconductor layer 2 based on the enlarged photoresist layer opening 6 and the shielding layer opening 7 to obtain a second doping region 9, wherein the second doping region 9 extends downward from the top surface of the semiconductor layer 2 by a second distance, the width of the second doping region 9 is greater than the width of the first doping region 8, and the bottom surface of the second doping region 9 is higher than the bottom surface of the first doping region 8, so that the longitudinal cross-section of the doping region composed of the first doping region 8 and the second doping region 9 is T-shaped.

[0091] Specifically, the depth of the second ion implantation can be controlled by adjusting the energy of the ion implantation, and the second distance is smaller than the first distance. The specific value of the second distance can be set according to the required device performance, and is not specifically limited in the present invention.

[0092] See also Figure 9 , executing step S8: removing the photoresist layer 4 and the shielding layer 1.

[0093] In one embodiment, the method of removing the photoresist layer 4 and the shielding layer 1 includes an ashing process. The photoresist layer 4 and the shielding layer 1 are both removed during the ashing process, which can reduce process load and side effects.

[0094] In one embodiment, the etching gases selected for the ashing process include O2, N2, N2H2, and Ar. The flow rate is controlled so that the molar ratio of the gases in the etching chamber satisfies O2:N2:N2H2=100:1:(3-5). The etching rate can be increased by adjusting the volume ratio of Ar (40% to 70%). High pressure conditions (greater than atmospheric pressure, for example, 1 to 3 times atmospheric pressure) and relatively high energy (bias) are used during the etching process.

[0095] In another embodiment, the shielding layer 1 may also be removed separately, that is, the photoresist layer 4 may be removed by ashing first, and then the shielding layer 1 may be removed by dry etching.

[0096] As an example, before removing the photoresist layer 4 and the shielding layer 1 , conventional wet cleaning may be used to remove surface dirt.

[0097] At this point, a semiconductor structure with a T-shaped longitudinal cross-section doped region is produced. In the above embodiment, the shielding layer 1 is a carbon layer, which has the advantage that it can be removed cleanly at one time together with the photoresist layer 4 through an ashing process without increasing the process and without affecting the previous film layer, or it can be easily removed alone through dry etching, with little impact on the quality of the previous film layer.

[0098] In other implementations, the shielding layer 1 may also be an aluminum layer, a copper layer, or an aluminum-copper alloy layer.

[0099] It should be pointed out that, because there are multiple gate structures spaced apart on the semiconductor layer before the shielding layer is formed, after the metal layer is deposited, the metal layer in the area with the gate structure is thinner, and the metal layer in the area without the gate structure is thicker, that is, the thickness of the metal layer is uneven. In the subsequent step of removing the metal layer, while ensuring that the metal layer in the area with a thicker thickness is completely etched, the polysilicon in the area with a thinner thickness may be affected. If the shielding layer adopts a carbon layer that is easier to remove, the ashing process can be used to completely remove the shielding layer without affecting the quality of the previous film layer. Therefore, the shielding layer 1 in the present invention adopts a carbon layer as a more preferred solution. However, compared with other metal layers, such as a tungsten (W) layer, the present invention adopts an aluminum layer, a copper layer or an aluminum-copper alloy layer as a shielding layer. Whether it is wet etching or dry etching, it is easier to completely remove it, and has less impact on subsequent processes. If a tungsten layer is used, it is difficult to accurately control the complete removal of W using dry etching, which has a greater impact on subsequent processes.

[0100] As an example, when the shielding layer 1 is made of aluminum, copper or aluminum-copper alloy, it is more preferable to use aluminum as the shielding layer 1 than copper or aluminum-copper alloy because the material cost is lower and it is relatively easier to remove.

[0101] As an example, when the shielding layer 1 is made of an aluminum layer, a copper layer or an aluminum-copper alloy layer, in the above step S4, when the shielding layer 1 is etched based on the patterned photoresist layer 4 to obtain a shielding layer opening 7 located below the photoresist layer opening 6, the etching method may include dry etching or wet etching.

[0102] As an example, when the shielding layer 1 is made of an aluminum layer, a copper layer or an aluminum-copper alloy layer, when trimming the photoresist layer 4 and the shielding layer 1 in the above step S6 to expand the photoresist layer opening 6 and the shielding layer opening 7, the photoresist layer 4 can be trimmed by isotropic dry etching first, and then the shielding layer 1 can be trimmed by dry etching or wet etching.

[0103] As an example, when the shielding layer 1 is made of an aluminum layer, a copper layer or an aluminum-copper alloy layer, when removing the photoresist layer 4 and the shielding layer 1 in the above step S8, the photoresist layer 4 can be first removed by ashing, and then the shielding layer 1 can be removed by dry etching or wet etching, and then conventional wet cleaning can be further used to remove surface dirt.

[0104] In one embodiment, the main components of the etching solution used to remove the shielding layer 1 by wet etching include Cu 2 + 、H2O2、H + 、NO 3- 、Cl - , and includes stabilizers.

[0105] In one embodiment, the etching gas used to remove the shielding layer 1 by dry etching includes at least one of Cl 2 and BCl 3 .

[0106] The present invention also provides a semiconductor structure, which can be formed using the manufacturing method of any of the above embodiments, the semiconductor structure includes a semiconductor layer, multiple gate structures and a P-type body region, wherein the multiple gate structures are located on the semiconductor layer and are arranged at intervals, the P-type body region is located in the semiconductor layer and between two adjacent gate structures, the P-type body region includes a first doping region and a second doping region, the first doping region and the second doping region both extend downward from the top surface of the semiconductor layer, the width of the second doping region is greater than the width of the first doping region, and the bottom surface of the second doping region is higher than the bottom surface of the first doping region.

[0107] As an example, the semiconductor structure may be a device using a BCD process or other types of devices.

[0108] In some embodiments, a P-well and an N-type drift region are formed in the semiconductor layer, the N-type drift region is located in the P-well, and the bottom surface of the N-type drift region is higher than the bottom surface of the P-well, the P-type body region is located in the N-type drift region, and the first doped region of the P-type body region passes through the bottom surface of the N-type drift region and is connected to the P-well.

[0109] In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, the manufacturing method comprising the following steps: sequentially forming a shielding layer and a photoresist layer, developing the photoresist layer in a preset area through a single exposure, developing to obtain a photoresist layer opening, and etching to obtain a shielding layer opening located below the photoresist layer opening, performing a first ion implantation on the semiconductor layer based on the photoresist layer opening and the shielding layer opening to obtain a first doped region, then trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening, and performing a second ion implantation on the semiconductor layer based on the enlarged photoresist layer opening and the shielding layer opening to obtain a second doped region, and then removing the photoresist layer and the shielding layer. The method of the present invention improves the manufacturing process by forming a shielding layer before the photoresist layer to shield ion implantation, thereby reducing the thickness of the photoresist layer. Using a thin photoresist thickness for patterning, this method enables low-end products to use Canon lithography equipment to create photoresist patterns in a single, low-energy exposure, followed by etching to complete the shielding layer patterning. This not only expands the process window and improves lithography issues, but also allows for better equipment utilization, addressing the insufficient production capacity of ASML lithography equipment. Compared to a two-exposure approach, semiconductor structures produced using the method of the present invention have fewer defects and a higher yield. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial value.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: forming a shielding layer on the semiconductor layer, wherein a plurality of gate structures spaced apart are formed on the semiconductor layer, and the shielding layer covers the gate structures; forming a photoresist layer on the shielding layer, and making the photoresist layer developable in a predetermined area by a single exposure; Patterning the photoresist layer by development to obtain a photoresist layer opening located in the predetermined area, wherein at least one of the photoresist layer openings is located between two adjacent gate structures, and a width of the photoresist layer opening is smaller than a distance between the two adjacent gate structures; Etching the shielding layer based on the patterned photoresist layer to obtain a shielding layer opening located below the photoresist layer opening; Performing a first ion implantation on the semiconductor layer based on the photoresist layer opening and the shielding layer opening to obtain a first doped region, wherein the first doped region extends downward from the top surface of the semiconductor layer by a first distance; trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening, wherein the enlarged shielding layer opening exposes the sidewall of the gate structure; performing a second ion implantation on the semiconductor layer based on the enlarged opening of the photoresist layer and the opening of the shielding layer to obtain a second doped region, wherein the second doped region extends downward from the top surface of the semiconductor layer by a second distance, the width of the second doped region is greater than the width of the first doped region, and the bottom surface of the second doped region is higher than the bottom surface of the first doped region; The photoresist layer and the shielding layer are removed.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The shielding layer includes a carbon layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The method of etching the shielding layer based on the patterned photoresist layer includes anisotropic dry etching.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The method of trimming the photoresist layer and the shielding layer to expand the photoresist layer opening and the shielding layer opening includes isotropic dry etching.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein: The method for removing the photoresist layer and the shielding layer includes an ashing process, and both the photoresist layer and the shielding layer are removed during the ashing process.

6. The method for manufacturing a semiconductor structure according to claim 2, wherein: Removing the photoresist layer and the shielding layer includes the following steps: removing the photoresist layer by ashing; The shielding layer is removed by dry etching.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The shielding layer includes an aluminum layer, a copper layer or an aluminum-copper alloy layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The method of etching the shielding layer based on the patterned photoresist layer includes dry etching or wet etching.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein: Trimming the photoresist layer and the shielding layer to enlarge the photoresist layer opening and the shielding layer opening comprises the following steps: trimming the photoresist layer by isotropic dry etching; The shielding layer is trimmed by dry etching or wet etching.

10. The method for manufacturing a semiconductor structure according to claim 7, wherein: Removing the photoresist layer and the shielding layer includes the following steps: removing the photoresist layer by ashing; The shielding layer is removed by dry etching or wet etching.

11. A semiconductor structure comprising: semiconductor layer; A plurality of gate structures are located on the semiconductor layer and spaced apart; a P-type body region located in the semiconductor layer and between two adjacent gate structures, the P-type body region comprising a first doped region and a second doped region, the first doped region and the second doped region both extending downward from a top surface of the semiconductor layer, the second doped region having a width greater than a width of the first doped region, and a bottom surface of the second doped region being higher than a bottom surface of the first doped region; The semiconductor structure is formed by using the method for manufacturing a semiconductor structure according to any one of claims 1 to 10.

Images