Complementary field effect transistor and manufacturing method thereof, memory device and electronic equipment

Abstract

The invention provides a complementary field effect transistor, a manufacturing method of the complementary field effect transistor, a memory device and electronic equipment. The complementary field effect transistor comprises an N-type field effect transistor, a P-type field effect transistor and a first isolation layer, wherein the N-type field effect transistor and the P-type field effect transistor are distributed in a stacked mode, and the first isolation layer is located between the N-type field effect transistor and the P-type field effect transistor and extends horizontally. The N-type field effect transistor and the P-type field effect transistor share a common grid electrode extending in the vertical direction. The N-type field effect transistor comprises a first channel layer surrounding the common grid electrode, and a first source electrode and a first drain electrode which surround the common grid electrode and are connected with the first channel layer; the P-type field effect transistor comprises a second channel layer surrounding the common grid electrode and a second source electrode and a second drain electrode which surround the common grid electrode and are connected with the second channel layer, the first isolation layer comprises a silicon oxide isolation layer or at least two groups of pn junction isolation layers, and each group of pn junction isolation layers comprises one N-type doping layer and one P-type doping layer. The device architecture provided by the invention can effectively inhibit current leakage.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a complementary field effect transistor and a manufacturing method thereof, a memory device, and an electronic device. Background Art

[0002] Complementary field effect transistor (CMOS) technology utilizes P-channel and N-channel semiconductor devices and is widely used in microprocessors and various memories. However, as the size of devices shrinks, higher requirements are placed on the structure and manufacturing process of CMOS devices. Summary of the invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] In one aspect, an exemplary embodiment of the present application provides a complementary field effect transistor, comprising a stacked N-type field effect transistor and a P-type field effect transistor, and a first isolation layer located between the N-type field effect transistor and the P-type field effect transistor and extending horizontally;

[0005] The N-type field effect transistor and the P-type field effect transistor share a common gate extending in a vertical direction;

[0006] The N-type field effect transistor includes a first channel layer surrounding the common gate, and a first source and a first drain surrounding the common gate and connected to the first channel layer; the P-type field effect transistor includes a second channel layer surrounding the common gate, and a second source and a second drain surrounding the common gate and connected to the second channel layer, the first isolation layer includes a silicon oxide isolation layer or at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one N-type doped layer and one P-type doped layer, and the N-type doped layers and the P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0007] In an exemplary embodiment, the pn junction isolation layer includes three groups of pn junction isolation layers.

[0008] In an exemplary embodiment, the main surface of the first channel layer surrounding the common gate extends vertically, and the first source and the first drain both surround the first channel layer and contact the main surface of the first channel layer and are spaced apart in the vertical direction; the main surface of the second channel layer surrounding the common gate extends vertically, and the second source and the second drain both surround the second channel layer and contact the main surface of the second channel layer and are spaced apart in the vertical direction.

[0009] In an exemplary embodiment, a horizontally extending second isolation layer is included between the first source and the first drain, and the second isolation layer is in contact with the main surface of the first channel layer, the first source, and the first drain; a horizontally extending third isolation layer is included between the second source and the second drain, and the third isolation layer is in contact with the main surface of the second channel layer, the second source, and the second drain.

[0010] In an exemplary embodiment, the second isolation layer and the third isolation layer each include a silicon oxide isolation layer.

[0011] In an exemplary embodiment, the main surface of the first channel layer surrounding the common gate extends horizontally and is located between the first source layer and the first drain layer extending horizontally; the main surface of the second channel layer surrounding the common gate extends horizontally and is located between the second source layer and the second drain layer extending horizontally.

[0012] In an exemplary embodiment, the first channel layer of the N-type field effect transistor includes N-type doped single crystal silicon; and the second channel layer of the P-type field effect transistor includes P-type doped single crystal silicon.

[0013] In an exemplary embodiment, the first source and the first drain of the N-type field effect transistor are N-type heavily doped single crystal silicon; the second source and the second drain of the P-type field effect transistor are P-type heavily doped single crystal silicon.

[0014] In an exemplary embodiment, the doping concentration of the first source and the first drain of the N-type field effect transistor is greater than the doping concentration of the first channel layer; the doping concentration of the second source and the second drain of the P-type field effect transistor is greater than the doping concentration of the second channel layer.

[0015] In an exemplary embodiment, the first source and the first drain of the N-type field effect transistor may have the same doping type as the first channel; the second source and the second drain of the P-type field effect transistor may have the same doping type as the second channel.

[0016] The channel layer of the p-type field effect transistor and the n-type field effect transistor share a substrate, and the substrate is a silicon substrate on an insulating layer.

[0017] On the one hand, an exemplary embodiment of the present application provides a complementary field effect transistor, comprising an N-type field effect transistor and the P-type field effect transistor and a first isolation layer located between the N-type field effect transistor and the P-type field effect transistor and extending horizontally; the N-type field effect transistor comprises a first source, a second isolation layer and a first drain extending horizontally and stacked vertically; the P-type field effect transistor comprises a second source, a third isolation layer and a second drain extending horizontally and stacked vertically; the N-type field effect transistor and the P-type field effect transistor further comprise a common gate, the common gate extending vertically through the second drain, the third isolation layer, the second source, the first isolation layer, the first drain and the third isolation layer and terminating at a side of the first source away from the second isolation layer; the N-type field effect transistor further comprises a first channel layer surrounding the common gate and extending vertically through the first drain and the second isolation layer and terminating at a side of the first source away from the second isolation layer; the P-type field effect transistor further comprises a second channel layer surrounding the common gate and extending vertically through the second drain and the third isolation layer and terminating at a side of the second source away from the third isolation layer;

[0018] The first isolation layer includes a silicon oxide isolation layer or at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0019] In an exemplary embodiment, the first source and the first drain both surround the first channel layer and contact the vertically extending main surface of the first channel layer and are spaced apart in the vertical direction; the second source and the second drain both surround the second channel layer and contact the vertically extending main surface of the second channel layer and are spaced apart in the vertical direction.

[0020] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a complementary field effect transistor, comprising the following steps:

[0021] Forming a stacked structure including a heavily N-type doped first source layer, a second isolation layer, a heavily N-type doped first drain layer, a first isolation layer, a heavily P-type doped second source layer, a third isolation layer, and a heavily P-type doped second drain layer in sequence on a substrate by epitaxial growth;

[0022] forming an annular groove penetrating the stacked structure and terminating at a side of the substrate close to the first source layer, and sequentially epitaxially growing an N-type doping material, a first isolation layer material, and a P-type doping material in the annular groove to form a first channel layer, a first isolation layer, and a second channel layer, respectively; and

[0023] forming a vertically extending common gate common to the N-type transistor and the P-type transistor;

[0024] The three isolation layers each include at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0025] In an exemplary embodiment, forming the common gate may include:

[0026] After sequentially epitaxially growing an N-type doping material, a first isolation layer material, and a P-type doping material in the annular groove to form a first channel layer, a first isolation layer, and a second channel layer, respectively, the material of the stacked structure in the annular groove is removed to form a through-hole structure penetrating the stacked structure and terminating at a side of the substrate close to the first source layer;

[0027] An insulating layer film and a conductive material film are sequentially deposited on the inner wall of the gate through hole to form a gate insulating layer and a common gate.

[0028] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a complementary field effect transistor, comprising the following steps:

[0029] Forming a stacked structure including a heavily N-type doped first source layer, a second sacrificial layer, a heavily N-type doped first drain layer, a first sacrificial layer, a heavily P-type doped second source layer, a third sacrificial layer, and a heavily P-type doped second drain layer in sequence on a substrate by epitaxial growth;

[0030] forming an annular groove penetrating the stacked structure and terminating at a side of the substrate close to the first source layer, and sequentially epitaxially growing an N-type doping material, a first sacrificial layer material, and a P-type doping material in the annular groove to form a first channel layer, a first sacrificial layer, and a second channel layer, respectively; and

[0031] forming a vertically extending common gate common to the N-type transistor and the P-type transistor;

[0032] Removing materials from the first sacrificial layer, the second sacrificial layer and the third sacrificial layer to form six isolation trenches on both sides of the common gate;

[0033] Filling the six isolation trenches with an isolation layer material to form a first isolation layer, a second isolation layer, and a third isolation layer;

[0034] The sacrificial layer comprises a GeSi sacrificial layer, and the three isolation layers comprise a silicon oxide isolation layer or at least two groups of pn junction isolation layers.

[0035] In yet another aspect, an exemplary embodiment of the present application provides a memory device including any one of the above complementary field effect transistors.

[0036] On the other hand, an exemplary embodiment of the present application provides an electronic device including any one of the above-mentioned storage devices.

[0037] In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0038] This application proposes a three-dimensional stacked CAA-CMOS structure and process solution, using multi-layer pn junctions or silicon dioxide as isolation layers, using SiGe single crystals or single crystal silicon as channels, and directly growing pMOS and nMOS by epitaxial in-situ doping, avoiding traditional bonding technology and saving costs. Compared with the planar structure, this structure effectively reduces the device area and supports multi-layer stacking, saving costs.

[0039] The pn junction in the device structure of the present application has unidirectional conductivity, and multiple pn junctions can serve as insulating layers.

[0040] The present application adopts multiple pn junctions or silicon oxide as the isolation layer between the source and drain of the PMOS tube and the NMOS tube, or the isolation layer between the PMOS tube and the NMOS tube, thereby significantly reducing the leakage current.

[0041] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0043] Figure 1 A schematic diagram of a vertical structure of a complementary field effect transistor provided for an exemplary embodiment of the present application;

[0044] Figure 2 A schematic diagram of a longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a complementary field effect transistor provided in an exemplary embodiment of the present application;

[0045] Figure 3 A schematic diagram of a longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a complementary field effect transistor provided in an exemplary embodiment of the present application;

[0046] Figure 4 A schematic diagram of a longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a complementary field effect transistor provided in an exemplary embodiment of the present application;

[0047] Figure 5 A schematic diagram of a longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a complementary field effect transistor provided in an exemplary embodiment of the present application; and

[0048] Figure 6 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a complementary field effect transistor provided in another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0050] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0051] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the drawings.

[0052] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0053] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0054] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0055] In this specification, "film" and "layer" can be interchanged. For example, "metal layer" can be replaced with "metal film" in some cases.

[0056] The gate-all-around FET is widely considered to be the next generation successor to the fin structure. The VGAA (Vertical gate-all-around) transistor is a vertical transistor that has been increasingly used in CMOS device scenarios in recent years. However, the inventors of the present application found that due to the complex process flow of VGAA, there are problems such as poor uniformity of the diameter (channel) of the nanowires, difficulty in self-alignment of the gate and the channel, and uneven doping of the source and drain, which seriously affects the performance of CMOS devices.

[0057] Therefore, an exemplary embodiment of the present application provides a complementary field effect transistor, comprising a stacked N-type field effect transistor and a P-type field effect transistor and a first isolation layer located between the N-type field effect transistor and the P-type field effect transistor and extending horizontally; the N-type field effect transistor and the P-type field effect transistor share a common gate extending in a vertical direction; the N-type field effect transistor comprises a first channel layer surrounding the common gate, and a first source and a first drain surrounding the common gate and connected to the first channel layer; the P-type field effect transistor comprises a second channel layer surrounding the common gate, and a second source and a second drain surrounding the common gate and connected to the second channel layer, the first isolation layer comprises a silicon oxide isolation layer or at least two groups of pn junction isolation layers, each group of the pn junction isolation layers comprises one N-type doped layer and one P-type doped layer, and the N-type doped layers and the P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0058] As used in this application, "vertically extending" refers to extending along a vertical direction, which can be understood as a direction perpendicular to the substrate. Similarly, "horizontally extending" refers to extending along a horizontal direction, which can be understood as a direction parallel to the substrate.

[0059] As used in this application, the term "an integrated structure" may refer to the fact that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B are formed into a film layer using the same material and are simultaneously formed into a structure having a connection relationship through the same patterning process.

[0060] Figure 1 A schematic diagram of a longitudinal structure of a complementary field effect transistor provided for an exemplary embodiment of the present application. Figure 1 As shown, the complementary field effect transistor may include an N-type field effect transistor 100 and a P-type field effect transistor 200 that are stacked and arranged, and a first isolation layer 41 that is located between the N-type field effect transistor 100 and the P-type field effect transistor 200 and extends horizontally. The N-type field effect transistor 100 and the P-type field effect transistor 200 share a common gate 60 that extends in a vertical direction. The N-type field effect transistor 100 may include a first channel layer 51 surrounding the common gate 60, and a first source 21 and a first drain 31 surrounding the common gate 60 and connected to the channel layer 51. The P-type field effect transistor 200 may include a second channel layer 52 surrounding the common gate 60, and a second source 22 and a second drain 32 surrounding the common gate 60 and connected to the second channel layer 52. The first isolation layer 41 may include at least two groups of pn junction isolation layers or silicon oxide isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and the P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0061] The present application reduces the leakage current density by 4 times compared with the single pn junction isolation in the prior art by adopting an enlarged p / n junction isolation layer, such as at least 2 groups of pn junction isolation layers, ie, pnpn junction isolation.

[0062] Continue to refer Figure 1 The first channel layer 51 of the N-type field effect transistor and the second channel layer 52 of the P-type field effect transistor are both annular and surround the common gate 60 .

[0063] In the present application, surrounding can be understood as partially or completely surrounding the common gate 60. In some embodiments, surrounding can be completely surrounding as a whole, and the cross-section of the channel layer after surrounding can be a closed ring, and the ring shape is adapted to the cross-sectional outer contour shape of the common gate 60. Exemplarily, the cross-section of the common gate 60 is, for example, a square structure. The interception direction of the cross section is intercepted along a direction perpendicular to the substrate 10. In an exemplary embodiment, surrounding can be partially surrounding, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0064] Continue to refer Figure 1In the N-type field effect transistor, the main surface of the first channel layer 51 surrounding the common gate 60 extends vertically, the first source 21 and the first drain 31 both surround the first channel layer 51 and contact the main surface of the first channel layer 51 and are spaced apart in the vertical direction. The main surface of the second channel layer 52 surrounding the common gate 60 extends vertically, the second source 22 and the second drain 32 both surround the second channel layer 52 and contact the main surface of the second channel layer 52 and are spaced apart in the vertical direction.

[0065] A horizontally extending second isolation layer 42 may be included between the first source 21 and the first drain 31, and the second isolation layer 42 is in contact with the main surface of the first channel layer 51, the first source 21, and the first drain 31. A horizontally extending third isolation layer 43 may be included between the second source 22 and the second drain 32, and the third isolation layer 43 is in contact with the main surface of the second channel layer 52, the second source 22, and the second drain 32.

[0066] In an exemplary embodiment, the second isolation layer and the third isolation layer may each include at least two groups of pn junction isolation layers or silicon oxide isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0067] In the present application, the position of the first source electrode and the position of the first drain electrode can be interchanged. When determining which one is the source electrode and which one is the drain electrode, it is related to the flow direction of the current in the transistor, and is not limited here. For example, the source electrode can represent the electrode from which the current flows out, and the drain electrode can represent the electrode into which the current flows. Similarly, the position of the second source electrode and the position of the second drain electrode can also be interchanged.

[0068] In an exemplary embodiment, a channel layer of a p-type field effect transistor is located above a channel layer of the n-type field effect transistor.

[0069] In an exemplary embodiment, the main surface of the first channel layer 51 surrounding the common gate 60 extends horizontally and is located between the first source layer 21 and the first drain layer 31 extending horizontally; the main surface of the second channel layer 52 surrounding the common gate 60 extends horizontally and is located between the second source layer 22 and the second drain layer 32 extending horizontally.

[0070] As used in this application, the term "main surface" means that the size of the surface of the film or layer extending along a certain direction is larger or much larger than the size of its surface extending along other directions, and the surface extending in this direction is called the main surface of the film or layer.

[0071] In an exemplary embodiment, the first channel layer of the N-type field effect transistor includes N-type doped single crystal Si; the second channel layer of the P-type field effect transistor includes P-type doped single crystal Si. The first source and the first drain of the N-type field effect transistor are N-type heavily doped single crystal silicon, that is, the doping concentration of the first source and the first drain of the N-type field effect transistor is greater than the doping concentration of the first channel layer; the second source and the second drain of the P-type field effect transistor are P-type heavily doped single crystal silicon, that is, the doping concentration of the second source and the second drain of the P-type field effect transistor is greater than the doping concentration of the second channel layer.

[0072] In an exemplary embodiment, the first channel layer of the N-type field effect transistor includes N-type doped single crystal GeSi; and the second channel layer of the P-type field effect transistor includes P-type doped single crystal GeSi.

[0073] In other exemplary embodiments, the complementary field effect transistor of the present application may include an N-type field effect transistor and the P-type field effect transistor and a first isolation layer located between the N-type field effect transistor and the P-type field effect transistor and extending horizontally; the N-type field effect transistor includes a first source, a second isolation layer, and a first drain that extend horizontally and are vertically stacked; the P-type field effect transistor includes a second source, a third isolation layer, and a second drain that extend horizontally and are vertically stacked; the N-type field effect transistor and the P-type field effect transistor also include a common gate that extends vertically through the second drain, the third isolation layer, the second source, the first isolation layer, the first drain, and the third isolation layer. layer and terminates at a side of the first source away from the second isolation layer; the N-type field effect transistor also includes a first channel layer surrounding the common gate and vertically extending through the first drain and the second isolation layer and terminating at a side of the first source away from the second isolation layer; the P-type field effect transistor also includes a second channel layer surrounding the common gate and vertically extending through the second drain and the third isolation layer and terminating at a side of the second source away from the third isolation layer; wherein the first isolation layer includes a silicon oxide isolation layer or at least 2 groups of pn junction isolation layers, each group of the pn junction isolation layers includes 1 n-type doped layer and 1 p-type doped layer, and the N-type doped layers and the P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0074] The complementary field effect transistor of the present application also includes an output terminal (Vout); a common gate 60 of the P-type field effect transistor and the N-type field effect transistor serves as an input terminal (Vin) of the complementary field effect transistor; a source of the P-type field effect transistor is connected to a power supply terminal Vdd; and a source of the N-type field effect transistor is connected to a ground electrode GND.

[0075] The technical solution of the present application is further explained below through the manufacturing process of the complementary field effect transistor of the exemplary embodiment of the present application. The "patterning process" mentioned in the exemplary embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature manufacturing process in the relevant technology. The "photolithography process" mentioned in the exemplary embodiment includes coating of film layer, mask exposure and development, which is a mature manufacturing process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of the exemplary embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0076] In an exemplary embodiment, a process for manufacturing a complementary field effect transistor may include:

[0077] S100: growing a single crystal silicon film on the substrate 10 by an epitaxial growth method, and heavily doping the single crystal silicon film with N type to form a first source layer 21; epitaxially growing an isolation layer film on the first source layer 21 to form a second isolation layer 42; epitaxially growing a single crystal silicon film on the second isolation layer 42, and heavily doping the single crystal silicon film with N type to form a first drain layer 31; epitaxially growing an isolation layer film on the first drain layer 31 to form a first isolation layer 41; sequentially forming a heavily P-doped second source layer 22, a third isolation layer 43, and a heavily P-doped second drain layer 32 on the first isolation layer 41 by a method of the type, to form a stacked structure, such as Figure 2 shown. Figure 2 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (S100) of a method for manufacturing a complementary field effect transistor according to an exemplary embodiment of the present application.

[0078] In an exemplary embodiment, each of the three isolation layers may include at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0079] The present application does not require bonding, but replaces conventional dielectric layer isolation by forming multiple P / N multilayers for isolation, thereby forming an enlarged P / N junction isolation for an n / p field effect transistor (FET).

[0080] S200: forming an annular groove (not shown) penetrating the stacked structure and terminating at the side of the substrate 10 close to the first source layer 21 by etching in the aforementioned stacked structure; then epitaxially growing N-type doped Si, pn junction isolation layer and P-type doped Si in the annular groove in sequence to form a first channel layer 51, a first isolation layer 41 and a second channel layer 52, respectively, as shown in FIG. Figure 3 shown. Figure 3 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (S200) of a method for manufacturing a complementary field effect transistor according to an exemplary embodiment of the present application.

[0081] S300: removing the material of the stacked structure in the annular groove to form a through hole structure K that penetrates the stacked structure and terminates at the side of the substrate 10 close to the first source layer 21; depositing an insulating layer film and a conductive material film on the inner wall of the through hole structure K in sequence to form a gate insulating layer 70 and a common gate 60, such as Figure 4 shown. Figure 4 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (S300) of a method for manufacturing a complementary field effect transistor according to an exemplary embodiment of the present application.

[0082] In an exemplary embodiment, the deposition may be performed by atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0083] In an exemplary embodiment, the gate insulating layer 70 may be a dielectric layer with a high dielectric constant, that is, a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The gate insulating layer 70 may be made of silicon oxide, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ) any one or more of.

[0084] In an exemplary embodiment, the common gate 60 may be made of TiN, metal tungsten W, or a composite metal of TiN / W.

[0085] S400: Open the source / drain / input / output terminals through etching and interconnection processes, such as Figure 5 shown. Figure 5 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a complementary field effect transistor provided in an exemplary embodiment of the present application.

[0086] In an exemplary embodiment, the connection electrode may be formed by physical vapor deposition (PVD) of metal platinum at 400°C.

[0087] In another exemplary embodiment, a process for manufacturing a complementary field effect transistor may include:

[0088] S1000: growing a semiconductor film on the substrate 10 by an epitaxial growth method, and heavily doping the semiconductor film with N-type to form a first source layer 21; epitaxially growing a sacrificial layer film on the first source layer 21 to form a second sacrificial layer; epitaxially growing a semiconductor film on the second sacrificial layer, and heavily doping the semiconductor film with N-type to form a first drain layer 31; epitaxially growing a sacrificial layer film on the first drain layer 31 to form a first sacrificial layer; sequentially forming a heavily P-doped second source layer 22, a third sacrificial layer, and a heavily P-doped second drain layer 32 on the first sacrificial layer by a method of the type described above to form a stacked structure.

[0089] In an exemplary embodiment, each of the three sacrificial layers may include a SiGe sacrificial layer.

[0090] S2000 : Same as S200 , forming a first channel layer 51 and a second channel layer 52 .

[0091] S3000 : Similar to S300 , a gate insulating layer 70 and a common gate 60 are formed.

[0092] S4000: removing the materials of the three sacrificial layers by etching to form six isolation trenches on both sides of the common gate 60, such as Figure 6 shown. Figure 6 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (S4000) of a method for manufacturing a complementary field effect transistor provided in another exemplary embodiment of the present application.

[0093] S5000: With SiO 2 The material fills the six isolation trenches to form three isolation layers.

[0094] S6000: Same as S400, the source / drain / input / output terminals are opened through etching and interconnection processes.

[0095] The stacked manufacturing process of the present application can control the doping depth and the channel width, thereby having the advantages of a simple process flow and a stable and controllable channel length.

[0096] An exemplary embodiment of the present application provides a method for manufacturing a complementary field effect transistor, comprising the following steps:

[0097] Forming a stacked structure including a heavily N-type doped first source layer, a second isolation layer, a heavily N-type doped first drain layer, a first isolation layer, a heavily P-type doped second source layer, a third isolation layer, and a heavily P-type doped second drain layer in sequence on a substrate by epitaxial growth;

[0098] forming an annular groove penetrating the stacked structure and terminating at a side of the substrate close to the first source layer, and sequentially epitaxially growing an N-type doping material, a first isolation layer material, and a P-type doping material in the annular groove to form a first channel layer, a first isolation layer, and a second channel layer, respectively; and

[0099] forming a vertically extending common gate common to the N-type transistor and the P-type transistor;

[0100] The three isolation layers each include at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

[0101] The exemplary embodiment of the present application further provides a memory device, comprising the complementary field effect transistor provided by the exemplary embodiment of the present application as above. The memory device may be, for example, a DRAM.

[0102] An exemplary embodiment of the present application further provides an electronic device, comprising the storage device provided by the exemplary embodiment of the present application as above.

[0103] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0104] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A complementary field effect transistor, characterized in that: The invention comprises a stacked N-type field effect transistor and a P-type field effect transistor and a first isolation layer located between the N-type field effect transistor and the P-type field effect transistor and extending horizontally; The N-type field effect transistor and the P-type field effect transistor share a common gate extending in a vertical direction; The N-type field effect transistor includes a first channel layer surrounding the common gate, and a first source and a first drain surrounding the common gate and connected to the first channel layer; the P-type field effect transistor includes a second channel layer surrounding the common gate, and a second source and a second drain surrounding the common gate and connected to the second channel layer, the first isolation layer includes a silicon oxide isolation layer or at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one N-type doped layer and one P-type doped layer, and the N-type doped layers and the P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

2. The complementary field effect transistor according to claim 1, characterized in that: The first isolation layer includes three groups of pn junction isolation layers.

3. The complementary field effect transistor according to claim 1, characterized in that: The main surface of the first channel layer surrounding the common gate extends vertically, and the first source and the first drain both surround the first channel layer and contact the main surface of the first channel layer and are spaced apart in the vertical direction; the main surface of the second channel layer surrounding the common gate extends vertically, and the second source and the second drain both surround the second channel layer and contact the main surface of the second channel layer and are spaced apart in the vertical direction.

4. The complementary field effect transistor according to claim 3, characterized in that: A horizontally extending second isolation layer is included between the first source and the first drain, and the second isolation layer is in contact with the main surface of the first channel layer, the first source and the first drain; a horizontally extending third isolation layer is included between the second source and the second drain, and the third isolation layer is in contact with the main surface of the second channel layer, the second source and the second drain.

5. The complementary field effect transistor according to claim 4, characterized in that: The second isolation layer and the third isolation layer both include silicon oxide isolation layers.

6. The complementary field effect transistor according to claim 1, characterized in that: The main surface of the first channel layer surrounding the common gate extends horizontally and is located between the first source layer and the first drain layer extending horizontally; the main surface of the second channel layer surrounding the common gate extends horizontally and is located between the second source layer and the second drain layer extending horizontally.

7. The complementary field effect transistor according to claim 1, characterized in that: The first channel layer of the N-type field effect transistor includes N-type doped single crystal silicon; the second channel layer of the P-type field effect transistor includes P-type doped single crystal silicon.

8. The complementary field effect transistor according to claim 7, characterized in that: The first source and the first drain of the N-type field effect transistor are N-type heavily doped single crystal silicon; the second source and the second drain of the P-type field effect transistor are P-type heavily doped single crystal silicon.

9. The complementary field effect transistor according to claim 8, characterized in that: The doping concentration of the first source and the first drain of the N-type field effect transistor is greater than the doping concentration of the first channel layer; the doping concentration of the second source and the second drain of the P-type field effect transistor is greater than the doping concentration of the second channel layer.

10. A complementary field effect transistor, characterized in that: It includes an N-type field effect transistor and the P-type field effect transistor, and a first isolation layer located between the N-type field effect transistor and the P-type field effect transistor and extending horizontally; The N-type field effect transistor includes a first source, a second isolation layer and a first drain extending horizontally and stacked vertically; the P-type field effect transistor includes a second source, a third isolation layer and a second drain extending horizontally and stacked vertically; the N-type field effect transistor and the P-type field effect transistor also include a common gate, which vertically extends through the second drain, the third isolation layer, the second source, the first isolation layer, the first drain and the third isolation layer and terminates at a side of the first source away from the second isolation layer; the N-type field effect transistor also includes a first channel layer surrounding the common gate and vertically extending through the first drain and the second isolation layer and terminating at a side of the first source away from the second isolation layer; the P-type field effect transistor also includes a second channel layer surrounding the common gate and vertically extending through the second drain and the third isolation layer and terminating at a side of the second source away from the third isolation layer; The first isolation layer includes a silicon oxide isolation layer or at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

11. The complementary field effect transistor according to claim 10, characterized in that: The first source and the first drain both surround the first channel layer and contact the vertically extending main surface of the first channel layer and are spaced apart in the vertical direction; the second source and the second drain both surround the second channel layer and contact the vertically extending main surface of the second channel layer and are spaced apart in the vertical direction.

12. A method for manufacturing a complementary field effect transistor, characterized in that: The steps include: Forming a stacked structure including a heavily N-type doped first source layer, a second isolation layer, a heavily N-type doped first drain layer, a first isolation layer, a heavily P-type doped second source layer, a third isolation layer, and a heavily P-type doped second drain layer in sequence on a substrate by epitaxial growth; forming an annular groove penetrating the stacked structure and terminating at a side of the substrate close to the first source layer, and sequentially epitaxially growing an N-type doping material, a first isolation layer material, and a P-type doping material in the annular groove to form a first channel layer, a first isolation layer, and a second channel layer, respectively; and forming a vertically extending common gate common to the N-type transistor and the P-type transistor; The three isolation layers each include at least two groups of pn junction isolation layers, each group of the pn junction isolation layers includes one n-type doped layer and one p-type doped layer, and the N-type doped layers and P-type doped layers of the multiple groups of the pn junction isolation layers are alternately distributed.

13. The manufacturing method according to claim 12, characterized in that: Forming a common gate includes: After sequentially epitaxially growing an N-type doping material, a first isolation layer material, and a P-type doping material in the annular groove to form a first channel layer, a first isolation layer, and a second channel layer, respectively, the material of the stacked structure in the annular groove is removed to form a through-hole structure penetrating the stacked structure and terminating at a side of the substrate close to the first source layer; An insulating layer film and a conductive material film are sequentially deposited on the inner wall of the gate through hole to form a gate insulating layer and a common gate.

14. A method for manufacturing a complementary field effect transistor, characterized in that: The steps include: Forming a stacked structure including a heavily N-type doped first source layer, a second sacrificial layer, a heavily N-type doped first drain layer, a first sacrificial layer, a heavily P-type doped second source layer, a third sacrificial layer, and a heavily P-type doped second drain layer in sequence on a substrate by epitaxial growth; Forming an annular groove that penetrates the stacked structure and terminates at a side of the substrate close to the first source layer, and sequentially epitaxially growing an N-type doping material, a first sacrificial layer material, and a P-type doping material in the annular groove to form a first channel layer, a first sacrificial layer, and a second channel layer, respectively; as well as forming a vertically extending common gate common to the N-type transistor and the P-type transistor; Removing materials from the first sacrificial layer, the second sacrificial layer and the third sacrificial layer to form six isolation trenches on both sides of the common gate; Filling the six isolation trenches with an isolation layer material to form a first isolation layer, a second isolation layer, and a third isolation layer; The sacrificial layer comprises a GeSi sacrificial layer, and the three isolation layers comprise a silicon oxide isolation layer or at least two groups of pn junction isolation layers.

15. A storage device, characterized in that: Comprising a complementary field effect transistor according to any one of claims 1-11.

16. An electronic device, characterized in that: Comprising the memory device according to claim 15.

17. The electronic device according to claim 16, characterized in that: The electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

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