Photoelectric chip and preparation method thereof, balanced photoelectric detector, and optical communication equipment

Abstract

The present application provides an optoelectronic chip and a method for preparing the same, a balanced photodetector, and an optical communication device. The optoelectronic chip includes a first chip, a second chip, and an electrode assembly. The first chip and the second chip are prepared from the same wafer. The first chip is prepared from the first part of the wafer, and the second chip is prepared from the second part of the wafer. The first part and the second part are connected and arranged adjacently; the electrode assembly connects the first chip and the second chip. The present application uses a first chip and a second chip formed in adjacent parts on the same wafer to form an optoelectronic chip, thereby improving the signal-to-noise ratio of the optoelectronic chip and the detection performance of the balanced photodetector; and the first chip and the second chip are combined together through the electrode assembly, thereby reducing the overall size of the optoelectronic chip and improving the output; the back-lighting method is used to save the wire bonding process in the packaging process, further reducing the crosstalk caused by the wire bonding and improving the signal-to-noise ratio.

Description

Technical Field

[0001] The present application belongs to the field of optical communication technology, and specifically relates to an optoelectronic chip and a preparation method thereof, a balanced photodetector, and an optical communication device. Background Art

[0002] In the related art, the P and N electrodes of two separate optoelectronic chips need to be connected together through patch and wire bonding to form an optoelectronic chip, which is then used in a balanced photodetector. However, due to the difference in performance of different regions of the wafer, the performance of the two separate optoelectronic chips also varies, and the patch and wire bonding methods also cause interference, resulting in a low signal-to-noise ratio of the optoelectronic chip, which reduces the detection performance of the balanced photodetector. Summary of the invention

[0003] In view of this, the first aspect of the present application provides an optoelectronic chip, which is applied to a balanced photodetector. The optoelectronic chip includes:

[0004] A first chip and a second chip, the first chip and the second chip are connected and arranged adjacent to each other, the first chip and the second chip are prepared from the same wafer, the first chip is prepared from a first part of the wafer, the second chip is prepared from a second part of the wafer, and the first part and the second part are connected and arranged adjacent to each other;

[0005] An electrode assembly is arranged on the same side of the first chip and the second chip, and the electrode assembly includes an N electrode, a P electrode, and a common electrode. The N electrode and the common electrode are both connected to the first chip, and the P electrode and the common electrode are both connected to the second chip.

[0006] Wherein, the first chip and the second chip include the same substrate, and the electrode assembly is arranged on a side of the first chip and the second chip away from the substrate;

[0007] The first chip further comprises a first light absorbing layer disposed between the substrate and the electrode assembly, a first active region is provided on a side of the first chip facing the electrode assembly, at least a portion of the first active region is disposed in the first light absorbing layer, the first active region forms a first PN junction, and the common electrode is connected to the first active region;

[0008] The second chip also includes a second light absorbing layer arranged between the substrate and the electrode assembly, the second light absorbing layer is spaced apart from the first light absorbing layer, the second chip has a second active area on the side facing the electrode assembly, at least part of the second active area is arranged in the second light absorbing layer, the second active area forms a second PN junction, and the P electrode is connected to the second active area.

[0009] The first chip further comprises a first connection layer disposed between the first light absorbing layer and the electrode assembly, the first active region comprises a first sub-region and a second sub-region connected to each other, the first sub-region is disposed on the first connection layer, the second sub-region is disposed on the first light absorbing layer, and the common electrode is connected to the first sub-region;

[0010] The second chip also includes a second connecting layer arranged between the second light absorbing layer and the electrode assembly, the second connecting layer and the first connecting layer are spaced apart, the second active area includes a third sub-area and a fourth sub-area connected to each other, the third sub-area is arranged in the second connecting layer, the fourth sub-area is arranged in the second light absorbing layer, and the P electrode is connected to the third sub-area.

[0011] The first chip further includes a first N-type contact layer disposed between the substrate and the first light absorbing layer, the N-electrode is disposed on a side of the first N-type contact layer away from the substrate, and the N-electrode is connected to the first N-type contact layer;

[0012] The second chip also includes a second N-type contact layer disposed between the substrate and the second light absorbing layer, the second N-type contact layer is spaced apart from the first N-type contact layer, the common electrode is disposed on a side of the second N-type contact layer away from the substrate, and the common electrode is connected to the second N-type contact layer.

[0013] The substrate has a first light incident area on a side facing away from the first connecting layer, and the first light incident area is arranged corresponding to the first active area;

[0014] A side of the substrate facing away from the second connecting layer has a second light incident area, and the second light incident area is arranged corresponding to the second active area.

[0015] The first chip further includes a first anti-transmission layer, which is disposed on a surface of the substrate away from the first connecting layer, and covers the first light incident area;

[0016] The second chip further includes a second anti-transmission layer, which is disposed on a surface of the substrate facing away from the second connecting layer, and covers the second light incident area.

[0017] Among them, the optoelectronic chip also includes a protective layer, which covers the first connecting layer, the first light absorbing layer, the first N-type contact layer, the second connecting layer, the second light absorbing layer, and the second N-type contact layer. The N-electrode also penetrates the protective layer and is connected to the first N-type contact layer. The common electrode also penetrates the protective layer and is connected to the first active area and the second N-type contact layer. The P electrode also penetrates the protective layer and is connected to the second active area.

[0018] Wherein, the optoelectronic chip meets at least one of the following conditions:

[0019] The absolute value of the difference in breakdown voltage between the first chip and the second chip is ≤0.4V;

[0020] The absolute value of the difference in responsivity between the first chip and the second chip is ≤0.1A / W;

[0021] The absolute value of the difference in capacitance between the first chip and the second chip is ≤0.1 pF.

[0022] The second aspect of the present application provides a method for preparing the optoelectronic chip provided in the first aspect of the present application, the preparation method comprising:

[0023] providing a wafer;

[0024] forming a first chip and a second chip, wherein the first chip and the second chip are connected and arranged adjacent to each other, the first chip is prepared from the first part of the wafer, the second chip is prepared from the second part of the wafer, and the first part and the second part are connected and arranged adjacent to each other;

[0025] An electrode assembly is formed, wherein the electrode assembly is disposed on the same side of the first chip and the second chip, and the electrode assembly includes an N electrode, a P electrode, and a common electrode. The N electrode and the common electrode are both connected to the first chip, and the P electrode and the common electrode are both connected to the second chip.

[0026] The wafer includes a substrate, and the step of forming the first chip and the second chip includes:

[0027] forming a first active region disposed in the first portion, the first active region forming a first PN junction, and forming a second active region disposed in the second portion, the second active region forming a second PN junction;

[0028] A first N-type contact layer, a first light absorption layer, and a first connection layer are sequentially stacked on the substrate, the first active region is disposed in the first connection layer and the first light absorption layer, and a second N-type contact layer, a second light absorption layer, and a second connection layer are sequentially stacked on the substrate, the second active region is disposed in the second connection layer and the second light absorption layer.

[0029] The step of forming the first chip and the second chip further includes:

[0030] forming a first light incident area, the first light incident area is arranged on a side of the substrate away from the first connection layer, and the first light incident area is arranged correspondingly to the first active area, and forming a second light incident area, the second light incident area is arranged on a side of the substrate away from the second connection layer, and the second light incident area is arranged correspondingly to the second active area;

[0031] A first anti-transmittance layer is formed, the first anti-transmittance layer is arranged on the surface of the substrate away from the first connecting layer, the first anti-transmittance layer covers the first light entrance area, and a second anti-transmittance layer is formed, the second anti-transmittance layer is arranged on the surface of the substrate away from the second connecting layer, the second anti-transmittance layer covers the second light entrance area.

[0032] The step of forming the first chip and the second chip further includes:

[0033] forming a protective layer, wherein the protective layer covers the first connecting layer, the first light absorbing layer, the first N-type contact layer, the second connecting layer, the second light absorbing layer, and the second N-type contact layer;

[0034] The step of forming the electrode assembly includes:

[0035] The N-electrode also penetrates the protective layer and is connected to the first N-type contact layer. The common electrode also penetrates the protective layer and is connected to the first active region and the second N-type contact layer. The P-electrode also penetrates the protective layer and is connected to the second active region.

[0036] A third aspect of the present application provides a balanced photodetector, which includes a processor and an optoelectronic chip as provided in the first aspect of the present application, wherein the processor is electrically connected to the optoelectronic chip and is used to control the optoelectronic chip.

[0037] The fourth aspect of the present application provides an optical communication device, which includes a transmitting chip and a balanced photodetector as provided in the third aspect of the present application, wherein the transmitting chip is used to transmit an optical signal, and the balanced photodetector is used to receive the optical signal.

[0038] The optoelectronic chip and its preparation method, balanced photodetector, and optical communication equipment provided by the present application use a first chip and a second chip formed in adjacent parts on the same wafer to form an optoelectronic chip. Since the performance difference between the adjacent parts of the same wafer is small, the performance difference between the first chip and the second chip is small, and the first chip and the second chip have a high degree of consistency. Therefore, by combining the first chip and the second chip, the signal-to-noise ratio of the optoelectronic chip can be improved, and the detection performance of the balanced photodetector can be improved; and, the present application forms an electrode assembly to combine the first chip and the second chip together through process design, thereby reducing the overall size of the optoelectronic chip and improving the output efficiency of the optoelectronic chip; the back-lighting method is used to save the wire bonding process in the packaging process, further reduce the crosstalk caused by the wire bonding, and thus improve the signal-to-noise ratio. Therefore, the optoelectronic chip provided by the present application has the advantages of high signal-to-noise ratio, good stability, small size, and high integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the implementation modes of the present application, the drawings required for use in the implementation modes of the present application will be described below.

[0040] Figure 1 A top view of an optoelectronic chip provided in one embodiment of the present application.

[0041] Figure 2 A bottom view of an optoelectronic chip provided in accordance with one embodiment of the present application.

[0042] Figure 3 A top view of a plurality of optoelectronic chips provided in accordance with an embodiment of the present application.

[0043] Figure 4 A bottom view of a plurality of optoelectronic chips provided in accordance with an embodiment of the present application.

[0044] Figure 5 A schematic cross-sectional view of an optoelectronic chip provided in accordance with an embodiment of the present application.

[0045] Figure 6 for Figure 5 Partial magnification Figure 1 .

[0046] Figure 7 for Figure 5 Partial magnification Figure 2 .

[0047] Figure 8 A schematic diagram of a process for preparing an optoelectronic chip provided in one embodiment of the present application.

[0048] Fig. 9 A schematic flow chart of a method for preparing an optoelectronic chip provided in another embodiment of the present application.

[0049] Fig.10 A schematic flow chart of a method for preparing an optoelectronic chip provided in yet another embodiment of the present application.

[0050] Fig.11 The present invention is a schematic flow chart of a method for preparing an optoelectronic chip according to yet another embodiment of the present application.

[0051] Fig.12 The present invention is a schematic flow chart of a method for preparing an optoelectronic chip provided in yet another embodiment of the present application.

[0052] Explanation of reference numerals: optoelectronic chip 1, first chip 10, first N-type contact layer 11, first light absorbing layer 12, first connecting layer 13, first active area 14, first sub-area 141, second sub-area 142, first light incident area 15, first anti-reflection layer 16, second chip 20, second N-type contact layer 21, second light absorbing layer 22, second connecting layer 23, second active area 24, third sub-area 241, fourth sub-area 242, second light incident area 25, second anti-reflection layer 26, substrate 31, protective layer 32, electrode assembly 40, N-electrode 41, P-electrode 42, common electrode 43. DETAILED DESCRIPTION

[0053] The following are preferred implementations of the present application. It should be noted that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application, and these improvements and modifications are also considered to be within the scope of protection of the present application.

[0054] In view of this, in order to solve the above problems, please refer to Figure 1-Figure 4 The present embodiment provides an optoelectronic chip 1, which is applied to a balanced photodetector. The optoelectronic chip 1 includes a first chip 10, a second chip 20, and an electrode assembly 40. The first chip 10 and the second chip 20 are connected and arranged adjacent to each other. The first chip 10 and the second chip 20 are prepared from the same wafer. The first chip 10 is prepared from the first part of the wafer, and the second chip 20 is prepared from the second part of the wafer. The first part and the second part are connected and arranged adjacent to each other. The electrode assembly 40 is arranged on the same side of the first chip 10 and the second chip 20. The electrode assembly 40 includes an N electrode 41, a P electrode 42, and a common electrode 43. The N electrode 41 and the common electrode 43 are both connected to the first chip 10, and the P electrode 42 and the common electrode 43 are both connected to the second chip 20.

[0055] The photoelectric chip 1 is applied to a balanced photodetector. The working principle of the balanced photodetector is to receive light from the same light source through two chips, and then obtain the output current difference of the two chips through a differential amplifier, thereby realizing accurate detection of the intensity of the light source. Since the two chips receive the same light source, the impact of common noise on the two chips is the same. This part of the noise can be suppressed through the differential amplifier, thereby improving the detection accuracy.

[0056] The first chip 10 and the second chip 20 are both capable of receiving optical signals and converting the optical signals into electrical signals, which can be transmitted to other components through the electrode assembly 40. The first chip 10 is connected to the second chip 20, for example, the first chip 10 and the second chip 20 share one or more layer structures. For another example, a structure of the first chip 10 abuts against another structure of the second chip 20.

[0057] The first chip 10 and the second chip 20 are obtained from the same wafer, wherein one wafer may be subjected to processes such as etching, diffusion doping, growth of functional layers, preparation of electrodes, grinding and polishing to obtain the first chip 10 and the second chip 20. The first chip 10 is located in the first part of the wafer, and the second chip 20 is located in the second part of the wafer. The first chip 10 and the second chip 20 form an optoelectronic chip 1, and multiple optoelectronic chips 1 may be prepared on one wafer at the same time. Moreover, when the preparation of the chips on the wafer is completed, the optoelectronic chips 1 may be cut separately on the wafer to reduce the cutting process that requires the chips to be cut separately in the related art, thereby improving production efficiency.

[0058] The N electrode 41 and the common electrode 43 in the electrode assembly 40 are electrically connected to the first chip 10, and the P electrode 42 and the common electrode 43 are connected to the second chip 20. It can also be understood that the first chip 10 and the second chip 20 are connected in parallel through the electrode assembly 40. Optionally, the material of the electrode assembly 40 is metal or alloy. Specifically, the N electrode 41 and the common electrode 43 directly abut the first chip 10, and the N electrode 41 and the common electrode 43 are directly electrically connected to the first chip 10, and are not indirectly connected to the first chip 10 through other components; the P electrode 42 and the common electrode 43 directly abut the second chip 20, and the P electrode 42 and the common electrode 43 are directly electrically connected to the second chip 20, and are not indirectly connected to the second chip 20 through other components, thereby reducing the overall size of the optoelectronic chip 1 and improving the output efficiency of the optoelectronic chip 1.

[0059] In summary, the optoelectronic chip 1 provided in the present embodiment adopts a first chip 10 and a second chip 20 formed in adjacent parts on the same wafer to form an optoelectronic chip 1. Since the performance difference between adjacent parts of the same wafer is small, the performance difference between the first chip 10 and the second chip 20 is small, and the first chip 10 and the second chip 20 are highly consistent. Therefore, by combining the first chip 10 and the second chip 20, the signal-to-noise ratio of the optoelectronic chip 1 can be improved, and the detection performance of the balanced photodetector can be improved; and, the present application forms an electrode assembly 40 through process design to combine the first chip 10 and the second chip 20 together, thereby reducing the overall size of the optoelectronic chip 1 and improving the output efficiency of the optoelectronic chip 1.

[0060] Therefore, the optoelectronic chip 1 provided in this embodiment has the advantages of high signal-to-noise ratio, good stability, small size and high integration.

[0061] The specific structure of the optoelectronic chip 1 is introduced below. Figure 1-Figure 5 In one embodiment, the first chip 10 and the second chip 20 include a same substrate 31 , and the electrode assembly 40 is disposed on a side of the first chip 10 and the second chip 20 away from the substrate 31 .

[0062] The first chip 10 also includes a first light absorbing layer 12 arranged between the substrate 31 and the electrode assembly 40. The first chip 10 has a first active area 14 on the side facing the electrode assembly 40. At least part of the first active area 14 is arranged in the first light absorbing layer 12. The first active area 14 forms a first PN junction. The common electrode 43 is connected to the first active area 14.

[0063] The second chip 20 also includes a second light absorbing layer 22 arranged between the substrate 31 and the electrode assembly 40, the second light absorbing layer 22 is spaced apart from the first light absorbing layer 12, the second chip 20 has a second active area 24 on the side facing the electrode assembly 40, at least part of the second active area 24 is arranged in the second light absorbing layer 22, the second active area 24 forms a second PN junction, and the P electrode 42 is connected to the second active area 24.

[0064] The substrate 31 is the base of the first chip 10 and the second chip 20, and is used to carry other film layers in the first chip 10 and the second chip 20. Optionally, the substrate 31 is an InP layer. In other words, the material of the substrate 31 is InP. The first chip 10 and the second chip 20 provided in this embodiment are formed by adjacent parts on the same wafer, and the first chip 10 and the second chip 20 are not cut, so the first chip 10 and the second chip 20 share the same substrate 31.

[0065] The first light absorbing layer 12 is used to convert the absorbed light energy into electrical energy. In the first chip 10, the first light absorbing layer 12 is used to convert the received light signal into an electrical signal. The first light absorbing layer 12 is arranged on the side of the substrate 31 facing the electrode assembly 40. For example, the first light absorbing layer 12 is directly arranged on the surface of the substrate 31, or there are other film layers between the first light absorbing layer 12 and the substrate 31, and the first light absorbing layer 12 is indirectly arranged on one side of the substrate 31. Optionally, the first light absorbing layer 12 is an InGaAs layer. In other words, the material of the first light absorbing layer 12 is InGaAs.

[0066] The second light absorbing layer 22 is used to convert the absorbed light energy into electrical energy. In the second chip 20, the second light absorbing layer 22 is used to convert the received light signal into an electrical signal. The second light absorbing layer 22 is arranged on the side of the substrate 31 facing the electrode assembly 40. For example, the second light absorbing layer 22 is directly arranged on the surface of the substrate 31, or there is another film layer between the second light absorbing layer 22 and the substrate 31, and the second light absorbing layer 22 is indirectly arranged on one side of the substrate 31. Optionally, the second light absorbing layer 22 is an InGaAs layer. In other words, the material of the second light absorbing layer 22 is InGaAs. Optionally, the first light absorbing layer 12 and the second light absorbing layer 22 are arranged in the same layer in the optoelectronic chip 1.

[0067] The first active region 14 connects the first light absorbing layer 12 and the common electrode 43, and can transmit the electrical signal converted by the first light absorbing layer 12 to the common electrode 43. The first active region 14 is obtained by performing a diffusion doping process on the wafer. For example, the entire first active region 14 is provided in the first light absorbing layer 12; or, part of the first active region 14 is provided in the first light absorbing layer 12, and another part of the first active region 14 is provided in other layer structures. In addition, the first active region 14 forms a first PN junction, and the first PN junction can be used as a diode. When an external voltage is applied, the photocurrent can be amplified, thereby improving the signal-to-noise ratio of the optoelectronic chip 1 and improving the detection performance of the balanced photodetector.

[0068] The second active region 24 connects the second light absorbing layer 22 and the P electrode 42, and can transmit the electrical signal converted by the second light absorbing layer 22 to the P electrode 42. The second active region 24 is obtained by performing a diffusion doping process on the wafer. For example, the entire second active region 24 is provided in the second light absorbing layer 22; or, part of the second active region 24 is provided in the second light absorbing layer 22, and another part of the second active region 24 is provided in other layer structures. In addition, the second active region 24 forms a second PN junction, and the second PN junction can be used as a diode. When an external voltage is applied, the photocurrent can be amplified, thereby improving the signal-to-noise ratio of the optoelectronic chip 1 and improving the detection performance of the balanced photodetector.

[0069] Optionally, the first active area 14 is exposed on the surface of the first chip 10, and the second active area 24 is exposed on the surface of the second chip 20. Optionally, at least part of the common electrode 43 is disposed on a side of the first active area 14 away from the substrate 31, and at least part of the P electrode 42 is disposed on a side of the second active area 24 away from the substrate 31. Optionally, the common electrode 43 abuts the first active area 14, and the P electrode 42 abuts the second active area 24. In other words, the common electrode 43 is directly electrically connected to the first active area 14, and the P electrode 42 is directly electrically connected to the second active area 24.

[0070] Optionally, the first active region 14 and the second active region 24 are both doped with Zn; and / or the doping concentration of the first active region 14 and the second active region 24 is both 2.0×10 18 ~6.0×10 18 cm -3 ; and / or, along the arrangement direction from the substrate 31 to the electrode assembly 40, the heights of the first active area 14 and the second active area 24 are both 1.0 μm to 1.2 μm.

[0071] In summary, this embodiment forms a first PN junction by setting a first active area 14 connecting the common electrode 43 and the first light absorbing layer 12, and forms a second PN junction by setting a second active area 24 connecting the P electrode 42 and the second light absorbing layer 22, which is beneficial to improving the electrical signal transmission performance between the light absorbing layer and the electrode assembly 40, and can amplify the photogenerated current, further improve the signal-to-noise ratio of the optoelectronic chip 1, and further improve the detection performance of the balanced photodetector.

[0072] Please refer to Figure 1-Figure 7 In one embodiment, the first chip 10 also includes a first connecting layer 13 disposed between the first light absorbing layer 12 and the electrode assembly 40, the first active area 14 includes a first sub-area 141 and a second sub-area 142 connected to each other, the first sub-area 141 is disposed in the first connecting layer 13, the second sub-area 142 is disposed in the first light absorbing layer 12, and the common electrode 43 is connected to the first sub-area 141.

[0073] The second chip 20 also includes a second connecting layer 23 arranged between the second light absorbing layer 22 and the electrode assembly 40, the second connecting layer 23 is spaced apart from the first connecting layer 13, the second active area 24 includes a third sub-area 241 and a fourth sub-area 242 connected to each other, the third sub-area 241 is arranged in the second connecting layer 23, the fourth sub-area 242 is arranged in the second light absorbing layer 22, and the P electrode 42 is connected to the third sub-area 241.

[0074] The first connection layer 13 can also be understood as the top layer of the first chip 10, the electrode assembly 40 abuts against the surface of the first connection layer 13 facing away from the substrate 31, and the first connection layer 13 abuts against the surface of the first light absorption layer 12 facing away from the substrate 31. In the first chip 10, the substrate 31, the first light absorption layer 12, and the first connection layer 13 are stacked in sequence. Optionally, the first connection layer 13 is an InP layer. In other words, the material of the first connection layer 13 is InP. Since the lattice of InGaAs can be fully matched with the InP material, the first light absorption layer 12 and the first connection layer 13 are abutted and matched, so as to obtain high-quality first light absorption layer 12 and first connection layer 13 during preparation, which is beneficial to improve the reliability of the optoelectronic chip 1.

[0075] The first active region 14 includes a first sub-region 141 and a second sub-region 142. The first sub-region 141 penetrates the first connection layer 13 along the thickness direction of the first connection layer 13. The first sub-region 141 is exposed on the surface of the first chip 10. At least part of the common electrode 43 is arranged on the side of the first sub-region 141 away from the substrate 31. The common electrode 43 abuts the first sub-region 141, and the common electrode 43 is directly electrically connected to the first sub-region 141. The second sub-region 142 penetrates the first light absorption layer 12 along the thickness direction of the first light absorption layer 12, but does not penetrate the first light absorption layer 12. Along the arrangement direction from the substrate 31 to the electrode assembly 40, the height of the first sub-region 141 is greater than the height of the second sub-region 142; further, the height of the first sub-region 141 is equal to the thickness of the first connection layer 13, and the height of the second sub-region 142 is less than the thickness of the first light absorption layer 12. Optionally, the doping concentration of the first sub-region 141 is greater than the doping concentration of the second sub-region 142 , so as to further improve the electrical signal transmission performance of the first active region 14 .

[0076] The second connection layer 23 can also be understood as the top layer of the second chip 20, the electrode assembly 40 abuts against the surface of the second connection layer 23 facing away from the substrate 31, and the second connection layer 23 abuts against the surface of the second light absorption layer 22 facing away from the substrate 31. In the second chip 20, the substrate 31, the second light absorption layer 22, and the second connection layer 23 are stacked in sequence. Optionally, the second connection layer 23 is an InP layer. In other words, the material of the second connection layer 23 is InP. Since the lattice of InGaAs can be fully matched with the InP material, the second light absorption layer 22 and the second connection layer 23 are abutted and matched, so as to obtain high-quality second light absorption layer 22 and second connection layer 23 during preparation, which is beneficial to improve the reliability of the optoelectronic chip 1. Optionally, the first connection layer 13 and the second connection layer 23 are arranged in the same layer in the optoelectronic chip 1.

[0077] The second active region 24 includes a third sub-region 241 and a fourth sub-region 242. The third sub-region 241 penetrates the second connection layer 23 along the thickness direction of the second connection layer 23. The third sub-region 241 is exposed on the surface of the second chip 20. At least part of the P electrode 42 is arranged on the side of the third sub-region 241 away from the substrate 31. The P electrode 42 abuts against the third sub-region 241, and the P electrode 42 is directly electrically connected to the third sub-region 241. The fourth sub-region 242 penetrates the second light absorption layer 22 along the thickness direction of the second light absorption layer 22, but does not penetrate the second light absorption layer 22. Along the arrangement direction from the substrate 31 to the electrode assembly 40, the height of the third sub-region 241 is greater than the height of the fourth sub-region 242; further, the height of the third sub-region 241 is equal to the thickness of the second connection layer 23, and the height of the fourth sub-region 242 is less than the thickness of the second light absorption layer 22. Optionally, the doping concentration of the third sub-region 241 is greater than the doping concentration of the fourth sub-region 242 , so as to further improve the electrical signal transmission performance of the second active region 24 .

[0078] In summary, this embodiment can improve the electrical signal transmission performance of the first active area 14 and the second active area 24 by setting the first active area 14 as the first sub-area 141 and the second sub-area 142 and the second active area 24 as the third sub-area 241 and the fourth sub-area 242, thereby improving the reliability of the optoelectronic chip 1.

[0079] Please refer to Figure 1-Figure 7 In one embodiment, the first chip 10 further includes a first N-type contact layer 11 disposed between the substrate 31 and the first light absorbing layer 12 , the N-electrode 41 is disposed on a side of the first N-type contact layer 11 away from the substrate 31 , and the N-electrode 41 is connected to the first N-type contact layer 11 .

[0080] The second chip 20 also includes a second N-type contact layer 21 disposed between the substrate 31 and the second light absorbing layer 22 , the second N-type contact layer 21 is spaced apart from the first N-type contact layer 11 , the common electrode 43 is disposed on a side of the second N-type contact layer 21 away from the substrate 31 , and the common electrode 43 is connected to the second N-type contact layer 21 .

[0081] The first N-type contact layer 11 connects the first light absorbing layer 12 and the N-electrode 41, and can transmit the electrical signal converted by the first light absorbing layer 12 to the N-electrode 41. In the first chip 10, the substrate 31, the first N-type contact layer 11, the first light absorbing layer 12, and the first connection layer 13 are stacked in sequence. Optionally, the first N-type contact layer 11 is an N-type semiconductor layer. In other words, the material of the first N-type contact layer 11 is an N-type semiconductor, for example, an N-type doped InGaAs layer.

[0082] The second N-type contact layer 21 connects the second light absorbing layer 22 and the common electrode 43, and can transmit the electrical signal converted by the second light absorbing layer 22 to the common electrode 43. In the second chip 20, the substrate 31, the second N-type contact layer 21, the second light absorbing layer 22, and the second connection layer 23 are stacked in sequence. Optionally, the second N-type contact layer 21 is an N-type semiconductor layer. In other words, the material of the second N-type contact layer 21 is an N-type semiconductor, for example, an N-type doped InGaAs layer. Optionally, the first N-type contact layer 11 and the second N-type contact layer 21 are arranged in the same layer in the optoelectronic chip 1.

[0083] Optionally, the first N-type contact layer 11 is protruding from the first light absorbing layer 12, and part of the first N-type contact layer 11 is exposed on the surface of the first chip 10, and the second N-type contact layer 21 is protruding from the second light absorbing layer 22, and part of the second N-type contact layer 21 is exposed on the surface of the second chip 20. Along the arrangement direction perpendicular to the substrate 31 to the electrode assembly 40, the width of the first N-type contact layer 11 is greater than the width of the first light absorbing layer 12, and the width of the second N-type contact layer 21 is greater than the width of the second light absorbing layer 22. Optionally, at least part of the N-electrode 41 is provided on the side of the first N-type contact layer 11 away from the substrate 31, and part of the common electrode 43 is provided on the side of the second N-type contact layer 21 away from the substrate 31. Optionally, the N-electrode 41 abuts the first N-type contact layer 11, and the common electrode 43 abuts the second N-type contact layer 21. In other words, the N-electrode 41 is directly electrically connected to the first N-type contact layer 11 , and the common electrode 43 is directly electrically connected to the second N-type contact layer 21 .

[0084] In summary, this embodiment improves the electrical signal transmission performance between the N-electrode 41 and the first light absorbing layer 12, and improves the electrical signal transmission performance between the common electrode 43 and the second light absorbing layer 22 by setting the first N-type contact layer 11 and the second N-type contact layer 21, thereby improving the electrical signal transmission performance between the light absorbing layer and the electrode assembly 40.

[0085] Please refer to Figure 1-Figure 5 In one embodiment, the substrate 31 has a first light incident area 15 on a side facing away from the first connection layer 13, and the first light incident area 15 is arranged correspondingly to the first active area 14. The substrate 31 has a second light incident area 25 on a side facing away from the second connection layer 23, and the second light incident area 25 is arranged correspondingly to the second active area 24.

[0086] The first light incident area 15 is used to receive incident light. The incident light enters the first chip 10 through the first light incident area 15. The incident direction of the incident light is as follows: Figure 5The first light incident area 15 is disposed opposite to the first active area 14. The first light incident area 15 is disposed on a side of the substrate 31 away from the first connection layer 13. The first active area 14 is disposed on a side of the first connection layer 13 away from the substrate 31. The orthographic projection of the first light incident area 15 on the first light absorption layer 12 overlaps with the orthographic projection of the first active area 14 on the first light absorption layer 12.

[0087] The second light incident area 25 is used to receive incident light. The incident light enters the second chip 20 through the second light incident area 25. The incident direction of the incident light is as follows: Figure 5 The second light incident area 25 is disposed opposite to the second active area 24. The second light incident area 25 is disposed on a side of the substrate 31 away from the second connection layer 23. The second active area 24 is disposed on a side of the second connection layer 23 away from the substrate 31. The orthographic projection of the second light incident area 25 on the second light absorption layer 22 overlaps with the orthographic projection of the second active area 24 on the second light absorption layer 22.

[0088] In summary, in this embodiment, the first light incident area 15 is arranged back to back with the first active area 14, and the second light incident area 25 is arranged back to back with the second active area 24, so that the optoelectronic chip 1 provided in this embodiment can be flipped on a carrier without the need for welding wires, thereby omitting the welding wires in the related technology, which can further improve the signal-to-noise ratio of the optoelectronic chip 1, further improve the detection performance of the balanced photodetector, and further reduce the overall size of the optoelectronic chip 1.

[0089] Please refer to Figure 1-Figure 5 In one embodiment, the first chip 10 further includes a first anti-transmission layer 16, which is disposed on a surface of the substrate 31 away from the first connection layer 13, and covers the first light entrance area 15. The second chip 20 further includes a second anti-transmission layer 26, which is disposed on a surface of the substrate 31 away from the second connection layer 23, and covers the second light entrance area 25.

[0090] The first anti-reflection layer 16 is used to reduce the reflectivity of the incident light so that more incident light can enter the first chip 10. In other words, the anti-reflection layer is used to increase the transmittance of the incident light. The incident light penetrates the first anti-reflection layer 16 and enters the first chip 10. The first anti-reflection layer 16 abuts against the surface of the substrate 31 away from the first connection layer 13, that is, the first anti-reflection layer 16 is directly arranged on the surface of the substrate 31 away from the first connection layer 13. In the first chip 10, the first anti-reflection layer 16, the substrate 31, the first N-type contact layer 11, the first light absorption layer 12, and the first connection layer 13 are stacked in sequence. The first anti-reflection layer 16 covers the first light entrance area 15, which can be understood as the orthographic projection of the first anti-reflection layer 16 on the first light absorption layer 12 covers the orthographic projection of the first light entrance area 15 on the first light absorption layer 12.

[0091] The second anti-reflection layer 26 is used to reduce the reflectivity of the incident light so that more incident light can enter the second chip 20. In other words, the anti-reflection layer is used to increase the transmittance of the incident light. The incident light penetrates the second anti-reflection layer 26 and enters the second chip 20. The second anti-reflection layer 26 abuts against the surface of the substrate 31 away from the second connection layer 23, that is, the second anti-reflection layer 26 is directly arranged on the surface of the substrate 31 away from the second connection layer 23. In the second chip 20, the second anti-reflection layer 26, the substrate 31, the second N-type contact layer 21, the second light absorption layer 22, and the second connection layer 23 are stacked in sequence. The second anti-reflection layer 26 covers the second light entrance area 25, which can be understood as the orthographic projection of the second anti-reflection layer 26 on the second light absorption layer 22 covers the orthographic projection of the second light entrance area 25 on the second light absorption layer 22. Optionally, the first anti-reflection layer 16 and the second anti-reflection layer 26 are arranged at intervals, and the first anti-reflection layer 16 and the second anti-reflection layer 26 are arranged in the same layer in the optoelectronic chip 1.

[0092] In summary, in this embodiment, the first anti-reflection layer 16 and the second anti-reflection layer 26 are provided to reduce the reflectivity of the incident light, so that more incident light can enter the optoelectronic chip 1 , thereby improving the responsiveness of the optoelectronic chip 1 .

[0093] Please refer to Figure 1-Figure 7 In one embodiment, the optoelectronic chip 1 further includes a protective layer 32, the protective layer 32 covers the first connecting layer 13, the first light absorbing layer 12, the first N-type contact layer 11, the second connecting layer 23, the second light absorbing layer 22, and the second N-type contact layer 21, the N-electrode 41 also penetrates the protective layer 32 and is connected to the first N-type contact layer 11, the common electrode 43 also penetrates the protective layer 32 and is connected to the first active area 14 and the second N-type contact layer 21, and the P-electrode 42 also penetrates the protective layer 32 and is connected to the second active area 24.

[0094] The protective layer 32 is used to suppress surface leakage of the first chip 10 and the second chip 20. The protective layer 32 covers the surfaces of the first connection layer 13, the first light absorption layer 12, the first N-type contact layer 11, the second connection layer 23, the second light absorption layer 22, and the second N-type contact layer 21. Optionally, the protective layer 32 also covers the surfaces of part of the first active area 14 and part of the second active area 24. The material of the protective layer 32 can be silicon oxide, silicon nitride, etc.

[0095] In summary, in this embodiment, by providing the protection layer 32 , the surface leakage of the first chip 10 and the second chip 20 can be suppressed, and the dark current of the optoelectronic chip 1 can be reduced, thereby improving the reliability of the optoelectronic chip 1 .

[0096] In one embodiment, the optoelectronic chip 1 satisfies at least one of the following conditions: the absolute value of the difference in breakdown voltage between the first chip 10 and the second chip 20 is ≤ 0.4 V. The absolute value of the difference in breakdown voltage between the first chip 10 and the second chip 20 can be specifically exemplified as 0.4 V, or 0.35 V, or 0.3 V, or 0.25 V, or 0.2 V, or 0.15 V, or 0.1 V, or 0.05 V, or 0 V, etc.

[0097] And / or, the absolute value of the difference in responsivity between the first chip 10 and the second chip 20 is ≤0.1A / W. The absolute value of the difference in responsivity between the first chip 10 and the second chip 20 can be specifically exemplified as 0.1A / W, or 0.09A / W, or 0.08A / W, or 0.07A / W, or 0.06A / W, or 0.05A / W, or 0.04A / W, or 0.03A / W, or 0.02A / W, or 0.01A / W, or 0A / W, etc.

[0098] And / or, the absolute value of the difference in capacitance between the first chip 10 and the second chip 20 is ≤0.1 pF. The absolute value of the difference in capacitance between the first chip 10 and the second chip 20 can be specifically exemplified as 0.1 pF, or 0.09 pF, or 0.08 pF, or 0.07 pF, or 0.06 pF, or 0.05 pF, or 0.04 pF, or 0.03 pF, or 0.02 pF, or 0.01 pF, or 0 pF, etc.

[0099] In summary, this embodiment combines the first chip 10 and the second chip 20 formed in adjacent parts on the same wafer into an optoelectronic chip 1, so that the performance difference between the first chip 10 and the second chip 20 is small, and the breakdown voltage, responsiveness, and capacitance between the first chip 10 and the second chip 20 are highly consistent, thereby improving the signal-to-noise ratio of the optoelectronic chip 1 and improving the detection performance of the balanced photodetector.

[0100] Please refer to Figure 1-Figure 8 The present application also provides a method for preparing the optoelectronic chip 1 as provided above in the present application, the preparation method comprising:

[0101] S100, provides one wafer.

[0102] S200, forming a first chip 10 and a second chip 20, wherein the first chip 10 and the second chip 20 are connected and arranged adjacent to each other, the first chip 10 is prepared from the first part of the wafer, the second chip 20 is prepared from the second part of the wafer, and the first part and the second part are connected and arranged adjacent to each other.

[0103] S300, forming an electrode assembly 40, wherein the electrode assembly 40 is disposed on the same side of the first chip 10 and the second chip 20, and the electrode assembly 40 includes an N electrode 41, a P electrode 42, and a common electrode 43, wherein the N electrode 41 and the common electrode 43 are both connected to the first chip 10, and the P electrode 42 and the common electrode 43 are both connected to the second chip 20.

[0104] In summary, the preparation method of the optoelectronic chip 1 provided in the present embodiment adopts a first chip 10 and a second chip 20 formed in adjacent parts on the same wafer to combine into an optoelectronic chip 1. Since the performance difference between adjacent parts of the same wafer is small, the performance difference between the first chip 10 and the second chip 20 is small, and the first chip 10 and the second chip 20 are highly consistent. Therefore, by combining the first chip 10 and the second chip 20, the signal-to-noise ratio of the optoelectronic chip 1 can be improved, and the detection performance of the balanced photodetector can be improved; and, the present application forms an electrode assembly 40 through process design to combine the first chip 10 and the second chip 20 together, thereby reducing the overall size of the optoelectronic chip 1 and improving the output efficiency of the optoelectronic chip 1.

[0105] Please refer to Figure 1-Figure 9 In one embodiment, the wafer includes a substrate 31, and the step S200 of forming the first chip 10 and the second chip 20 includes:

[0106] S210 , forming a first active region 14 disposed in the first portion, the first active region 14 forming a first PN junction, and forming a second active region 24 disposed in the second portion, the second active region 24 forming a second PN junction.

[0107] Specifically, a passivation film is first formed on the surface of the wafer, and the passivation film is used to block the diffusion of doped elements in the non-diffusion area to form a specific diffusion area; then a diffusion window is etched on the passivation film, that is, the passivation film in a partial area is removed; then, specific elements are diffused and doped at the diffusion window to form a first active area 14 and a second active area 24.

[0108] Optionally, the material of the passivation film can be SiN or SiO 2 In other words, the passivation film is a SiN dielectric film or a SiO 2 Dielectric film, etc.

[0109] S220, forming a first N-type contact layer 11, a first light absorption layer 12, and a first connection layer 13 stacked in sequence on the substrate 31, the first active region 14 is arranged in the first connection layer 13 and the first light absorption layer 12, and forming a second N-type contact layer 21, a second light absorption layer 22, and a second connection layer 23 stacked in sequence on the substrate 31, the second active region 24 is arranged in the second connection layer 23 and the second light absorption layer 22.

[0110] Specifically, the remaining passivation film is first removed, and then an etching process is performed to form a PN table stacked sequentially on the substrate 31. In other words, an etching process is performed to form a first N-type contact layer 11, a first light absorption layer 12, and a first connection layer 13 stacked sequentially on the substrate 31, and a second N-type contact layer 21, a second light absorption layer 22, and a second connection layer 23 stacked sequentially on the substrate 31.

[0111] Please refer to Figure 1-Figure 10 In one embodiment, in the step S200 of forming the first chip 10 and the second chip 20, the step further includes:

[0112] S230, forming a first light entrance zone 15, wherein the first light entrance zone 15 is disposed on a side of the substrate 31 away from the first connecting layer 13, and the first light entrance zone 15 is disposed correspondingly to the first active zone 14, and forming a second light entrance zone 25, wherein the second light entrance zone 25 is disposed on a side of the substrate 31 away from the second connecting layer 23, and the second light entrance zone 25 is disposed correspondingly to the second active zone 24.

[0113] S240, forming a first anti-transmittance layer 16, wherein the first anti-transmittance layer 16 is disposed on a surface of the substrate 31 away from the first connecting layer 13, and the first anti-transmittance layer 16 covers the first light entrance area 15, and forming a second anti-transmittance layer 26, wherein the second anti-transmittance layer 26 is disposed on a surface of the substrate 31 away from the second connecting layer 23, and the second anti-transmittance layer 26 covers the second light entrance area 25.

[0114] Optionally, a grinding and polishing process is performed on a side of the substrate 31 in the wafer facing away from the first connection layer 13 to reduce the overall thickness of the wafer and the overall size of the optoelectronic chip 1 .

[0115] Specifically, an anti-reflection film is first grown on the surface of the substrate 31 away from the first connection layer 13, and then the anti-reflection films corresponding to the first light incident area 15 and the second light incident area 25 are retained, and the redundant anti-reflection films are removed by etching process, thereby obtaining the first anti-reflection layer 16 and the second anti-reflection layer 26. In this preparation process, the first anti-reflection layer 16 and the second anti-reflection layer 26 are prepared at the same time, simplifying the process and improving the output efficiency.

[0116] The optoelectronic chip 1 prepared in this embodiment adopts the back-lighting method, which saves the wire bonding process in the packaging process, further reduces the crosstalk caused by the wire bonding, and thus improves the signal-to-noise ratio.

[0117] Please refer to Figure 1-Figure 12 In one embodiment, in the step S200 of forming the first chip 10 and the second chip 20, the step further includes:

[0118] S250 , forming a protection layer 32 , wherein the protection layer 32 covers the first connection layer 13 , the first light absorption layer 12 , the first N-type contact layer 11 , the second connection layer 23 , the second light absorption layer 22 , and the second N-type contact layer 21 .

[0119] In step S300 of forming the electrode assembly 40, the following steps are included:

[0120] S310, the N-electrode 41 also penetrates the protective layer 32 and is connected to the first N-type contact layer 11, the common electrode 43 also penetrates the protective layer 32 and is connected to the first active area 14 and the second N-type contact layer 21, and the P-electrode 42 also penetrates the protective layer 32 and is connected to the second active area 24.

[0121] Specifically, first, a protective layer 32 is generated to cover the first connection layer 13, the first light absorption layer 12, the first N-type contact layer 11, the second connection layer 23, the second light absorption layer 22, and the second N-type contact layer 21; then, a first through hole, a second through hole, a third through hole, and a fourth through hole are etched on the protective layer 32, the first N-type contact layer 11 is exposed from the first through hole, the first active area 14 is exposed from the second through hole, the second N-type contact layer 21 is exposed from the third through hole, and the second active area 24 is exposed from the fourth through hole; an N-electrode 41, a common electrode 43, and a P-electrode 42 are formed on the protective layer 32, and the N-electrode 41 is also arranged in the first through hole and connected to the first N-type contact layer 11, the common electrode 43 is also arranged in the second through hole and the third through hole and connected to the first active area 14 and the second N-type contact layer 21, and the P-electrode 42 is also arranged in the fourth through hole and connected to the second active area 24.

[0122] The following is a detailed introduction to a method for preparing an optoelectronic chip 1 in one embodiment. First, a passivation film is formed on the surface of a provided wafer; then a diffusion window is etched on the passivation film; then, specific elements are diffused and doped at the diffusion window to form a first active area 14 and a second active area 24.

[0123] Then, the remaining passivation film is removed, and then an etching process is performed to form a PN table stacked in sequence on the substrate 31. In other words, through the etching process, a first N-type contact layer 11, a first light absorption layer 12, and a first connection layer 13 stacked in sequence on the substrate 31 are formed, and a second N-type contact layer 21, a second light absorption layer 22, and a second connection layer 23 stacked in sequence on the substrate 31 are formed.

[0124] Next, a protective layer 32 is generated to cover the first connection layer 13, the first light absorption layer 12, the first N-type contact layer 11, the second connection layer 23, the second light absorption layer 22, and the second N-type contact layer 21; then a plurality of through holes are etched on the protective layer 32; and then an electrode assembly 40 is formed, and part of the electrode assembly 40 is disposed in the through hole to realize electrical connection between the electrode assembly 40 and the first chip 10 and the second chip 20; wherein the N-electrode 41 is connected to the first N-type contact layer 11, the common electrode 43 is connected to the first active area 14 and the second N-type contact layer 21, and the P-electrode 42 is connected to the second active area 24.

[0125] Subsequently, the side of the substrate 31 in the wafer facing away from the first connection layer 13 is ground and polished to reduce the overall thickness of the wafer and the overall size of the optoelectronic chip 1; then, an anti-reflection film is grown on the surface of the substrate 31 facing away from the first connection layer 13; the anti-reflection films corresponding to the first light entrance area 15 and the second light entrance area 25 are retained, and the excess anti-reflection films are removed by an etching process to obtain the first anti-reflection layer 16 and the second anti-reflection layer 26; finally, the optoelectronic chip 1 provided above in the present application is obtained.

[0126] The present application also provides a balanced photoelectric detector, which includes a processor and an optoelectronic chip as provided above in the present application, wherein the processor is electrically connected to the optoelectronic chip, and the processor is used to control the optoelectronic chip.

[0127] Balanced photodetectors can be used in optical communications, fiber optic sensing, optical measurement, optical imaging, optical remote sensing and other fields, which are not limited in this application.

[0128] Specifically, the balanced photodetector can be used in intelligent driving, sweeping robots, mobile phones, tablet computers, laptops, PDAs, personal computers (PCs), personal digital assistants (PDAs), portable media players (PMPs), headphones, cameras, smart wearable devices, smart screens, display screens, wind power generation equipment, etc. It is understandable that the above-mentioned application fields of the balanced photodetector should not be understood as limiting the balanced photodetector provided in the embodiments of the present application.

[0129] In summary, the balanced photodetector provided by the present application adopts the optoelectronic chip provided by the present application. The optoelectronic chip adopts a first chip and a second chip formed in adjacent parts on the same wafer to form a photoelectric chip. Since the performance difference between adjacent parts of the same wafer is small, the performance difference between the first chip and the second chip is small, and the first chip and the second chip are highly consistent. Therefore, by combining the first chip and the second chip, the signal-to-noise ratio of the optoelectronic chip can be improved, and the detection performance of the balanced photodetector can be improved; and, the present application forms an electrode assembly to combine the first chip and the second chip together through process design, thereby reducing the overall size of the optoelectronic chip and improving the output efficiency of the optoelectronic chip; adopts the back-side light input method to save the wire bonding process in the packaging process, further reduce the crosstalk caused by the wire bonding, and thus improve the signal-to-noise ratio.

[0130] The present application also provides an optical communication device, which includes a transmitting chip and a balanced photodetector as provided above in the present application, wherein the transmitting chip is used to transmit an optical signal, and the balanced photodetector is used to receive the optical signal.

[0131] In summary, the optical communication equipment provided by the present application adopts the balanced photodetector provided by the present application, and adopts the first chip and the second chip formed in adjacent parts on the same wafer to form a photoelectric chip. Since the performance difference on adjacent parts of the same wafer is small, the performance difference between the first chip and the second chip is small, and the first chip and the second chip are highly consistent. Therefore, by combining the first chip and the second chip, the signal-to-noise ratio of the photoelectric chip can be improved, and the detection performance of the balanced photodetector can be improved; and, the present application forms an electrode assembly to combine the first chip and the second chip together through process design, thereby reducing the overall size of the photoelectric chip and improving the output efficiency of the photoelectric chip; adopts the back-side light input method to save the wire bonding process in the packaging process, further reduce the crosstalk caused by the wire bonding, and thus improve the signal-to-noise ratio.

[0132] In order to make the purpose and advantages of the present application clearer, the effects of the optoelectronic chip of the present application are further described in detail below in conjunction with specific embodiments.

[0133] Embodiment 1-4: The optoelectronic chips are obtained by the above-mentioned preparation method of the present application, and the breakdown voltage, responsivity, and capacitance of the first chip and the second chip in each optoelectronic chip are detected.

[0134] Among them, Table 1 gives the breakdown voltage, responsivity, and capacitance of the first chip and the second chip in each optoelectronic chip of Examples 1-4, and also gives the absolute value of the difference in breakdown voltage between the first chip and the second chip, the absolute value of the difference in responsivity between the first chip and the second chip, and the absolute value of the difference in capacitance between the first chip and the second chip for reference.

[0135]

[0136] According to Table 1, by combining the first chip and the second chip formed in adjacent parts on the same wafer as an optoelectronic chip, the performance difference between the first chip and the second chip is small, and the breakdown voltage, responsiveness, and capacitance between the first chip and the second chip are highly consistent. The absolute value of the difference in breakdown voltage between the first chip and the second chip is ≤0.4V, the absolute value of the difference in responsiveness between the first chip and the second chip is ≤0.1A / W, and the absolute value of the difference in capacitance between the first chip and the second chip is ≤0.1pF, thereby improving the signal-to-noise ratio of the optoelectronic chip and improving the detection performance of the balanced photodetector.

[0137] Unless otherwise specified or there is a contradiction, the terms and phrases used in this application have the following meanings:

[0138] In this application, "first", "second", etc. are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0139] In this application, "one or several" refers to any one, any two or more of the listed items. Among them, "several" refers to any two or more of the listed items.

[0140] In the present application, it is necessary to understand that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0141] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0142] Mentioning "embodiment" and "implementation method" in this application means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrases in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments. In addition, it should also be understood that the features, structures or characteristics described in the various embodiments of the present application can be arbitrarily combined to form another embodiment that does not deviate from the spirit and scope of the technical solution of the present application, provided that there is no contradiction between them.

[0143] The above is part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications are also considered to be within the scope of protection of the present application.

Claims

1. An optoelectronic chip, characterized in that: Applied to a balanced photoelectric detector, the photoelectric chip comprises: A first chip and a second chip, the first chip and the second chip are connected and arranged adjacent to each other, the first chip and the second chip are prepared from the same wafer, the first chip is prepared from a first part of the wafer, the second chip is prepared from a second part of the wafer, and the first part and the second part are connected and arranged adjacent to each other; an electrode assembly, the electrode assembly being disposed on the same side of the first chip and the second chip, the electrode assembly comprising an N electrode, a P electrode, and a common electrode, the N electrode and the common electrode being both connected to the first chip, and the P electrode and the common electrode being both connected to the second chip; The first chip and the second chip include a same substrate, and the electrode assembly is disposed on a side of the first chip and the second chip away from the substrate; The first chip further comprises a first light absorbing layer disposed between the substrate and the electrode assembly, a first active region is provided on a side of the first chip facing the electrode assembly, at least a portion of the first active region is disposed in the first light absorbing layer, the first active region forms a first PN junction, and the common electrode is connected to the first active region; The second chip further includes a second light absorbing layer disposed between the substrate and the electrode assembly, the second light absorbing layer being spaced apart from the first light absorbing layer, the second chip having a second active region on a side facing the electrode assembly, at least a portion of the second active region being disposed in the second light absorbing layer, the second active region forming a second PN junction, and the P electrode being connected to the second active region; The first chip further includes a first connection layer disposed between the first light absorbing layer and the electrode assembly, the first active area includes a first sub-area and a second sub-area connected to each other, the first sub-area is disposed in the first connection layer, the second sub-area is disposed in the first light absorbing layer, and the common electrode is connected to the first sub-area; The second chip further includes a second connection layer disposed between the second light absorbing layer and the electrode assembly, the second connection layer is spaced apart from the first connection layer, the second active region includes a third sub-region and a fourth sub-region connected to each other, the third sub-region is disposed in the second connection layer, the fourth sub-region is disposed in the second light absorbing layer, and the P electrode is connected to the third sub-region; Along the arrangement direction from the substrate to the electrode assembly, the height of the first sub-region is greater than the height of the second sub-region; the height of the first sub-region is equal to the thickness of the first connecting layer, and the height of the second sub-region is less than the thickness of the first light absorbing layer; the doping concentration of the first sub-region is greater than the doping concentration of the second sub-region; the height of the third sub-region is greater than the height of the fourth sub-region; the height of the third sub-region is equal to the thickness of the second connecting layer, and the height of the fourth sub-region is less than the thickness of the second light absorbing layer; the doping concentration of the third sub-region is greater than the doping concentration of the fourth sub-region; A first light incident area is provided on a side of the substrate facing away from the first connecting layer, and the first light incident area is arranged corresponding to the first active area; A second light incident area is provided on a side of the substrate facing away from the second connecting layer, and the second light incident area is arranged correspondingly to the second active area; The optoelectronic chip satisfies at least one of the following conditions: The absolute value of the difference in breakdown voltage between the first chip and the second chip is ≤0.4V; The absolute value of the difference in responsivity between the first chip and the second chip is ≤0.1A / W; The absolute value of the difference in capacitance between the first chip and the second chip is ≤0.1 pF.

2. The optoelectronic chip according to claim 1, characterized in that: The first chip further includes a first N-type contact layer disposed between the substrate and the first light absorbing layer, the N-electrode is disposed on a side of the first N-type contact layer away from the substrate, and the N-electrode is connected to the first N-type contact layer; The second chip also includes a second N-type contact layer disposed between the substrate and the second light absorbing layer, the second N-type contact layer is spaced apart from the first N-type contact layer, the common electrode is disposed on a side of the second N-type contact layer away from the substrate, and the common electrode is connected to the second N-type contact layer.

3. The optoelectronic chip according to claim 1, characterized in that: The first chip further includes a first anti-reflection layer, which is disposed on a surface of the substrate away from the first connecting layer, and covers the first light incident area; The second chip further includes a second anti-transmission layer, which is disposed on a surface of the substrate facing away from the second connecting layer, and covers the second light incident area.

4. The optoelectronic chip according to claim 2, characterized in that: The optoelectronic chip also includes a protective layer, which covers the first connecting layer, the first light absorbing layer, the first N-type contact layer, the second connecting layer, the second light absorbing layer, and the second N-type contact layer. The N-electrode also penetrates the protective layer and is connected to the first N-type contact layer. The common electrode also penetrates the protective layer and is connected to the first active area and the second N-type contact layer. The P-electrode also penetrates the protective layer and is connected to the second active area.

5. A method for preparing an optoelectronic chip as claimed in claim 1, characterized in that: The preparation method comprises: providing a wafer; forming a first chip and a second chip, wherein the first chip and the second chip are connected and arranged adjacent to each other, the first chip is prepared from the first part of the wafer, the second chip is prepared from the second part of the wafer, and the first part and the second part are connected and arranged adjacent to each other; An electrode assembly is formed, wherein the electrode assembly is disposed on the same side of the first chip and the second chip, and the electrode assembly includes an N electrode, a P electrode, and a common electrode. The N electrode and the common electrode are both connected to the first chip, and the P electrode and the common electrode are both connected to the second chip.

6. The method for preparing an optoelectronic chip according to claim 5, characterized in that: The wafer includes a substrate, and the step of forming the first chip and the second chip includes: forming a first active region disposed in the first portion, the first active region forming a first PN junction, and forming a second active region disposed in the second portion, the second active region forming a second PN junction; A first N-type contact layer, a first light absorption layer, and a first connection layer are sequentially stacked on the substrate, the first active region is disposed in the first connection layer and the first light absorption layer, and a second N-type contact layer, a second light absorption layer, and a second connection layer are sequentially stacked on the substrate, the second active region is disposed in the second connection layer and the second light absorption layer.

7. The method for preparing an optoelectronic chip according to claim 6, characterized in that: The step of forming the first chip and the second chip further includes: forming a first light incident area, the first light incident area is arranged on a side of the substrate away from the first connection layer, and the first light incident area is arranged correspondingly to the first active area, and forming a second light incident area, the second light incident area is arranged on a side of the substrate away from the second connection layer, and the second light incident area is arranged correspondingly to the second active area; A first anti-transmittance layer is formed, the first anti-transmittance layer is arranged on the surface of the substrate away from the first connecting layer, the first anti-transmittance layer covers the first light entrance area, and a second anti-transmittance layer is formed, the second anti-transmittance layer is arranged on the surface of the substrate away from the second connecting layer, the second anti-transmittance layer covers the second light entrance area.

8. The method for preparing an optoelectronic chip according to claim 6, characterized in that: The step of forming the first chip and the second chip further includes: forming a protective layer, wherein the protective layer covers the first connecting layer, the first light absorbing layer, the first N-type contact layer, the second connecting layer, the second light absorbing layer, and the second N-type contact layer; The step of forming the electrode assembly includes: The N-electrode also penetrates the protective layer and is connected to the first N-type contact layer. The common electrode also penetrates the protective layer and is connected to the first active region and the second N-type contact layer. The P-electrode also penetrates the protective layer and is connected to the second active region.

9. A balanced photodetector, characterized in that: The balanced photodetector comprises a processor and the optoelectronic chip according to any one of claims 1 to 4, wherein the processor is electrically connected to the optoelectronic chip and is used to control the optoelectronic chip.

10. An optical communication device, characterized in that: The optical communication device comprises a transmitting chip and the balanced photodetector as claimed in claim 9, wherein the transmitting chip is used to transmit an optical signal, and the balanced photodetector is used to receive the optical signal.

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