Image sensor

Abstract

An image sensor includes a substrate having a plurality of pixel regions and a deep device isolation pattern disposed in the substrate between the pixel regions. The plurality of pixel regions includes a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region adjacent to each other in a first direction and a second direction. The deep device isolation pattern includes first portions interposed between the first pixel region and the second pixel region and between the third pixel region and the fourth pixel region and spaced apart from each other in the second direction, and a second portion interposed between the first pixel region and the third pixel region and between the second pixel region and the fourth pixel region and spaced apart from each other in the first direction. The first pixel region includes a first extended active pattern extending in a first direction to the second pixel region and disposed between the first portions of the deep device isolation pattern.

Description

[0001] This application is a divisional application of a patent application with a filing date of May 19, 2022, application number 202210556606.8, and title “Image Sensor”. Technical Field

[0002] The present disclosure relates to image sensors, and in particular to complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0003] Image sensor can be a semiconductor device that converts an optical image into an electrical signal. With the latest developments in the computer and communication industries, the demand for high-performance image sensors in various applications such as digital cameras, video cameras, personal communication systems, game consoles, security cameras, miniature cameras for medical applications, robots, etc. is increasing. Such image sensors can be classified into various types including at least a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. Typically, a CMOS type image sensor (CIS) device can include a plurality of pixels arranged in two dimensions. Each pixel can include a photodiode (PD) that converts incident light into an electrical signal. Pixels can be defined by a deep isolation pattern disposed between them. Summary of the invention

[0004] Embodiments of the present disclosure provide an image sensor configured to minimize crosstalk between pixels and increase the size of a gate electrode and a method of manufacturing the same.

[0005] Embodiments of the present disclosure provide an image sensor having an increased integration density and a method of manufacturing the same.

[0006] According to an embodiment of the present disclosure, an image sensor may include: a substrate including a plurality of pixel regions; and a deep device isolation pattern, the deep device isolation pattern being disposed in the substrate between the pixel regions. The plurality of pixel regions may include: a first pixel region and a second pixel region, the first pixel region and the second pixel region being adjacent to each other in a first direction parallel to the first surface of the substrate; a third pixel region, the third pixel region being adjacent to the first pixel region in a second direction, the second direction being parallel to the first surface of the substrate and intersecting the first direction; and a fourth pixel region, the fourth pixel region being adjacent to the second pixel region in the second direction and adjacent to the third pixel region in the first direction. The deep device isolation pattern may include: a first portion, the first portion being between the first pixel region and the second pixel region and between the third pixel region and the fourth pixel region, and being spaced apart from each other in the second direction; and a second portion, the second portion being between the first pixel region and the third pixel region and between the second pixel region and the fourth pixel region, and being spaced apart from each other in the first direction. The first pixel region may include a first extended active pattern. The first extended active pattern may extend to the second pixel region in the first direction and may be disposed between the first portions of the deep device isolation pattern.

[0007] According to an embodiment of the present disclosure, an image sensor may include: a substrate having a first surface and a second surface disposed opposite to each other; and a deep device isolation pattern, the deep device isolation pattern penetrating the substrate. The deep device isolation pattern may have a top surface exposed to the outside of the substrate near the first surface of the substrate and a bottom surface exposed to the outside of the substrate near the second surface of the substrate. The substrate may include: a first pixel region and a second pixel region, the first pixel region and the second pixel region are adjacent to each other in a first direction parallel to the first surface; a third pixel region, the third pixel region is adjacent to the first pixel region in a second direction parallel to the first surface and intersecting the first direction; and a fourth pixel region, the fourth pixel region is adjacent to the second pixel region in the second direction and adjacent to the third pixel region in the first direction. The deep device isolation pattern may include: a first portion, the first portion is between the first pixel region and the second pixel region and between the third pixel region and the fourth pixel region, and is spaced apart from each other in the second direction; and a second portion, the second portion is between the first pixel region and the third pixel region and between the second pixel region and the fourth pixel region, and is spaced apart from each other in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram schematically illustrating an image sensor according to an embodiment of the present disclosure.

[0009] Figure 2 is a circuit diagram showing an active pixel sensor array of an image sensor according to an embodiment of the present disclosure.

[0010] Figure 3 is a top view showing an image sensor according to an embodiment of the present disclosure.

[0011] Figure 4A , Figure 4B and Figure 4C are respectively along Figure 3 Cross-sectional views taken along line AA', line BB' and line CC'.

[0012] Figure 5A , Fig. 6A and Fig. 7A It is along Figure 3 A cross-sectional view taken along line AA′ of FIG. 1 is shown to illustrate a method of manufacturing an image sensor according to an embodiment of the present disclosure.

[0013] Figure 5B , Figure 6B and Figure 7B It is along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 is shown to illustrate a method of manufacturing an image sensor according to an embodiment of the present disclosure.

[0014] Figure 5C , Figure 6C and Figure 7C It is along Figure 3 A cross-sectional view taken along line CC' of FIG. 1 is provided to illustrate a method of manufacturing an image sensor according to an embodiment of the present disclosure.

[0015] Figure 8 is a top view showing an image sensor according to an embodiment of the present disclosure.

[0016] Fig.9A , Fig. 9B and Fig. 9C are respectively along Figure 8 Cross-sectional views taken along line AA', line BB' and line CC'.

[0017] Fig.10 It is along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 is shown to illustrate an image sensor according to an embodiment of the present disclosure.

[0018] Figures 11 to 16is a top view showing an image sensor according to an embodiment of the present disclosure.

[0019] Fig.17A , Fig. 17B and Fig. 17C are respectively along Figure 3 sectional views taken along lines AA′, BB′, and CC′ of FIG. 1 to illustrate an image sensor according to an embodiment of the present disclosure.

[0020] Fig.18 is a top view showing an image sensor according to an embodiment of the present disclosure.

[0021] Fig.19 It is along Fig.18 A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0022] Exemplary embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, wherein like reference numerals may be used to refer to like features, but not limited thereto.

[0023] Figure 1 An image sensor according to an embodiment of the present disclosure is shown.

[0024] refer to Figure 1 , the image sensor 101 may include an active pixel sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7 and an input / output (I / O) buffer 8.

[0025] The active pixel sensor array 1 may include a plurality of pixels arranged two-dimensionally and used to convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) provided from the row driver 3. In addition, the electrical signal converted by the active pixel sensor array 1 may be provided to the CDS 6.

[0026] The row driver 3 may provide a plurality of driving signals for driving pixels to the active pixel sensor array 1 based on the results decoded by the row decoder 2. In the case where the pixels are arranged in a matrix shape, the driving signals may be applied to the pixels of each row.

[0027] The timing generator 5 may be configured to provide timing signals and control signals to the row decoder 2 and the column decoder 4 .

[0028] The CDS 6 may be configured to receive the electrical signal generated by the active pixel sensor array 1 and perform a hold and a sampling operation on the received electrical signal. In addition, the CDS 6 may be configured to perform a double sampling operation using a specific noise level and a signal level of the electrical signal and then output a difference level corresponding to the difference between the noise level and the signal level.

[0029] The ADC 7 may be configured to convert an analog signal containing information on the difference level output from the CDS 6 into a digital signal and output the converted digital signal.

[0030] The I / O buffer 8 may be configured to latch the digital signal and then sequentially output the latched digital signal to an image signal processing unit (not shown) based on the result of decoding by the column decoder 4 .

[0031] Figure 2 An active pixel sensor array of an image sensor according to an embodiment of the present disclosure is shown.

[0032] refer to Figure 1 and Figure 2 , the active pixel sensor array 1 may include a portion 200 having a plurality of pixels PX arranged in a matrix shape. Each pixel PX may include a transfer transistor TX and logic transistors RX, SX, and DX. The logic transistor may include a reset transistor RX, a select transistor SX, and a drive transistor DX. The transfer transistor TX, the reset transistor RX, and the select transistor SX may include a transfer gate TG, a reset gate RG, and a select gate SG, respectively. Each pixel PX may also include a photoelectric conversion device PD and a floating diffusion region FD.

[0033] The photoelectric conversion device PD may be configured to generate and maintain photoelectric charges whose amount is proportional to the amount of light incident from the outside. The photoelectric conversion device PD may be a photodiode including a p-type impurity region and an n-type impurity region. The transfer transistor TX may be configured to transfer the charge generated in the photoelectric conversion device PD to the floating diffusion region FD. The floating diffusion region FD may be configured to receive the charge generated in the photoelectric conversion device PD and cumulatively store the charge therein. The drive transistor DX may be controlled by the amount of photoelectric charge stored in the floating diffusion region FD.

[0034] The reset transistor RX may be configured to periodically release the charge stored in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power supply voltage V DD If the reset transistor RX is turned on, the power supply voltage V connected to the source electrode of the reset transistor RX DDmay be applied to the floating diffusion region FD. Therefore, the reset transistor RX may be turned on, and in this case, the charges stored in the floating diffusion region FD may be discharged; that is, the floating diffusion region FD may be reset.

[0035] The drive transistor DX may be used as a source follower buffer amplifier. The drive transistor DX may be configured to amplify a change in the potential of the floating diffusion region FD and output the amplified signal to the output line V OUT .

[0036] The select transistor SX can be used to select a row of pixels P to be read out during a read operation. If the select transistor SX is turned on, the power supply voltage V DD It can be applied to the drain electrode of the driving transistor DX.

[0037] Figure 2 A unit pixel PX including one photoelectric conversion device PD and four transistors TX, RX, DX, and SX is shown, but the present disclosure is not limited to this structure of the image sensor. For example, the reset transistor RX, the drive transistor DX, or the selection transistor SX can be shared by adjacent pixels PX. In this case, the integration density of the image sensor can be increased.

[0038] Figure 3 An image sensor according to an embodiment of the present disclosure is shown. Figure 4A , Figure 4B and Figure 4C Shown along Figure 3 Cross-sectional views taken along line AA', line BB' and line CC'.

[0039] refer to Figure 3 and FIG. 4A to FIG. 4C , for example, in cross sections 400A, 400B, and 400C, image sensor 300 may include photoelectric conversion layer 10, interconnection layer 20, and optically transparent layer 30. Photoelectric conversion layer 10 may be disposed between interconnection layer 20 and optically transparent layer 30.

[0040] The photoelectric conversion layer 10 may include a substrate 100, and the substrate 100 may include a plurality of pixel regions PXR1, PXR2, PXR3, and PXR4. The substrate 100 may be a semiconductor substrate (e.g., a silicon wafer, a germanium wafer, a silicon germanium wafer, a II-VI compound semiconductor wafer, or a III-V compound semiconductor wafer) or a silicon on insulator (SOI) wafer. The substrate 100 may have a first surface 100a and a second surface 100b disposed opposite to each other. The pixel regions PXR1, PXR2, PXR3, and PXR4 may be arranged two-dimensionally in a first direction D1 and a second direction D2 parallel to the first surface 100a of the substrate 100. The first direction D1 and the second direction D2 may intersect each other or may not be parallel to each other.

[0041] The photoelectric conversion layer 10 may further include a deep device isolation pattern 150 disposed to penetrate the substrate 100 and disposed between the pixel regions PXR1, PXR2, PXR3, and PXR4. The deep device isolation pattern 150 may be disposed to penetrate the substrate 100 in a third direction D3 perpendicular to the first surface 100a of the substrate 100. The deep device isolation pattern 150 may extend from the first surface 100a of the substrate 100 toward the second surface 100b of the substrate 100. A top surface 150U of the deep device isolation pattern 150 may be exposed to the outside of the substrate 100 near the first surface 100a, and a bottom surface 150B of the deep device isolation pattern 150 may be exposed to the outside of the substrate 100 near the second surface 100b. In other words, the first surface 100a of the substrate 100 may expose the top surface 150U of the deep device isolation pattern 150, and the second surface 100b of the substrate 100 may expose the bottom surface 150B of the deep device isolation pattern 150. A top surface 150U of the deep device isolation pattern 150 may be substantially coplanar with the first surface 100a of the substrate 100, and a bottom surface 150B of the deep device isolation pattern 150 may be substantially coplanar with the second surface 100b of the substrate 100. The deep device isolation pattern 150 may prevent crosstalk from occurring between adjacent pixel regions among the pixel regions PXR1, PXR2, PXR3, and PXR4.

[0042] The deep device isolation pattern 150 may include semiconductor patterns 152 and 154 penetrating at least a portion of the substrate 100, a gap-filling insulating pattern 158 located on the semiconductor patterns 152 and 154, and a sidewall insulating pattern 156 interposed between the semiconductor patterns 152 and 154 and the substrate 100. The sidewall insulating pattern 156 may extend from the side surfaces of the semiconductor patterns 152 and 154 to the side surfaces of the gap-filling insulating pattern 158. The semiconductor patterns 152 and 154 may include a first semiconductor pattern 152 and a second semiconductor pattern 154, the first semiconductor pattern 152 being disposed penetrating at least a portion of the substrate 100, and the second semiconductor pattern 154 being interposed between the first semiconductor pattern 152 and the sidewall insulating pattern 156. The first semiconductor pattern 152 may cover the topmost surface of the second semiconductor pattern 154 and may be in contact with the sidewall insulating pattern 156. The gap-filling insulating pattern 158 may be disposed on the first semiconductor pattern 152. The first semiconductor pattern 152 may extend into a region between the gap-filling insulating pattern 158 and the second semiconductor pattern 154 , and may make contact with the sidewall insulating pattern 156 .

[0043] The first semiconductor pattern 152 and the second semiconductor pattern 154 may be formed of a doped semiconductor material or include a doped semiconductor material. In an embodiment, the first semiconductor pattern 152 and the second semiconductor pattern 154 may be formed of a p-type or n-type semiconductor material or include a p-type or n-type semiconductor material. As an example, the first semiconductor pattern 152 and the second semiconductor pattern 154 may be formed of boron-doped polysilicon or include boron-doped polysilicon. The sidewall insulating pattern 156 and the gap-filling insulating pattern 158 may be formed of, for example, at least one of silicon oxide, silicon nitride and / or silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride and / or silicon oxynitride.

[0044] The pixel regions PXR1, PXR2, PXR3, and PXR4 may include a first pixel region PXR1, a second pixel region PXR2, a third pixel region PXR3, and a fourth pixel region PXR4 that are adjacent to each other in the first direction D1 and the second direction D2. As an example, the first pixel region PXR1 may be adjacent to the second pixel region PXR2 in the first direction D1, and the third pixel region PXR3 may be adjacent to the first pixel region PXR1 in the second direction D2. The fourth pixel region PXR4 may be adjacent to the second pixel region PXR2 in the second direction D2, and may be adjacent to the third pixel region PXR3 in the first direction D1. However, the present disclosure is not limited to the aforementioned arrangement of the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4. For example, the first pixel region PXR1 may be adjacent to the second pixel region PXR2 in the second direction D2, and the third pixel region PXR3 may be adjacent to the first pixel region PXR1 in the first direction D1. The fourth pixel region PXR4 may be adjacent to the second pixel region PXR2 in the first direction D1, and may be adjacent to the third pixel region PXR3 in the second direction D2. For the sake of brevity, the following description will refer to an example in which the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 are arranged so that the first pixel region PXR1 and the second pixel region PXR2 are adjacent to each other in the first direction D1.

[0045] When viewed in a top view, the deep device isolation pattern 150 may be disposed to surround the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4. The deep device isolation pattern 150 may include a first portion 150P1 and a second portion 150P2, the first portion 150P1 extending to a region between the first pixel region PXR1 and the second pixel region PXR2 and a region between the third pixel region PXR3 and the fourth pixel region PXR4, respectively, and the second portion 150P2 extending to a region between the first pixel region PXR1 and the third pixel region PXR3 and a region between the second pixel region PXR2 and the fourth pixel region PXR4, respectively. The first portions 150P1 may be interposed between the first pixel region PXR1 and the second pixel region PXR2 and between the third pixel region PXR3 and the fourth pixel region PXR4, respectively, and may be spaced apart from each other in the second direction D2. Each first portion 150P1 may have a strip shape extending in the second direction D2. The second portions 150P2 may be interposed between the first and third pixel regions PXR1 and PXR3 and between the second and fourth pixel regions PXR2 and PXR4, respectively, and may be spaced apart from each other in the first direction D1. Each second portion 150P2 may have a bar shape extending in the first direction D1.

[0046] The first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may be partially separated from each other by the first portion 150P1 and the second portion 150P2 of the deep device isolation pattern 150. In an embodiment, the first pixel region PXR1 and the second pixel region PXR2 may be partially separated from each other by one first portion 150P1 of the deep device isolation pattern 150, and the third pixel region PXR3 and the fourth pixel region PXR4 may be partially separated from each other by another first portion 150P1 of the deep device isolation pattern 150. The first pixel region PXR1 and the third pixel region PXR3 may be partially separated from each other by one second portion 150P2 of the deep device isolation pattern 150, and the second pixel region PXR2 and the fourth pixel region PXR4 may be partially separated from each other by another second portion 150P2 of the deep device isolation pattern 150. Because the first portions 150P1 are spaced apart from each other in the second direction D2 and the second portions 150P2 are spaced apart from each other in the first direction D1, the first to fourth pixel regions PXR1, PXR2, PXR3, and PXR4 of the substrate 100 may be partially connected to each other.

[0047] Each of the pixel regions PXR1, PXR2, PXR3, and PXR4 may include a photoelectric conversion region 110. The substrate 100 may have a first conductivity type, and the photoelectric conversion region 110 may be an impurity region having a second conductivity type different from the first conductivity type. In an embodiment, the first conductivity type and the second conductivity type may be p-type and n-type, respectively. In this case, the impurity of the second conductivity type may include an n-type impurity (e.g., phosphorus, arsenic, bismuth, and / or antimony). The photoelectric conversion region 110 and the substrate 100 may form a pn junction used as a photodiode. In an embodiment, the semiconductor pattern 152 or 154 of the deep device isolation pattern 150 may be formed of or include a doped semiconductor material containing an impurity of the first conductivity type (e.g., p-type).

[0048] The shallow device isolation pattern 105 may be disposed adjacent to the first surface 100a of the substrate 100. The pixel regions PXR1, PXR2, PXR3, and PXR4 may each include active patterns ACT, EACT1, and EACT2 defined by the shallow device isolation pattern 105. The shallow device isolation pattern 105 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] The first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may each include an active pattern ACT defined by a shallow device isolation pattern 105. The first pixel region PXR1 and the second pixel region PXR2 may further include a first extended active pattern EACT1 defined by the shallow device isolation pattern 105. The first extended active pattern EACT1 may extend from the first pixel region PXR1 to the second pixel region PXR2 in the first direction D1. The third pixel region PXR3 and the fourth pixel region PXR4 may further include a second extended active pattern EACT2 defined by the shallow device isolation pattern 105. The second extended active pattern EACT2 may extend from the third pixel region PXR3 to the fourth pixel region PXR4 in the first direction D1.

[0050] The first extended active pattern EACT1 and the second extended active pattern EACT2 may be disposed between the first portion 150P1 of the deep device isolation pattern 150. The second portion 150P2 of the deep device isolation pattern 150 may be disposed between the first extended active pattern EACT1 and the second extended active pattern EACT2. The shallow device isolation pattern 105 may be interposed between the first portion 150P1 of the deep device isolation pattern 150, between the first extended active pattern EACT1 and the second extended active pattern EACT2, and between the second portion 150P2 of the deep device isolation pattern 150.

[0051] The deep device isolation pattern 150 may be disposed to penetrate the shallow device isolation pattern 105 and may extend into the substrate 100. The gap-filling insulating pattern 158 of the deep device isolation pattern 150 may be disposed in the shallow device isolation pattern 105. The gap-filling insulating pattern 158 may be disposed to penetrate the shallow device isolation pattern 105 and contact the semiconductor pattern 152 or 154. The sidewall insulating pattern 156 of the deep device isolation pattern 150 may extend into a region between the shallow device isolation pattern 105 and the gap-filling insulating pattern 158.

[0052] The transfer gate electrode TG and the floating diffusion region FD may be disposed on the first surface 100a of the substrate 100 and on each of the pixel regions PXR1, PXR2, PXR3, and PXR4. As an example, the transfer gate electrode TG and the floating diffusion region FD may be disposed on the active pattern ACT of each of the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4. The transfer gate electrode TG and the floating diffusion region FD may constitute Figure 2 The transfer transistor TX of the transfer gate electrode TG may be provided. The lower portion of the transfer gate electrode TG may be provided to penetrate the active pattern ACT and may extend into the substrate 100. The upper portion of the transfer gate electrode TG may protrude above the top surface of the active pattern ACT (i.e., the first surface 100a of the substrate 100). The floating diffusion region FD may be provided in a portion of the active pattern ACT located on one side of the transfer gate electrode TG. The floating diffusion region FD may be a doped region having a second conductivity type (e.g., n-type) different from the first conductivity type of the substrate 100.

[0053] A plurality of gate electrodes EG1, G1, EG2, and G2 may be disposed on the first surface 100a of the substrate 100 and on the first extended active pattern EACT1 and the second extended active pattern EACT2. The gate electrodes EG1, G1, EG2, and G2 may include a first gate electrode G1 and a first extended gate electrode EG1 disposed on the first extended active pattern EACT1 and a second gate electrode G2 and a second extended gate electrode EG2 disposed on the second extended active pattern EACT2. The first gate electrode G1 and the first extended gate electrode EG1 may be spaced apart from each other on the first extended active pattern EACT1. The first extended gate electrode EG1 may be disposed on the first pixel region PXR1 and may extend to the second pixel region PXR2. That is, a portion of the first extended gate electrode EG1 may overlap vertically (e.g., in the third direction D3) with the first pixel region PXR1, and another portion of the first extended gate electrode EG1 may overlap vertically (e.g., in the third direction D3) with the second pixel region PXR2. The second gate electrode G2 and the second extended gate electrode EG2 may be spaced apart from each other on the second extended active pattern EACT2. The second extended gate electrode EG2 may be disposed on the third pixel region PXR3 and may extend to the fourth pixel region PXR4. That is, a portion of the second extended gate electrode EG2 may overlap vertically (e.g., in the third direction D3) with the third pixel region PXR3, and another portion of the second extended gate electrode EG2 may overlap vertically (e.g., in the third direction D3) with the fourth pixel region PXR4.

[0054] The source / drain region SD may be disposed in a portion of the first extended active pattern EACT1 located on both sides of each of the first gate electrode G1 and the first extended gate electrode EG1, and disposed in a portion of the second extended active pattern EACT2 located on both sides of each of the second gate electrode G2 and the second extended gate electrode EG2. In an embodiment, the source / drain region SD may be a doped region having a second conductivity type (e.g., n-type) different from the first conductivity type of the substrate 100.

[0055] The first gate electrode G1, the first extended gate electrode EG1, the second gate electrode G2, the second extended gate electrode EG2, and the source / drain region SD may constitute Figure 2 As an example, at least one of the first gate electrode G1, the first extended gate electrode EG1, the second gate electrode G2, and the second extended gate electrode EG2 may be used as a driving transistor DX, a selection transistor SX, and a reset transistor RX. Figure 2 The driving gate electrode of the driving transistor DX, and at least one of the first gate electrode G1, the first extended gate electrode EG1, the second gate electrode G2, and the second extended gate electrode EG2 may be used as Figure 2At least one of the first gate electrode G1, the first extended gate electrode EG1, the second gate electrode G2, and the second extended gate electrode EG2 may be used as a selection gate electrode of the selection transistor SX. Figure 2 The reset gate electrode of the reset transistor RX.

[0056] The gate dielectric layer GI can be between the transfer gate electrode TG and the substrate 100 (i.e., the active pattern ACT), between each of the first gate electrode G1 and the first extended gate electrode EG1 and the substrate 100 (i.e., the first extended active pattern EACT1), and between each of the second gate electrode G2 and the second extended gate electrode EG2 and the substrate 100 (i.e., the second extended active pattern EACT2).

[0057] The interconnection layer 20 may be disposed on the first surface 100a of the substrate 100. The interconnection layer 20 may include a first interlayer insulating layer 210 and a second interlayer insulating layer 240 sequentially stacked on the first surface 100a of the substrate 100. The first interlayer insulating layer 210 may be disposed on the first surface 100a of the substrate 100 to cover the gate electrodes TG, G1, EG1, G2, and EG2. The interconnection layer 20 may also include a contact plug 220 connected to the gate electrodes TG, G1, EG1, G2, and EG2, a floating diffusion region FD, and a source / drain region SD, and a conductive line 230 connected to the contact plug 220. The contact plug 220 may be disposed to penetrate the first interlayer insulating layer 210, and may be connected to the gate electrodes TG, G1, EG1, G2, and EG2, the floating diffusion region FD, and the source / drain region SD. The conductive line 230 may be disposed in the second interlayer insulating layer 240. At least some of the contact plugs 220 may extend into the second interlayer insulating layer 240 and may be connected to the conductive wires 230. The first interlayer insulating layer 210 and the second interlayer insulating layer 240 may be formed of or include at least one insulating material, and the contact plugs 220 and the conductive wires 230 may be formed of at least one conductive material.

[0058] The optically transparent layer 30 may be disposed on the second surface 100b of the substrate 100. The optically transparent layer 30 may include a color filter array 320 and a microlens array 330 disposed on the second surface 100b of the substrate 100. The color filter array 320 may be disposed between the second surface 100b of the substrate 100 and the microlens array 330. The optically transparent layer 30 may be configured to converge and filter incident light from the outside, thereby providing the light into the photoelectric conversion layer 10.

[0059] The color filter array 320 may include a plurality of color filters 320 respectively disposed on the pixel regions PXR1, PXR2, PXR3, and PXR4. In an embodiment, the color filters 320 on the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may be configured to achieve the same color. The microlens array 330 may include a plurality of microlenses 330 respectively disposed on the color filters 320. Each microlens 330 may be disposed to overlap vertically (e.g., in a third direction D3) with the photoelectric conversion region 110 of the corresponding pixel region PXR1, PXR2, PXR3, or PXR4.

[0060] The anti-reflection layer 310 may be interposed between the second surface 100b of the substrate 100 and the color filter array 320. The anti-reflection layer 310 may be configured to prevent light incident into the substrate 100 through the second surface 100b from being reflected, and thus, the light may be effectively guided into the photoelectric conversion region 110. The first insulating layer 312 may be interposed between the anti-reflection layer 310 and the color filter array 320, and the second insulating layer 322 may be interposed between the color filter array 320 and the microlens array 330. A grid 315 may be interposed between the first insulating layer 312 and the color filter array 320. The grid 315 may vertically overlap the deep device isolation pattern 150. The grid 315 may guide light incident into the substrate 100 through the second surface 100b into the photoelectric conversion region 110. The grid 315 may be formed of or include at least one metal material. The color filter array 320 may extend into a region between adjacent grids 315 and may contact the first insulating layer 312 .

[0061] According to an embodiment of the present disclosure, the first portion 150P1 of the deep device isolation pattern 150 may be respectively interposed between the first pixel region PXR1 and the second pixel region PXR2 and between the third pixel region PXR3 and the fourth pixel region PXR4, and the second portion 150P2 of the deep device isolation pattern 150 may be respectively interposed between the first pixel region PXR1 and the third pixel region PXR3 and between the second pixel region PXR2 and the fourth pixel region PXR4. Therefore, the crosstalk between the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3 and the fourth pixel region PXR4 may be minimized.

[0062] In addition, the first portions 150P1 of the deep device isolation pattern 150 may be spaced apart from each other in the second direction D2, and the first extended active pattern EACT1 and the second extended active pattern EACT2 may be disposed between the first portions 150P1. The first extended active pattern EACT1 may extend from the first pixel region PXR1 to the second pixel region PXR2 in the first direction D1, and the second extended active pattern EACT2 may extend from the third pixel region PXR3 to the fourth pixel region PXR4 in the first direction D1. Since the first extended active pattern EACT1 and the second extended active pattern EACT2 both extend to pixel regions adjacent to each other, the size of the gate electrode (e.g., the first extended gate electrode EG1 and the second extended gate electrode EG2) disposed on each of the first extended active pattern EACT1 and the second extended active pattern EACT2 may be increased. Therefore, the size reduction of the gate electrode and the subsequent degradation of the characteristics of the gate electrode that occur when the integration density of the image sensor increases may be prevented.

[0063] Therefore, in the image sensor according to the embodiment of the present disclosure, crosstalk between adjacent pixels can be minimized and the size of the gate electrode can be increased, and this can increase the integration density of the image sensor.

[0064] Figure 5A , Fig. 6A and Fig. 7A Shows along Figure 3 A cross-sectional view taken along line AA′ of FIG. 1 is shown to illustrate a method of manufacturing an image sensor according to an embodiment of the present disclosure. Figure 5B , Figure 6B and Figure 7B Shows along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 is shown to illustrate a method of manufacturing an image sensor according to an embodiment of the present disclosure. Figure 5C , Figure 6C and Figure 7C Shows along Figure 3 A cross-sectional view taken along line CC' of FIG. 1 to illustrate a method for manufacturing an image sensor according to an embodiment of the present disclosure. For the sake of brevity, this document refers to FIG. Figures 1 to 3 and FIG. 4A to FIG. 4C Described elements may be identified by the same or similar reference numerals without repeating overlapping descriptions thereof.

[0065] refer to Figure 3 and FIG. 5A to FIG. 5C, for example, in cross sections 500A, 500B, and 500C, a substrate 100 having a first surface 100a and a second surface 100b disposed opposite to each other may be provided. The substrate 100 may have a first conductivity type (e.g., p-type). A first trench T1 may be formed near the first surface 100a of the substrate 100. The formation of the first trench T1 may include forming a first mask pattern 103 on the first surface 100a of the substrate 100 and etching the substrate 100 using the first mask pattern 103 as an etching mask. The first trench T1 may define active patterns ACT, EACT1, and EACT2 in the substrate 100.

[0066] A device isolation layer 105L may be formed on the first surface 100a of the substrate 100. The device isolation layer 105L may be formed to cover the first mask pattern 103 and to cover the first trench T1. The device isolation layer 105L may be formed of, for example, at least one of a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer, or include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0067] A second trench T2 may be formed in the substrate 100. The formation of the second trench T2 may include forming a second mask pattern (not shown) on the device isolation layer 105L to define a region in which the second trench T2 is to be formed and etching the device isolation layer 105L and the substrate 100 using the second mask pattern as an etching mask. The second trench T2 may define a plurality of pixel regions PXR1, PXR2, PXR3, and PXR4 in the substrate 100. The pixel regions PXR1, PXR2, PXR3, and PXR4 may each include active patterns ACT, EACT1, and EACT2 defined by the first trench T1.

[0068] The pixel regions PXR1, PXR2, PXR3, and PXR4 may include a first pixel region PXR1, a second pixel region PXR2, a third pixel region PXR3, and a fourth pixel region PXR4 that are adjacent to each other in the first direction D1 and the second direction D2. In an embodiment, the first pixel region PXR1 and the second pixel region PXR2 may be adjacent to each other in the first direction D1, and the third pixel region PXR3 may be adjacent to the first pixel region PXR1 in the second direction D2. The fourth pixel region PXR4 may be adjacent to the second pixel region PXR2 in the second direction D2, and may be adjacent to the third pixel region PXR3 in the first direction D1. The arrangement of the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may not be limited to the above structure.

[0069] When viewed in a top view, the second trench T2 may be disposed to surround the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4. The second trench T2 may extend in the second direction D2 between the first pixel region PXR1 and the second pixel region PXR2 and between the third pixel region PXR3 and the fourth pixel region PXR4, and may extend in the first direction D1 between the first pixel region PXR1 and the third pixel region PXR3 and between the second pixel region PXR2 and the fourth pixel region PXR4. The first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may be partially separated from each other by the second trench T2, and the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 of the substrate 100 may be partially connected to each other.

[0070] The first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may each include an active pattern ACT defined by the first trench T1. The first pixel region PXR1 and the second pixel region PXR2 may further include a first extended active pattern EACT1 defined by the first trench T1. The first extended active pattern EACT1 may extend from the first pixel region PXR1 to the second pixel region PXR2 in the first direction D1. The third pixel region PXR3 and the fourth pixel region PXR4 may further include a second extended active pattern EACT2 defined by the first trench T1. The second extended active pattern EACT2 may extend from the third pixel region PXR3 to the fourth pixel region PXR4 in the first direction D1.

[0071] refer to Figure 3 and FIG. 6A to FIG. 6C , for example, in the cross sections 600A, 600B, and 600C, a deep device isolation pattern 150 may be formed to fill the second trench T2. The deep device isolation pattern 150 may include a sidewall insulation pattern 156 conformally covering the inner surface of the second trench T2, a semiconductor pattern 152 or 154 filling a lower region of the second trench T2, and a gap filling insulation pattern 158 disposed on the semiconductor pattern 152 or 154 to fill a remaining region of the second trench T2. The semiconductor pattern 152 or 154 may include a first semiconductor pattern 152 and a second semiconductor pattern 154, the first semiconductor pattern 152 being disposed to fill a portion of the second trench T2, and the second semiconductor pattern 154 being disposed between the first semiconductor pattern 152 and the sidewall insulation pattern 156.

[0072] In an embodiment, the formation of the deep device isolation pattern 150 may include: forming a sidewall insulation layer on the device isolation layer 105L to conformally cover the inner surface of the second trench T2; forming a second semiconductor layer on the sidewall insulation layer to fill a portion of the second trench T2; anisotropically etching the second semiconductor layer to form a second semiconductor pattern 154; forming a first semiconductor layer on the second semiconductor pattern 154 to fill the second trench T2; etching the first semiconductor layer in an etch-back manner to form a first semiconductor pattern 152; forming an insulating gap-filling layer to fill the remaining area of ​​the second trench T2; and planarizing the insulating gap-filling layer and the sidewall insulation layer to form a gap-filling insulating pattern 158 and a sidewall insulation pattern 156. The formation of the second semiconductor pattern 154 may also include implanting impurities of a first conductive type (e.g., p-type impurities) into the second semiconductor pattern 154. The planarization process for forming the gap-filling insulating pattern 158 and the sidewall insulating pattern 156 may include planarizing the insulating gap-filling layer, the sidewall insulating layer, and the device isolation layer 105L to expose the first surface 100a of the substrate 100. As a result of the planarization process, the first mask pattern 103 may be removed, and a shallow device isolation pattern 105 filling the first trench T1 may be formed.

[0073] refer to Figure 3 and 7A to 7C , for example, in cross sections 700A, 700B, and 700C, a photoelectric conversion region 110 may be formed in each of the pixel regions PXR1, PXR2, PXR3, and PXR4. The formation of the photoelectric conversion region 110 may include implanting impurities having a second conductivity type (e.g., n-type) different from the first conductivity type (e.g., p-type) into the substrate 100.

[0074] A thinning process may be performed on the second surface 100b of the substrate 100 to partially remove the substrate 100 and the deep device isolation pattern 150. The thinning process may include grinding or polishing the second surface 100b of the substrate 100 and performing an anisotropic and / or isotropic etching process. As a result of the thinning process, a lower portion of the deep device isolation pattern 150 may be removed, and the deep device isolation pattern 150 may have a bottom surface 150B substantially coplanar with the second surface 100b of the substrate 100.

[0075] A transfer gate electrode TG and a floating diffusion region FD may be formed on the first surface 100a of the substrate 100 and on each of the pixel regions PXR1, PXR2, PXR3, and PXR4. In an embodiment, the transfer gate electrode TG and the floating diffusion region FD may be formed on the active pattern ACT of each of the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4. The lower portion of the transfer gate electrode TG may be disposed to penetrate the active pattern ACT and may extend into the substrate 100. The upper portion of the transfer gate electrode TG may protrude above the top surface of the active pattern ACT (i.e., the first surface 100a of the substrate 100). The floating diffusion region FD may be formed by doping an impurity having a second conductivity type different from the first conductivity type of the substrate 100 (e.g., an n-type impurity) into a portion of the active pattern ACT located on one side of the transfer gate electrode TG.

[0076] A plurality of gate electrodes EG1, G1, EG2, and G2 may be formed on the first surface 100a of the substrate 100 and on the first and second extended active patterns EACT1 and EACT2. The gate electrodes EG1, G1, EG2, and G2 may include a first gate electrode G1 and a first extended gate electrode EG1 on the first extended active pattern EACT1 and a second gate electrode G2 and a second extended gate electrode EG2 on the second extended active pattern EACT2. The first extended gate electrode EG1 may be formed to extend from the first pixel region PXR1 to the second pixel region PXR2, and the second extended gate electrode EG2 may be formed to extend from the third pixel region PXR3 to the fourth pixel region PXR4.

[0077] Source / drain regions SD may be formed in two portions of the first extended active pattern EACT1 located on both sides of each of the first gate electrode G1 and the first extended gate electrode EG1 and in two portions of the second extended active pattern EACT2 located on both sides of each of the second gate electrode G2 and the second extended gate electrode EG2. The source / drain regions SD may be formed by doping impurities having a second conductivity type (e.g., n-type impurities) into the first extended active pattern EACT1 and the second extended active pattern EACT2.

[0078] A gate dielectric layer GI may be formed between the transfer gate electrode TG and the substrate 100 (i.e., the active pattern ACT), between each of the first gate electrode G1 and the first extended gate electrode EG1 and the substrate 100 (i.e., the first extended active pattern EACT1), and between each of the second gate electrode G2 and the second extended gate electrode EG2 and the substrate 100 (i.e., the second extended active pattern EACT2).

[0079] The photoelectric conversion layer 10 may be formed by the aforementioned manufacturing process. The interconnection layer 20 may be formed on the first surface 100a of the substrate 100. As an example, a first interlayer insulating layer 210 may be formed on the first surface 100a of the substrate 100 to cover the gate electrodes TG, G1, EG1, G2, and EG2. Some contact plugs 220 may be formed to penetrate the first interlayer insulating layer 210 and may be connected to the floating diffusion region FD and the corresponding source / drain region SD. A second interlayer insulating layer 240 may be formed on the first interlayer insulating layer 210. Other contact plugs 220 and conductive wires 230 may be formed in the second interlayer insulating layer 240. Other contact plugs 220 may be formed to penetrate the first interlayer insulating layer 210 and the second interlayer insulating layer 240 and may be connected to the corresponding source / drain region SD and the gate electrodes TG, G1, EG1, G2, and EG2. The conductive wire 230 may be connected to the contact plugs 220.

[0080] Return to reference Figure 3 and FIG. 4A to FIG. 4C , an optically transparent layer 30 may be formed on the second surface 100b of the substrate 100. In an embodiment, an anti-reflection layer 310 and a first insulating layer 312 may be sequentially formed on the second surface 100b of the substrate 100. A grid 315 may be formed on the first insulating layer 312, and the grid 315 may vertically overlap the deep device isolation pattern 150. In an embodiment, the formation of the grid 315 may include depositing a metal layer on the first insulating layer 312 and patterning the metal layer.

[0081] A color filter array 320 may be formed on the first insulating layer 312 to cover the grid 315. The color filter array 320 may include a plurality of color filters 320, and the color filters 320 may be respectively disposed on the pixel regions PXR1, PXR2, PXR3, and PXR4. A second insulating layer 322 may be formed on the color filter array 320, and a microlens array 330 may be formed on the second insulating layer 322. The microlens array 330 may include a plurality of microlenses 330 respectively disposed on the color filters 320. Each microlens 330 may be formed to overlap vertically (e.g., in a third direction D3) with the photoelectric conversion region 110 of a corresponding pixel region among the pixel regions PXR1, PXR2, PXR3, and PXR4.

[0082] Figure 8 An image sensor according to an embodiment of the present disclosure is shown. Fig.9A , Fig. 9B and Fig. 9C Shown along Figure 8 For the sake of simplicity, the following will mainly describe the cross-sectional view taken along the lines A-A', B-B' and CC'. Figures 1 to 3 and FIG. 4A to FIG. 4CThe characteristics of image sensors are different characteristics.

[0083] refer to Figure 8 and 9A to 9C , for example, in cross sections 900A, 900B, and 900C, the shallow device isolation pattern 105 of the image sensor 800 may be disposed adjacent to the first surface 100a of the substrate 100. The pixel regions PXR1, PXR2, PXR3, and PXR4 may each include an extended active pattern EACT1 or EACT2 defined by the shallow device isolation pattern 105. In an embodiment, the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 may each include an extended active pattern EACT1 or EACT2 defined by the shallow device isolation pattern 105. The first pixel region PXR1 and the second pixel region PXR2 may include a first extended active pattern EACT1 defined by the shallow device isolation pattern 105. The first extended active pattern EACT1 may extend from the first pixel region PXR1 to the second pixel region PXR2 in the first direction D1. The third pixel region PXR3 and the fourth pixel region PXR4 may include a second extended active pattern EACT2 defined by the shallow device isolation pattern 105. The second extended active pattern EACT2 may extend from the third pixel region PXR3 to the fourth pixel region PXR4 in the first direction D1.

[0084] The first extended active pattern EACT1 may extend toward both sides of one first portion 150P1 of the deep device isolation pattern 150. Therefore, one first portion 150P1 of the deep device isolation pattern 150 may be interposed between the first extended active pattern EACT1 on the first pixel region PXR1 and the first extended active pattern EACT1 on the second pixel region PXR2. The second extended active pattern EACT2 may extend toward both sides of the other first portion 150P1 of the deep device isolation pattern 150. Therefore, the other first portion 150P1 of the deep device isolation pattern 150 may be interposed between the second extended active pattern EACT2 on the third pixel region PXR3 and the second extended active pattern EACT2 on the fourth pixel region PXR4.

[0085] A portion of the first extended active pattern EACT1 and a portion of the second extended active pattern EACT2 may be disposed between the first portions 150P1 of the deep device isolation pattern 150, and may extend in the first direction D1 between the first portions 150P1 of the deep device isolation pattern 150. The second portion 150P2 of the deep device isolation pattern 150 may be disposed between the first extended active pattern EACT1 and the second extended active pattern EACT2. The shallow device isolation pattern 105 may be interposed between the first portions 150P1 of the deep device isolation pattern 150, between the first extended active pattern EACT1 and the second extended active pattern EACT2, and between the second portions 150P2 of the deep device isolation pattern 150.

[0086] The transfer gate electrode TG and the floating diffusion region FD may be disposed on the first surface 100a of the substrate 100 and on each of the pixel regions PXR1, PXR2, PXR3, and PXR4. In an embodiment, the transfer gate electrode TG and the floating diffusion region FD may be disposed on the first extended active pattern EACT1 of each of the first pixel region PXR1 and the second pixel region PXR2 and on the second extended active pattern EACT2 of each of the third pixel region PXR3 and the fourth pixel region PXR4. The transfer gate electrode TG and the floating diffusion region FD may constitute Figure 2 The transfer transistor TX of the transfer gate electrode TG may be provided. The lower portion of the transfer gate electrode TG may be provided to penetrate the first extended active pattern EACT1 or the second extended active pattern EACT2, and may extend into the substrate 100. The upper portion of the transfer gate electrode TG may protrude above the top surface of the first extended active pattern EACT1 or the second extended active pattern EACT2 (i.e., the first surface 100a of the substrate 100). The floating diffusion region FD may be provided at one side of the transfer gate electrode TG, and may be provided in the first extended active pattern EACT1 or the second extended active pattern EACT2.

[0087] The gate electrodes EG1, G1, EG2, and G2 may be disposed on the first surface 100a of the substrate 100 and on the first extended active pattern EACT1 and the second extended active pattern EACT2. The gate electrodes EG1, G1, EG2, and G2 may include a first gate electrode G1 and a first extended gate electrode EG1 disposed on the first extended active pattern EACT1 and a second gate electrode G2 and a second extended gate electrode EG2 disposed on the second extended active pattern EACT2. The first extended gate electrode EG1 may extend from the first pixel region PXR1 to the second pixel region PXR2, and the second extended gate electrode EG2 may extend from the third pixel region PXR3 to the fourth pixel region PXR4. The source / drain region SD may be disposed in a portion of the first extended active pattern EACT1 located on both sides of each of the first gate electrode G1 and the first extended gate electrode EG1, and in a portion of the second extended active pattern EACT2 located on both sides of each of the second gate electrode G2 and the second extended gate electrode EG2. The first gate electrode G1, the first extended gate electrode EG1, the second gate electrode G2, the second extended gate electrode EG2, and the source / drain region SD may constitute Figure 2 The drive transistor DX, the selection transistor SX and the reset transistor RX.

[0088] The gate dielectric layer GI may be disposed between the transfer gate electrode TG and the substrate 100 (i.e., the first extended active pattern EACT1 or the second extended active pattern EACT2), between each of the first gate electrode G1 and the first extended gate electrode EG1 and the substrate 100 (i.e., the first extended active pattern EACT1), and between each of the second gate electrode G2 and the second extended gate electrode EG2 and the substrate 100 (i.e., the second extended active pattern EACT2).

[0089] According to the present embodiment, the area of ​​the first extended active pattern EACT1 can be maximized, and the adjacent first pixel region PXR1 and second pixel region PXR2 can share the first extended active pattern EACT1. In addition, the area of ​​the second extended active pattern EACT2 can be maximized, and the adjacent third pixel region PXR3 and fourth pixel region PXR4 can share the second extended active pattern EACT2. Because the areas of the first extended active pattern EACT1 and the second extended active pattern EACT2 are maximized, the gate electrodes TG, G1, EG1, G2, and EG2 can be more freely arranged, and the sizes of the gate electrodes TG, G1, EG1, G2, and EG2 can be easily increased.

[0090] In addition, the first portion 150P1 of the deep device isolation pattern 150 may be respectively interposed between the first pixel region PXR1 and the second pixel region PXR2 and between the third pixel region PXR3 and the fourth pixel region PXR4, and the second portion 150P2 of the deep device isolation pattern 150 may be respectively interposed between the first pixel region PXR1 and the third pixel region PXR3 and between the second pixel region PXR2 and the fourth pixel region PXR4. Therefore, the crosstalk between the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3 and the fourth pixel region PXR4 may be minimized.

[0091] Therefore, in the image sensor according to the embodiment of the present disclosure, crosstalk between adjacent pixels can be minimized and the size of the gate electrode can be increased, and this can increase the integration density of the image sensor.

[0092] Fig.10 Shows along Figure 3 A cross-sectional view taken along line BB' of FIG. 1 is shown to illustrate an image sensor according to an embodiment of the present disclosure. For the sake of brevity, the following will mainly describe Figures 1 to 3 and FIG. 4A to FIG. 4C The characteristics of image sensors are different characteristics.

[0093] refer to Figure 3 and Fig.10 , for example, in the cross section 1000, the doped region IM may be disposed in the first extended active pattern EACT1 or the second extended active pattern EACT2. The doped region IM may have the same conductivity type as the substrate 100. The doped region IM may be a region doped with impurities of a first conductivity type (e.g., p-type impurities). The doped region IM may be electrically connected to the corresponding contact plug 220 and the corresponding conductive line 230. A ground voltage may be applied to the substrate 100 through the corresponding conductive line 230, the corresponding contact plug 220, and the doped region IM. In an embodiment, the first portion 150P1 and the second portion 150P2 of the deep device isolation pattern 150 may be spaced apart from each other, and the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4 of the substrate 100 may be connected to each other. In this case, a ground voltage may be commonly applied to portions of the first, second, third, and fourth pixel regions PXR1, PXR2, PXR3, and PXR4 of the substrate 100 through corresponding conductive lines 230, corresponding contact plugs 220, and the doping region IM.

[0094] Figures 11 to 16 A top view of an image sensor according to an embodiment of the present disclosure is shown. For the sake of brevity, the following will mainly describe Figures 1 to 3 and FIG. 4A to FIG. 4C The characteristics of image sensors are different characteristics.

[0095] refer to Figures 11 to 16 , the microlens array 330 may include a plurality of microlenses 330 as shown in the image sensors 1100 , 1200 , 1300 , 1400 , 1500 , and 1600 .

[0096] In an embodiment, Fig.11 As shown, microlenses 330 may be disposed on pixel regions PXR1, PXR2, PXR3, and PXR4, respectively. Each microlens 330 may be disposed to vertically overlap the photoelectric conversion region 110 of a corresponding pixel region among pixel regions PXR1, PXR2, PXR3, and PXR4 (eg, in a third direction D3).

[0097] although Fig.11 The embodiment is shown and described as having a first pixel region PXR1 disposed at the upper left corner of each pixel in the first row but disposed at the lower left corner of each pixel in the second row, but this is for the sake of brevity of description and the embodiment is not limited thereto. For example, in an optional embodiment, the different arrangements of the pixel regions may be as a checkerboard pattern rather than varying by row. In addition, although these two different pixel region arrangements are shown for illustrative purposes, the number of different pixel region arrangements may be greater, such as four, with the first pixel region being on the upper right side in the third arrangement and on the lower right side in the fourth arrangement.

[0098] In another embodiment, if Figure 12 to Figure 14 As shown, each microlens 330 may be disposed on two pixel regions selected from the pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other. Each microlens 330 may overlap the two pixel regions vertically (e.g., in a third direction D3), and may overlap the photoelectric conversion regions 110 of the two pixel regions vertically (e.g., in a third direction D3). As an example, Fig.12 As shown, each microlens 330 may be disposed on two pixel regions (e.g., the first pixel region PXR1 and the second pixel region PXR2) selected from the pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other in the first direction D1 and vertically overlap the two pixel regions. As another example, Fig.13 As shown, each microlens 330 may be disposed on two pixel regions (e.g., the first pixel region PXR1 and the third pixel region PXR3) selected from the pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other in the second direction D2 and vertically overlap the two pixel regions. As another example, Fig.14As shown, one microlens 330 may be disposed on two pixel regions (e.g., the first pixel region PXR1 and the second pixel region PXR2) selected from the pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other in the first direction D1 and vertically overlap the two pixel regions. Another microlens 330 may be disposed on two pixel regions (e.g., the first pixel region PXR1 and the third pixel region PXR3) selected from the pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other in the second direction D2 and vertically overlap the two pixel regions.

[0099] In other embodiments, Fig.15 As shown, each microlens 330 may be disposed on four pixel regions (e.g., the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4) selected from the pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other. Each microlens 330 may overlap the four pixel regions (e.g., the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4) vertically (e.g., in the third direction D3), and may overlap the photoelectric conversion regions 110 of the four pixel regions (e.g., the first pixel region PXR1, the second pixel region PXR2, the third pixel region PXR3, and the fourth pixel region PXR4) vertically (e.g., in the third direction D3).

[0100] In yet another embodiment, Fig.16 As shown, each microlens 330 may be disposed on sixteen pixel regions selected from pixel regions PXR1, PXR2, PXR3, and PXR4 and adjacent to each other. As an example, pixel regions PXR1, PXR2, PXR3, and PXR4 may include a plurality of pixel groups arranged in a first direction D1 and a second direction D2. Each pixel group may include a first pixel region PXR1, a second pixel region PXR2, a third pixel region PXR3, and a fourth pixel region PXR4 adjacent to each other. Each microlens 330 may be disposed on at least four pixel groups selected from the pixel groups and vertically overlap the four pixel groups.

[0101] Fig.17A , Fig. 17B and Fig. 17C Shown along Figure 3 , and a cross-sectional view taken along line A-A', line B-B', and line CC' of FIG. 1 to illustrate an image sensor according to an embodiment of the present disclosure. For the sake of brevity, the following will mainly describe Figures 1 to 3 and FIG. 4A to FIG. 4C The characteristics of image sensors are different characteristics.

[0102] refer to Figure 3 and 17A to 17C , for example, in the cross sections 1700A, 1700B, and 1700C, the insulating isolation pattern 108 may be disposed in the active pattern ACT of each of the pixel regions PXR1, PXR2, PXR3, and PXR4 close to (or adjacent to) the first surface 100a of the substrate 100. The insulating isolation pattern 108 may be formed of, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0103] The transfer gate electrode TG and the first floating diffusion region FD1 may be disposed in the active pattern ACT of each of the pixel regions PXR1, PXR2, PXR3, and PXR4 close to (or adjacent to) the first surface 100a of the substrate 100. The transfer gate electrode TG and the first floating diffusion region FD1 may constitute Figure 2 The transfer transistor TX of the first floating diffusion region FD1 may be provided in the active pattern ACT of each of the pixel regions PXR1, PXR2, PXR3, and PXR4 near (or adjacent to) the first surface 100a of the substrate 100. The insulating isolation pattern 108 may be interposed between the first floating diffusion region FD1 and the second floating diffusion region FD2. The first floating diffusion region FD1 and the second floating diffusion region FD2 may be impurity regions doped with impurities of a second conductivity type (e.g., n-type impurities).

[0104] The second floating diffusion region FD2 may be connected to a corresponding contact plug 220 in the interconnection layer 20. The semiconductor pattern 152 or 154 of the deep device isolation pattern 150 may be connected to a corresponding contact plug 220 in the interconnection layer 20. The semiconductor pattern 152 or 154 of the deep device isolation pattern 150 may be electrically connected to the second floating diffusion region FD2 through a corresponding contact plug 220 and a corresponding conductive line 230.

[0105] Pixel regions PXR1, PXR2, PXR3, and PXR4 may each include a first photoelectric conversion region 110a. The first photoelectric conversion region 110a may be an impurity region doped with second conductivity type impurities (eg, n-type impurities). The first photoelectric conversion region 110a together with the substrate 100 may form a pn junction serving as a photodiode.

[0106] The optically transparent layer 30 may be disposed on the second surface 100b of the substrate 100. The optically transparent layer 30 may include a color filter array 320 and a microlens array 330 disposed on the second surface 100b of the substrate 100. The color filter array 320 may be disposed between the second surface 100b of the substrate 100 and the microlens array 330. The color filter array 320 may include a plurality of color filters 320 disposed on the pixel regions PXR1, PXR2, PXR3, and PXR4, respectively, and the microlens array 330 may include a plurality of microlenses 330 disposed on the color filters 320, respectively.

[0107] The first insulating layer 312 may be disposed between the second surface 100b of the substrate 100 and the color filter array 320. The light blocking patterns 314a may be disposed on the first insulating layer 312 and respectively disposed between the color filters 320. The low refractive index patterns 314b may be respectively disposed between the color filters 320 and disposed on the light blocking patterns 314a. The third insulating layer 316 may be interposed between each light blocking pattern 314a and each low refractive index pattern 314b, and may be disposed in a region between each color filter 320 and each low refractive index pattern 314b. The third insulating layer 316 may extend into a region between each color filter 320 and the microlens array 330.

[0108] The pixel electrodes 350 may be disposed on the pixel regions PXR1, PXR2, PXR3, and PXR4, respectively. The pixel electrodes 350 may be disposed on the color filters 320, respectively, and the third insulating layer 316 may be interposed between the pixel electrodes 350 and the color filters 320. The electrode separation pattern 354 may be disposed between the pixel electrodes 350. The fourth insulating layer 318 may be disposed between the pixel electrode 350 and the third insulating layer 316, and may extend into a space between the electrode separation pattern 354 and the low refractive index pattern 314b.

[0109] The second photoelectric conversion layer 110b may be disposed on the pixel electrode 350 and the electrode separation pattern 354, and the common electrode 356 may be disposed on the second photoelectric conversion layer 110b. The second photoelectric conversion layer 110b may be disposed between the pixel electrode 350 and the common electrode 356 and between the electrode separation pattern 354 and the common electrode 356. The pixel electrode 350, the electrode separation pattern 354, the second photoelectric conversion layer 110b and the common electrode 356 may be disposed between the color filter array 320 and the microlens array 330. The second photoelectric conversion layer 110b may be, for example, an organic photoelectric conversion layer. The second photoelectric conversion layer 110b may include a p-type organic semiconductor material and an n-type organic semiconductor material disposed to form a pn junction. Alternatively, the second photoelectric conversion layer 110b may include quantum dots or chalcogenide materials. The pixel electrode 350 and the common electrode 356 may be formed of, or include, for example, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or an organic transparent conductive material.

[0110] Each pixel electrode 350 may be electrically connected to the semiconductor pattern 152 or 154 of the deep device isolation pattern 150 through the via plug 340. The via plug 340 may be connected to the semiconductor pattern 152 or 154 of the deep device isolation pattern 150, and may be connected to the corresponding pixel electrode 350 through the first insulating layer 312, the corresponding light blocking pattern 314a, the third insulating layer 316, the corresponding low refractive index pattern 314b, and the fourth insulating layer 318. The semiconductor pattern 152 or 154 of the deep device isolation pattern 150 may be electrically connected to the second floating diffusion region FD2 through the corresponding contact plug 220 and the corresponding conductive line 230.

[0111] The second insulating layer 322 may be interposed between the common electrode 356 and the microlens array 330. The first insulating layer 312, the second insulating layer 316, the third insulating layer 318, and the fourth insulating layer 322 and the electrode separation pattern 354 may be formed of, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0112] In addition to the above differences, the image sensor according to the present embodiment can be compared with the reference Figures 1 to 3 and FIG. 4A to FIG. 4C The image sensors described are essentially the same.

[0113] Fig.18 A top view of an image sensor according to an embodiment of the present disclosure is shown, and Fig.19 Shows along Fig.18For the sake of brevity, the following will mainly describe Figures 1 to 3 and FIG. 4A to FIG. 4C The characteristics of image sensors are different characteristics.

[0114] refer to Fig.18 and Fig.19 , for example, in cross section 1900, the image sensor 1800 may include: a substrate 100, including a pixel array region AR, an optical black region OB, and a pad region PR; an interconnection layer 20, disposed on a first surface 100a of the substrate 100; a base substrate 40, disposed on the interconnection layer 20; and an optically transparent layer 30, disposed on a second surface 100b of the substrate 100. The interconnection layer 20 may be disposed between the first surface 100a of the substrate 100 and the base substrate 40. The interconnection layer 20 may include an upper interconnection layer 21 disposed adjacent to the first surface 100a of the substrate 100 and a lower interconnection layer 23 disposed between the upper interconnection layer 21 and the base substrate 40. The pixel array region AR may include a plurality of pixel regions PXR and a deep device isolation pattern 150 disposed therebetween. The pixel array region may be configured to have a plurality of pixel regions PXR and a plurality of pixel regions PXR disposed therebetween. The pixel array region may be configured to have a plurality of pixel regions PXR and a plurality of pixel regions PXR disposed therebetween. Figures 1 to 17C The features in the image sensor described are essentially the same features.

[0115] The first connection structure 50, the first contact 81, and the bulk color filter 90 may be disposed on the optical black area OB of the substrate 100. The first connection structure 50 may include a first light blocking pattern 51, a first isolation pattern 53, and a first covering pattern 55. The first light blocking pattern 51 may be disposed on the second surface 100b of the substrate 100. The first light blocking pattern 51 may cover the first insulating layer 312, and may conformally cover the inner surface of each of the third trench TR3 and the fourth trench TR4. The first light blocking pattern 51 may be disposed to penetrate the photoelectric conversion layer 10 and the upper interconnection layer 21. The first light blocking pattern 51 may be connected to the semiconductor pattern 152 or 154 of the deep device isolation pattern 150 of the photoelectric conversion layer 10, and may be connected to the interconnection lines in the upper interconnection layer 21 and the lower interconnection layer 23. Therefore, the first connection structure 50 may electrically connect the photoelectric conversion layer 10 to the interconnection layer 20. The first light blocking pattern 51 may be formed of at least one metal material (e.g., tungsten), or include at least one metal material (e.g., tungsten). The first light blocking pattern 51 may block light incident into the optical black area OB.

[0116] The first contact 81 may fill the remaining area of ​​the third trench TR3. The first contact 81 may be formed of at least one metal material (e.g., aluminum), or include at least one metal material (e.g., aluminum). The first contact 81 may be connected to the semiconductor pattern 152 or 154 of the deep device isolation pattern 150. A bias may be applied to the semiconductor pattern 152 or 154 through the first contact 81. The first isolation pattern 53 may fill the remaining area of ​​the fourth trench TR4. The first isolation pattern 53 may penetrate the photoelectric conversion layer 10 and may penetrate a portion of the interconnection layer 20. The first isolation pattern 53 may be formed of at least one insulating material, or include at least one insulating material. The first capping pattern 55 may be disposed on the first isolation pattern 53. The first capping pattern 55 may be formed of the same material as the gap-filling insulating pattern 158 of the deep device isolation pattern 150, or include the same material as the gap-filling insulating pattern 158 of the deep device isolation pattern 150.

[0117] The bulk color filter 90 may be disposed on the first connection structure 50 and the first contact 81. The bulk color filter 90 may cover the first connection structure 50 and the first contact 81. The first protection layer 71 may be disposed on the bulk color filter 90 to hermetically seal the bulk color filter 90.

[0118] The additional photoelectric conversion region 110' and the dummy region 111 may be disposed in a corresponding pixel region PXR, and the pixel region PXR is disposed in the optical black region OB. The additional photoelectric conversion region 110' may be a doped region having a second conductivity type (e.g., n-type) different from the first conductivity type of the substrate 100. The additional photoelectric conversion region 110' may have a structure similar to the photoelectric conversion region 110 in the pixel region PXR of the pixel array region AR, but may not perform the same function as the photoelectric conversion region 110 (i.e., a function of generating an electrical signal from incident light). The dummy region 111 may not be doped with impurities.

[0119] The second connection structure 60, the second contact 83, and the second protection layer 73 may be disposed on the pad region PR of the substrate 100. The second connection structure 60 may include a second light blocking pattern 61, a second isolation pattern 63, and a second capping pattern 65.

[0120] The second light-blocking pattern 61 may be disposed on the second surface 100b of the substrate 100. The second light-blocking pattern 61 may cover the first insulating layer 312, and may conformally cover the inner surface of each of the fifth trench TR5 and the sixth trench TR6. The second light-blocking pattern 61 may be disposed to penetrate the photoelectric conversion layer 10 and the upper interconnection layer 21. The second light-blocking pattern 61 may be connected to the interconnection line in the lower interconnection layer 23. Thus, the second connection structure 60 may electrically connect the photoelectric conversion layer 10 to the interconnection layer 20. The second light-blocking pattern 61 may be formed of at least one metal material (e.g., tungsten), or include at least one metal material (e.g., tungsten). The second light-blocking pattern 61 may block light incident into the pad region PR.

[0121] The second contact 83 may fill the remaining area of ​​the fifth trench TR5. The second contact 83 may be formed of at least one metal material (e.g., aluminum), or include at least one metal material (e.g., aluminum). The second contact 83 may be used as an electrical connection path between the image sensor and an external device. The second isolation pattern 63 may fill the remaining area of ​​the sixth trench TR6. The second isolation pattern 63 may penetrate the photoelectric conversion layer 10, and may penetrate a portion of the interconnect layer 20. The second isolation pattern 63 may be formed of an insulating material or include an insulating material. The second covering pattern 65 may be disposed on the second isolation pattern 63. The second covering pattern 65 may be formed of the same material as the gap-filling insulating pattern 158 of the deep device isolation pattern 150, or include the same material as the gap-filling insulating pattern 158 of the deep device isolation pattern 150. The second protective layer 73 may cover the second connection structure 60.

[0122] The current applied through the second contact 83 may be supplied to the semiconductor pattern 152 or 154 of the deep device isolation pattern 150 through the second light blocking pattern 61, the interconnection line in the interconnection layer 20, and the first light blocking pattern 51. The electrical signal generated from the photoelectric conversion region 110 in the pixel region PXR of the pixel array region AR may be transmitted to the outside through the interconnection line in the interconnection layer 20, the second light blocking pattern 61, and the second contact 83.

[0123] According to an embodiment of the present disclosure, the deep device isolation pattern may include a first portion and a second portion, the first portion being between the first pixel region and the second pixel region and between the third pixel region and the fourth pixel region and being spaced apart from each other in the second direction, and the second portion being between the first pixel region and the third pixel region and between the second pixel region and the fourth pixel region and being spaced apart from each other in the first direction. The first pixel region to the fourth pixel region may be partially separated from each other by the first portion and the second portion of the deep device isolation pattern, and therefore, the crosstalk between the first pixel region to the fourth pixel region may be minimized.

[0124] In addition, because the first portions of the deep device isolation pattern are spaced apart from each other in the second direction, the first extended active pattern extending from the first pixel region to the second pixel region and the second extended active pattern extending from the third pixel region to the fourth pixel region can be disposed between the first portions. Because both the first extended active pattern and the second extended active pattern extend to adjacent pixel regions, the size of the gate electrode disposed on each of the first extended active pattern and the second extended active pattern can be easily increased.

[0125] Therefore, in the image sensor according to the embodiment of the present disclosure, crosstalk between adjacent pixels can be minimized and the size of the gate electrode can be increased, and this can increase the integration density of the image sensor.

[0126] While exemplary embodiments based on the inventive concept have been particularly shown and described, it will be understood by those skilled in the relevant art that changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. An image sensor, comprising: a substrate including a first surface, a second surface opposite to the first surface, a first photoelectric conversion region located in a first pixel region, and a second photoelectric conversion region located in a second pixel region; a first microlens, the first microlens being disposed on the first photoelectric conversion region; a second microlens, the second microlens being disposed on the second photoelectric conversion region; a first transfer transistor, the first transfer transistor being disposed in the first pixel region; a second transfer transistor, the second transfer transistor being disposed in the second pixel region; a deep device isolation pattern, wherein the deep device isolation pattern is located between the first photoelectric conversion region and the second photoelectric conversion region; A first transistor, the first transistor is shared by the first photoelectric conversion region and the second photoelectric conversion region, the first transistor comprising: a first portion vertically overlapping with the first pixel region in a first direction and a second portion vertically overlapping with the second photoelectric conversion region in the first direction; a first floating diffusion region located in the first pixel region in the substrate, the first floating diffusion region configured to store charges generated in the first photoelectric conversion region; and a second floating diffusion region, the second floating diffusion region being located in the second pixel region in the substrate, the second floating diffusion region being configured to store charges generated in the second photoelectric conversion region, wherein the first floating diffusion region is spaced apart from the second floating diffusion region, wherein the first direction is perpendicular to the first surface, wherein the deep device isolation pattern contacts the first surface and the second surface, and Wherein, the image sensor is configured to receive light through the second surface.

2. The image sensor according to claim 1, wherein: The first transistor is a driving transistor.

3. The image sensor according to claim 2, wherein: The driving transistor has a first width in a second direction perpendicular to the first direction in a plan view, and has a second width in a third direction perpendicular to the second direction in the plan view, and Wherein, the second width is greater than the first width.

4. The image sensor according to claim 3, wherein: The deep device isolation pattern comprises: a first pattern in contact with the first surface and spaced apart from the second surface; and a second pattern, the second pattern being in contact with the second surface and spaced apart from the first surface, The first pattern vertically overlaps with the second pattern in the first direction.

5. The image sensor according to claim 4, wherein: The deep device isolation pattern further includes: Grooves, Wherein, the second pattern is arranged in the groove.

6. The image sensor according to claim 5, wherein: The deep device isolation pattern further includes: A third pattern is in the trench and is located between a sidewall of the trench and the second pattern.

7. The image sensor according to claim 6, wherein: The deep device isolation pattern further includes: A fourth pattern is in the groove and located between the third pattern and the second pattern.

8. The image sensor according to claim 7, wherein: The first pattern and the third pattern are insulating patterns.

9. The image sensor according to claim 8, wherein: The first pattern has a first height in the first direction, and the second pattern has a second height in the second direction, and Wherein, the second height is greater than the first height.

10. The image sensor according to claim 9, wherein: The first pattern has a third width on the first surface along the third direction in the top view, and the second pattern has a fourth width on the second surface along the third direction in the top view, and Wherein, the third width is greater than the fourth width.

11. The image sensor according to claim 10, further comprising: a selection transistor disposed in the second pixel region, wherein the first photoelectric conversion region and the second photoelectric conversion region are arranged along the third direction in the top view, and The driving transistor and the selecting transistor are arranged along the third direction.

12. The image sensor according to claim 11, wherein: The selection transistor has a first length in the third direction, wherein the driving transistor has a second length in the third direction, and Wherein, the second length is greater than the first length.

13. An image sensor, comprising: a substrate including a first surface, a second surface opposite to the first surface, a first photoelectric conversion region located in a first pixel region, and a second photoelectric conversion region located in a second pixel region; a first microlens, the first microlens being disposed on the first photoelectric conversion region; a second microlens, the second microlens being disposed on the second photoelectric conversion region; a first transfer transistor, the first transfer transistor being disposed in the first pixel region; a second transfer transistor, the second transfer transistor being disposed in the second pixel region; a deep device isolation pattern, the deep device isolation pattern being located between the first photoelectric conversion region and the second photoelectric conversion region, the deep device isolation pattern comprising a first pattern in contact with the first surface and a second pattern in contact with the second surface; a selection transistor disposed in the second pixel region, A first transistor, the first transistor is shared by the first photoelectric conversion region and the second photoelectric conversion region, the first transistor comprising: a first portion vertically overlapping with the first pixel region in a first direction and a second portion vertically overlapping with the second photoelectric conversion region in the first direction; wherein the first direction is perpendicular to the first surface, wherein the selection transistor has a first length in a second direction parallel to the first surface, wherein the first transistor has a second length in the second direction, wherein the second length is greater than the first length, wherein the first pattern contacts the second pattern, wherein the first pattern vertically overlaps with the second pattern in the first direction, and Wherein, the image sensor is configured to receive light through the second surface.

14. The image sensor according to claim 13, wherein: The first pattern includes a first material, and the second pattern includes a second material different from the first material.

15. The image sensor according to claim 14, wherein: The first transistor is a driving transistor.

16. The image sensor according to claim 15, wherein: The deep device isolation pattern further includes: a groove, the groove being in contact with the second surface; a third pattern in the trench and between a sidewall of the trench and the second pattern; and a fourth pattern, the fourth pattern being in the groove and between the third pattern and the second pattern, Wherein, the first pattern and the third pattern are insulating patterns.

17. The image sensor according to claim 16, wherein: Each of the first transfer transistor and the second transfer transistor includes: a third portion extending into the substrate; and A fourth portion is located on the first surface.

18. An image sensor, comprising: A substrate, the substrate comprising a first surface, a second surface opposite to the first surface, a first photoelectric conversion region located in a first pixel region, a second photoelectric conversion region located in a second pixel region disposed adjacent to the first pixel region in a first direction in a plan view, and a third photoelectric conversion region located in a third pixel region disposed adjacent to the first pixel region in a second direction in a plan view; a first transfer transistor, the first transfer transistor being disposed in the first pixel region; a second transfer transistor, the second transfer transistor being disposed in the second pixel region; a third transfer transistor, the third transfer transistor being disposed in the third pixel region; a deep device isolation pattern, the deep device isolation pattern being located between the first photoelectric conversion region and the second photoelectric conversion region and between the first photoelectric conversion region and the third photoelectric conversion region, the deep device isolation pattern comprising a first pattern in contact with the first surface and a second pattern in contact with the second surface; a selection transistor, the selection transistor being disposed in the second pixel region; as well as a driving transistor, the driving transistor being shared by the first photoelectric conversion region and the third photoelectric conversion region, the driving transistor comprising: a first portion vertically overlapping with the first pixel region in a third direction perpendicular to the first direction and a second portion vertically overlapping with the second photoelectric conversion region in the third direction, wherein the second direction is perpendicular to the first direction, wherein the selection transistor has a first length in the first direction, wherein the driving transistor has a second length in the first direction, wherein the second length is greater than the first length, wherein the first pattern contacts the second pattern, wherein the first pattern vertically overlaps with the second pattern in the third direction, and Wherein, the image sensor is configured to receive light through the second surface.

19. The image sensor according to claim 18, wherein: The deep device isolation pattern further includes: a groove, the groove being in contact with the second surface; a third pattern in the trench and between a sidewall of the trench and the second pattern; and a fourth pattern, the fourth pattern being in the groove and between the third pattern and the second pattern, Wherein, the first pattern and the third pattern are insulating patterns.

Images