Substrate and preparation method and application thereof

Abstract

The invention belongs to the field of solar cells, and provides a substrate and a preparation method and application thereof. The method comprises the steps of providing a substrate, wherein a tunneling oxide layer is arranged on the surface of one side of the substrate; forming a first amorphous silicon layer on the surface of one side, far away from the substrate, of the tunneling oxide layer at a first temperature; stacking operation is sequentially carried out on the side face, away from the tunneling oxide layer, of the first amorphous silicon layer, each round of stacking operation comprises the steps that a second amorphous silicon layer is formed at a second temperature and a third amorphous silicon layer is formed at a third temperature in sequence, the first temperature and the third temperature are smaller than the second temperature, and the second temperature is smaller than the third temperature. The third temperature is higher than the first temperature. According to the method provided by the embodiment of the invention, the time for preparing the substrate can be saved, and the obtained substrate has relatively good compactness and shows an excellent passivation effect.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a substrate and a preparation method and application thereof. Background Art

[0002] The tunneling oxide passivated contact (TOPcon) cell, due to its unique tunneling characteristics, can significantly reduce the recombination of electrons and holes, greatly increase the cell's opening voltage and current density, especially the double-sided poly structure TOPcon cell, whose limit efficiency is closest to the limit efficiency of silicon. The TBC (TOPCON & BC-back contact passivation) cell combines the advantages of the BC (back contact) cell and the TOPcon cell to become one of the most competitive cell structures in the industry.

[0003] However, whether it is the double-sided poly structure of the TOPcon cell or the single-sided poly structure of the TBC cell, the thickness of the poly needs to be relatively high. The deposition of such a thick poly using LPCVD will greatly increase its deposition time, thereby affecting production capacity. Therefore, how to reduce the poly deposition time and release production capacity while ensuring the passivation advantage is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a substrate and a preparation method and application thereof to solve or alleviate one or more of the following technical problems: how to reduce the poly deposition time while ensuring the passivation advantage, thereby releasing production capacity.

[0005] According to a first aspect of an embodiment of the present application, a method for preparing a substrate is proposed, comprising providing a base, wherein one surface of the base has a tunneling oxide layer; forming a first amorphous silicon layer at a first temperature on a surface of the tunneling oxide layer away from the base; and sequentially performing a stacking operation on a side of the first amorphous silicon layer away from the tunneling oxide layer, wherein each round of the stacking operation comprises sequentially forming a second amorphous silicon layer at a second temperature and forming a third amorphous silicon layer at a third temperature, wherein the first temperature and the third temperature are respectively lower than the second temperature, and the third temperature is higher than the first temperature.

[0006] The method of the embodiment of the present application can save time in preparing the substrate, and the obtained substrate has good density and exhibits excellent passivation effect.

[0007] Specifically, the deposition time is saved because the second temperature is high relative to the first temperature and the third temperature, and the grain size of silicon is poor at high temperature, which is conducive to improving the speed of the second amorphous silicon layer. The first temperature and the third temperature are relatively low temperatures, and the grain size of silicon is small at low temperatures, so that the growth of the first amorphous silicon layer or the third amorphous silicon layer is slow and dense. This dense first amorphous silicon layer can be used as a barrier layer for subsequent doping elements, blocking the expansion of doped elements into the tunneling oxide layer, thereby improving the passivation effect of the substrate; the dense third amorphous silicon layer provides the possibility of reducing the saturation current density and high-concentration doping in the subsequent metallization area. And the third temperature is greater than the first temperature, but the third temperature is lower than the second temperature. Such a small temperature difference shortens the cooling time, thereby reducing the process time; the third amorphous silicon layer formed at low temperature has better compactness, which is beneficial to slowing down the diffusion of doped elements; in addition, the third amorphous silicon layer is used as a contact layer with the metal electrode in the future, and its higher compactness is conducive to obtaining a higher doping concentration, thereby improving the formation of good contact between the metal electrode and it.

[0008] According to an embodiment of the present application, the first temperature is 530-590°C.

[0009] According to an embodiment of the present application, the second temperature is 590-620°C.

[0010] According to an embodiment of the present application, the third temperature is 530-590°C.

[0011] According to an embodiment of the present application, the time for forming the first amorphous silicon layer is 800-1500 seconds.

[0012] According to an embodiment of the present application, the time for forming the second amorphous silicon layer is 2500-3500 seconds.

[0013] According to an embodiment of the present application, the time for forming the third amorphous silicon layer is 400-1000s.

[0014] According to an embodiment of the present application, the number of rounds of the stacking operation is 1 round.

[0015] According to an embodiment of the present application, the thickness of the substrate is 110-250 μm.

[0016] According to an embodiment of the present application, the thickness of the tunnel oxide layer is 0.8-2 nm.

[0017] According to an embodiment of the present application, the thickness of the first amorphous silicon layer is 15-45 nm.

[0018] According to an embodiment of the present application, the thickness of the second amorphous silicon layer is 50-200 nm; According to an embodiment of the present application, the thickness of the third amorphous silicon layer is 20-60 nm.

[0019] The second aspect of the embodiment of the present application provides a substrate. It includes: a substrate; a tunneling oxide layer, the tunneling oxide layer is located on one side of the substrate; a first amorphous silicon layer, the first amorphous silicon layer is located on a side of the tunneling oxide layer away from the substrate, and the first amorphous silicon layer is formed at a first temperature; a fourth amorphous silicon layer, the fourth amorphous silicon layer includes a second amorphous silicon layer and a third amorphous silicon layer alternately stacked, the second amorphous silicon layer is located on a side of the first amorphous silicon layer away from the tunneling oxide layer, the second amorphous silicon layer is formed at a second temperature, and the third amorphous silicon layer is formed at a third temperature, wherein the first temperature and the third temperature are respectively less than the second temperature, and the third temperature is greater than the first temperature. The substrate of the embodiment of the present application has a good passivation effect.

[0020] According to an embodiment of the present application, the fourth amorphous silicon layer is a second amorphous silicon layer, a third amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer which are sequentially stacked.

[0021] The third aspect of the embodiment of the present application provides an application of a substrate containing an amorphous silicon layer prepared by the method of the first aspect or the substrate containing an amorphous silicon layer of the second aspect, including the application of the substrate containing an amorphous silicon layer in the preparation of a solar cell. The substrate containing an amorphous silicon layer prepared by the above method or the above amorphous silicon substrate can be used to prepare a solar cell, and has better passivation performance when used to prepare a solar cell.

[0022] According to an embodiment of the present application, the solar cell includes a tunneling passivation contact solar cell and a back contact solar cell.

[0023] According to an embodiment of the present application, the solar cell method includes: diffusing phosphorus on the substrate to obtain a phosphorus-doped layer; or diffusing boron on the substrate to obtain a boron-doped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0025] Figure 1 is a schematic structural diagram of a substrate in some embodiments; Figure 2 Schematic diagrams of the structures of substrates of other embodiments.

[0026] Reference numerals: 1: substrate; 2: tunneling oxide layer; 3: first amorphous silicon layer; 4: second amorphous silicon layer; 5: third amorphous silicon layer; 6: fourth amorphous silicon layer. DETAILED DESCRIPTION

[0027] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0029] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, including the two endpoint integers of the numerical range, and each integer between the two endpoints, is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0032] At present, the traditional LPCVD deposition uses the same temperature to deposit poly (amorphous silicon layer), which can obtain a high-density poly layer, and has certain advantages in passivation, but the deposition rate is too slow, resulting in a long time to deposit thicker poly, affecting production efficiency. In addition, if the poly layer is deposited at a high temperature, the poly deposition time can be greatly saved, achieving the purpose of saving production capacity, but the high-temperature deposition of poly will lead to poor poly density, thereby affecting the poly passivation effect, and then causing the photoelectric performance of solar cells to decline.

[0033] Accordingly, in a first aspect of an embodiment of the present application, a method for preparing a substrate containing an amorphous silicon layer is proposed, comprising: (1) providing a substrate, wherein one side surface of the substrate has a tunneling oxide layer; (2) forming a first amorphous silicon layer at a first temperature on a side surface of the tunneling oxide layer away from the substrate; (3) sequentially performing a stacking operation on a side of the first amorphous silicon layer away from the tunneling oxide layer, wherein each round of the stacking operation comprises sequentially forming a second amorphous silicon layer at a second temperature and forming a third amorphous silicon layer at a third temperature, wherein the first temperature and the third temperature are respectively lower than the second temperature, and the third temperature is higher than the first temperature.

[0034] The method of the embodiment of the present application can save time in preparing the substrate, and the obtained substrate has good density and exhibits excellent passivation effect.

[0035] Specifically, the deposition time is saved because the second temperature is high relative to the first temperature and the third temperature, and the grain size of silicon is poor at high temperature, which is conducive to improving the speed of the second amorphous silicon layer. The first temperature and the third temperature are relatively low temperatures, and the grain size of silicon is small at low temperatures, so that the growth of the first amorphous silicon layer or the third amorphous silicon layer is slow and dense. This dense first amorphous silicon layer can be used as a barrier layer for subsequent doping elements, blocking the expansion of doped elements into the tunneling oxide layer, thereby improving the passivation effect of the substrate; the dense third amorphous silicon layer provides the possibility of reducing the saturation current density and high-concentration doping in the subsequent metallization area. And the third temperature is greater than the first temperature, but the third temperature is lower than the second temperature. Such a small temperature difference shortens the cooling time, thereby reducing the process time; the third amorphous silicon layer formed at low temperature has better compactness, which is beneficial to slowing down the diffusion of doped elements; in addition, the third amorphous silicon layer is used as a contact layer with the metal electrode in the future, and its higher compactness is conducive to obtaining a higher doping concentration, thereby improving the formation of good contact between the metal electrode and it.

[0036] According to the method of the embodiment of the present application, step (1) provides a substrate, and one side surface of the substrate has a tunneling oxide layer.

[0037] In some embodiments, in step (1), the substrate may be an N-type, P-type or intrinsic substrate.

[0038] Optionally, the method further includes cleaning the substrate, wherein the cleaning conditions are a mixture of ammonia and hydrogen peroxide, a mixture of hydrochloric acid and hydrogen peroxide, or hydrofluoric acid.

[0039] Optionally, the substrate has a thickness of 110-250 µm.

[0040] Optionally, the thickness of the tunnel oxide layer is 0.8-2 nm.

[0041] In some embodiments, after step (1) and before step (2), at least one tunneling oxide layer is formed on the side of the tunneling oxide layer away from the substrate. In this way, tunneling oxide layers exist on both opposite sides of the substrate. This structure is conducive to slowing down the damage of subsequent doping elements (such as phosphorus or boron) to the substrate during the diffusion process.

[0042] According to an embodiment of the present application, in step (2), a first amorphous silicon layer is formed at a first temperature on a surface of the tunnel oxide layer that is away from the substrate.

[0043] In some embodiments, the first temperature is 530-590° C. The first amorphous silicon layer formed at the first temperature has good compactness and strong blocking ability to doping elements, which can greatly improve the integrity of the tunneling oxide layer (or the tunneling oxide layer and the tunneling oxide layer).

[0044] Optionally, the thickness of the first amorphous silicon layer is 15-45 nm. This thickness range is conducive to slowing down the damage to the tunneling layer close to the substrate during the diffusion of the doping elements, and a lower thickness can reduce the time for forming the substrate as a whole.

[0045] In some embodiments, the time for forming the first amorphous silicon layer is 800-1500 seconds, for example, 800 seconds, 900 seconds, 1200 seconds, or 1500 seconds.

[0046] In some other embodiments, tunnel oxide layers exist on two opposite sides of the substrate, and the first amorphous silicon layer is formed on both tunnel oxide layers.

[0047] According to an embodiment of the present application, step (3) performs a stacking operation in sequence on a side of the first amorphous silicon layer away from the tunneling oxide layer, and each round of the stacking operation includes sequentially forming a second amorphous silicon layer at a second temperature, and forming a third amorphous silicon layer at a third temperature, wherein the first temperature and the third temperature are respectively lower than the second temperature, and the third temperature is higher than the first temperature.

[0048] In some embodiments, the second temperature is 590-620° C. The second temperature is high relative to the first temperature and the third temperature, which is beneficial to increase the deposition speed and reduce the deposition time.

[0049] In some embodiments, the third temperature is 530-590° C. The third temperature is low relative to the second temperature, so that the third amorphous silicon layer obtained has good compactness and corrosion resistance, so that when the doping elements are diffused thereon, a higher concentration of dopant can be obtained, thereby improving the contact between the metal electrode and the doping layer (phosphorus doping layer or boron doping layer).

[0050] In some embodiments, the thickness of the second amorphous silicon layer is 50-200 nm. A thicker second amorphous silicon layer is formed at a higher temperature, and the second amorphous silicon layer is deposited at a higher rate at a high temperature, thereby reducing the formation time of the entire substrate.

[0051] In some embodiments, the thickness of the third amorphous silicon layer is 20-60 nm. The third amorphous silicon layer formed at low temperature has better compactness, which is beneficial to slowing down the diffusion of doping elements; in addition, the third amorphous silicon layer is used as a subsequent contact layer with the metal electrode, and its higher compactness is conducive to obtaining a higher doping concentration, thereby improving the good contact between the metal electrode and the third amorphous silicon layer.

[0052] In some embodiments, the time for forming the second amorphous silicon layer is 2500-3500 seconds, for example, 2500 seconds, 2200 seconds, 3000 seconds, or 3500 seconds.

[0053] In some embodiments, the time for forming the third amorphous silicon layer is 400-1000 s, for example, 400 s, 600 s, 600 s, or 1000 s.

[0054] In some other embodiments, tunnel oxide layers are provided on two opposite sides of the substrate, and a first amorphous silicon layer is provided on both tunnel oxide layers. On the sides of the two first amorphous silicon layers away from the tunnel oxide layer, the second amorphous silicon layer is formed at a second temperature, and the third amorphous silicon layer is formed at a third temperature. In this way, the tunnel oxide layer, the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer are stacked on both opposite sides of the substrate.

[0055] In some embodiments, the first amorphous silicon layer, the second amorphous silicon layer, and the third amorphous silicon layer may be formed by LPCVD or PECVD deposition.

[0056] As some specific examples, the preparation method of the substrate includes: providing an N-type silicon wafer, one side surface of the N-type silicon wafer has a tunneling oxide layer; forming a first amorphous silicon layer at a first temperature on the side surface of the tunneling oxide layer away from the N-type silicon wafer; stacking operations in sequence on the side of the first amorphous silicon layer away from the tunneling oxide layer: forming a second amorphous silicon layer at a second temperature, forming a third amorphous silicon layer at a third temperature, forming a second amorphous silicon layer at a second temperature, and forming a third amorphous silicon layer at a third temperature, wherein the first temperature and the third temperature are respectively less than the second temperature, and the third temperature is greater than the first temperature. This method can save the deposition time of the substrate containing the amorphous silicon layer; the first amorphous silicon layer deposited at the first temperature can be used as a blocking layer during subsequent doping to block the internal expansion of the doping elements, thereby improving the passivation effect of the substrate containing the amorphous silicon layer; the third amorphous silicon layer deposited at the third temperature and the first amorphous silicon layer deposited at the first temperature both have good compactness and corrosion resistance, thereby meeting the requirements of high dopant concentration and low contact.

[0057] According to a second aspect of the present application, a substrate is provided. Figure 1 , the substrate comprises a substrate 1; a tunneling oxide layer 2, the tunneling oxide layer 2 is located on one side of the substrate 1; a first amorphous silicon layer 3, the first amorphous silicon layer 3 is located on one side of the tunneling oxide layer 2 away from the substrate 1, and the first amorphous silicon layer 3 is formed at a first temperature; a fourth amorphous silicon layer 6, the fourth amorphous silicon layer 6 comprises a second amorphous silicon layer 4 and a third amorphous silicon layer 5 which are alternately stacked, the second amorphous silicon layer 4 is located on one side of the first amorphous silicon layer 3 away from the tunneling oxide layer 2, the second amorphous silicon layer 4 is deposited at a second temperature, and the third amorphous silicon layer 5 is deposited at a third temperature, wherein the first temperature and the third temperature are respectively less than the second temperature, and the third temperature is greater than the first temperature. The substrate of the embodiment of the present application has a good passivation effect. This is because the first temperature and the third temperature are relatively low temperatures, and the grain size of silicon is small at low temperatures, so that the growth of the first amorphous silicon layer or the third amorphous silicon layer is slow and dense. This dense first amorphous silicon layer can be used as a barrier layer for subsequent doping elements, blocking the expansion of doped elements into the tunnel oxide layer, thereby improving the passivation effect of the substrate; the dense third amorphous silicon layer provides the possibility of reducing the saturation current density and high-concentration doping in the subsequent metallization area. In addition, the third temperature is greater than the first temperature, but the third temperature is lower than the second temperature. Such a small temperature difference shortens the cooling time, thereby reducing the process time; the third amorphous silicon layer formed at a low temperature has a better density, which is beneficial to slowing down the diffusion of doped elements; in addition, the third amorphous silicon layer is used as a subsequent contact layer with the metal electrode, and its higher density is conducive to obtaining a higher doping concentration, thereby improving the good contact with the metal electrode.

[0058] As an example, the substrate includes a base; a tunneling oxide layer, the tunneling oxide layer is located on a side of the base; a first amorphous silicon layer, the first amorphous silicon layer is located on a side of the tunneling oxide layer away from the base, and the first amorphous silicon layer is formed at a first temperature; a fourth amorphous silicon layer, the fourth amorphous silicon layer includes a second amorphous silicon layer, a third amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer stacked in sequence, the second amorphous silicon layer is located on a side of the first amorphous silicon layer away from the tunneling oxide layer, the second amorphous silicon layer is formed at a second temperature, and the third amorphous silicon layer is formed at a third temperature, wherein the first temperature and the third temperature are respectively lower than the second temperature, and the third temperature is higher than the first temperature.

[0059] In some embodiments, reference Figure 2 Tunneling oxide layers 2 are uniformly present on two opposite sides of the substrate 1, a first amorphous silicon layer 3 is disposed on a side of the tunneling oxide layer 2 away from the substrate, a fourth amorphous silicon layer 6 is disposed on the first amorphous silicon layer 3, the fourth amorphous silicon layer 6 includes a second amorphous silicon layer 4 and a third amorphous silicon layer 5 which are spaced apart, and the second amorphous silicon layer 4 is located on a side of the first amorphous silicon layer 3 away from the tunneling oxide layer 2.

[0060] In some embodiments, the first temperature is 530-590° C. The first amorphous silicon layer at the first temperature has better compactness and stronger blocking capability for doping elements, and can greatly improve the integrity of the tunneling oxide layer (tunneling oxide layer and tunneling oxide layer).

[0061] In some embodiments, the second temperature is 590-620° C. The second temperature is high, which is beneficial to increase the deposition speed and reduce the deposition time.

[0062] In some embodiments, the third temperature is 530-590° C. The third temperature is a low temperature, so that the third amorphous silicon layer obtained has good compactness and corrosion resistance, thereby meeting the requirements of high dopant concentration and low contact.

[0063] The third aspect of the embodiment of the present application provides an application of a substrate prepared by the method of the first aspect or a substrate containing an amorphous silicon layer of the second aspect, including application of the substrate in preparing a solar cell. The substrate prepared by the above method or the above substrate can be used to prepare a solar cell, and has better passivation performance when used to prepare a solar cell.

[0064] In some embodiments, the solar cell includes a tunneling passivated contact solar cell and a back contact solar cell.

[0065] In some embodiments, the method for preparing a solar cell includes: diffusing phosphorus on the substrate to obtain a phosphorus-doped layer; or diffusing boron on the substrate to obtain a boron-doped layer. Boron diffusion or phosphorus diffusion is performed on the side of the substrate having the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer. During diffusion, due to the high density of the third amorphous silicon layer, a doped layer with a higher dopant concentration can be obtained.

[0066] The preparation process of tunnel passivation contact solar cells is taken as an example for explanation.

[0067] As some examples, the method for preparing a tunnel passivation contact solar cell using the substrate prepared by the above method or the above amorphous silicon substrate comprises: S1-1: a substrate (substrate structure such as Figure 2 ) perform phosphorus diffusion and annealing to convert the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer into phosphorus-doped polycrystalline silicon layers; S2-1: perform boron diffusion and annealing on the product obtained in step S1-1 to convert the amorphous silicon layer into a boron-doped polycrystalline silicon layer; S3-1: deposit a passivation layer, an anti-reflection layer and prepare electrodes to obtain a tunnel passivated solar cell.

[0068] In other examples, the method for preparing a tunnel passivation contact solar cell using the amorphous silicon layer substrate prepared by the above method or the amorphous silicon substrate comprises: S1-2: treating a substrate (substrate structure such as Figure 2 ) perform phosphorus diffusion and annealing to convert the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer into phosphorus-doped polycrystalline silicon layers; S2-2: perform boron diffusion and annealing on the product obtained in step S1-1 to convert the amorphous silicon layer into a boron-doped polycrystalline silicon layer; S3-2: deposit a passivation layer, an anti-reflection layer and prepare electrodes to obtain a tunneling passivated solar cell.

[0069] It is understandable that the conditions not mentioned in the preparation process of the tunnel passivation contact solar cell are prior art and will not be described in detail here.

[0070] The following is an example of a method for preparing a back contact passivated solar cell: As some examples, the method for preparing a back contact passivated solar cell using the amorphous silicon layer substrate prepared by the above method or the amorphous silicon substrate comprises: S1-3: treating the amorphous silicon layer substrate (substrate structure as Figure 1) to perform phosphorus diffusion (860-910°C, 15-35min) to transform the amorphous silicon layer (the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer) into a phosphorus-doped polysilicon layer to obtain a phosphorus-doped layer; S2-3: according to a preset pattern, removing the boron-doped layer and the tunneling oxide layer in the non-pattern area; S3-3: depositing a second amorphous silicon layer at a second temperature and a third amorphous silicon layer at a third temperature on a side of the tunneling oxide layer away from the substrate in sequence to obtain the substrate containing the amorphous silicon layer, wherein the first temperature and the third temperature are deposited sequentially; The temperatures are respectively lower than the second temperature, and the third temperature is higher than the first temperature; S4-3: performing boron diffusion (930-1050°C, 15-35min) on the product obtained in step S3-3 to convert the amorphous silicon layer (the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer) into a boron-doped polycrystalline silicon layer to obtain a boron-doped layer; S5-3: removing the phosphorus-doped layer in the non-pattern area according to a preset pattern to insulate the phosphorus-doped layer from the boron-doped layer; S6-3: depositing a passivation layer, an anti-reflection layer and preparing an electrode to obtain a tunnel passivated solar cell.

[0071] As some other examples, the method for preparing a back contact passivated solar cell using the amorphous silicon layer substrate prepared by the above method or the amorphous silicon substrate comprises: S1-3: treating a substrate containing an amorphous silicon layer (substrate structure such as Figure 1 ) to perform boron diffusion and annealing to convert the amorphous silicon layer into a boron-doped polysilicon layer to obtain a boron-doped layer; S2-3: according to a preset pattern, remove the boron-doped layer and the tunneling oxide layer in the non-pattern area; S3-3: sequentially deposit a second amorphous silicon layer at a second temperature and a third amorphous silicon at a third temperature on a side of the tunneling oxide layer away from the substrate to obtain the substrate containing the amorphous silicon layer, wherein the first temperature and the third temperature are respectively less than the second temperature, and the third temperature is greater than the first temperature; S4-3: perform phosphorus diffusion and annealing on the product obtained in step S3-3 to convert the amorphous silicon layer into a phosphorus-doped polysilicon layer to obtain a phosphorus-doped layer; S5-3: according to a preset pattern, remove the phosphorus-doped layer in the non-pattern area to insulate the phosphorus-doped layer and the boron-doped layer; S6-3: deposit a passivation layer, an anti-reflection layer and prepare electrodes to obtain a tunneling passivated solar cell.

[0072] It is understandable that the conditions not mentioned in the preparation process of the tunnel passivation contact solar cell are prior art and will not be described in detail here.

[0073] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0074] Example 1 (S1) A 100 μm N-type silicon wafer is textured and then RCA cleaned. The cleaning conditions are one or more of ammonia and hydrogen peroxide mixed cleaning, hydrochloric acid and hydrogen peroxide mixed cleaning, and hydrofluoric acid cleaning.

[0075] (S2) The silicon wafer is placed in LPCVD to deposit 1 nm of SiOx. The deposition conditions are temperature 600°C and time 2000 s.

[0076] (S3) A first amorphous silicon layer is deposited at a first low temperature of 560° C. for 1200 seconds to obtain a first amorphous silicon layer with a thickness of 40 nm.

[0077] (S4) depositing a second amorphous silicon layer at a second temperature of 600° C. for 3000 s, to obtain a second amorphous silicon layer with a thickness of 150 nm.

[0078] (S5) depositing a third amorphous silicon layer at a third temperature of 585° C. for 500 s, to obtain a third amorphous silicon layer with a thickness of 20 nm.

[0079] (S6) Depositing a second amorphous silicon layer at a second temperature of 600° C. for 3000 s to obtain a second amorphous silicon layer with a thickness of 150 nm.

[0080] (S7) Depositing a third amorphous silicon layer at a third temperature of 585° C. for 900 s to obtain a second amorphous silicon layer with a thickness of 40 nm to obtain an amorphous silicon layer-containing substrate, wherein the amorphous silicon layer includes a first amorphous silicon layer, a second amorphous silicon layer, a third amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer.

[0081] (S8) Phosphorus is diffused into the substrate to convert each amorphous silicon layer into a phosphorus-doped polysilicon layer; the phosphorus diffusion conditions are a temperature of 900° C. and a time of 25 minutes.

[0082] (S9) According to a preset pattern, the phosphorus-doped layer and the tunnel oxide layer in the non-patterned area are removed by laser.

[0083] (S10) Repeating steps (S2-S7) on a side of the tunnel oxide layer away from the substrate.

[0084] (S11) performing boron diffusion (1000° C., 25 min) on the product obtained in step S10 to convert the amorphous silicon layer into a boron-doped polysilicon layer to obtain a boron-doped layer.

[0085] (S12) removing the boron-doped layer in the non-patterned area by laser according to a preset pattern, so as to insulate the phosphorus-doped layer from the boron-doped layer; (S13) depositing a passivation layer, an anti-reflection layer and preparing electrodes to obtain a tunnel passivation back contact solar cell.

[0086] Examples 2 and 3 The tunnel passivation solar cell was prepared according to the method of Example 1, except that the first temperature was 530° C. and 580° C. respectively.

[0087] Examples 4 and 5 A tunnel passivation solar cell was prepared according to the method of Example 1, except that the second temperature was 590° C. and 620° C., respectively.

[0088] Comparative Example 1 A tunnel passivation solar cell was prepared according to the method of Example 1, except that the first temperature was 590°C.

[0089] Comparative Example 2 A tunnel passivation solar cell was prepared according to the method of Example 1, except that the second temperature was 570°C. Comparative Example 3 A tunnel passivation solar cell was prepared according to the method of Example 1, except that the first temperature, the second temperature and the third temperature were all 610°C.

[0091] The batteries of the above embodiments and comparative examples were tested as follows. The test results are shown in Table 1.

[0092] Photoelectric conversion efficiency, short-circuit current, open-circuit voltage, and fill factor testing: The specific testing method is to place the battery under a light source of 100 mW / cm 2 The results are obtained by connecting the source meter using the four-wire method under AM 1.5G simulated sunlight at 25°C.

[0093] Table 1

[0094] By comparing Examples 1-5 and Comparative Examples 1-3, it can be seen that the substrate prepared by the method of the present application is used to prepare a solar cell, and the performance of the obtained solar cell is better. This is because the first amorphous silicon layer and the third amorphous silicon layer formed at low temperature have better compactness, which is beneficial to slow down the diffusion of doping elements; in addition, the third amorphous silicon layer is used as a subsequent contact layer with the metal electrode, and its higher compactness is conducive to obtaining a higher doping concentration, thereby improving the good contact between the metal electrode and it. Forming the second amorphous silicon layer at high temperature is conducive to reducing the time to obtain the substrate as a whole.

[0095] It should also be noted that the "some embodiments", "other embodiments", "embodiments", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0096] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a substrate, characterized in that: include: Providing a substrate, wherein a surface of one side of the substrate has a tunneling oxide layer; Forming a first amorphous silicon layer at a first temperature on a surface of the tunnel oxide layer away from the substrate; A stacking operation is sequentially performed on a side of the first amorphous silicon layer away from the tunnel oxide layer, wherein each round of the stacking operation includes sequentially forming a second amorphous silicon layer at a second temperature and forming a third amorphous silicon layer at a third temperature, The first temperature and the third temperature are respectively lower than the second temperature, and the third temperature is higher than the first temperature.

2. The preparation method according to claim 1, characterized in that: The first temperature is 530-590° C.; And / or, the second temperature is 590-620°C; And / or, the third temperature is 530-590°C.

3. The preparation method according to claim 1, characterized in that: The time for forming the first amorphous silicon layer is 800-1500s; and / or, the time for forming the second amorphous silicon layer is 2500-3500 s; And / or, the time for forming the third amorphous silicon layer is 400-1000s.

4. The preparation method according to claim 1, characterized in that: The number of rounds of the stacking operation is 1 round.

5. The preparation method according to claim 1, characterized in that: The thickness of the substrate is 110-250 μm; And / or, the thickness of the tunnel oxide layer is 0.8-2 nm; And / or, the thickness of the first amorphous silicon layer is 15-45 nm; And / or, the thickness of the second amorphous silicon layer is 50-200 nm; And / or, the thickness of the third amorphous silicon layer is 20-60 nm.

6. A substrate, characterized in that include: substrate; A tunneling oxide layer, wherein the tunneling oxide layer is located on a side of the substrate; a first amorphous silicon layer, the first amorphous silicon layer is located on a side of the tunnel oxide layer away from the substrate, and the first amorphous silicon layer is formed at a first temperature; A fourth amorphous silicon layer, the fourth amorphous silicon layer includes a second amorphous silicon layer and a third amorphous silicon layer which are alternately stacked, the second amorphous silicon layer is located on a side of the first amorphous silicon layer away from the tunneling oxide layer, the second amorphous silicon layer is formed using a second temperature, and the third amorphous silicon layer is formed using a third temperature, wherein the first temperature and the third temperature are respectively lower than the second temperature, and the third temperature is higher than the first temperature.

7. The substrate according to claim 6, characterized in that The fourth amorphous silicon layer is a second amorphous silicon layer, a third amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer which are stacked in sequence.

8. A use of a substrate prepared by the method according to any one of claims 1 to 5 or a substrate according to claim 6 or 7, characterized in that: The invention also comprises application of the substrate in preparing solar cells.

9. The use according to claim 8, characterized in that: The solar cells include tunnel passivated contact solar cells and back contact solar cells.

10. The use according to claim 9, characterized in that: The method for preparing a solar cell comprises: Diffusion of phosphorus into the substrate to obtain a phosphorus-doped layer; Alternatively, boron is diffused into the substrate to obtain a boron-doped layer.

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