Back contact battery, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a back contact battery, a manufacturing method thereof and a photovoltaic module. The back contact battery comprises a semiconductor substrate, a first semiconductor layer and a second semiconductor layer, the first surface of the semiconductor substrate is provided with a plurality of groove structures, and the groove bottoms of the groove structures are pyramid-shaped suede surfaces; and along the thickness direction of the semiconductor substrate, the distance between the surface, deviating from the semiconductor substrate, of the second semiconductor layer arranged at the pyramid tip of the groove bottom and the surface, deviating from the semiconductor substrate, of the first semiconductor layer is h0, and h0 is larger than or equal to 292 nm and smaller than or equal to 15288 nm. H0 is set in a reasonable range, the situation that teeth of the roller extend into the groove structure to scratch the second semiconductor layer located at the groove bottom is reduced, meanwhile, it is guaranteed that the light absorption rate of the second semiconductor layer in the groove structure and the photoelectric conversion rate of the back contact cell cannot be reduced, and it is further guaranteed that the cell piece has enough mechanical strength.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a back-contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] Crystalline silicon solar cells occupy more than 95% of the photovoltaic market due to their mature industrial system. Higher photoelectric conversion efficiency, lower production costs, and longer service life are the key to breaking through the bottleneck of solar cell development and exploring practical applications of solar energy. According to the power output relationship of solar cells, to improve their photoelectric conversion efficiency, it is necessary to maximize the open circuit voltage, fill factor, and short circuit current.

[0003] In the manufacturing process of back-contact batteries, the deposition of thin films will inevitably cause wrap-around plating on the other side of the battery cell, seriously affecting the battery performance and appearance. In order to remove the wrap-around plating on the front or back without affecting the film layer on the other side, the existing technology mostly uses wet processes such as chain processes to etch the battery cell on one side. In the wet chain process, the battery cell needs to be driven forward by the roller in the tank to complete the etching, water washing, drying and other steps. However, in the current wet process, the roller will cause serious scratches on the surface of the battery cell, affecting the subsequent film deposition and thus seriously affecting the battery performance. Summary of the invention

[0004] The purpose of the present application is to provide a back-contact cell and a method for manufacturing the same, as well as a photovoltaic module, so as to reduce the situation where the teeth on the roller scratch the surface of the cell and improve the yield of the cell.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A back contact battery, comprising:

[0007] A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface has a plurality of groove structures, wherein the groove structures are concave toward the second surface relative to the rest of the first surface, and the groove bottoms of the groove structures are pyramid-shaped velvet surfaces;

[0008] A first semiconductor layer is disposed on a portion of the first surface except for the groove structure;

[0009] A second semiconductor layer is disposed at the bottom of the groove structure; the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer;

[0010] Among them, along the thickness direction of the semiconductor substrate, the distance between the surface of the second semiconductor layer at the top of the pyramid arranged at the bottom of the groove and away from the semiconductor substrate is h0, 292nm≤h0≤15288nm.

[0011] Optionally, 2992nm≤h0≤8288nm.

[0012] In the preparation process of the back contact battery, after the second semiconductor layer is made, the semiconductor substrate formed with the second semiconductor layer needs to be cleaned. During the cleaning, the semiconductor substrate is conveyed forward by a roller. On the one hand, if h0 is too small, the teeth of the roller will easily contact and scratch the second semiconductor layer at the bottom of the groove after extending into the groove structure. The second semiconductor layer at the bottom of the groove is used for passivation and carrier collection. If the second semiconductor layer is scratched or damaged, it will greatly affect the passivation effect and the effect of collecting carriers, and thus have a greater impact on the photoelectric conversion efficiency of the back contact battery; on the other hand, if h0 is too large, the depth of the groove structure needs to be set deeper, that is, more parts of the semiconductor substrate need to be removed, which will reduce the overall mechanical strength of the battery cell, and the back contact battery uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If too much of the semiconductor substrate is removed, the transmission path of light in the semiconductor substrate will be reduced, and the light absorption rate of light in the semiconductor substrate will be reduced. In this way, the number of photogenerated carriers, that is, holes and electrons, generated by irradiation on the semiconductor substrate will be reduced, thereby reducing the photoelectric conversion efficiency of the back contact battery. Combining the above two aspects, in the back-contact battery provided in the embodiment of the present invention, h0 is set within a reasonable range to reduce the situation where the teeth of the roller extend into the groove structure and scratch the second semiconductor layer at the bottom of the groove, while ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back-contact battery will not be reduced, and it is also ensured that the battery cell has sufficient mechanical strength.

[0013] In one implementation, the second semiconductor layer is also arranged on the side wall of the groove structure and extends onto part of the first semiconductor layer; along the thickness direction of the semiconductor substrate, the distance between the surface of the second semiconductor layer at the pyramid top at the bottom of the groove structure away from the semiconductor substrate and the surface of the second semiconductor layer covering the first semiconductor layer away from the semiconductor substrate is h1, 312nm≤h1≤15348nm. Setting h1 within a reasonable range can reduce the situation where the teeth of the roller extend into the groove structure to scratch the second semiconductor layer at the bottom of the groove, while ensuring that the light absorption rate of the second semiconductor layer in the groove structure and the photoelectric conversion rate of the back contact battery will not be reduced, and also ensure that the battery cell has sufficient mechanical strength. In the case where the second semiconductor layer extends to the side of the first semiconductor layer away from the semiconductor substrate, the second semiconductor layer arranged on the side of the first semiconductor layer away from the semiconductor substrate can increase the distance between the teeth of the roller and the second semiconductor layer at the pyramid top covering the bottom of the groove, so h1 can be set within the range of 312nm≤h1≤15348nm, which can further prevent the teeth of the roller from extending into the groove structure to scratch the second semiconductor layer at the bottom of the groove.

[0014] Optionally, 3012nm≤h1≤8348nm.

[0015] In one implementation, along the thickness direction of the semiconductor substrate, the distance between the pyramid tip of the bottom portion of the groove structure of the semiconductor substrate and the surface of the first semiconductor layer away from the semiconductor substrate is h2, 330nm≤h2≤15300nm. In this technical solution, h2 is set within a reasonable range, so as to further prevent the teeth of the roller from extending into the groove structure and scratching the pyramid at the bottom of the groove structure during the cleaning process, and further ensure that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back contact battery will not be reduced, and the battery cell has sufficient mechanical strength.

[0016] Optionally, 3030nm≤h2≤8300nm.

[0017] In one implementation, the distance from the pyramid top at the bottom of the groove structure of the semiconductor substrate to the surface of the first surface other than the groove structure is h3, 300nm≤h3≤15000nm. In this case, the depth of the groove structure is kept within a reasonable range, which not only ensures that the light absorption rate of the semiconductor substrate and the photoelectric conversion rate of the back contact battery will not be reduced, but also ensures that the battery cell has sufficient mechanical strength; at the same time, it also ensures that after other film layers are formed on the semiconductor substrate, when the semiconductor substrate is cleaned, the teeth of the roller will not contact the pyramid at the bottom of the groove structure after extending into the groove structure, or will not contact the film layer deposited on the pyramid at the bottom of the groove structure, such as the second semiconductor layer, so as to ensure that the teeth of the roller will not scratch the pyramid at the bottom of the groove structure, or will not scratch the film layer formed on the pyramid at the bottom of the groove structure.

[0018] Optionally, 3000nm≤h3≤8000nm.

[0019] In one implementation, the size of the pyramid base at the bottom of the groove of the semiconductor substrate is in the range of 500nm to 7000nm, and the height of the pyramid is in the range of 300nm to 6000nm. The size of the pyramid base and the height of the pyramid are set within a reasonable range, so that the bottom of the groove structure can ensure the light trapping effect, while the height of the pyramid at the bottom of the groove is appropriately reduced, so that the top of the pyramid at the bottom of the groove is further away from the surface of the first semiconductor layer away from the semiconductor substrate; in this way, it can be further ensured that other film layers, such as but not limited to the second semiconductor layer or the transparent conductive layer, arranged at the top of the pyramid at the bottom of the groove are also further away from the surface of the first semiconductor layer away from the semiconductor substrate, thereby avoiding the situation where the teeth of the roller extend into the groove structure and scratch the second semiconductor layer or the transparent conductive layer at the bottom of the groove. In addition, after the texturing process is completed, in the process of cleaning the semiconductor substrate, it can be avoided that the teeth of the roller extend into the groove structure and contact the pyramid at the bottom of the groove structure, thereby ensuring that the teeth of the roller will not scratch the top of the pyramid at the bottom of the groove structure.

[0020] Optionally, the base size of the pyramid is 1000nm to 3500nm, and the height of the pyramid is in the range of 300nm to 6000nm.

[0021] In one implementation, the spacing between adjacent first semiconductor layers is L, 200μm≤L≤800μm. In this technical solution, the spacing L between adjacent first semiconductor layers is set within a reasonable range, so that when the teeth of the roller extend into the groove structure, the two side walls of the groove structure can be offset against the conical teeth to limit the length of the roller teeth extending into the groove structure, thereby appropriately increasing the distance between the roller teeth and the pyramid tip at the bottom of the groove; in this way, it can be further ensured that the distance between the second semiconductor layer set at the pyramid tip at the bottom of the groove and the surface of the first semiconductor layer away from the semiconductor substrate is appropriately increased, further avoiding the situation where the teeth of the roller extend into the groove structure and scratch the second semiconductor layer at the bottom of the groove. In addition, the spacing L between adjacent first semiconductor layers is set within a reasonable range, so that the teeth of the roller are not easy to extend into the groove structure to scratch the pyramid at the bottom of the groove structure, the second semiconductor layer set at the bottom of the groove, or the transparent conductive layer set at the bottom of the groove, while preventing the width of the second semiconductor layer from being too small, affecting the collection of carriers by the second semiconductor layer.

[0022] Optionally, 350 μm≤L≤600 μm.

[0023] In one implementation, the width of the groove bottom of the groove structure is L1, 170μm≤L1≤790μm. In this technical solution, the width L1 of the groove bottom of the groove structure is set within a reasonable range, so that the teeth of the roller are not easy to extend into the groove structure to scratch the pyramid at the bottom of the groove structure, the second semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer arranged at the bottom of the groove, and at the same time, the width of the second semiconductor layer is prevented from being too small, which affects the collection of carriers by the second semiconductor layer.

[0024] Optionally, the width L1 of the groove bottom of the groove structure is 320 μm to 590 μm.

[0025] In one implementation, 0.36≤h0 / L≤76.4. It can be understood that if the depth of the groove structure is deeper, the length of the roller teeth allowed to extend into the groove structure is greater, under the premise of ensuring that the pyramid spire at the bottom of the groove, the second semiconductor layer on the pyramid spire at the bottom of the groove, and the transparent conductive layer on the pyramid spire at the bottom of the groove are not scratched. In this way, when the depth of the groove structure is deeper, the opening width of the groove structure can be appropriately increased, and the opening width of the groove structure is roughly equal to the spacing between adjacent first semiconductor layers, which is L. Based on this, the embodiment of the present application sets the ratio of h0 / L within a reasonable range to ensure that the roller teeth extend into the groove structure without scratching the pyramid spire at the bottom of the groove, the second semiconductor layer at the pyramid spire at the bottom of the groove, and the transparent conductive layer at the pyramid spire at the bottom of the groove, and increase the width of the second semiconductor layer, thereby improving the collection efficiency of the second semiconductor layer for carriers.

[0026] In one implementation, the sidewall of the groove structure includes an inclined surface, and along a direction away from the middle area of ​​the groove bottom, the inclined surface is inclined in a direction away from the second surface;

[0027] The width of the inclined surface is L2, 5μm≤L2≤15μm. In the technical solution, the width L2 of the inclined surface is set within a reasonable range to prevent the teeth of the roller from scratching the inclined surface or the film layer deposited on the inclined surface after extending into the groove structure, while ensuring that the formation quality of the second semiconductor layer at the side wall of the groove structure is improved and the carrier collection efficiency of the second semiconductor layer is improved.

[0028] In one implementation, the inclined surface includes a pyramid-shaped pile surface;

[0029] The size of the pyramid located on the inclined surface is larger than the size of the pyramid located at the bottom of the groove. In this case, it can be understood that, within the same range, the number of pyramids formed on the surface of the region with the larger-sized pyramids is relatively small, which is conducive to reducing the roughness of the surface of the region. Based on this, when the size of the pyramid formed on the inclined surface is larger than the pyramid formed on the bottom of the groove structure, it is conducive to reducing the roughness of the inclined surface, improving the formation quality of the second semiconductor layer on the inclined surface, and improving the field passivation effect of the second semiconductor layer on the inclined surface.

[0030] In one implementation, the height of the pyramid located on the inclined surface and at the junction of the non-inclined surface and the groove bottom ranges from 50nm to 3000nm, and the size of the base is 2000nm to 8000nm; setting the height and base size of the pyramid on the inclined surface within a reasonable range can prevent the teeth of the roller from contacting the pyramid on the inclined surface after extending into the groove structure, thereby ensuring that the teeth of the roller will not scratch the pyramid on the inclined surface or the film layer deposited on the pyramid, and at the same time help reduce the roughness of the inclined surface and improve the formation quality of the second semiconductor layer on the inclined surface.

[0031] The pyramid located on the inclined surface and at the junction of the inclined surface and the groove bottom has a tower height ranging from 1000nm to 9000nm, and a tower base size ranging from 1000nm to 9000nm. In this case, the size of the pyramid at the junction of the inclined surface and the groove bottom is larger than the size of the pyramid located on the inclined surface, which is conducive to reducing the roughness of the junction of the inclined surface and the groove bottom, thereby improving the formation quality of the second semiconductor layer at this position.

[0032] Optionally, the pyramid located on the inclined surface and at the junction of the non-inclined surface and the bottom of the groove has a tower height of 100nm to 2000nm, and a tower base of 100nm to 2000nm;

[0033] The height of the pyramid located on the inclined surface and at the junction of the inclined surface and the groove bottom is 1500nm~5000nm, and the base is 1500nm~5000nm.

[0034] In one implementation, the pyramid tip at the bottom of the groove of the semiconductor substrate is in an arc shape. In this case, compared with the pyramid tip in a pointed shape, the height of the pyramid tip in an arc shape is appropriately reduced, thereby increasing the distance between the pyramid tip at the bottom of the groove and the surface of the first semiconductor layer away from the semiconductor substrate, and also increasing the distance between the second semiconductor layer at the pyramid tip at the bottom of the groove and the surface of the first semiconductor layer away from the semiconductor substrate, further reducing the probability that the teeth of the roller extend into the groove structure and scratch the pyramid at the bottom of the groove structure, the second semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer arranged at the bottom of the groove.

[0035] In one implementation, the radius of curvature of the arc-shaped pyramid tip is 70 nm to 150 nm; and / or,

[0036] The curvature range of the arc-shaped pyramid tip is 30° to 150°. Setting the curvature radius and curvature range of the arc-shaped pyramid tip within a suitable range can not only appropriately reduce the pyramid height, thereby reducing the situation where the pyramid at the bottom of the groove is scratched, but also ensure the light trapping effect of the groove structure.

[0037] In one implementation, the back contact cell further comprises a transparent conductive layer, which is disposed on a side of the first semiconductor layer and the second semiconductor layer away from the semiconductor substrate, and the transparent conductive layer is provided with an opening penetrating through the thickness thereof;

[0038] Along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer on the pyramid top at the bottom of the groove and the surface of the transparent conductive layer on the first semiconductor layer and the surface of the semiconductor substrate is greater than or equal to 316nm and less than or equal to 15385nm. In this case, after the transparent conductive layer is formed, during the cleaning of the semiconductor substrate, the teeth of the roller will not contact the transparent conductive layer at the bottom of the groove structure after extending into the groove structure, thereby preventing the teeth of the roller from scratching the transparent conductive layer on the pyramid top at the bottom of the groove structure. At the same time, it also ensures that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back contact battery will not be reduced, and it also ensures that the battery cell has sufficient mechanical strength.

[0039] In one implementation, the second semiconductor layer is also arranged on the side wall of the groove structure and extends to part of the first semiconductor layer; the thickness of the second semiconductor layer located at the bottom of the groove of the groove structure is less than the thickness of the second semiconductor layer located at the side wall of the groove structure and / or covering the first semiconductor layer. In this way, the thickness of the second semiconductor layer covering the first semiconductor layer is relatively large. When the second semiconductor layer covering the first semiconductor layer supports the roller, the teeth on the roller can be farther away from the second semiconductor layer at the bottom of the groove structure or the transparent conductive layer arranged on the second semiconductor layer; at the same time, the thickness of the second semiconductor layer located at the bottom of the groove structure is relatively small, which can also make the second semiconductor layer at the bottom of the groove structure or the transparent conductive layer arranged on the second semiconductor layer farther away from the teeth on the roller. In summary, it can be seen that when the thickness of the second semiconductor layer at the bottom of the groove structure is less than the thickness of the second semiconductor layer covering the first semiconductor layer, the distance between the teeth on the roller and the second semiconductor layer at the bottom of the groove structure or the transparent conductive layer arranged on the second semiconductor layer is further increased, further reducing the situation where the teeth of the roller extend into the groove structure to scratch the second semiconductor layer at the bottom of the groove or the transparent conductive layer arranged on the second semiconductor layer.

[0040] A photovoltaic module, such as any of the back-contact cells described above. The beneficial effects of the photovoltaic module are the same as those of the back-contact cells described above, which will not be described in detail here.

[0041] A method for manufacturing a back contact battery, comprising:

[0042] A semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface has first regions and second regions alternately distributed;

[0043] forming a first semiconductor layer on the first surface;

[0044] The first semiconductor layer located in the second area is etched, and the part of the semiconductor substrate located in the second area is subjected to texturing treatment; after the texturing treatment, the part of the semiconductor substrate corresponding to the second area is concave in the direction from the second surface to the first surface relative to the first area in the direction of the second surface, forming a groove structure, and the bottom of the groove structure is a pyramid-shaped velvet surface;

[0045] forming a second semiconductor layer on the first surface, and removing a portion of the second semiconductor layer to expose the first semiconductor layer; the second semiconductor layer and the first semiconductor layer have opposite conductivity types;

[0046] A semiconductor substrate having a first semiconductor layer and a second semiconductor layer formed thereon is placed in a cleaning solution for cleaning and is transferred via a roller; wherein the first surface faces the roller; and the teeth of the roller do not contact the second semiconductor layer on the top of the pyramid disposed at the bottom of the groove.

[0047] In the above-mentioned manufacturing method of the back-contact battery, during the process of cleaning the semiconductor substrate on which the first semiconductor layer and the second semiconductor layer are formed, the first surface of the semiconductor substrate faces the roller, and the teeth on the roller may extend into the interior of the groove structure due to the weight of the semiconductor substrate itself, the pressure of the water film and / or the pressure of the drying roller, but the teeth of the roller do not contact the second semiconductor layer on the top of the pyramid arranged at the bottom of the groove. In this way, the teeth of the roller can be prevented from extending into the groove structure and scratching the second semiconductor layer at the bottom of the groove, thereby ensuring the performance of the back-contact battery.

[0048] In one implementation, along the thickness direction of the semiconductor substrate, the surface of the second semiconductor layer at the top of the pyramid at the bottom of the groove facing away from the semiconductor substrate is at a distance h0 from the surface of the first semiconductor layer facing away from the semiconductor substrate, 292nm≤h0≤15288nm, thereby reducing the situation where the teeth of the roller extend into the groove structure and scratch the second semiconductor layer on the top of the pyramid at the bottom of the groove, while ensuring that the absorbance of the second semiconductor layer in the groove structure and the photoelectric conversion rate of the back contact battery are not reduced, and also ensuring that the battery cell has sufficient mechanical strength.

[0049] Optionally, 3030nm≤h2≤8300nm.

[0050] In one implementation, along the thickness direction of the semiconductor substrate, the distance from the pyramid tip of the groove bottom of the semiconductor substrate to the surface of the first surface excluding the groove structure is h3, 300nm≤h3≤15000nm.

[0051] Optionally, 3000nm≤h3≤8000nm.

[0052] In one implementation, and / or, the second semiconductor layer is also arranged on the side wall of the groove structure and extends onto a portion of the first semiconductor layer; along the thickness direction of the semiconductor substrate, the surface of the second semiconductor layer at the top of the pyramid at the bottom of the groove structure that is away from the semiconductor substrate is at a distance h1 from the surface of the second semiconductor layer covering the first semiconductor layer that is away from the semiconductor substrate, 312nm≤h1≤15348nm.

[0053] Optionally, 3012nm≤h1≤8348nm.

[0054] In one implementation, after the texturing treatment and before the second semiconductor layer is formed on the first surface, the manufacturing method of the back contact battery further includes: placing the semiconductor substrate formed with the first semiconductor layer into a cleaning liquid for cleaning, and transferring it through a roller; wherein the first surface faces the roller; and the teeth of the roller do not contact the pyramid top at the bottom of the groove. With this technical solution, after the groove bottom of the groove structure is texturized, the semiconductor substrate is cleaned to remove the texturing liquid remaining on the surface, and during the cleaning process, the teeth of the roller do not contact the pyramid top set at the bottom of the groove, thereby preventing the teeth of the roller from scratching the pyramid top at the bottom of the groove, thereby ensuring the performance of the back contact battery.

[0055] In one implementation, along the thickness direction of the semiconductor substrate, the distance between the pyramid top at the bottom of the groove structure and the surface of the first semiconductor layer away from the semiconductor substrate is h2, 330nm≤h2≤15300nm. Thus, during the cleaning process, it is ensured that after the teeth of the roller extend into the groove structure, they will not contact the pyramid at the bottom of the groove structure, and the teeth of the roller will not scratch the pyramid top at the bottom of the groove structure. At the same time, it is ensured that the light absorption rate of the second semiconductor layer in the groove structure and the photoelectric conversion rate of the back contact battery will not be reduced, and it is also ensured that the battery cell has sufficient mechanical strength.

[0056] Optionally, 3030nm≤h2≤8300nm.

[0057] In one implementation, after the semiconductor substrate having the first semiconductor layer and the second semiconductor layer formed thereon is placed in a cleaning solution for cleaning, the method for manufacturing a back contact battery further includes: forming a transparent conductive layer on a side of the first semiconductor layer and the second semiconductor layer away from the semiconductor substrate, wherein the transparent conductive layer is provided with an opening penetrating the thickness thereof;

[0058] A semiconductor substrate having a transparent conductive layer formed thereon is placed in a cleaning solution for cleaning and is transferred by a roller, wherein the first surface faces the roller; and the teeth of the roller do not contact the transparent conductive layer on the top of the pyramid arranged at the bottom of the groove.

[0059] In one implementation, along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer on the pyramid top at the bottom of the groove and the surface of the transparent conductive layer on the first semiconductor layer and the surface of the semiconductor substrate is greater than or equal to 316nm and less than or equal to 15385nm. In this case, after the transparent conductive layer is formed, during the cleaning of the semiconductor substrate, the teeth of the roller will not contact the transparent conductive layer on the pyramid top at the bottom of the groove structure after extending into the groove structure, thereby preventing the teeth of the roller from scratching the transparent conductive layer at the bottom of the groove structure. At the same time, it also ensures that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back contact battery will not be reduced, and it also ensures that the battery cell has sufficient mechanical strength.

[0060] In one implementation, after the texturing treatment and before the second semiconductor layer is formed on the first surface, the manufacturing method of the back contact battery further includes: modifying the pyramid tip at the bottom of the groove structure so that the tip of the pyramid at the bottom of the groove is in an arc shape; wherein the radius of curvature of the pyramid tip is 70nm to 150nm; and / or the curvature range of the pyramid tip is 30° to 150°. Compared with the pyramid with a pointed tip, the height of the pyramid with an arc tip is appropriately reduced, thereby increasing the distance between the pyramid tip at the bottom of the groove and the surface of the first semiconductor layer away from the semiconductor substrate, and also increasing the distance between the second semiconductor layer at the pyramid tip at the bottom of the groove and the surface of the first semiconductor layer away from the semiconductor substrate, further reducing the probability that the teeth of the roller are not easy to extend into the groove structure and scratch the pyramid at the bottom of the groove structure, the second semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer arranged at the bottom of the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0062] Figure 1A schematic diagram of a photovoltaic module provided in an embodiment of the present application;

[0063] Figure 2 A partial cross-sectional view of a back contact battery provided in an embodiment of the present application;

[0064] Figure 3 A schematic diagram of a semiconductor substrate having a first semiconductor layer formed thereon by roller transfer provided in an embodiment of the present application;

[0065] Figure 4a SEM image of a portion of the structure of the back contact battery provided in the embodiment of the present application at the side wall of the groove structure Figure 1 ;

[0066] Figure 4b for Figure 4a A partial enlarged view of the

[0067] Figure 5 SEM image of a portion of the structure of the back contact battery provided in the embodiment of the present application at the side wall of the groove structure Figure 2 ;

[0068] Figure 6 A top view SEM image of a part of the structure of the back contact battery provided in an embodiment of the present application at the side wall of the groove structure;

[0069] Figure 7 A cross-sectional view of a semiconductor substrate provided in an embodiment of the present application;

[0070] Figure 8 Schematic diagram of the opening position of the transparent conductive layer of the back contact battery provided in the embodiment of the present application Figure 1 ;

[0071] Fig. 9 Schematic diagram of the opening position of the transparent conductive layer of the back contact battery provided in the embodiment of the present application Figure 2 ;

[0072] Fig.10 Schematic diagram of the opening position of the transparent conductive layer of the back contact battery provided in the embodiment of the present application Figure 3 ;

[0073] Fig.11 Schematic diagram 4 of the opening position of the transparent conductive layer of the back contact battery provided in the embodiment of the present application;

[0074] Fig.12 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0075] Fig.13 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0076] Fig.14 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0077] Fig.15 A fourth schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention;

[0078] Fig.16 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided by an embodiment of the present invention Figure 5 .

[0079] Reference numerals:

[0080] 1-semiconductor substrate, 2-first semiconductor layer, 3-first passivation layer, 4-second semiconductor layer, 5-second passivation layer, 6-groove structure, 6a-groove bottom, 6b-inclined surface, 7-roller, 7a-teeth, 8-transparent conductive layer, 8a-opening, 9-mask layer. DETAILED DESCRIPTION

[0081] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0082] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0083] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0084] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0085] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0086] The present application provides a photovoltaic module, which includes a plurality of back-contact cells, and the plurality of back-contact cells are electrically connected in series and / or in parallel. For example, Figure 1 A schematic diagram of a plurality of back contact cells electrically connected together is provided. Figure 1 As shown, multiple back-contact cells are arranged in sequence along direction A to form a cell string, and multiple back-contact cells in the cell string are connected in series. Two or more cell strings are arranged in sequence along direction A to form a group of cell strings, and multiple groups of cell strings are arranged in sequence along direction B.

[0087] In the manufacturing process of the back contact battery, after the groove bottom of the groove structure of the semiconductor substrate is textured, after the first semiconductor layer and the second semiconductor layer are formed, and after the transparent conductive layer 8 is formed, the semiconductor substrate needs to be cleaned to remove the residues and stains left in the process. The cleaning generally adopts a wet process such as a chain process or a roller liquid process to clean the battery cell. During the cleaning process, a roller is used to transport the battery cell. The roller has teeth, and the surface of the semiconductor substrate that needs to be cleaned faces the roller. In this way, due to the weight of the semiconductor substrate itself, the pressure of the water film and / or the pressure of the drying roller, the teeth of the roller may extend into the interior of the groove structure and contact with the pyramid at the bottom of the groove structure, the second semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer 8 arranged at the bottom of the groove, resulting in scratches on the pyramid at the bottom of the groove structure, the second semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer 8 arranged at the bottom of the groove, affecting the performance of the back contact battery.

[0088] In view of the above situation, in order to reduce the situation where the teeth on the roller scratch the surface of the battery cell and improve the yield of the battery cell, the present application also provides a back-contact battery, which can be used in the above-mentioned photovoltaic module.

[0089] The present application provides a back-contact battery, which includes: a semiconductor substrate, the semiconductor substrate having a first surface and a second surface relative to each other, the first surface having a plurality of groove structures, the groove structures being recessed toward the second surface relative to the rest of the first surface, and the groove bottoms of the groove structures being pyramid-shaped velvet surfaces; a first semiconductor layer, arranged on a portion of the first surface other than the groove structures; a second semiconductor layer, arranged at the groove bottoms of the grooves; the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; wherein, along the thickness direction of the semiconductor substrate, a surface of the second semiconductor layer at the pyramid tip arranged at the groove bottom that is away from the semiconductor substrate is at a distance h0 from a surface of the first semiconductor layer that is away from the semiconductor substrate, and 292nm≤h0≤15288nm.

[0090] See also Figure 2 A back contact cell provided in a specific embodiment of the present application includes: a semiconductor substrate 1, a first semiconductor layer 2, a second semiconductor layer 4, a transparent conductive layer 8, a first passivation layer 3, a second passivation layer 5, a first electrode, a second electrode, etc. The semiconductor substrate 1 has a first surface and a second surface opposite to each other. The first semiconductor layer 2 and the second semiconductor layer 4 are both disposed on the first surface of the semiconductor substrate 1.

[0091] Among them, along the direction parallel to the first surface of the semiconductor substrate 1, the first semiconductor layer 2 is formed on a partial area of ​​the first surface of the semiconductor substrate 1. A plurality of groove structures 6 are formed on the portion of the first surface of the semiconductor substrate 1 exposed outside the first semiconductor layer 2. The groove structure 6 is recessed in the direction of the second surface relative to the rest of the first surface. That is, the groove structure 6 is arranged below the rest of the first surface, and the first semiconductor layer 2 is arranged on the portion of the first surface other than the groove structure 6. The second semiconductor layer 4 is arranged at the bottom 6a of the groove structure 6, that is, the second semiconductor layer 4 covers the surface of the bottom 6a of the groove structure 6. The first semiconductor layer 2 and the second semiconductor layer 4 have opposite conductivity types, so as to collect and extract electrons and holes respectively, which is conducive to the formation of photocurrent. The presence of the groove structure 6 can at least partially stagger the electrode structures that are electrically in contact with the first semiconductor layer 2 and the second semiconductor layer 4 respectively along the thickness direction of the semiconductor substrate 1, which is conducive to suppressing leakage.

[0092] Furthermore, the groove bottom 6a of the groove structure 6 is a pyramid-shaped velvet surface, and the pyramid-shaped velvet surface has an uneven feature. When the pyramid-shaped velvet surface is formed on the groove bottom 6a of the groove structure 6, it is beneficial to increase the surface area of ​​the groove bottom 6a of the groove structure 6, improve the light trapping effect of the groove structure 6, and facilitate more light to be refracted into the semiconductor substrate 1 through the groove bottom 6a of the groove structure 6 and used by the semiconductor substrate 1. In addition, the portion of the second semiconductor layer 4 located on the groove bottom 6a of the groove structure 6, the side of the second semiconductor layer 4 formed on the groove bottom 6a through deposition and other processes that is away from the semiconductor substrate 1 will also fluctuate with the fluctuation of the groove bottom 6a, that is, the side of the portion of the second semiconductor layer 4 formed on the groove bottom 6a that is away from the semiconductor substrate 1 also has roughly the same undulating morphology as the groove bottom 6a of the groove structure 6. Therefore, when a pyramid-shaped velvet surface is formed on the groove bottom 6a of the groove structure 6, the side of the second semiconductor layer 4 formed on the groove bottom 6a that is away from the semiconductor substrate 1 also has a corresponding uneven feature, which is beneficial to increase the surface area of ​​the second semiconductor layer 4 formed on the groove bottom 6a that is away from the semiconductor substrate 1, and then help to increase the contact area between the second semiconductor layer 4 and the corresponding electrode, help to reduce the contact resistance between the second semiconductor layer 4 and the corresponding electrode, and further improve the working performance of the back contact battery.

[0093] In some embodiments, Figure 2 As shown, along the thickness direction of the semiconductor substrate 1, the distance between the surface of the second semiconductor layer 4 disposed at the pyramid tip of the groove bottom 6a facing away from the semiconductor substrate 1 and the surface of the first semiconductor layer 2 facing away from the semiconductor substrate 1 is h0, 292nm≤h0≤15288nm. In other words, along the direction from the second surface to the first surface of the semiconductor substrate 1, the minimum distance between the surface of the second semiconductor layer 4 disposed at the groove bottom 6a facing away from the semiconductor substrate 1 and the surface of the first semiconductor layer 2 facing away from the semiconductor substrate 1 is h0, 292nm≤h0≤15288nm. Exemplarily, h0 may be 292 nm, 500 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm, 15000 nm or 15288 nm.

[0094] In the preparation process of the back contact battery, after the second semiconductor layer 4 is made, the semiconductor substrate 1 formed with the second semiconductor layer 4 needs to be cleaned. During the cleaning, the semiconductor substrate 1 is transferred forward by the roller 7. On the one hand, if h0 is too small, the teeth 7a of the roller 7 will easily contact and scratch the second semiconductor layer 4 located at the bottom 6a of the groove after extending into the groove structure 6. The second semiconductor layer 4 located at the bottom 6a of the groove is used for passivation and carrier collection. If the second semiconductor layer 4 is scratched or damaged, it will greatly affect the passivation effect and the effect of collecting carriers, and further affect the photoelectric conversion efficiency of the back contact battery. On the other hand, if h0 is too large, the depth of the groove structure 6 needs to be set deeper, that is, more parts of the semiconductor substrate 1 need to be removed, which will reduce the overall mechanical strength of the battery cell, and the back contact battery uses light to separate electrons and holes on the semiconductor substrate 1 to generate electricity. If too much of the semiconductor substrate 1 is removed, the transmission path of light in the semiconductor substrate 1 will be reduced, and the light absorption rate of the semiconductor substrate 1 will be reduced. In this way, the number of photogenerated carriers, that is, holes and electrons, generated by irradiation on the semiconductor substrate 1 will be reduced, thereby reducing the photoelectric conversion rate of the back contact battery. Combining the above two aspects, in the back contact battery provided by the embodiment of the present invention, h0 is set within a reasonable range to reduce the situation where the teeth 7a of the roller 7 extend into the groove structure 6 and scratch the second semiconductor layer 4 located at the bottom 6a of the groove, while ensuring that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the back contact battery will not be reduced, and it is also ensured that the battery cell has sufficient mechanical strength.

[0095] In some embodiments, 2992nm≤h0≤8288nm. Exemplarily, h0 is 2992nm, 3500nm, 4500nm, 5500nm, 6500nm, 7500nm or 8288nm. This can further prevent the teeth 7a of the roller 7 from extending into the groove structure 6 and scratching the second semiconductor layer 4 at the groove bottom 6a, and further ensure that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the back contact battery will not be reduced, and the battery cell has sufficient mechanical strength.

[0096] In actual application, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate 1. The semiconductor substrate 1 can be a substrate made of any semiconductor material such as a silicon substrate, a silicon germanium substrate, a germanium substrate or a gallium arsenide substrate.

[0097] It can be understood that the first surface of the semiconductor substrate 1 corresponds to the backlight surface of the back contact battery, and the second surface of the semiconductor substrate 1 corresponds to the light-facing surface of the back contact battery. Based on this, the light-facing surface of the semiconductor substrate 1 can be a plane, or the light-facing surface of the semiconductor substrate 1 can also be a velvet surface. Among them, because the velvet surface has a light trapping effect, when the light-facing surface of the semiconductor substrate 1 is a velvet surface, the reflectivity of the light-facing surface can be reduced, which is conducive to allowing more light to be refracted from the light-facing surface into the semiconductor substrate 1 and absorbed and utilized by the semiconductor substrate 1, which is conducive to improving the photoelectric conversion efficiency of the back contact battery.

[0098] The second semiconductor layer 4 may be disposed only on the groove bottom 6 a of the groove structure 6 , or may be disposed on the groove bottom 6 a of the groove structure 6 and the sidewall of the groove structure 6 .

[0099] In some embodiments, Figure 2 As shown, the second semiconductor layer 4 is also arranged on the side wall of the groove structure 6, and the second semiconductor layer 4 also extends to the part of the first semiconductor layer 2 away from the semiconductor substrate 1. Along the thickness direction of the semiconductor substrate 1, the distance between the surface of the second semiconductor layer 4 arranged at the pyramid tip of the groove bottom 6a away from the semiconductor substrate 1 and the surface of the second semiconductor layer 4 covering the first semiconductor layer 2 away from the semiconductor substrate 1 is h1, 312nm≤h1≤15348nm.

[0100] In the case where the second semiconductor layer 4 extends to the side of the first semiconductor layer 2 away from the semiconductor substrate 1, the second semiconductor layer 4 disposed on the side of the first semiconductor layer 2 away from the semiconductor substrate 1 can increase the distance between the teeth of the roller and the second semiconductor layer 4 at the pyramid tip covering the bottom of the groove. In order to prevent the teeth of the roller from scratching the second semiconductor layer 4 at the bottom of the groove, h1 can be set within the range of 312nm≤h1≤15348nm. Exemplarily, h1 is 312nm, 500nm, 1000nm, 2000nm, 3000nm, 4000nm, 5000nm, 6000nm, 7000nm, 8000nm, 9000nm, 10000nm, 11000nm, 12000nm, 13000nm, 14000nm or 15348nm, etc. This can further prevent the teeth 7a of the roller 7 from extending into the groove structure 6 and scratching the second semiconductor layer 4 at the bottom 6a of the groove.

[0101] In some examples, 3012 nm ≤ h1 ≤ 8348 nm.

[0102] like Figure 2 and Figure 3As shown, along the thickness direction of the semiconductor substrate 1, the distance between the pyramid tip of the groove bottom 6a of the groove structure 6 of the semiconductor substrate and the surface of the first semiconductor layer 2 facing away from the semiconductor substrate 1 is h2, 330nm≤h2≤15300nm. In other words, along the direction from the second surface to the first surface of the semiconductor substrate 1, the minimum distance between the pyramid tip of the groove bottom 6a of the groove structure 6 and the surface of the first semiconductor layer 2 facing away from the semiconductor substrate 1 is h2, 330nm≤h2≤15300nm.

[0103] In the process of manufacturing back-contact batteries, after forming the first semiconductor layer 2 and texturing the bottom 6a of the groove structure 6, and before forming the second semiconductor layer 4, the semiconductor substrate 1 needs to be cleaned to remove the texturing liquid remaining on the surface. Considering that if h2 is too small, during the cleaning process, after the teeth 7a of the roller 7 extend into the groove structure 6, it will contact the pyramid of the bottom 6a of the groove structure 6, and then scratch the pyramid top of the bottom 6a of the groove structure 6. If the pyramid top is scratched, the number of defects will increase. When the second semiconductor layer 4 is subsequently deposited, it will affect the film quality of the second semiconductor layer 4, and then affect the passivation and carrier collection function of the second semiconductor layer 4. Therefore, damage to the pyramid top will have a greater impact on the subsequent process; if h2 is too large, a groove needs to be set. The depth of the groove structure 6 is deep, that is, more parts of the semiconductor substrate 1 need to be removed, which will reduce the overall mechanical strength of the battery cell. In addition, the back contact battery uses light to separate electrons and holes on the semiconductor substrate 1 to generate electricity. If too much of the semiconductor substrate 1 is removed, the transmission path of light in the semiconductor substrate 1 will be reduced, and the light absorption rate of the semiconductor substrate 1 will be reduced. In this way, the number of photogenerated carriers, that is, holes and electrons, generated by irradiation on the semiconductor substrate 1 will be reduced, thereby reducing the photoelectric conversion rate of the back contact battery. In view of the above situation, in this technical solution, h2 is set within the range of 330nm to 15300nm, so as to further prevent the teeth 7a of the roller 7 from extending into the groove structure 6 and scratching the pyramid of the groove bottom 6a of the groove structure 6 during the cleaning process, and further ensure that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the back contact battery will not be reduced, and the battery cell has sufficient mechanical strength.

[0104] Exemplarily, h2 is 330 nm, 500 nm, 800 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm, 15000 nm or 15300 nm.

[0105] In some examples, 3030nm≤h2≤8300nm.

[0106] In some specific embodiments, Figure 2 As shown, along the thickness direction of the semiconductor substrate 1, the distance from the pyramid tip of the groove bottom of the semiconductor substrate to the surface of the first surface other than the groove structure 6 is h3, 300nm≤h3≤15000nm. At this time, other film layers formed on the semiconductor substrate 1 are not considered, and only the distance from the pyramid tip of the semiconductor substrate to the surface of the first surface other than the groove structure 6 is considered.

[0107] In this case, the depth of the groove structure 6 is maintained within a reasonable range, which ensures that the light absorption rate of the semiconductor substrate 1 and the photoelectric conversion rate of the back contact battery will not decrease, and the battery cell has sufficient mechanical strength; at the same time, it also ensures that after other film layers are formed on the semiconductor substrate 1, when the semiconductor substrate 1 is cleaned, the teeth 7a of the roller 7 will not contact the pyramid at the bottom 6a of the groove structure 6 after extending into the groove structure 6, or will not contact the film layer deposited on the pyramid at the bottom 6a of the groove structure 6, such as the second semiconductor layer, to ensure that the teeth 7a of the roller 7 will not scratch the pyramid at the bottom 6a of the groove structure 6, or will not scratch the film layer formed on the pyramid at the bottom 6a of the groove structure 6.

[0108] Exemplarily, h3 is 300 nm, 500 nm, 800 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm or 15000 nm.

[0109] In some examples, 3000nm≤h3≤8000nm.

[0110] In some specific embodiments, the size of the pyramid base of the groove bottom 6a of the semiconductor substrate 1 is in the range of 500nm to 7000nm, and the size of the pyramid height is in the range of 300nm to 6000nm. The size of the pyramid includes the size of the base and the size of the height. The size of the base of the pyramid refers to the maximum size of the bottom of the pyramid along the direction parallel to the first surface, and this maximum size can be the size of the diagonal of the base or the size of the side length of the base; the height of the pyramid refers to the size of the top of the pyramid extending to the base along the direction perpendicular to the first surface.

[0111] It is understandable that, when the distance from the bottom of the pyramid to the surface of the first surface other than the groove structure or to other film layers formed on the semiconductor substrate is constant, the larger the size of the pyramid, the smaller the distance from the top of the pyramid to the surface of the first surface other than the groove structure or to other film layers formed on the semiconductor substrate. That is to say, when actually manufacturing a back contact battery, the distance from the top of the pyramid to the surface of the first surface other than the groove structure or to other film layers formed on the semiconductor substrate is closely related to the size of the pyramid. Considering that if the size of the pyramid is too large, during the cleaning process, after the teeth 7a of the roller 7 extend into the groove structure 6, it is easy to contact the pyramid at the groove bottom 6a of the groove structure 6 or the film layer deposited on the pyramid, and then scratch the pyramid top of the groove bottom 6a of the groove structure 6 or the film layer deposited on the pyramid, so when designing a back contact battery, it is necessary to match the size of the pyramid with the distance from the top of the pyramid to the surface of the first surface other than the groove structure or to other film layers formed on the semiconductor substrate, so as to avoid the roller scratching the pyramid top or the film layer deposited on the pyramid during the cleaning process. In addition, if the size of the pyramid is too small, the surface area of ​​the groove bottom 6a of the groove structure 6 will be reduced, thereby affecting the light trapping effect of the groove structure 6 and the surface area of ​​the film layer deposited on the groove bottom 6a. Therefore, in this technical solution, on the one hand, the base size and the height of the pyramid of the groove bottom 6a of the semiconductor substrate 1 are set within a reasonable range, so that the groove bottom 6a of the groove structure 6 ensures the light trapping effect, while the height of the pyramid of the groove bottom 6a is appropriately reduced, so that the pyramid tip of the groove bottom 6a is further away from, for example, the surface of the first semiconductor layer 2 away from the semiconductor substrate 1; in this way, it can be further ensured that other film layers arranged on the pyramid tip of the groove bottom 6a, such as but not limited to the second semiconductor layer 4 or the transparent conductive layer 8, are also further away from the surface of the first semiconductor layer 2 away from the semiconductor substrate 1, thereby avoiding the situation where the teeth 7a of the roller 7 extend into the groove structure 6 and scratch the second semiconductor layer 4 or the transparent conductive layer 8 located at the groove bottom 6a. Moreover, after the texturing treatment is completed, during the process of cleaning the semiconductor substrate, the teeth 7a of the roller 7 can be prevented from extending into the groove structure 6 and contacting the pyramid of the groove bottom 6a of the groove structure 6, thereby ensuring that the teeth 7a of the roller 7 will not scratch the top of the pyramid of the groove bottom 6a of the groove structure 6.

[0112] Exemplarily, the base size of the pyramid is 500nm, 800nm, 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2200nm, 2500nm, 2800nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, 5500nm, 6000nm, 6500nm or 7000nm, etc. In addition, the tower height is 300nm, 500nm, 800nm, 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2200nm, 2500nm, 2800nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, 5500nm or 6000nm, etc.

[0113] In some examples, the base size of the pyramid is 1000nm to 3500nm, and the height of the pyramid ranges from 300nm to 6000nm.

[0114] like Figure 2As shown, the spacing between adjacent first semiconductor layers 2 is L, 200μm≤L≤800μm. That is, the width of the area not covered by the first semiconductor layer 2 is L, or the maximum width between the side walls of the groove structure 6 is L. On the one hand, if the spacing L between adjacent first semiconductor layers 2 is too small, the width of the second semiconductor layer 4 will be too small, that is, the area of ​​the semiconductor substrate 1 covered by the second semiconductor layer 4 is small, and the size of the area of ​​the semiconductor substrate 1 covered by the second semiconductor layer 4 affects the number of carriers collected by the second semiconductor layer 4. If the spacing L between adjacent first semiconductor layers 2 is too large, that is, the area of ​​the semiconductor substrate 1 covered by the second semiconductor layer 4 is large, the area of ​​the semiconductor substrate 1 covered by the first semiconductor layer 2 is small, and the size of the area of ​​the semiconductor substrate 1 covered by the first semiconductor layer 2 affects the number of carriers collected by the first semiconductor layer 2. Therefore, when setting the spacing between adjacent first semiconductor layers 2, it is necessary to comprehensively consider the area of ​​the semiconductor substrate 1 covered by the first semiconductor layer 2 and the area of ​​the semiconductor substrate 1 covered by the second semiconductor layer 4. On the other hand, the cross-section of the teeth 7a of the roller 7 is generally conical. The wider the notch of the groove structure 6, the longer the length of the teeth 7a of the roller 7 extending into the groove structure 6. In this way, if the spacing L between adjacent first semiconductor layers 2 is too large, the notch of the groove structure 6 is wider, the longer the length of the teeth 7a of the roller 7 extending into the groove structure 6, the smaller the distance between the teeth 7a of the roller 7 and the pyramid tip of the groove bottom 6a, and it is easier to scratch the pyramid at the groove bottom 6a of the groove structure 6, the second semiconductor layer 4 arranged at the groove bottom 6a, or the transparent conductive layer 8 arranged at the groove bottom 6a. Therefore, in order to prevent the roller from scratching the pyramid tip or the film layer deposited on the pyramid during the cleaning process, when designing a back contact battery, it is necessary to match the spacing L between adjacent first semiconductor layers 2 with the distance from the pyramid tip to the surface of the first surface other than the groove structure or to other film layers formed on the semiconductor substrate, so as to prevent the roller from scratching the pyramid tip at the groove bottom or the film layer deposited on the pyramid tip during the cleaning process.

[0115] In view of the above situation, in this technical solution, the spacing L between adjacent first semiconductor layers 2 is set within a reasonable range, so that when the teeth 7a of the roller 7 extend into the groove structure 6, the two side walls of the groove structure 6 can be against the conical teeth 7a to limit the length of the teeth 7a of the roller 7 extending into the groove structure 6, thereby appropriately increasing the distance between the teeth 7a of the roller 7 and the pyramid top of the groove bottom 6a; in this way, it can be further ensured that the distance between the second semiconductor layer 4 arranged at the pyramid top of the groove bottom 6a and the surface of the first semiconductor layer 2 away from the semiconductor substrate 1 is appropriately increased, further avoiding the situation where the teeth 7a of the roller 7 extend into the groove structure 6 and scratch the second semiconductor layer 4 located at the groove bottom 6a. In addition, the spacing L between adjacent first semiconductor layers 2 is set within a reasonable range, so that the teeth 7a of the roller 7 are not easily extended into the groove structure 6 to scratch the pyramid at the bottom 6a of the groove structure 6, the second semiconductor layer 4 arranged at the bottom 6a of the groove, or the transparent conductive layer 8 arranged at the bottom 6a of the groove, while preventing the width of the second semiconductor layer 4 from being too small to affect the collection of carriers by the second semiconductor layer 4.

[0116] For example, the interval L between adjacent first semiconductor layers 2 may be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm or 800 μm.

[0117] In some examples, 350 μm ≤ L ≤ 600 μm.

[0118] In some embodiments, 0.36≤h0 / L≤76.4. It can be understood that if the depth of the groove structure 6 is deeper, the length of the teeth 7a of the roller 7 that are allowed to extend into the groove structure 6 is greater, under the premise of not scratching the pyramid spire of the groove bottom 6a, the second semiconductor layer 4 located on the pyramid spire of the groove bottom 6a, and the transparent conductive layer 8 located on the pyramid spire of the groove bottom 6a. In this way, when the depth of the groove structure 6 is deeper, the notch width of the groove structure 6 can be appropriately increased, and the notch width of the groove structure 6 is approximately equal to the spacing between adjacent first semiconductor layers 2, which is L. Based on this, the embodiment of the present application sets the ratio of h0 / L within a reasonable range to ensure that the teeth 7a of the roller 7 extend into the groove structure 6 without scratching the pyramid spire of the groove bottom 6a, the second semiconductor layer 4 located on the pyramid spire of the groove bottom 6a, and the transparent conductive layer 8 located on the pyramid spire of the groove bottom 6a, and increase the width of the second semiconductor layer 4, thereby improving the collection efficiency of the second semiconductor layer 4 for carriers.

[0119] Illustratively, h0 / L can be 0.36, 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, or 76.4.

[0120] like Figure 2 As shown, the width of the groove bottom 6a of the groove structure 6 is L1, 170μm≤L1≤790μm. It can be understood that the spacing L between adjacent first semiconductor layers is related to the width L1 of the groove bottom of the groove structure 6. The width L1 of the groove bottom of the groove structure 6 increases, and the spacing L between adjacent first semiconductor layers increases. When designing a back contact battery, on the one hand, if the width L1 of the groove bottom 6a of the groove structure 6 is too small, the width of the second semiconductor layer 4 will be too small, that is, the area covered by the second semiconductor layer 4 on the semiconductor substrate 1 is small, which affects the number of carriers collected by the second semiconductor layer 4; on the other hand, if the width L1 of the groove bottom 6a of the groove structure 6 is too wide, that is, the area covered by the second semiconductor layer 4 on the semiconductor substrate 1 is large, then the area covered by the first semiconductor layer 2 on the semiconductor substrate 1 is small, and the size of the area covered by the first semiconductor layer 2 on the semiconductor substrate 1 affects the number of carriers collected by the first semiconductor layer 2. Therefore, when setting the width of the groove bottom 6a of the groove structure 6, it is necessary to comprehensively consider the area covered by the first semiconductor layer 2 on the semiconductor substrate 1 and the area covered by the second semiconductor layer 4 on the semiconductor substrate 1. In addition, if the width L1 of the groove bottom 6a of the groove structure 6 is too wide, the groove opening of the groove structure 6 will also be wider, and the teeth 7a of the roller 7 will be more likely to extend into the groove structure 6 through the groove opening, and it will be easier to scratch the pyramid at the groove bottom 6a of the groove structure 6, the second semiconductor layer 4 disposed at the groove bottom 6a, or the transparent conductive layer 8 disposed at the groove bottom 6a. In view of the above situation, in this technical solution, the width L1 of the groove bottom 6a of the groove structure 6 is set within a reasonable range, so that the teeth 7a of the roller 7 are not likely to extend into the groove structure 6 to scratch the pyramid at the groove bottom 6a of the groove structure 6, the second semiconductor layer 4 disposed at the groove bottom 6a, or the transparent conductive layer 8 disposed at the groove bottom 6a, and at the same time, the width of the second semiconductor layer 4 is prevented from being too small, which affects the collection of carriers by the second semiconductor layer 4.

[0121] Exemplarily, the width L1 of the groove bottom 6a of the groove structure 6 is 170μm, 180μm, 200μm, 230μm, 250μm, 280μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, 520μm, 550μm, 580μm, 600μm, 620μm, 650μm, 690μm, 700μm, 720μm, 750μm or 790μm, etc. Optionally, the width L1 of the groove bottom 6a of the groove structure 6 is 320μm to 590μm.

[0122] In some embodiments, Figure 2As shown, the side wall of the groove structure 6 includes an inclined surface 6b, and along the direction away from the middle area of ​​the groove bottom 6a, the inclined surface 6b is inclined in the direction away from the second surface. It should be noted that in this solution, from the bottom to the top of the inclined surface 6b, the extension direction of the inclined surface 6b is roughly a straight line, and the inclined surface 6b is not concave in the direction close to the second surface. Such a configuration is beneficial to making the height transition trend from the bottom 6a of the groove structure 6 with a lower surface to the area with a higher surface for forming the first semiconductor layer 2 in the first surface of the semiconductor substrate 1 relatively gentle, so that when the second semiconductor layer 4 is formed, the second semiconductor layer 4 is better coated on the side wall of the groove structure 6, preventing the second semiconductor layer 4 from having unfilled gaps at the side wall of the groove structure 6 with a surface height difference, reducing the number of defects located on the first surface side of the back contact battery, and also helping to improve the formation quality of the second semiconductor layer 4 at the side wall of the groove structure 6, thereby improving the field passivation effect of the formation quality of the second semiconductor layer 4 at the side wall of the groove structure 6, reducing the carrier recombination rate here, and helping to improve the photoelectric conversion line efficiency of the back contact battery.

[0123] Wherein, the width of the inclined surface 6b is L2, 5μm≤L2≤15μm. Since the inclined surface 6b is higher than the groove bottom 6a, if the width L2 of the inclined surface 6b is too wide, the teeth 7a of the roller 7 will easily scratch the inclined surface 6b or the film layer deposited on the inclined surface 6b after extending into the groove structure 6; if the width L2 of the inclined surface 6b is too narrow, the height difference and height change trend of the inclined surface 6b remain unchanged, resulting in a large inclination angle of the inclined surface 6b. In the process of forming the second semiconductor layer 4, a gap is easily formed between the second semiconductor layer 4 and the inclined surface 6b, which increases the number of defects in the second semiconductor layer 4 formed at the inclined surface 6b. In view of the above situation, in the present technical solution, the width L2 of the inclined surface 6b is set within a reasonable range to prevent the teeth 7a of the roller 7 from scratching the inclined surface 6b or the film layer deposited on the inclined surface 6b after extending into the groove structure 6, while ensuring that the formation quality of the second semiconductor layer 4 at the side wall of the groove structure 6 is improved, thereby improving the carrier collection efficiency of the second semiconductor layer 4.

[0124] Illustratively, the width L2 of the inclined surface 6 b is 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm.

[0125] In some embodiments, the sidewall of the groove structure also includes a platform, and the platform is located on the side of the inclined surface 6b away from the groove bottom 6a. And the sidewall of the groove structure 6 also includes a vertical surface extending in a direction perpendicular to the first surface, and the vertical surface is located on the side of the platform away from the semiconductor substrate 1. The surface of the above-mentioned platform is a polished surface, and the platform can be arranged parallel to the second surface or inclined relative to the second surface. With this technical solution, the arrangement of the platform can increase the spacing L between adjacent first semiconductor layers 2, which is conducive to increasing the width of the second semiconductor layer 4, thereby increasing the collection efficiency of the second semiconductor layer 4 for carriers.

[0126] Along the width direction of the groove structure 6, the width of the platform can be greater than or equal to 100nm and less than or equal to 600nm. For example, the width of the platform can be 100nm, 200nm, 300nm, 400nm, 500nm or 600nm, etc. In the actual manufacturing process, after the first semiconductor layer 2 is formed as a whole layer on the first surface, it is necessary to pattern the first semiconductor layer 2 under the masking action of the mask layer 9. Then, under the masking action of the mask layer 9, the portion of the semiconductor substrate 1 exposed outside the mask layer 9 is etched to form the above-mentioned groove structure 6. Among them, when etching the semiconductor substrate 1, the etchant can not only etch the portion of the semiconductor substrate 1 exposed outside the masking action along the thickness direction of the semiconductor substrate 1, but also have a certain etching effect on the first semiconductor layer 2 and the portion of the semiconductor substrate 1 located below the edge area of ​​the mask layer 9 along the direction parallel to the second surface, thereby forming the above-mentioned groove structure 6 under the partial isotropic etching action of the etchant, realizing the platform in the groove structure 6, and lower than the first surface. The formation of the above-mentioned platform is conducive to a smoother transition trend of the second semiconductor layer 4 in the area where the inclined surface 6b and the vertical surface meet, preventing the second semiconductor layer 4 from having defects such as gaps in the area where the inclined surface 6b and the vertical surface meet, i.e., the platform area, thereby improving the formation quality of the area where the inclined surface 6b and the vertical surface meet, i.e., the platform area.

[0127] In some embodiments, Figure 2 as well as Figure 4a-Figure 6 As shown, the inclined surface 6b includes a pyramid-shaped velvet surface, and the size of the pyramid located on the inclined surface 6b is larger than the size of the pyramid located at the groove bottom 6a. In this case, it can be understood that, within the same range, the number of pyramids formed on the surface of the region with a larger pyramid size is relatively small, which is conducive to reducing the roughness of the surface of the region. Based on this, when the size of the pyramid formed on the inclined surface 6b is larger than the pyramid formed on the groove bottom 6a of the groove structure 6, it is conducive to reducing the roughness of the inclined surface 6b, improving the formation quality of the second semiconductor layer 4 on the inclined surface 6b, and improving the field passivation effect of the second semiconductor layer 4 on the inclined surface 6b.

[0128] It should be noted that the size of the pyramids at the bottom of the groove 6a is uniform, while the size of the pyramids at the inclined surface 6b is uneven. The pyramids located at the inclined surface 6b include the pyramids located at the inclined surface and at the junction of the non-inclined surface and the bottom of the groove, that is, the pyramids located at the inclined surface far from the bottom of the groove, and also include the pyramids located at the junction of the inclined surface and the bottom of the groove.

[0129] It is understandable that Figure 4a-Figure 6 As shown, a part of the inclined surface 6b forms a complete pyramid-shaped velvet surface, and a part of the inclined surface 6b can also form an incomplete pyramid-shaped velvet surface, and the incomplete pyramid-shaped velvet surface can be, for example, a quasi-triangular prism structure. Based on this, when other factors are the same, the surface area of ​​the quasi-triangular prism structure is larger than that of the plane morphology. Therefore, when at least part of the surface of the inclined surface 6b forms a quasi-triangular prism structure, it is beneficial for the inclined surface 6b to have a good light trapping effect, further improving the utilization rate of light by the back contact battery. In addition, when other factors are the same, the surface of the quasi-triangular prism structure is lower in roughness than the surface of the pyramid-shaped velvet morphology, and its surface is relatively smooth, which is beneficial to improve the coating effect of the second semiconductor layer 4 on the inclined surface 6b. Of course, in addition to the complete pyramid-shaped velvet surface and the incomplete pyramid-shaped velvet surface formed on the inclined surface 6b, other structures may also be formed, such as a raised strip structure. For a structure without a pyramid spire and in a strip shape, it can be considered as a raised strip structure. The present application does not limit the size of the raised strip structure.

[0130] In some embodiments, Figure 4a and Figure 4b As shown in FIG. 1 , the height of the pyramid located on the inclined surface 6b and at the junction of the non-inclined surface and the bottom of the groove ranges from 50nm to 3000nm, and the size of the base is from 2000nm to 8000nm. The pyramid on the inclined surface 6b includes a first side surface and a second side surface, wherein the first side surface is substantially parallel to the inclined surface 6b, and the second side surface intersects the inclined surface 6b. The height of the pyramid on the inclined surface 6b refers to the distance a between the top of the pyramid and the plane passing through the bottom of the second side surface and parallel to the second surface, that is, Figure 4a and Figure 4b The base size of the pyramid on the inclined surface 6b refers to the distance b from the bottom of the second side extending to the first side in a direction parallel to the second surface, that is, as Figure 4a and Figure 4b The horizontal dotted line part.

[0131] Considering that if the size of the pyramid on the inclined surface 6b is too large, the teeth 7a of the roller 7 will easily contact the pyramid on the inclined surface 6b after extending into the groove structure 6 during the cleaning process, thereby scratching the pyramid on the inclined surface 6b or the film layer deposited on the pyramid on the inclined surface; therefore, when designing a back-contact battery, it is necessary to make the size of the pyramid located on the inclined surface 6b and at the junction of the non-inclined surface and the groove bottom consistent with the width L2 of the inclined surface, the width L1 of the groove bottom of the groove structure, and the surface of the second semiconductor layer 4 at the top of the pyramid at the groove bottom arranged along the thickness direction of the semiconductor substrate 1 away from the semiconductor substrate 1 The distance h0 between the surface of the first semiconductor layer 2 and the surface away from the semiconductor substrate, the distance h2 between the pyramid top of the groove bottom 6a of the groove structure 6 of the semiconductor substrate and the surface of the first semiconductor layer 2 away from the semiconductor substrate 1, and the distance h3 between the pyramid top of the groove bottom of the semiconductor substrate and the surface of the first surface other than the groove structure 6, that is, the size of the pyramid located on the inclined surface 6b and at the junction of the non-inclined surface and the groove bottom needs to match the above L1, L2, h0, h2 and h3, so as to avoid the roller scratching the pyramid top on the inclined surface 6b or the film layer deposited on the pyramid during the cleaning process. For example, when h3 is larger, the size of the pyramid on the inclined surface 6b can be set larger; when h3 is smaller, the size of the pyramid on the inclined surface 6b can be set smaller; when L1 is larger, the size of the pyramid on the inclined surface 6b can be set smaller.

[0132] On the other hand, if the size of the pyramid on the inclined surface is too small, it is not conducive to reducing the roughness of the surface of the inclined surface 6b, which may affect the formation quality of the second semiconductor layer 4 on the inclined surface 6b. In view of the above situation, the height and base size of the pyramid on the inclined surface 6b are set within a reasonable range, which can prevent the teeth 7a of the roller 7 from contacting the pyramid on the inclined surface 6b after extending into the groove structure 6, thereby ensuring that the teeth 7a of the roller 7 will not scratch the pyramid on the inclined surface 6b or the film layer deposited on the pyramid, and at the same time, it is conducive to reducing the roughness of the surface of the inclined surface 6b and improving the formation quality of the second semiconductor layer 4 on the inclined surface 6b.

[0133] For example, the height of the pyramid located on the inclined surface 6b and at the junction of the non-inclined surface 6b and the groove bottom 6a is 50nm, 100nm, 150nm, 200nm, 500nm, 800nm, 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2200nm, 2500nm, 2800nm ​​or 3000nm. The base size of the pyramid located on the inclined surface 6b and at the junction of the non-inclined surface 6b and the groove bottom 6a is 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, 5500nm, 6000nm, 6500nm, 7000nm, 7500nm or 8000nm.

[0134] In some examples, the pyramid located on the inclined surface 6 b and at the junction of the non-inclined surface 6 b and the groove bottom 6 a has a height of 100 nm to 2000 nm, and a base of 100 nm to 2000 nm.

[0135] In other embodiments, Figure 6 , the intersection of the inclined surface 6b and the groove bottom 6a is the side of the dotted line close to the first semiconductor layer 2, located on the inclined surface 6b, and the pyramid located at the intersection of the inclined surface 6b and the groove bottom 6a has a tower height range of 1000nm to 9000nm, and a tower base size of 1000nm to 9000nm. In this case, compared with the non-intersection position of the inclined surface 6b and the groove bottom 6a, the intersection of the inclined surface 6b and the groove bottom 6a is farther away from the tooth 7a extending into the groove structure 6, so the size of the pyramid at the intersection of the inclined surface 6b and the groove bottom 6a can be appropriately increased, so that the size of the pyramid at the intersection of the inclined surface 6b and the groove bottom 6a is greater than the size of the pyramid located on the inclined surface 6b, which is conducive to reducing the roughness of the intersection of the inclined surface 6b and the groove bottom 6a, thereby improving the formation quality of the second semiconductor layer 4 at this position.

[0136] Exemplarily, the height of the pyramid located on the inclined surface 6b and at the junction of the inclined surface 6b and the groove bottom 6a is 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2200nm, 2500nm, 2800nm, 3000nm, 4000nm, 4500nm, 5000nm, 5500nm, 6000nm, 6500nm, 7000nm, 7500nm, 8000nm, 8500nm or 9000nm. The tower base size is 1000nm, 1200nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, 5500nm, 6000nm, 6500nm, 7000nm, 7500nm, 8000nm, 8500nm or 9000nm.

[0137] In some examples, the pyramid located on the inclined surface 6 b and at the junction of the inclined surface 6 b and the groove bottom 6 a has a height of 1500 nm to 5000 nm, and a base of 1500 nm to 5000 nm.

[0138] like Figure 7 As shown, in other embodiments, the pyramid tip of the groove bottom 6a of the semiconductor substrate 1 is in an arc shape. In this case, compared with the pyramid with a pointed tip, the height of the pyramid with an arc-shaped tip is appropriately reduced, thereby increasing the distance between the pyramid tip of the groove bottom 6a and the surface of the first semiconductor layer 2 that is away from the semiconductor substrate 1, and also increasing the distance between the second semiconductor layer 4 located at the pyramid tip of the groove bottom 6a and the surface of the first semiconductor layer 2 that is away from the semiconductor substrate 1, further reducing the probability that the teeth 7a of the roller 7 extend into the groove structure 6 and scratch the pyramid of the groove bottom 6a of the groove structure 6, the second semiconductor layer 4 arranged at the groove bottom 6a, or the transparent conductive layer 8 arranged at the groove bottom 6a. In addition, the pyramid tip of the groove bottom 6a of the semiconductor substrate 1 is in an arc shape, which can appropriately increase the contact area between the pyramid tip and the second semiconductor layer 4, which is conducive to improving the deposition quality of the second semiconductor layer 4 at the pyramid tip, reducing the formation defects of the second semiconductor layer 4, and improving the passivation effect.

[0139] In some embodiments, the radius of curvature of the arc-shaped pyramid tip is 70 nm to 150 nm.

[0140] In some embodiments, the arc angle of the arc-shaped pyramid spire ranges from 30° to 150°.

[0141] It is understandable that, on the one hand, if the curvature radius and curvature range of the arc-shaped pyramid spire are too large, part of the light irradiated to the arc-shaped pyramid spire cannot be refracted into the semiconductor substrate 1 and utilized, affecting the light trapping effect of the groove structure 6; if the curvature radius and curvature range of the arc-shaped pyramid spire are too small, the purpose of appropriately reducing the height of the pyramid cannot be achieved. Based on this, setting the curvature radius and curvature range of the arc-shaped pyramid spire within a suitable range can not only appropriately reduce the height of the pyramid, thereby reducing the situation where the pyramid at the groove bottom 6a is scratched, but also ensure the light trapping effect of the groove structure 6.

[0142] Exemplarily, the curvature radius of the top of the pyramid with an arc-shaped spire is 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm or 150nm, and can be 100nm to 110nm. The curvature range of the top of the pyramid with an arc-shaped spire is 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140° or 150°.

[0143] In some embodiments, the surface of the semiconductor substrate 1 other than the groove structure 6 may be a polished surface or may be formed with a texture structure. In the case where the surface of the semiconductor substrate 1 other than the groove structure 6 is formed with a texture structure, the texture structure is square, specifically, it may be roughly in the shape of a tower base, which may be convexly arranged along the direction from the second surface to the first surface, or may be concavely arranged along the direction from the second surface to the first surface. In this case, it is beneficial to increase the specific surface area of ​​the semiconductor substrate 1 other than the groove structure 6. Secondly, the first semiconductor layer 2 formed on the semiconductor substrate 1 other than the groove structure 6 has a side facing away from the semiconductor substrate 1 with substantially the same undulating features as the surface of the semiconductor substrate 1 other than the groove structure 6. Therefore, in the case where the semiconductor substrate 1 other than the groove structure 6 has a larger specific surface area, it is also beneficial to increase the specific surface area of ​​the first semiconductor layer 2 on the side facing away from the semiconductor substrate 1, thereby increasing the contact area between the first semiconductor layer 2 and the corresponding electrode, and reducing the contact resistance. At the same time, compared with the pyramid-shaped texture structure, when the texture structure on the surface of the semiconductor substrate 1 except the groove structure 6 is square, it is beneficial to make the surface of the semiconductor substrate 1 except the groove structure 6 have a relatively low surface roughness, which is beneficial to improving the formation quality of the above-mentioned first semiconductor layer 2 and ensuring that the first semiconductor layer 2 has a higher carrier collection ability and passivation effect.

[0144] In terms of conductivity type, the conductivity type of the first semiconductor layer 2 can be N-type, in which case the conductivity type of the second semiconductor layer 4 is P-type; or the conductivity type of the first semiconductor layer 2 can also be P-type, in which case the conductivity type of the second semiconductor layer 4 is N-type.

[0145] In addition, the materials of the first semiconductor layer 2 and the second semiconductor layer 4 may be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs), etc. Taking the case where the materials of the first semiconductor layer 2 and the second semiconductor layer 4 are both silicon (Si) as an example, the second semiconductor layer 4 may include one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. In this case, especially when the second semiconductor layer 4 is doped amorphous silicon, the second semiconductor layer 4 is more easily scratched. The second semiconductor layer 4 is used for passivation and carrier collection, and scratching has a greater impact on the passivation effect and carrier collection effect; and when the second semiconductor layer 4 is doped polycrystalline silicon, for example, when the back contact battery is a TBC (Tunnel Oxide Passivated Contact Back Contact) battery, the second semiconductor layer 4 has a passivation layer on the side away from the semiconductor substrate, and the passivation layer can play a passivation role. At this time, the second semiconductor layer 4 has a small impact on the passivation performance of the solar cell after being scratched, and the isolation groove of the TBC battery has an insulating material, which can passivate the isolation groove, so the insulating material has a small impact on the performance of the solar cell after being scratched. In view of the above situation, when the second semiconductor layer 4 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, it is necessary to avoid the second semiconductor layer 4 located at the bottom 6a of the groove structure 6 from being scratched by the teeth 7a of the roller 7 extending into the groove structure 6 to ensure that the performance of the back contact battery is not affected.

[0146] In addition, the first semiconductor layer 2 can be doped polysilicon. In this case, the doped polysilicon layer has higher carrier transport characteristics. Therefore, when the first semiconductor layer 2 is a doped polysilicon layer, the carrier transport efficiency is higher, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. Of course, the first semiconductor layer 2 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The first semiconductor layer 2 can be additionally formed on the semiconductor substrate 1 by deposition technology, and can also be formed in the semiconductor substrate 1 by diffusion, ion implantation, etc.

[0147] like Figure 2As shown, in some embodiments, the above-mentioned back contact battery may further include a first passivation layer 3, which is located between the first semiconductor layer 2 and the semiconductor substrate 1. The projection of the first passivation layer 3 on the semiconductor substrate 1 may overlap with the projection of the first semiconductor layer 2 on the semiconductor substrate 1. In this case, the passivation contact structure composed of the first passivation layer 3 and the first semiconductor layer 2 has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate in the area where the first semiconductor layer 2 is formed on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the back contact battery. The material and thickness of the first passivation layer 3 can be set according to the material of the first semiconductor layer 2 and actual needs, and are not specifically limited here.

[0148] The material of the first passivation layer 3 can be determined according to the material of the first semiconductor layer 2. For example, when the first semiconductor layer 2 includes a doped polycrystalline silicon layer, the first passivation layer 3 is a tunneling oxide layer. For another example, when the first semiconductor layer 2 includes at least one of a doped amorphous silicon layer, a doped nanocrystalline silicon layer, and a doped microcrystalline silicon layer, the first passivation layer 3 includes an intrinsic amorphous silicon layer. Secondly, the embodiment of the present invention does not specifically limit the material of the first passivation layer 3.

[0149] like Figure 2 As shown, in some embodiments, the above-mentioned back contact battery may further include a second passivation layer 5, which is located between the second semiconductor layer 4 and the semiconductor substrate 1. The projection of the second passivation layer 5 on the semiconductor substrate 1 may overlap with the projection of the second semiconductor layer 4 on the semiconductor substrate 1. In this case, the passivation contact structure composed of the second passivation layer 5 and the second semiconductor layer 4 can realize the selective collection of carriers and reduce the carrier recombination rate in the area where the second semiconductor layer 4 is formed on the first surface of the semiconductor substrate 1. The material and thickness of the second passivation layer 5 can be set according to the material of the second semiconductor layer 4 and actual needs, and are not specifically limited here. For example: when the material of the second semiconductor layer 4 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second passivation layer 5 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer.

[0150] As for the thickness of the second passivation layer 5, since the thickness of the second passivation layer 5 will affect its own transmission resistance and passivation effect, and further affect the forward leakage loss and reverse breakdown voltage of the back contact battery, the thickness of the second passivation layer 5 can be determined according to the requirements of the forward leakage loss and reverse breakdown voltage of the back contact battery in the actual application scenario, and no specific limitation is made here.

[0151] In other embodiments, the back contact battery further includes a transparent conductive layer 8, which is disposed on the side of the first semiconductor layer 2 and the second semiconductor layer 4 away from the semiconductor substrate 1, and the transparent conductive layer 8 is provided with an opening 8a that runs through the thickness thereof, and the opening 8a disconnects the transparent conductive layer 8 on the first semiconductor layer 2 and the transparent conductive layer 8 on the second semiconductor layer 4 from each other. The transparent conductive layer 8 has a high electrical conductivity, and can timely conduct the collected carriers to reduce the carrier recombination rate, and the transparent conductive layer 8 can reduce the contact resistance between the first semiconductor layer 2 and the second semiconductor layer 4 and the electrode.

[0152] Among them, Figure 8 As shown, the orthographic projection of the opening 8a penetrating the transparent conductive layer 8 on the first surface is located inside the orthographic projection of the portion of the second semiconductor layer 4 extending onto the first semiconductor layer 2 on the first surface, so that the second semiconductor layer 4 can be prevented from being electrically connected to the first semiconductor layer 2 through the transparent conductive layer 8, thereby preventing leakage. In addition, it can also ensure that the carriers collected in the portion of the second semiconductor layer 4 located in the groove structure 6 can be transmitted to the electrode in contact with the first semiconductor layer 2 through the transparent conductive layer 8, thereby improving the conversion efficiency of the battery.

[0153] Or, if Fig. 9 As shown, along the width direction of the opening 8a, the orthographic projection of the opening 8a on the first surface partially overlaps with the orthographic projection of the portion of the second semiconductor layer 4 extending onto the first semiconductor layer 2 on the first surface, and partially overlaps with the orthographic projection of the portion of the first semiconductor layer 2 not covered by the second semiconductor layer 4 on the first surface. In this way, the second semiconductor layer 4 can be prevented from being electrically connected to the first semiconductor layer 2 through the transparent conductive layer 8, thereby preventing leakage.

[0154] Or, if Fig.10 As shown, along the width direction of the opening 8a, the orthographic projection of the opening 8a on the first surface partially overlaps with the orthographic projection of the portion of the second semiconductor layer 4 extending onto the first semiconductor layer 2 on the first surface, and partially overlaps with the orthographic projection of the portion of the second semiconductor layer 4 covering the inclined surface 6b or the groove bottom 6a on the first surface. In this way, the second semiconductor layer 4 can be prevented from being electrically connected to the first semiconductor layer 2 through the transparent conductive layer 8, thereby preventing leakage.

[0155] Or, if Fig.11 As shown, along the width direction of the opening 8a, the orthographic projection of the opening 8a on the first surface partially overlaps with the orthographic projection of the portion of the first semiconductor layer 2 not covered by the second semiconductor layer 4 on the first surface, and partially overlaps with the orthographic projection of the portion of the second semiconductor layer 4 covering the inclined surface 6b or the groove bottom 6a on the first surface. In this way, the width of the opening 8a is large, and the distance between the transparent conductive layers 8 located on both sides of the opening 8a is large, which further avoids the second semiconductor layer 4 and the first semiconductor layer 2 from contacting and producing recombination.

[0156] In the above technical solution, along the thickness direction of the semiconductor substrate 1, the distance between the surface of the transparent conductive layer 8 disposed on the pyramid top of the groove bottom 6a away from the semiconductor substrate 1 and the surface of the transparent conductive layer 8 disposed on the first semiconductor layer 2 away from the semiconductor substrate 1 is greater than or equal to 316nm, and less than or equal to 15385nm. Here, "the transparent conductive layer 8 disposed on the first semiconductor layer 2" may refer to being disposed only on the first semiconductor layer 2, or may refer to being disposed on the overlapping area of ​​the first semiconductor layer 2 and the second semiconductor layer 4. In this case, after the transparent conductive layer 8 is formed, if the distance between the surface of the transparent conductive layer 8 disposed on the pyramid top of the groove bottom 6a away from the semiconductor substrate 1 and the surface of the transparent conductive layer 8 disposed on the first semiconductor layer 2 away from the semiconductor substrate 1 is too small, then during the cleaning process, after the teeth 7a of the roller 7 extend into the groove structure 6, it is easy to contact the transparent conductive layer 8 on the pyramid top of the groove bottom 6a of the groove structure 6 and scratch the transparent conductive layer 8 on the pyramid top. Therefore, when designing a back-contact battery, it is necessary to make the distance between the surface of the transparent conductive layer 8 arranged on the pyramid top at the groove bottom 6a facing away from the semiconductor substrate 1 and the surface of the transparent conductive layer 8 arranged on the first semiconductor layer 2 facing away from the semiconductor substrate 1 match, the distance between the surface of the second semiconductor layer 4 arranged on the pyramid top at the groove bottom 6a facing away from the semiconductor substrate 1 and the surface of the second semiconductor layer 4 covering the first semiconductor layer 2 facing away from the semiconductor substrate 1 is h1, and the spacing L between adjacent first semiconductor layers 2, so as to ensure that during the cleaning process of the semiconductor substrate 1, after the teeth 7a of the roller 7 extend into the groove structure 6, they will not contact the transparent conductive layer 8 located at the groove bottom 6a of the groove structure 6, thereby preventing the teeth 7a of the roller 7 from scratching the transparent conductive layer 8 on the pyramid top at the groove bottom 6a of the groove structure 6.

[0157] Exemplarily, the distance between the surface of the transparent conductive layer 8 at the top of the pyramid at the bottom of the groove 6a that is away from the semiconductor substrate 1 and the surface of the transparent conductive layer 8 arranged on the first semiconductor layer 2 that is away from the semiconductor substrate 1 is 316nm, 1000nm, 2000nm, 3000nm, 4000nm, 5000nm, 6000nm, 7000nm, 8000nm, 9000nm, 10000nm, 11000nm, 12000nm, 13000nm, 14000nm, 15000nm or 15385nm, optionally, it can be 3016nm to 8385nm.

[0158] In addition, the material of the transparent conductive layer 8 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide.

[0159] In some embodiments, the thickness of the second semiconductor layer 4 located at the groove bottom 6a of the groove structure 6 is less than the thickness of the second semiconductor layer 4 located at the sidewall of the groove structure 6 and / or covered on the first semiconductor layer 2. In this way, the thickness of the second semiconductor layer 4 covered on the first semiconductor layer 2 is relatively large, and when the second semiconductor layer 4 covered on the first semiconductor layer 2 supports the roller 7, the teeth 7a on the roller 7 can be further away from the second semiconductor layer 4 at the groove bottom 6a of the groove structure 6 or the transparent conductive layer 8 disposed on the second semiconductor layer 4; at the same time, the thickness of the second semiconductor layer 4 located at the groove bottom 6a of the groove structure 6 is relatively small, and the second semiconductor layer 4 located at the groove bottom 6a of the groove structure 6 or the transparent conductive layer 8 disposed on the second semiconductor layer 4 can also be further away from the teeth 7a on the roller 7. From the above, it can be known that when the thickness of the second semiconductor layer 4 located at the groove bottom 6a of the groove structure 6 is less than the thickness of the second semiconductor layer 4 covering the first semiconductor layer 2, the distance between the teeth 7a on the roller 7 and the second semiconductor layer 4 at the groove bottom 6a of the groove structure 6 or the transparent conductive layer 8 arranged on the second semiconductor layer 4 is further increased, thereby further reducing the situation in which the teeth 7a of the roller 7 extend into the groove structure 6 and scratch the second semiconductor layer 4 located at the groove bottom 6a or the transparent conductive layer 8 arranged on the second semiconductor layer 4.

[0160] In each of the above embodiments, the back contact cell may further include a passivation layer and an anti-reflection layer disposed on the second surface, and the passivation layer on the second surface is located between the second surface of the semiconductor substrate 1 and the anti-reflection layer. Among them, the function of the passivation layer on the second surface is to passivate the surface defects of the semiconductor substrate and reduce recombination. For example, the silicon-oxygen hanging bonds on the front of the crystalline silicon substrate layer may be passivated by field passivation or by chemical bond connection. The function of the anti-reflection layer is to block the light reflected from the upper surface of the crystalline silicon by regulating the material and thickness of the anti-reflection layer. The material type of the second surface passivation layer is not particularly limited, for example, including but not limited to a-Si, polycrystalline silicon, microcrystalline silicon, silicon oxide, etc. The material of the anti-reflection layer includes but is not limited to silicon nitride material.

[0161] The present invention provides a method for manufacturing a back contact battery. Figures 12 to 16 The manufacturing process is described in detail with reference to the cross-sectional view of the operation shown in FIG. 1 . Specifically, the manufacturing method of the back contact battery includes the following steps:

[0162] S1: Provide a semiconductor substrate 1, wherein the semiconductor substrate 1 has a first surface and a second surface opposite to each other. The first surface has first regions and second regions that are alternately distributed. The first region is used to form a first semiconductor layer 2, and the second region is used to form a groove structure 6.

[0163] Before this step, in some embodiments, the semiconductor substrate 1 can also be placed in a polishing and cleaning machine to remove the cut damage layer of the semiconductor substrate 1 using a polishing liquid. In addition, in this step, the morphology of the first surface and the second surface of the semiconductor substrate 1 after polishing and cleaning can be adjusted by adjusting parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step can be omitted.

[0164] S2: forming a first semiconductor layer 2 on the first surface.

[0165] In the actual manufacturing process, in some examples, such as Fig.12 As shown, a first semiconductor layer 2 arranged in an entire layer may be formed on the first surface first, and then, as shown in FIG. Fig.13 As shown, a mask layer 9 is formed on the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1, and then Fig.14 As shown, the mask layer 9 is selectively etched to remove the portion of the mask layer 9 corresponding to the second region, and retain the portion of the mask layer 9 corresponding to the first region; then, the first semiconductor layer 2 is selectively etched to remove the portion of the first semiconductor layer 2 corresponding to the second region, and retain the portion of the first semiconductor layer 2 corresponding to the first region, thereby completing the patterning of the first semiconductor layer 2.

[0166] It should be noted that, in the case where the back contact battery also includes a first passivation layer 3, in this step, before forming the first semiconductor layer 2, deposition and etching processes may be used to form a first passivation layer 3 that only covers the first region; or, a first passivation layer 3 that is set as a whole layer may be formed on the first surface first, and then a first semiconductor layer 2 that is set as a whole layer may be formed. Then, a mask layer 9 is formed, and under the masking effect of the mask layer 9, laser etching or wet chemical process or other etching methods are used to remove the first semiconductor layer 2 and the first passivation layer 3 corresponding to the second region, and retain the first semiconductor layer 2 and the first passivation layer 3 corresponding to the first region. Of course, after forming the mask layer 9, the mask layer 9, the first semiconductor layer 2 and the first passivation layer 3 located in the second region may be removed simultaneously by the laser process.

[0167] In this step, the first semiconductor layer 2 and the first passivation layer 3 can be realized by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), etc. When the first passivation layer 3 is an oxide tunneling layer, the oxide tunneling layer can be formed by the above-mentioned method, and can also be generated by a high-temperature reaction of oxygen with the first surface of the semiconductor substrate 1, or the oxide tunneling layer can also be generated by a wet chemical method, such as the reaction of silicon with ozone, the oxidation reaction of silicon with nitric acid, etc. to generate the oxide tunneling layer.

[0168] It should be noted that the material of the first passivation layer 3 can be referred to above and will not be described in detail here.

[0169] The thickness of the first passivation layer 3 may be 1 nm to 4 nm, for example, 1 nm, 1.4 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, etc.

[0170] The mask layer 9 may be formed, for example, by LPCVD or PECVD. In some examples, the material of the mask layer 9 may include silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbide, or intrinsic silicon.

[0171] S3: Etching the first semiconductor layer 2 located in the second area, and performing texturing treatment on the portion of the semiconductor substrate 1 located in the second area; after the texturing treatment, the portion of the semiconductor substrate 1 corresponding to the second area is concave along the direction from the second surface to the first surface relative to the first area in the direction of the second surface, forming a groove structure 6, and the bottom of the groove structure 6 is a pyramid-shaped texturing surface.

[0172] Next, if Fig.15 and Fig.16As shown, the portion of the semiconductor substrate 1 corresponding to the second region is selectively etched to remove the first semiconductor layer 2 located in the second region and expose the semiconductor substrate 1 located in the second region. Then, the portion of the semiconductor substrate 1 located in the second region is subjected to a texturing treatment so that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming a groove structure 6. In the actual manufacturing process, the portion of the semiconductor substrate 1 corresponding to the second region can be texturized by a texturing liquid under the masking action of the mask layer 9 so that while forming the velvet surface, the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming a groove structure 6. The texturing liquid is used for texturing so that the groove bottom 6a of the groove structure 6 is a pyramid-shaped velvet surface, and at least a part of the inclined surface 6b of the groove structure 6 is also formed with a pyramid-shaped velvet surface, and the size of the pyramid located on the inclined surface 6b is larger than the size of the pyramid located on the groove bottom 6a, so as to reduce the roughness of the inclined surface 6b, improve the formation quality of the second semiconductor layer 4 on the inclined surface 6b, and improve the field passivation effect of the second semiconductor layer 4 on the inclined surface 6b.

[0173] Among them, during the texturing process, the texturing liquid can not only etch the portion of the semiconductor substrate 1 exposed outside the mask effect along the thickness direction of the semiconductor substrate 1, but also has a certain etching effect on the first semiconductor layer 2 and the portion of the semiconductor substrate 1 located below the edge area of ​​the mask layer 9 along the direction parallel to the second surface, thereby forming the above-mentioned groove structure 6 under the isotropic etching action of the texturing liquid, and the side wall of the groove structure 6 includes a platform and an inclined surface 6b.

[0174] S4: forming a second semiconductor layer 4 on the first surface, and removing a portion of the second semiconductor layer 4 to expose the first semiconductor layer 2; the second semiconductor layer 4 and the first semiconductor layer 2 have opposite conductivity types;

[0175] Then, a second semiconductor layer 4 is formed on the first surface of the entire semiconductor substrate 1, and then a portion of the second semiconductor layer 4 is removed by a laser process or a wet etching process to expose the first semiconductor layer 2. The first semiconductor layer 2 may be exposed in its entirety or in part. In some embodiments, a portion of the second semiconductor layer 4 extends to a side of the first semiconductor layer 2 that is away from the semiconductor substrate 1. The second semiconductor layer 4 and the first semiconductor layer 2 have opposite conductivity types.

[0176] In the actual manufacturing process, chemical vapor deposition and doping processes can be used to form the second semiconductor layer 4 disposed entirely on the first surface. Then, laser etching and other processes are used to remove the portion of the second semiconductor layer 4 located above at least a portion of the first semiconductor layer 2. In addition, in some embodiments, the mask layer 9 can be removed by wet chemical processes after the texturing treatment and before the second semiconductor layer 4 is formed.

[0177] Wherein, when the back contact battery further includes the second passivation layer 5, after the texturing treatment and before forming the second semiconductor layer 4, the manufacturing method of the back contact battery further includes the step of forming a second passivation layer 5 covering the first surface.

[0178] Specifically, before forming the second semiconductor layer 4, a deposition process can be used to form an entire second passivation layer 5 disposed on the first surface, and then an etching process such as a laser etching process is used to remove the second semiconductor layer 4 and the portion of the second passivation layer 5 located above at least a portion of the first semiconductor layer 2.

[0179] Here, the materials of the second passivation layer 5 and the second semiconductor layer 4 can refer to the above description, which will not be repeated here.

[0180] S5: The semiconductor substrate 1 formed with the first semiconductor layer 2 and the second semiconductor layer 4 is placed in a cleaning solution for cleaning, and is transferred through a roller 7; wherein the first surface faces the roller 7, and the teeth 7a of the roller 7 do not contact the second semiconductor layer 4 on the top of the pyramid arranged at the bottom of the groove 6a.

[0181] During the process of cleaning the semiconductor substrate 1 on which the first semiconductor layer 2 and the second semiconductor layer 4 are formed, the first surface of the semiconductor substrate 1 faces the roller 7, and the teeth 7a on the roller 7 may extend into the groove structure 6 due to the weight of the semiconductor substrate 1 itself, the pressure of the water film and / or the pressure of the drying roller 7. However, in the present application, due to the design of the back contact battery structure, the teeth 7a of the roller 7 do not contact the second semiconductor layer 4 on the pyramid top arranged at the bottom of the groove 6a. In this way, the teeth 7a of the roller 7 can be prevented from extending into the groove structure 6 and scratching the second semiconductor layer 4 located at the bottom of the groove 6a, thereby ensuring the performance of the back contact battery.

[0182] In some examples, in the back contact battery formed by the above manufacturing method, along the thickness direction of the semiconductor substrate 1, the distance between the surface of the second semiconductor layer 4 at the pyramid tip of the groove bottom 6a away from the semiconductor substrate 1 and the surface of the first semiconductor layer 2 away from the semiconductor substrate 1 is h0, 292nm≤h0≤15288nm. This can further prevent the teeth 7a of the roller 7 from extending into the groove structure 6 to scratch the second semiconductor layer 4 at the groove bottom 6a, and further ensure that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the back contact battery will not be reduced, and the battery cell has sufficient mechanical strength.

[0183] In some examples, in the back contact battery formed by the above manufacturing method, the second semiconductor layer 4 is also arranged on the side wall of the groove structure 6, and the second semiconductor layer 4 also extends to the part of the first semiconductor layer 2 away from the semiconductor substrate 1. Along the thickness direction of the semiconductor substrate 1, the distance between the surface of the second semiconductor layer 4 at the pyramid tip at the groove bottom 6a away from the semiconductor substrate 1 and the surface of the second semiconductor layer 4 covering the first semiconductor layer 2 away from the semiconductor substrate 1 is h1, 312nm≤h1≤15348nm. In the case where the second semiconductor layer 4 extends to the side of the first semiconductor layer 2 away from the semiconductor substrate 1, the second semiconductor layer 4 arranged on the side of the first semiconductor layer 2 away from the semiconductor substrate 1 can increase the distance between the teeth of the roller and the second semiconductor layer 4 at the pyramid tip covering the groove bottom. In order to avoid the teeth of the roller scratching the second semiconductor layer 4 at the groove bottom, h1 can be set in the range of 312nm≤h1≤15348nm, which can further prevent the teeth 7a of the roller 7 from extending into the groove structure 6 and scratching the second semiconductor layer 4 at the groove bottom 6a.

[0184] In some examples, in the back contact battery formed by the above manufacturing method, along the thickness direction of the semiconductor substrate 1, the distance from the pyramid top of the groove bottom of the semiconductor substrate to the surface of the first surface other than the groove structure 6 is h3, 300nm≤h3≤15000nm. Such a setting ensures that the light absorption rate of the semiconductor substrate 1 and the photoelectric conversion rate of the back contact battery will not be reduced, and the battery cell has sufficient mechanical strength; at the same time, it also ensures that after other film layers are formed on the semiconductor substrate 1, when the semiconductor substrate 1 is cleaned, the teeth 7a of the roller 7 will not contact the pyramid of the groove bottom 6a of the groove structure 6 after extending into the groove structure 6, or will not contact the film layer deposited on the pyramid of the groove bottom 6a of the groove structure 6, such as the second semiconductor layer, so as to ensure that the teeth 7a of the roller 7 will not scratch the pyramid of the groove bottom 6a of the groove structure 6, or will not scratch the film layer formed on the pyramid of the groove bottom 6a of the groove structure 6.

[0185] In some embodiments, after the texturing treatment in step S3 and before the second semiconductor layer 4 is formed on the first surface in step S4, the method for manufacturing the back contact battery further includes the steps of: placing the semiconductor substrate 1 formed with the first semiconductor layer 2 in a cleaning solution for cleaning, and transferring it through a roller 7; wherein the first surface faces the roller 7; and the teeth 7a of the roller 7 do not contact the top of the pyramid at the bottom 6a of the groove. With this technical solution, after the bottom 6a of the groove structure 6 is texturized, the semiconductor substrate 1 is cleaned to remove the texturing liquid remaining on the surface, and during the cleaning process, the teeth 7a of the roller 7 do not contact the pyramid arranged at the bottom 6a of the groove, thereby preventing the teeth 7a of the roller 7 from scratching the pyramid at the bottom 6a of the groove, thereby ensuring the performance of the back contact battery.

[0186] In some embodiments, along the thickness direction of the semiconductor substrate 1, the distance between the pyramid tip of the groove bottom 6a of the groove structure 6 and the surface of the first semiconductor layer 2 facing away from the semiconductor substrate 1 is h2, 330nm≤h2≤15300nm. Setting h2 in this range further prevents the teeth 7a of the roller 7 from extending into the groove structure 6 and scratching the pyramid of the groove bottom 6a of the groove structure 6 during the cleaning process, and further ensures that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the back contact battery will not be reduced, and the battery cell has sufficient mechanical strength.

[0187] In other embodiments, after step S5 of placing the semiconductor substrate 1 formed with the first semiconductor layer 2 and the second semiconductor layer 4 into the cleaning solution for cleaning, the method for manufacturing the back contact battery further includes: forming a transparent conductive layer 8 on the side of the first semiconductor layer 2 and the second semiconductor layer 4 away from the semiconductor substrate 1, the transparent conductive layer 8 being provided with an opening 8a extending through its thickness; placing the semiconductor substrate 1 formed with the transparent conductive layer 8 into the cleaning solution for cleaning, and transferring it through a roller 7, wherein the first surface faces the roller 7; the teeth 7a of the roller 7 are not in contact with the transparent conductive layer 8 on the top of the pyramid arranged at the bottom of the groove 6a.

[0188] In the actual manufacturing process, the transparent conductive layer 8 may be formed by PVD such as sputtering, and a laser process or an etching paste process may be used to open an opening 8a that penetrates the transparent conductive layer 8. Exemplarily, the thickness of the transparent conductive layer 8 may be greater than or equal to 10 nm and less than or equal to 500 nm; optionally, the thickness of the transparent conductive layer 8 may be greater than or equal to 50 nm and less than or equal to 200 nm.

[0189] The material of the transparent conductive layer 8 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide. The transparent conductive layer 8 may be a single-layer film or a laminated film.

[0190] In addition, the opening 8a can be formed by a laser process, and a laser with a pulse width of nanosecond or picosecond can be selected. The laser wavelength of the laser can be selected as needed, for example, a 355nm, 532nm, or 1064nm laser can be used. In some examples, a 355nm picosecond laser can be used. Of course, the opening 8a can also be formed using an etching solution or an etching paste.

[0191] In some embodiments, along the thickness direction of the semiconductor substrate 1, the distance between the surface of the transparent conductive layer 8 disposed on the pyramid top of the groove bottom 6a facing away from the semiconductor substrate 1 and the surface of the transparent conductive layer 8 disposed on the first semiconductor layer 2 facing away from the semiconductor substrate 1 is greater than or equal to 316nm, and less than or equal to 15385nm. In this case, after the transparent conductive layer 8 is formed, during the cleaning process of the semiconductor substrate 1, after the teeth 7a of the roller 7 extend into the groove structure 6, they will not contact the transparent conductive layer 8 located on the pyramid top of the groove bottom 6a of the groove structure 6, thereby preventing the teeth 7a of the roller 7 from scratching the transparent conductive layer 8 at the groove bottom 6a of the groove structure 6. At the same time, it is also ensured that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the back contact battery will not be reduced, and it is also ensured that the battery cell has sufficient mechanical strength.

[0192] In the above embodiment, after the semiconductor substrate 1 having the transparent conductive layer 8 is placed in a cleaning solution for cleaning in step S6, the method for manufacturing a back contact battery further includes manufacturing a first electrode and a second electrode. The first electrode 11 can be formed on the portion of the transparent conductive layer 8 corresponding to the first semiconductor layer 2, and the second electrode can be formed on the portion of the transparent conductive layer 8 corresponding to the second semiconductor layer 4 by a process such as screen printing.

[0193] The material of the first electrode and the second electrode may include one or more of silver, copper, and aluminum.

[0194] In other embodiments, after the texturing treatment in step S3 and before forming the second semiconductor layer 4 on the first surface in step S4, the manufacturing method of the back contact battery further includes: modifying the top of the pyramid at the groove bottom 6a of the groove structure 6 so that the top of the pyramid at the groove bottom 6a is in an arc shape. Compared with the pyramid with a pointed top, the height of the pyramid with an arc-shaped top is appropriately reduced, thereby increasing the distance between the top of the pyramid at the groove bottom 6a and the surface of the first semiconductor layer 2 away from the semiconductor substrate 1, and further reducing the probability that the teeth 7a of the roller 7 extend into the groove structure 6 and scratch the pyramid at the groove bottom 6a of the groove structure 6, the second semiconductor layer 4 arranged at the groove bottom 6a, or the transparent conductive layer 8 arranged at the groove bottom 6a.

[0195] In the actual manufacturing process, the top of the pyramid at the bottom 6a of the groove structure 6 can be modified by a wet process. For example, a mixed solution containing a fluorine / chloride ion source and an oxidant is used to etch the pyramid at the bottom 6a of the groove. The etching speed of the pyramid valley is very slow, and only the top of the pyramid can fully contact the etching solution. The etching rate gradually decreases from the top of the pyramid along the slope of the pyramid to the bottom of the pyramid. On the other hand, the reaction products at the bottom of the tower are too few to accumulate, so there is no significant difference in the etching rate at the bottom of the tower, and finally a pyramid with an arc-shaped top is obtained.

[0196] In some examples, the radius of curvature of the arc-shaped pyramid tip is 70 nm to 150 nm; and / or the curvature of the arc-shaped pyramid tip is in the range of 30° to 150°.

[0197] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0198] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface has a plurality of groove structures, wherein the groove structures are recessed toward the second surface relative to the rest of the first surface, and the groove bottoms of the groove structures are pyramid-shaped velvet surfaces; A first semiconductor layer is provided on a portion of the first surface except the groove structure; A second semiconductor layer is disposed at the bottom of the groove structure; the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; Among them, along the thickness direction of the semiconductor substrate, the distance between the surface of the second semiconductor layer at the top of the pyramid at the bottom of the groove facing away from the semiconductor substrate and the surface of the first semiconductor layer facing away from the semiconductor substrate is h0, 292nm≤h0≤15288nm.

2. The back contact cell according to claim 1, characterized in that: The second semiconductor layer is also disposed on the sidewall of the groove structure and extends onto a portion of the first semiconductor layer; Along the thickness direction of the semiconductor substrate, the distance between the surface of the second semiconductor layer at the top of the pyramid at the bottom of the groove structure facing away from the semiconductor substrate and the surface of the second semiconductor layer covering the first semiconductor layer facing away from the semiconductor substrate is h1, 312nm≤h1≤15348nm.

3. The back contact cell according to claim 1, characterized in that: Along the thickness direction of the semiconductor substrate, the distance between the pyramid tip at the bottom of the groove structure of the semiconductor substrate and the surface of the first semiconductor layer facing away from the semiconductor substrate is h2, 330nm≤h2≤15300nm.

4. The back contact cell according to claim 1, characterized in that: Along the thickness direction of the semiconductor substrate, the distance from the pyramid tip at the bottom of the groove structure of the semiconductor substrate to the surface of the first surface other than the groove structure is h3, 300nm≤h3≤15000nm.

5. The back contact cell according to any one of claims 1 to 4, characterized in that: The size of the pyramid base at the bottom of the groove of the semiconductor substrate ranges from 500nm to 7000nm, and the height of the pyramid ranges from 300nm to 6000nm.

6. The back contact cell according to any one of claims 1 to 4, characterized in that: The distance between adjacent first semiconductor layers is L, 200 μm≤L≤800 μm; and / or, The width of the groove bottom of the groove structure is L1, and 170 μm≤L1≤790 μm.

7. The back contact cell according to claim 6, characterized in that: 0.36≤h0 / L≤76.

4.

8. The back contact cell according to claim 1, characterized in that: The side wall of the groove structure comprises an inclined surface, and along the direction away from the middle area of ​​the groove bottom, the inclined surface is inclined in the direction away from the second surface; The width of the inclined surface is L2, 5μm≤L2≤15μm.

9. The back contact cell according to claim 8, characterized in that: The inclined surface includes a pyramid-shaped suede surface; The size of the pyramid located on the inclined surface is greater than the size of the pyramid located on the groove bottom.

10. The back contact cell according to claim 8 or 9, characterized in that: The pyramid located on the inclined surface and not at the junction of the inclined surface and the groove bottom has a height ranging from 50nm to 3000nm, and a base size ranging from 2000nm to 8000nm; The pyramid located on the inclined surface and at the junction of the inclined surface and the groove bottom has a tower height ranging from 1000nm to 9000nm, and a tower base size ranging from 1000nm to 9000nm.

11. The back contact cell according to claim 1, characterized in that: The pyramid tip of the groove bottom of the semiconductor substrate is in an arc shape; The radius of curvature of the arc-shaped pyramid spire is 70nm-150nm; and / or the curvature range of the arc-shaped pyramid spire is 30°-150°.

12. The back contact cell according to claim 1, characterized in that: The back contact battery further comprises a transparent conductive layer, which is disposed on a side of the first semiconductor layer and the second semiconductor layer away from the semiconductor substrate, and the transparent conductive layer is provided with an opening penetrating through the thickness thereof; Along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer at the top of the pyramid at the bottom of the groove and away from the semiconductor substrate is greater than or equal to 316nm and less than or equal to 1538nm.

13. The back contact cell according to claim 1, characterized in that: The second semiconductor layer is also disposed on the sidewall of the groove structure and extends onto a portion of the first semiconductor layer; The thickness of the second semiconductor layer located at the bottom of the groove structure is smaller than the thickness of the second semiconductor layer located at the sidewall of the groove structure and / or covering the first semiconductor layer.

14. A photovoltaic module, characterized in that: A back contact cell as claimed in any one of claims 1 to 13.

15. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; The first surface has first areas and second areas that are alternately distributed; forming a first semiconductor layer on the first surface; Etching the first semiconductor layer located in the second area, and performing a texturing process on the portion of the semiconductor substrate located in the second area; After the texturing treatment, the portion of the semiconductor substrate corresponding to the second region is concave in the direction from the second surface to the first surface relative to the first region toward the second surface, forming a groove structure, and the bottom of the groove structure is a pyramid-shaped texture surface; forming a second semiconductor layer on the first surface, and removing a portion of the second semiconductor layer to expose the first semiconductor layer; the second semiconductor layer and the first semiconductor layer have opposite conductivity types; The semiconductor substrate formed with the first semiconductor layer and the second semiconductor layer is placed in a cleaning liquid for cleaning and transferred by a roller; wherein the first surface faces the roller; and the teeth of the roller do not contact the second semiconductor layer on the top of the pyramid arranged at the bottom of the groove.

16. The method for manufacturing a back contact battery according to claim 15, characterized in that: Along the thickness direction of the semiconductor substrate, a distance between a surface of the second semiconductor layer disposed at the pyramid tip at the bottom of the groove and away from the semiconductor substrate and a surface of the first semiconductor layer and away from the semiconductor substrate is h0, 292nm≤h0≤15288nm; And / or, the distance from the pyramid tip of the groove bottom of the semiconductor substrate to the surface of the first surface other than the groove structure is h3, 300nm≤h3≤15000nm; And / or, the second semiconductor layer is also arranged on the side wall of the groove structure and extends onto a portion of the first semiconductor layer; along the thickness direction of the semiconductor substrate, the distance between the surface of the second semiconductor layer at the top of the pyramid at the bottom of the groove structure facing away from the semiconductor substrate and the surface of the second semiconductor layer covering the first semiconductor layer facing away from the semiconductor substrate is h1, 312nm≤h1≤15348nm.

17. The method for manufacturing a back contact battery according to claim 15, characterized in that: After the texturing treatment and before forming the second semiconductor layer on the first surface, the method for manufacturing the back-contact battery further includes: placing the semiconductor substrate formed with the first semiconductor layer into a cleaning liquid for cleaning, and transferring it through the roller; wherein the first surface faces the roller; and the teeth of the roller do not contact the top of the pyramid at the bottom of the groove.

18. The method for manufacturing a back contact battery according to claim 17, characterized in that: Along the thickness direction of the semiconductor substrate, the distance between the pyramid tip at the bottom of the groove structure and the surface of the first semiconductor layer away from the semiconductor substrate is h2, 330nm≤h2≤15300nm.

19. The method for manufacturing a back contact battery according to claim 15, characterized in that: After the semiconductor substrate having the first semiconductor layer and the second semiconductor layer formed thereon is placed in a cleaning solution for cleaning, the method for manufacturing a back contact battery further comprises: forming a transparent conductive layer on a side of the first semiconductor layer and the second semiconductor layer away from the semiconductor substrate, wherein the transparent conductive layer is provided with an opening penetrating the thickness thereof; The semiconductor substrate formed with the transparent conductive layer is placed in a cleaning solution for cleaning and is transferred by the roller; wherein the first surface faces the roller; and the teeth of the roller do not contact the transparent conductive layer on the top of the pyramid arranged at the bottom of the groove.

20. The method for manufacturing a back contact battery according to claim 19, characterized in that: Along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer arranged on the pyramid top at the bottom of the groove and away from the semiconductor substrate is greater than or equal to 316nm and less than or equal to 15385nm.

21. The method for manufacturing a back contact battery according to claim 15, characterized in that: After the texturing treatment and before forming the second semiconductor layer on the first surface, the method for manufacturing the back contact battery further includes: The pyramid top of the groove bottom of the groove structure is modified so that the pyramid top of the groove bottom The pyramid tip is in an arc shape; wherein the curvature radius of the arc-shaped pyramid tip is 70nm to 150nm; And / or, the arc angle of the arc-shaped pyramid spire ranges from 30° to 150°.

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