Metallized back contact solar cell structure and manufacturing method thereof

Abstract

The invention discloses a metalized back contact solar cell structure and a manufacturing method thereof, and the structure comprises a silicon substrate, a front surface film layer structure disposed at the upper end of the silicon substrate, a silicon substrate surface film layer structure, an emitter region film layer structure, and a silicon substrate surface film layer structure disposed on the back surface of the lower end of the silicon substrate. The surface film layer structure of the silicon substrate sequentially comprises a first tunneling passivation dielectric layer and a back surface doped film layer from top to bottom; a passivation dielectric film layer is arranged at the lower end of the silicon substrate surface film layer structure; the emitter region film layer structure is intermittently nested in the silicon substrate surface film layer structure, and the emitter region film layer structure comprises a second tunneling passivation dielectric layer and an emitter doped film layer from top to bottom in sequence; and a special gap structure is arranged between the silicon substrate surface film layer structure and the emitter region film layer structure. Due to the specific parameter setting of the gap structure, the reverse bias value of the back contact cell structure can exceed the reverse bias value borne by an existing solar cell with electrodes arranged on the two faces.

Description

Technical Field

[0001] The invention belongs to the technical field of solar energy, and in particular relates to a metallized back-contact solar cell structure and a manufacturing method thereof. Background Art

[0002] As an important pillar of the global renewable energy transformation, solar photovoltaics supports the goal of achieving international energy transformation and responding to climate challenges. The photoelectric conversion efficiency of solar cells has always been one of the important considerations for the development of photovoltaic industry technology. The pursuit of higher efficiency has been driving research institutions and manufacturers around the world to continuously seek innovative solutions in order to maximize the conversion efficiency of cells. Under the background of energy transformation, technological iteration has accelerated, the efficiency of PERC (Passivated Emitter and Rear Cell) cells has reached its limit, the N-type era has arrived, and multiple technology paths have developed. In particular, the discovery and application of LECO (Laser-enhanced contact optimization) technology has greatly reduced the composite and metal contact resistance of the metal region of N-type TOPCon (Tunnel Oxide Passivated Contact) cells, thereby significantly improving the open circuit voltage and fill factor of N-type TOPCon cells, and obtaining a cell efficiency improvement of more than 0.3%. The application of this technology has made TOPCon cells quickly become the mainstream technology for industrialization.

[0003] The LECO process technology was first discovered by the German company Cell Engineering GmbH in 2016 as a patented technology, and was initially developed for recycling unsintered solar cells. Subsequently, through the joint efforts of various research institutions and scientific research institutes, it has been successfully applied to the industrial production of N-type TOPCon cells.

[0004] In recent years, with the continuous development of TOPCon battery industrialization technology, a new metallization solution LECO technology has been widely used in the metallization process of industrial TOPCon batteries. The introduction of this process has greatly improved the recombination loss and contact resistance loss in the metal contact area. The industry unanimously believes that the introduction of this technology can increase the efficiency of N-type TOPCon batteries by more than 0.3%. However, the application of LECO technology must meet two conditions at the same time: ① In the LECO process technology, a highly concentrated laser beam needs to be scanned horizontally on the battery to induce a large number of photogenerated carriers locally; ② While the laser beam is scanning, it is necessary to separate the generated free carriers by applying a reverse bias, and the reverse bias value needs to be maintained above 10V. For N-type TOPCon batteries, the metal positive and negative electrodes are respectively set on the front and back of the battery, which can withstand a reverse bias of more than 10V and keep the PN junction from being broken down. This technology has achieved a good ohmic contact between the metal electrode of the N-type TOPCon battery and the crystalline silicon substrate. However, for the back-contact cell structure, the reverse bias voltage tolerance range is much less than 10V (the typical value of the tolerable reverse bias voltage is 5-8V), so this technology cannot be used in the back-contact solar cell structure. Therefore, there is no solution to apply LECO technology to the back-contact cell structure to form an ohmic contact.

[0005] At present, LECO process technology can only be applied to solar cell structures with a reverse bias withstand value of more than 10V, especially solar cells with metal electrodes arranged on the front and back of the cell, which can withstand a large reverse bias. Figure 1 As shown, Figure 1 (a) is the principle diagram of LECO process technology. Figure 1 (a) It can be seen that in the LECO process, the focused laser beam scans laterally on the battery, locally inducing the generation of a large number of photogenerated carriers, and at the same time applying a reverse bias to separate the free carriers, thereby generating a local high reverse current. The current passes through the sintered silver paste and the point contact with the silicon wafer surface, generating instantaneous high temperature, causing the silver paste to form an alloy with silicon, forming a good ohmic contact. Figure 1 (b) is a typical N-type TOPCon cell structure. For an N-type TOPCon cell, the positive electrode is located on the front surface (light-absorbing surface) of the cell, the negative electrode is located on the back surface of the cell, and the cell edge is insulated. Therefore, a focused laser beam is used to locally irradiate the cell structure, and a reverse bias voltage of more than 10V is applied to form a good ohmic contact. At present, the reverse bias voltage of the LECO technology applied to the TOPCon cell in industrial practice is about 14V.

[0006] However, for the back-contact solar cell structure, its characteristic is that the metal contact electrodes are all set on the back of the cell, avoiding the shading of the metal grid lines on the light-absorbing surface, making the most of the incident light and reducing the optical loss, thus having a higher short-circuit current and conversion efficiency, and therefore having a more efficient advantage in the cell structure design. If the LECO technology can be superimposed on the back-contact cell structure, a higher cell conversion efficiency will be obtained.

[0007] However, the positive and negative electrodes of the back contact battery are both located on the back surface of the battery, and the emitter doped region and the silicon substrate heavily doped region are distributed in an interdigitated manner on the back surface of the battery, such as Figure 2 As shown in the figure, the emitter doped region and the heavily doped region of the silicon substrate are in contact with each other on the back surface, so the reverse bias voltage is less than 5V. If the reverse bias voltage continues to increase, the pn junction breakdown phenomenon will occur at the contact point between the emitter doped region and the heavily doped region of the silicon substrate. There is also a structural design, such as Figure 3 As shown in FIG. 1 , a gap region is specially added between the emitter doping region and the heavily doped region of the silicon substrate. Although this structure can further increase the reverse bias value, it is far from satisfying the reverse bias value (greater than 10V) required for LECO technology to form an ohmic contact. Therefore, there has been no solution to apply LECO technology to a back contact battery structure in order to form an ohmic contact between metal and silicon. Summary of the invention

[0008] The present invention provides a metallized back-contact solar cell structure and a manufacturing method, which are used to solve the problem mentioned in the background technology that the current back-contact cell structure can withstand a low reverse bias value and cannot use the LECO technology to achieve ohmic contact of the metal electrode of the cell. The cell structure can solve the above problem of low reverse bias value (the new back-contact cell structure can make the reverse bias reach the same level as the reverse bias withstand value of the TOPCon cell), so that the back-contact cell structure can completely use the LECO technology to achieve ohmic contact of the metal electrode, thereby reducing metal composite and contact resistance, and achieving a leapfrog improvement in cell efficiency.

[0009] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: In the first aspect, the present invention provides a metallized back-contact solar cell structure, comprising: a silicon substrate, a front surface film structure arranged at the upper end of the silicon substrate, a silicon substrate surface film structure, and an emitter region film structure, wherein the front surface film structure is, from top to bottom, an anti-reflection dielectric film layer and a front surface field passivation doping layer in sequence; a silicon substrate surface film structure is arranged on the back surface of the lower end of the silicon substrate, wherein the silicon substrate surface film structure is, from top to bottom, a first tunneling passivation dielectric layer and a back surface doping film layer in sequence; a passivation dielectric film layer is arranged at the lower end of the silicon substrate surface film structure; the emitter region film structure is intermittently nested in the silicon substrate surface film structure, wherein the emitter region film structure is, from top to bottom, a second tunneling passivation dielectric layer and an emitter doping film layer in sequence, and a first metal electrode and a second metal electrode are arranged at the lower end of the passivation dielectric film layer; a gap structure is arranged between the silicon substrate surface film structure and the emitter region film structure.

[0010] Preferably, the gap structure is in the shape of a groove in the silicon substrate, and the depth of the gap structure is greater than the width of the gap structure, the gap structure and the emitter region film structure and the silicon substrate surface film structure are arranged perpendicular to each other, the minimum circumference of the gap structure is greater than or equal to 15 μm, and the maximum depth of the gap structure is less than the thickness of the silicon substrate.

[0011] Preferably, the thickness of the silicon substrate is 80-200 μm.

[0012] Preferably, the surface of the gap structure is a suede structure or a polished surface structure, and the surface of the gap structure is covered with a passivation dielectric film layer.

[0013] Preferably, the lateral width of the film layer structure in the emitter region is greater than the lateral width of the film layer structure on the surface of the silicon substrate.

[0014] In a second aspect, the present invention further provides a method for manufacturing a metallized back contact solar cell structure, comprising the following steps:

[0015] Step S1: selecting an N-type or P-type silicon wafer as a silicon substrate, and then performing a texturing treatment on both sides of the silicon substrate so that the silicon substrate forms a surface light trapping structure;

[0016] Step S2: selecting any one surface of the silicon substrate as the front surface and the other surface as the back surface, and doping the front surface of the silicon substrate with a phosphorus source or a boron source to form a front surface field passivation doping layer;

[0017] Step S3: polishing the back surface of the silicon substrate;

[0018] Step S4: depositing a first tunnel passivation dielectric layer and a back surface doped film layer on the back surface in sequence;

[0019] Step S5: intermittently removing the first tunnel passivation dielectric layer and the back surface doping film layer in step S4, so that the polished surface of the back surface of the silicon substrate is exposed by intermittently removing part thereof;

[0020] Step S6: depositing a second tunnel passivation dielectric layer and an emitter doping film layer on the back surface of the silicon substrate in sequence;

[0021] Step S7: intermittently removing the second tunnel passivation dielectric layer and the emitter doping film layer in step S6;

[0022] Step S8: using laser process technology superimposed with wet cleaning process technology to carve grooves on the back surface of the silicon substrate to form the gap structure;

[0023] Step S9: depositing an anti-reflection dielectric film layer on the front surface of the silicon substrate, and depositing a passivation dielectric film layer on the back surface;

[0024] Step S10: depositing a passivation dielectric film layer on the back surface through screen printing, sintering and LECO process technology to form a first metal electrode and a second metal electrode, and making the first metal electrode and the second metal electrode form ohmic contact with the emitter doped film layer and the back surface doped film layer respectively.

[0025] Beneficial effects of the present invention:

[0026] The battery structure of the present invention provides a special gap structure between the film structure of the silicon substrate surface on the back surface of the battery and the film structure of the emitter region, and the reverse bias value of the battery structure of the present invention can exceed the reverse bias value of the TOPCon battery proposed in the background technology. It solves the problem that the reverse bias value of the conventional back contact battery structure and the back contact battery with a conventional gap structure is low, so that the back contact battery structure can completely use LECO technology to achieve ohmic contact of the metal electrode, thereby reducing metal composite and contact resistance, and achieving a leapfrog improvement in battery efficiency.

[0027] The design of the gap structure in the back contact solar cell structure. The design of this special structure enables the LECO technology developed in the past two years to be applied in the metallization process of the back contact solar cell, thereby greatly reducing the composite and metal contact resistance losses in the metal contact area, and further improving the efficiency of the back contact solar cell structure; ① The design of the back contact cell gap structure and the tunneling passivated back contact solar cell structure with this special gap structure; ② The manufacturing method of the corresponding cell structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the application of LECO technology proposed as background technology in the TOPCon battery metallization process;

[0029] Figure 2 A schematic diagram of a conventional back contact battery structure with no gap proposed as background technology;

[0030] Figure 3 A schematic diagram of a back contact battery structure provided with a conventional gap structure proposed in the background art;

[0031] Figure 4 A schematic diagram of the structure of a metallized back-contact solar cell according to the present invention;

[0032] Figure 5 It is a partial schematic diagram of a metallized back-contact solar cell structure of the present invention.

[0033] In the figure: silicon substrate 10, front surface film structure 20, front surface field passivation doping layer 21, anti-reflection dielectric film layer 22, silicon substrate surface film structure 30, first tunneling passivation dielectric layer 31, back surface doped film layer 32, passivation dielectric film layer 40, emitter region film structure 50, second tunneling passivation dielectric layer 51, emitter doped film layer 52, first metal electrode 61, second metal electrode 62, gap structure 100. DETAILED DESCRIPTION

[0034] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. For the purpose of clear description, many physical details will be described together in the following description. However, it should be understood that these physical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these physical details are not necessary. In addition, for the purpose of simplifying the illustration, some conventional structures and components will be depicted in a simple schematic manner in the illustration.

[0035] Embodiment 1:

[0036] like Figure 4-5As shown, the present invention provides a metallized back-contact solar cell structure, comprising: a silicon substrate 10, a front surface film layer structure 20 arranged at the upper end of the silicon substrate 10, a silicon substrate surface film layer structure 30, and an emitter region film layer structure 50, wherein the front surface film layer structure 20 is composed of an anti-reflection dielectric film layer 22 and a front surface field passivation doping layer 21 from top to bottom; a silicon substrate surface film layer structure 30 is arranged on the back surface of the lower end of the silicon substrate 10, and the silicon substrate surface film layer structure 30 is composed of a first tunnel passivation dielectric layer 31 from top to bottom. , a back surface doped film layer 32; a passivation dielectric film layer 40 is arranged at the lower end of the silicon substrate surface film layer structure 30; the emitter region film layer structure 50 is intermittently nested in the silicon substrate surface film layer structure 30, and the emitter region film layer structure 50 is sequentially composed of a second tunneling passivation dielectric layer 51 and an emitter doped film layer 52 from top to bottom, and a first metal electrode 61 and a second metal electrode 62 are arranged at the lower end of the passivation dielectric film layer 40; a gap structure 100 is arranged between the silicon substrate surface film layer structure 30 and the emitter region film layer structure 50.

[0037] Furthermore, the gap structure 100 is in the shape of a groove in the silicon substrate 10, and the depth of the gap structure 100 is greater than the width of the gap structure 100, the gap structure 100 and the emitter region film layer structure 50 and the silicon substrate surface film layer structure 30 are arranged perpendicular to each other, the minimum circumference of the gap structure 100 is greater than or equal to 15 μm, and the maximum depth of the gap structure 100 is less than the thickness of the silicon substrate 10. Due to the groove setting of the gap structure 100, the transmission distance of the carriers between the first metal electrode 61 and the second metal electrode 62 under the reverse bias condition is increased, which is equal to or even exceeds the TOPCon battery proposed in the background art (such as Figure 1 The increase in the transmission distance increases the transmission resistance of the carrier under reverse bias conditions, so that the reverse bias value of the battery structure of the present invention can exceed the reverse bias value of the TOPCon battery proposed in the background technology. Therefore, the design of the battery structure can completely achieve ohmic contact of the metal electrode through LECO technology.

[0038] Furthermore, the thickness of the silicon substrate 10 is 80-200 μm.

[0039] Furthermore, the surface of the gap structure 100 is a suede structure or a polished surface structure, and the surface of the gap structure 100 is covered with a passivation dielectric film layer 40 .

[0040] Furthermore, the lateral width of the emitter region film layer structure 50 is greater than the lateral width of the silicon substrate surface film layer structure 30 .

[0041] Example 2: The present invention also provides a specific example of a method for manufacturing a metallized back contact solar cell structure;

[0042] Step 1: Select an N-type original silicon wafer, first immerse the original silicon wafer in a mixed solution with a temperature of 65°C to 80°C and a volume ratio of H2O2:NaOH:H2O=1:3:50 for pre-cleaning, and then use a mixed solution with a volume ratio of NaOH:ADDI (texturing additive):H2O=2:1:60 to complete a double-sided texturing process at a temperature of 80°C to 90°C, so that the silicon substrate 10 forms a sample with a light trapping structure;

[0043] Step 2: Stick the samples obtained in step 1 together in pairs and load them into the slot of a quartz boat for single-sided diffusion. Then place the quartz boat carrying the samples in a low-pressure phosphorus diffusion furnace tube, and deposit the phosphorus source at a pressure of 100-300 mbar and a temperature of 780°C-850°C. Then, push and distribute the phosphorus source at a temperature of 850°C-950°C to form a front surface field passivation doping layer 21.

[0044] Step three: define the phosphorus-doped surface of the sample obtained in step two as the front surface (light-absorbing surface), and use chain etching equipment and trough wet cleaning equipment to polish the back surface of the sample obtained above, removing 3 to 5 μm of silicon wafer thickness during polishing; wherein, the chain etching uses an HF solution with a volume fraction of 10% to 15%, and the back surface polishing uses a NaOH solution with a volume fraction of 15% to 20%.

[0045] Step 4: depositing a first tunnel passivation dielectric layer 31 on the back surface by thermal oxidation, and then depositing a layer of in-situ phosphorus-doped polysilicon film layer as the back surface doped film layer 32 by low pressure chemical vapor deposition (LPCVD), the thickness of the first tunnel passivation dielectric layer 31 is 1 to 3 nm, and the thickness of the back surface doped film layer 32 is 100 to 200 nm;

[0046] Step 5: using an ultraviolet picosecond laser to intermittently remove the first tunnel passivation dielectric layer 31 and the back surface doping film layer 32 deposited in step 4, and cleaning and polishing with a NaOH solution to expose the polished surface of the back surface of the silicon substrate by intermittently removing part of the surface;

[0047] Step 6: depositing a second tunnel passivation dielectric layer 51 on the back surface by plasma chemical vapor deposition (PECVD), and then depositing a layer of in-situ boron-doped amorphous or microcrystalline silicon film layer as an emitter passivation doped film layer 52 by physical vapor deposition (PVD), wherein the thickness of the second tunnel passivation dielectric layer 51 is 1-2 nm, and the thickness of the emitter passivation doped film layer 52 is 200-300 nm;

[0048] Step 7: using an ultraviolet picosecond laser to selectively remove the second tunnel passivation dielectric layer 51 and the emitter doped film layer 52 deposited on the surface of the back surface doped film layer 32 in step 6;

[0049] Step 8: Use an energy density of 10J / cm 2 The groove of the gap structure 100 is formed by a nanosecond laser of 0.0400 nm and above on the back surface, wherein the depth of the groove of the gap structure 100 is a 0、 The width is b0, a0 is greater than or equal to 5 μm, the sum of 2a0+b0 is greater than or equal to 15 μm, and the maximum value of a0 is less than the thickness of the silicon substrate 10. Then, the surface damage layer of the gap structure 100 caused by the laser grooving process is removed by polishing through a wet cleaning process.

[0050] Step nine: depositing an anti-reflection dielectric film layer 22 on the front side of the silicon substrate 10 by plasma chemical vapor deposition (PECVD), the anti-reflection dielectric film layer 22 is a 70-80nm SiNx:H film layer, the flow ratio of SiH4 to NH3 in the SiNx:H film layer is about 1:5, and the process temperature of depositing the anti-reflection dielectric film layer 22 is set to 450°C to 480°C; the passivation dielectric film layer 40 deposited on the back surface is a composite film layer, the composite film layer is sequentially a 5-15nm Al2O3 film layer and a 70-90nm SiNz:H film layer, the flow ratio of SiH4 to NH3 during the SiNy:H film coating process is about 1:4, in order to improve the density of the SiNz:H film layer, the temperature of the deposited passivation dielectric film layer 40 is set to 490°C to 550°C;

[0051] Step 10: Print the first metal electrode 61 and the second metal electrode 62 separately by screen printing, then dry and pre-sinter them in a chain sintering furnace, and finally use LECO technology to load a reverse bias of 10V or more between the first metal electrode 61 and the second metal electrode 62. At the same time, laser irradiate the front surface or back surface of the battery to form a large number of photogenerated carriers. Under the combined action of reverse bias and laser illumination, the first metal electrode 61 and the second metal electrode 62 form good ohmic contacts with the emitter passivation doped film layer 52 and the back surface passivation doped film layer 32 respectively.

[0052] The design of this gap structure increases the carrier transmission distance at the intersection of the emitter region and the substrate region, thereby greatly improving the reverse bias tolerance range of the back contact battery structure. When the value of 2a0+b0 is equal to the thickness of the silicon substrate, the reverse bias value that can be tolerated can reach the same reverse bias value as the current TOPCon battery. Therefore, the back contact battery structure can fully use LECO technology to realize the metallization process.

[0053] The above is only one way to select an N-type silicon substrate for the production of the battery. Specifically, when the silicon substrate 10 is an n-type silicon substrate, the front surface field passivation doping layer 21 is an n-type doped layer; the back surface passivation doping film layer 32 is an n-type doped polysilicon layer or an amorphous silicon layer; the emitter passivation doping film layer 52 is a p-type doped polysilicon layer or an amorphous silicon layer; the first metal electrode 61 is a positive electrode, and the second metal electrode 62 is a negative electrode. When the silicon substrate 10 is a p-type silicon substrate, the front surface field passivation doping layer 21 is a p-type doped layer; the back surface passivation doping film layer 32 is a p-type doped polysilicon layer or an amorphous silicon layer; the emitter passivation doping film layer 52 is an n-type doped polysilicon layer or an amorphous silicon layer; the first metal electrode 61 is a negative electrode, and the second metal electrode 62 is a positive electrode. The front surface anti-reflection dielectric film layer 22 is a SiNx:H film layer or a stacked film structure of a SiONy film layer and a SiNx:H film layer, and the back surface passivation dielectric film layer 40 is an Al2O3 film layer or a stacked film structure of an Al2O3 film layer and a SiNz:H film layer.

[0054] The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A metallized back contact solar cell structure, characterized in that: include: A silicon substrate (10), a front surface film structure (20) arranged on the upper end of the silicon substrate (10), a silicon substrate surface film structure (30), and an emitter region film structure (50), wherein the front surface film structure (20) is composed of an anti-reflection dielectric film layer (22) and a front surface field passivation doping layer (21) in order from top to bottom; a silicon substrate surface film structure (30) is arranged on the back surface of the lower end of the silicon substrate (10), wherein the silicon substrate surface film structure (30) is composed of a first tunneling passivation dielectric layer (31) and a back surface doping film layer (32) in order from top to bottom; and the silicon substrate A passivation dielectric film layer (40) is arranged at the lower end of the body surface film layer structure (30); the emitter region film layer structure (50) is intermittently nested in the silicon substrate surface film layer structure (30); the emitter region film layer structure (50) comprises, from top to bottom, a second tunneling passivation dielectric layer (51) and an emitter doping film layer (52); a first metal electrode (61) and a second metal electrode (62) are arranged at the lower end of the passivation dielectric film layer (40); and a gap structure (100) is arranged between the silicon substrate surface film layer structure (30) and the emitter region film layer structure (50).

2. The structure according to claim 1, characterized in that: The gap structure (100) is in the shape of a groove in the silicon substrate (10), and the depth of the gap structure (100) is greater than the width of the gap structure (100). The gap structure (100) and the emitter region film layer structure (50) and the silicon substrate surface film layer structure (30) are arranged perpendicular to each other. The minimum circumference of the gap structure (100) is greater than or equal to 15 μm, and the maximum depth of the gap structure (100) is less than the thickness of the silicon substrate (10).

3. The structure according to claim 2, characterized in that: The thickness of the silicon substrate (10) is 80-200 μm.

4. The structure according to claim 1, characterized in that The surface of the gap structure (100) is a suede surface structure or a polished surface structure, and the surface of the gap structure (100) is covered with a passivation dielectric film layer (40).

5. The structure according to claim 1 or 2, characterized in that: The lateral width of the emitter region film layer structure (50) is greater than the lateral width of the silicon substrate surface film layer structure (30).

6. A method for manufacturing a metallized back contact solar cell structure according to any one of claims 1 to 5, characterized in that: The steps include: Step S1: selecting an N-type or P-type silicon wafer as a silicon substrate (10), and then performing a texturing treatment on both sides of the silicon substrate (10), so that the silicon substrate (10) forms a surface light trapping structure; Step S2: selecting any one surface of the silicon substrate (10) as the front surface and the other surface as the back surface, and performing phosphorus source or boron source doping on the front surface of the silicon substrate (10) to form a front surface field passivation doping layer (21); Step S3: polishing the back surface of the silicon substrate (10); Step S4: depositing a first tunnel passivation dielectric layer (31) and a back surface doped film layer (32) on the back surface in sequence; Step S5: intermittently removing the first tunnel passivation dielectric layer (31) and the back surface doping film layer (32) in step S4, so that the polished surface of the intermittently removed portion of the back surface of the silicon substrate (10) is exposed; Step S6: depositing a second tunnel passivation dielectric layer (51) and an emitter doping film layer (52) on the back surface of the silicon substrate in sequence; Step S7: intermittently removing the second tunnel passivation dielectric layer (51) and the emitter doped film layer (52) in step S6; Step S8: using laser process technology superimposed with wet cleaning process technology to carve grooves on the back surface of the silicon substrate (10) to form the gap structure (100); Step S9: depositing an anti-reflection dielectric film layer (22) on the front surface of the silicon substrate (10), and depositing a passivation dielectric film layer (40) on the back surface; Step S10: depositing a passivation dielectric film layer (40) on the back surface by screen printing, sintering and LECO process technology to form a first metal electrode (61) and a second metal electrode (62), and making the first metal electrode (61) and the second metal electrode (62) form ohmic contact with the emitter doped film layer (52) and the back surface doped film layer (32) respectively.

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