Back contact battery and photovoltaic module

Abstract

The invention discloses a back contact cell and a photovoltaic module, relates to the technical field of photovoltaic, and aims to perform field passivation on a first region and an overlapping region through a doping layer, and the doping layer can form a favorable electric field consistent with the induction direction of a first doped silicon layer so as to improve the collection efficiency of the first doped silicon layer on current carriers. The back contact cell includes a semiconductor substrate, a tunneling passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer, and a doped layer. The tunneling passivation layer and the first doped silicon layer are sequentially arranged on the first region and the overlapping region in a stacked mode. The intrinsic silicon layer and the second doped silicon layer are sequentially arranged on the second area in a stacked mode and further extend to cover the tunneling passivation layer and the first doped silicon layer which are located in the overlapping area. The doped layer is disposed within the first region and the overlapping region of the semiconductor substrate. And the doping concentration of a first doping element with the same conduction type as that of the first doping silicon layer in the doping layer is greater than that of the first doping element in the second region of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back contact cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0003] However, the passivation effect on the backlight side of the existing back contact cell is relatively poor, which is not conducive to improving the conversion efficiency of the back contact cell. Summary of the invention

[0004] The object of the present invention is to provide a back-contact cell and a photovoltaic module, so as to perform field passivation on the first region and the overlapping region of the semiconductor substrate through a doping layer, and the doping layer can form a favorable electric field consistent with the induction direction of the first doped silicon layer, thereby improving the collection efficiency of the first doped silicon layer for carriers, reducing the carrier recombination rate, and facilitating improving the conversion efficiency of the back-contact cell.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a back contact battery, which includes: a semiconductor substrate, a tunneling passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer and a doped layer. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface includes a first region and a second region alternately spaced and an overlapping region between the first region and the second region. Along the thickness direction of the semiconductor substrate, the tunneling passivation layer and the first doped silicon layer are sequentially stacked on the first region and the overlapping region. Along the thickness direction of the semiconductor substrate, the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region. Moreover, the stacked intrinsic silicon layer and the second doped silicon layer also extend from the second region to cover the tunneling passivation layer and the first doped silicon layer located in the overlapping region. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer. The doped layer is arranged in the first region and the overlapping region of the semiconductor substrate. The doping concentration of the first doping element in the doping layer, which has the same conductivity type as the first doped silicon layer, is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate. Along the direction from the first surface to the second surface, the doping concentration of the second doping element having the same conductivity type as the second doped silicon layer in each portion of the second region of the semiconductor substrate is the same.

[0006] In the case of adopting the above technical solution, in the back contact battery provided by the present invention, the first surface of the semiconductor substrate is not only provided with a selective contact structure consisting of a tunneling passivation layer and a first doped silicon layer, but also provided with a selective contact structure consisting of an intrinsic silicon layer and a second doped silicon layer. Specifically, the above selective contact structure can not only realize the selective collection of carriers, but also passivate the first surface of the semiconductor substrate, reduce the carrier recombination rate on the first surface side of the semiconductor substrate, and help improve the conversion efficiency of the back contact battery. In addition, the stacked intrinsic silicon layer and the second doped silicon layer also extend from the second region to cover the tunneling passivation layer and the first doped silicon layer located in the overlapping region. At this time, along the distribution direction of the first region and the second region, there is no groove isolation between the first doped silicon layer and the second doped silicon layer, which can increase the setting area of ​​the first doped silicon layer and the second doped silicon layer on the first surface, and improve the carrier collection efficiency.

[0007] In addition, a doping layer is also provided in the first region and the overlapping region of the semiconductor substrate, wherein the doping layer is doped with a first doping element of the same conductivity type as the first doped silicon layer, and the doping concentration of the first doping element in the doping layer is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate. At this time, the doping concentration of the first doping element in the doping layer is high, and the conductivity type of the first doping element is the same as the conductivity type of the first doped silicon layer, so the first region and the overlapping region of the semiconductor substrate can be field passivated by the doping layer to improve the passivation effect. Moreover, the conductivity type of the first doping element in the doping layer is the same as the conductivity type of the first doped silicon layer, so the doping layer can form a favorable electric field consistent with the induction direction of the first doped silicon layer, and the existence of the favorable electric field can play a role in repelling minority carriers and attracting majority carriers on the surface of the first region and the overlapping region of the semiconductor substrate, thereby improving the collection efficiency of the first doped silicon layer for carriers, further reducing the carrier recombination rate, and facilitating the improvement of the conversion efficiency of the back contact battery.

[0008] Furthermore, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer in each part of the second region of the semiconductor substrate is the same, that is, there is no inner-diffused doping region with the same conductivity type as the second doped silicon layer in the second region of the semiconductor substrate, which can prevent the above-mentioned doping layer and the inner-diffused doping region with the opposite conductivity type to the doping layer from electrically contacting each other, thereby ensuring that the back-contact battery has a higher conversion efficiency.

[0009] As a possible implementation, the second region includes a groove. Along the direction from the second surface to the first surface, the surface height of the second doped silicon layer at the bottom of the groove facing away from the semiconductor substrate is less than the surface height of the doped layer facing away from the tunnel passivation layer.

[0010] When the above technical solution is adopted, the second area includes a groove. The existence of the groove not only indicates that after the tunneling passivation layer and the first doped silicon layer are patterned, the parts of the two located in the second area have been completely removed, thereby improving the yield of the back contact battery. At the same time, because the surface height of the part of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate is less than the surface height of the doped layer away from the tunneling passivation layer, that is, at this time, there is no structurally opposite part between the doped layer and the second doped silicon layer along the thickness direction of the semiconductor substrate. In other words, the existence of the groove can also stagger the doped layer and the first doped silicon layer with the second doped silicon layer of opposite conductivity type along the thickness direction of the semiconductor substrate, thereby reducing the risk of leakage between the doped layer and the second doped silicon layer, which is conducive to further improving the conversion efficiency of the back contact battery. In addition, it can be understood that the portion of the second doped silicon layer located at the bottom of the groove is mainly used to collect and conduct carriers. Therefore, the surface height of the portion of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate is set to be smaller than the surface height of the doped layer away from the tunneling passivation layer. It is also beneficial to prevent the first doping element in the doping layer with a conductivity type opposite to that of the second doped silicon layer from diffusing into the second doped silicon layer, thereby ensuring that the second doped silicon layer has a higher carrier collection ability for the portion at the bottom of the groove.

[0011] As a possible implementation solution, the depth of the groove is greater than or equal to 300 nm and less than or equal to 15 μm.

[0012] When the above technical solution is adopted, the depth of the groove is within the above range, which is conducive to preventing the high risk of leakage caused by the small offset distance between the doped layer and the second doped silicon layer located at the bottom of the groove along the thickness direction of the semiconductor substrate due to the small depth of the groove. In addition, it can also prevent the light absorption depth of the part of the semiconductor substrate corresponding to the groove from being small due to the large depth of the groove, ensuring that the semiconductor substrate has a high photoelectric conversion efficiency, and then ensuring that the back contact battery has a high working performance.

[0013] As a possible implementation scheme, along the direction from the second surface to the first surface, the difference between the surface height of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate and the surface height of the doped layer away from the tunnel passivation layer is greater than or equal to 180nm and less than or equal to 14.7μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the groove depth being greater than or equal to 300nm and less than or equal to 15μm described above, and will not be repeated here.

[0014] As a possible implementation scheme, along the width direction of the overlapping region, the width of the doped layer is greater than or equal to the width of the first doped silicon layer. In this case, the doped layer has a larger formation range, which is conducive to improving the field passivation effect of the doped layer and further reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate.

[0015] As a possible implementation scheme, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer is greater than 0 and less than or equal to 50μm. In this case, the width of the doped layer is approximately the same as the width of the first doped silicon layer, ensuring that under the passivation effect of the doped layer, the first region and the overlapping region of the semiconductor substrate have a higher carrier recombination rate. In addition, it can be understood that the overlapping region is adjacent to the second region, and the second doped silicon layer located in the second region is mainly used to collect and guide out carriers, and the conductivity type of the first doping element doped in the doped layer is opposite to the conductivity type of the second doped silicon layer. Based on this, when the difference between the width of the doped layer and the width of the first doped silicon layer is within the above range, it can be prevented that the width of the doped layer is large, resulting in a small distance between the edge of the doped layer and the edge of the second doped silicon layer, thereby reducing the risk of leakage between the doped silicon and the second doped silicon layer.

[0016] As a possible implementation scheme, the second region includes a groove. Along the width direction of the overlapping region, the side of the groove has a first sub-region and a second sub-region that are continuously distributed, and the second sub-region is close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases from the second surface to the first surface. The surface of the second sub-region is a plane. In addition, the doped layer also extends to the second sub-region of the semiconductor substrate; or, the doped layer also extends to the second sub-region of the semiconductor substrate and a partial region of the first sub-region close to the second sub-region.

[0017] When the above technical solution is adopted, when the depth of the groove is fixed, the surface of the first sub-region on the side of the groove is inclined relative to the surface of the first region, and the cross-sectional area of ​​the part of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface, which is beneficial to increase the lateral spacing between the doped layer and the second doped silicon layer located on the bottom of the groove, so that the edge of the doped layer only extends from the overlapping area to the second sub-region of the semiconductor substrate and the partial area of ​​the first sub-region close to the second sub-region, but does not extend to the bottom surface of the groove, further reducing the risk of leakage between the two.

[0018] As a possible implementation scheme, the doping concentration of the first doping element in the doping layer gradually increases along the direction from the second surface to the first surface. In this case, along the direction from the second surface to the first surface, a high-low junction can be formed between different regions of the doping layer, and the built-in electric field of the high-low junction is consistent with the induced direction of the first doped silicon layer, which can further improve the collection efficiency of the first doped silicon layer for carriers, further reduce the carrier recombination rate, and help improve the conversion efficiency of the back contact battery.

[0019] As a possible implementation scheme, the doping concentration of the first doping element in the first doped silicon layer is greater than the doping concentration of the first doping element in the doping layer. In this case, it is ensured that the first doped silicon layer has a higher field passivation effect, and the carrier collection ability of the first doped silicon layer is improved. In addition, a high-low junction can be formed between the first doped silicon layer and the doped layer, and the built-in electric field direction of the high-low junction is consistent with the induced direction of the first doped silicon layer, further improving the carrier collection ability of the first doped silicon layer.

[0020] As a possible implementation scheme, the above-mentioned back contact battery also includes a transparent conductive layer. The transparent conductive layer covers the side of the first doped silicon layer and the second doped silicon layer away from the semiconductor substrate. An insulating groove is provided in the transparent conductive layer to disconnect the portions of the transparent conductive layer corresponding to the first area and the second area from each other. The portion of the transparent conductive layer with the same conductivity type as the carriers transmitted by the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate. In this case, the transparent conductive layer has good conductivity and can improve the carrier collection efficiency. In addition, the portion of the transparent conductive layer with the same conductivity type as the carriers transmitted by the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate, preventing the portion of the transparent conductive layer with the same conductivity type as the carriers transmitted by the second doped silicon layer from overlapping with the doped silicon layer doped with the first doping element with the opposite conductivity type to the second doped silicon layer, thereby increasing the risk of leakage and ensuring that the back contact battery has high electrical reliability.

[0021] As a possible implementation solution, along the thickness direction of the semiconductor substrate, the doping depth of the doping layer is greater than or equal to 1 nm and less than or equal to 300 nm.

[0022] When the above technical solution is adopted, the doping depth of the doping layer is within the above range, which is conducive to preventing the poor field passivation ability of the doping layer due to the small doping depth of the doping layer. In addition, it can also prevent the high Auger recombination rate in the semiconductor substrate due to the large doping depth of the doping layer from affecting its own passivation effect, ensuring that the first area and the overlapping area where the semiconductor substrate is formed with the doping layer have a low carrier recombination rate. If in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer into the doping layer, then the doping depth of the doping layer is within the above range, and it can also prevent the doping concentration of the first doping element in the first doped silicon layer from being low due to the large doping depth of the doping layer, ensuring that the first doped silicon layer has a high carrier collection efficiency.

[0023] As a possible implementation solution, the doping concentration of the first doping element in the doping layer is less than or equal to 9×10 20 / cm 3 , and greater than or equal to 8×10 9 / cm 3 . In this case, it is possible to prevent the poor passivation effect of the doping layer due to the low doping concentration of the first doping element in the doping layer. In addition, it is also possible to prevent the low carrier collection efficiency of the first doped silicon layer due to the large doping concentration of the first doping element in the doping layer, which causes the energy band to be recessed, thereby ensuring that the back contact battery has a higher conversion efficiency. If in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer into the doping layer, the doping concentration of the first doping element in the doping layer is within the above range, and it is also possible to prevent the low doping concentration of the first doping element in the first doped silicon layer due to the large doping concentration of the first doping element in the doping layer, thereby ensuring that the first doped silicon layer has a higher carrier collection efficiency.

[0024] As a possible implementation solution, the thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm.

[0025] When the above technical solution is adopted, the thickness of the first doped silicon layer is within the above range, which can prevent the first doped silicon layer from having a low field passivation effect due to its small thickness, thereby ensuring that the first doped silicon layer has a higher carrier collection efficiency. At the same time, if in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer to the doping layer, then the thickness of the first doped silicon layer is within the above range, which can also prevent the first doping element diffused from the first doped silicon layer to the doping layer from having a low doping concentration due to the small thickness of the first doped silicon layer, thereby ensuring that the doping layer has a higher field passivation effect. In addition, it can also prevent the large amount of consumables used in the first doped silicon layer due to the large thickness of the first doped silicon layer, and the problem of the doping concentration of the first doping element in the doping layer being too high, thereby ensuring that the back contact battery has a higher conversion efficiency.

[0026] As a possible implementation solution, the doping concentration of the first doping element in the first doped silicon layer is greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3 The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the thickness of the first doped silicon layer being greater than or equal to 20 nm and less than or equal to 300 nm described above, and will not be repeated here.

[0027] As a possible implementation solution, the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 20 nm.

[0028] In the case of adopting the above technical solution, on the second region of the semiconductor substrate, the intrinsic silicon layer is located between the semiconductor substrate and the second doped silicon layer, which can play a diffusion barrier role for the doped elements in the second doped silicon layer. Based on this, the thickness of the intrinsic silicon layer is within the above range, which can prevent the intrinsic silicon layer from having a weak diffusion barrier effect on the doped elements in the second doped silicon layer due to its small thickness, and ensure that no inner diffusion doped layer with the same conductivity type as the second doped silicon layer is formed in the second region. In addition, it can also prevent the intrinsic silicon layer from having a large transmission resistance due to its large thickness, and ensure that the second doped silicon layer has a high carrier collection efficiency.

[0029] As a possible implementation solution, the doping concentration of the second doping element in the second doped silicon layer is greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3In this case, while ensuring that the second doped silicon layer has a high field passivation effect, the second doping element in the second doped silicon layer is prevented from being high and easily diffusing into the second region of the semiconductor substrate to form an inner diffusion doping layer, ensuring that the doped layer will not electrically contact the inner diffusion doping region with a conductivity type opposite to its own, resulting in a high risk of leakage, thereby ensuring that the back contact battery has a high conversion efficiency.

[0030] As a possible implementation scheme, the thickness of the second doped silicon layer is greater than or equal to 10 nm and less than or equal to 100 nm. The application principle of the beneficial effect in this case can refer to the above-mentioned doping concentration of the second doping element in the second doped silicon layer being greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3 The application principle of the beneficial effect will not be repeated here.

[0031] As a possible implementation scheme, the sum of the thickness of the second doped silicon layer and the intrinsic silicon layer is greater than or equal to 15nm and less than or equal to 120nm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the thickness of the intrinsic silicon layer being greater than or equal to 5nm and less than or equal to 20nm, and the thickness of the second doped silicon layer being greater than or equal to 10nm and less than or equal to 100nm described above, which will not be repeated here.

[0032] As a possible implementation scheme, the conductivity types of the above-mentioned first doped silicon layer and the doped layer are the same as the conductivity type of the semiconductor substrate. The second region of the semiconductor substrate does not have a second doping element. In this case, a high-low junction can be formed between each adjacent two of the semiconductor substrate, the doped layer and the first doped silicon layer. Under the action of the built-in electric field of the high-low junction, the collection efficiency of the first doped silicon layer for carriers can be further improved, and the conversion efficiency of the back contact battery can be further improved. The second region of the semiconductor substrate has a second doping element with a conductivity type opposite to that of the doped layer, which can ensure that the doped layer will not electrically contact the inner expansion doping region with a conductivity type opposite to its own, resulting in a higher risk of leakage, thereby ensuring that the back contact battery has a higher conversion efficiency.

[0033] As a possible implementation scheme, the conductivity type of the doped layer and the first doped silicon layer is N-type, and the conductivity type of the second doped silicon layer is P-type.

[0034] As a possible implementation scheme, the second region includes a groove, the bottom surface of the groove is a velvet surface, and the thickness of the second doped silicon layer located on the bottom of the groove is smaller than the thickness of the second doped silicon layer located in the overlapping region.

[0035] When the above technical solution is adopted, the thickness of the second doped silicon layer located at the bottom of the groove is relatively small. Under the premise of ensuring that it has a good field passivation effect, it can prevent the second doped elements in the second doped silicon layer located at the bottom of the groove from diffusing into the second region of the semiconductor substrate due to the large thickness of the second doped silicon layer. It can ensure that the doped layer will not electrically contact the inner diffusion doped region with the opposite conductivity type to its own, resulting in a higher risk of leakage, thereby ensuring that the back contact battery has a higher conversion efficiency.

[0036] In a second aspect, the present invention provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0037] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0039] Figure 1 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 1 ;

[0040] Figure 2 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 2 ;

[0041] Figure 3 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 3 ;

[0042] Figure 4 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 4 ;

[0043] Figure 5 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 5 ;

[0044] Figure 6 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 6 ;

[0045] Figure 7 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 7 ;

[0046] Figure 8Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 8 ;

[0047] Fig. 9 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 9 ;

[0048] Fig.10 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 10 ;

[0049] Fig.11 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 10 one;

[0050] Fig.12 Schematic diagram of the structure of the back contact battery provided by the embodiment of the present invention Figure 10 two.

[0051] Figure numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is an overlapping region, 15 is a tunneling passivation layer, 16 is a first doped silicon layer, 17 is an intrinsic silicon layer, 18 is a second doped silicon layer, 19 is a doped layer, 20 is a groove, 21 is a first sub-region, 22 is a second sub-region, 23 is a transparent conductive layer, 24 is an insulating groove, 25 is a surface passivation layer, and 26 is an anti-reflection layer. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0053] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0054] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0056] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] In a first aspect, an embodiment of the present invention provides a back contact battery. Figure 1As shown, the back contact cell provided by the embodiment of the present invention includes: a semiconductor substrate 11, a tunneling passivation layer 15, a first doped silicon layer 16, an intrinsic silicon layer 17, a second doped silicon layer 18 and a doped layer 19. The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface includes a first region 12 and a second region 13 that are alternately distributed, and an overlapping region 14 between the first region 12 and the second region 13. Along the thickness direction of the semiconductor substrate 11, the tunneling passivation layer 15 and the first doped silicon layer 16 are sequentially stacked on the first region 12 and the overlapping region 14. Along the thickness direction of the semiconductor substrate 11, the intrinsic silicon layer 17 and the second doped silicon layer 18 are sequentially stacked on the second region 13. Moreover, the stacked intrinsic silicon layer 17 and the second doped silicon layer 18 also extend from the second region 13 to cover the tunneling passivation layer 15 and the first doped silicon layer 16 located on the overlapping region 14. It can be understood that the overlapping region 14 refers to a region where the tunneling passivation layer 15 and the first doped silicon layer 16, the intrinsic silicon layer 17 and the second doped silicon layer 18 are simultaneously provided. The conductivity type of the second doped silicon layer 18 is opposite to the conductivity type of the first doped silicon layer 16. The doped layer 19 is provided in the first region 12 and the overlapping region 14 of the semiconductor substrate 11. The doping concentration of the first doping element of the same conductivity type as the first doped silicon layer 16 in the doping layer 19 is greater than the doping concentration of the first doping element in the second region 13 of the semiconductor substrate 11. Along the direction from the first surface to the second surface, the doping concentration of the second doping element of the same conductivity type as the second doped silicon layer 18 in each part of the second region 13 of the semiconductor substrate 11 is the same.

[0058] When the above technical solution is adopted, Figure 1As shown, in the back contact battery provided by the embodiment of the present invention, the first surface of the semiconductor substrate 11 is not only provided with a selective contact structure consisting of a tunnel passivation layer 15 and a first doped silicon layer 16, but also provided with a selective contact structure consisting of an intrinsic silicon layer 17 and a second doped silicon layer 18. Specifically, the above-mentioned selective contact structure can not only realize the selective collection of carriers, but also passivate the first surface of the semiconductor substrate 11, reduce the carrier recombination rate on the first surface side of the semiconductor substrate 11, and help improve the conversion efficiency of the back contact battery. In addition, the stacked intrinsic silicon layer 17 and the second doped silicon layer 18 also extend from the second region 13 to cover the tunnel passivation layer 15 and the first doped silicon layer 16 located on the overlapping region 14. At this time, along the distribution direction of the first region 12 and the second region 13, there is no groove isolation between the first doped silicon layer 16 and the second doped silicon layer 18, which can increase the setting area of ​​the first doped silicon layer 16 and the second doped silicon layer 18 on the first surface, and improve the carrier collection efficiency. In addition, a doping layer 19 is also provided in the first region 12 and the overlapping region 14 of the semiconductor substrate 11, and the doping layer 19 is doped with a first doping element of the same conductivity type as the first doped silicon layer 16, and the doping concentration of the first doping element in the doping layer 19 is greater than the doping concentration of the first doping element in the second region 13 of the semiconductor substrate 11. At this time, the doping concentration of the first doping element in the doping layer 19 is relatively high, and the conductivity type of the first doping element is the same as the conductivity type of the first doped silicon layer 16. Therefore, the first region 12 and the overlapping region 14 of the semiconductor substrate 11 can be field passivated by the doping layer 19 to improve the passivation effect. Moreover, the conductivity type of the first doping element in the doping layer 19 is the same as the conductivity type of the first doped silicon layer 16, so the doping layer 19 can form a favorable electric field in the same direction as the first doped silicon layer 16. The existence of the favorable electric field can repel minority carriers and attract majority carriers on the surface of the first region 12 and the overlapping region 14 of the semiconductor substrate 11, thereby improving the collection efficiency of the first doped silicon layer 16 for carriers, further reducing the carrier recombination rate, and facilitating the improvement of the conversion efficiency of the back contact battery. Furthermore, along the direction from the first surface to the second surface, the doping concentration of the second doping element of the same conductivity type as the second doped silicon layer 18 in each part of the second region 13 of the semiconductor substrate 11 is the same, that is, there is no inner doping region of the same conductivity type as the second doped silicon layer 18 in the second region 13 of the semiconductor substrate 11, which can prevent the above-mentioned doping layer 19 from being electrically contacted with the inner doping region of the opposite conductivity type to the doping layer 19 (i.e., the inner doping region of the same conductivity type as the second doped silicon layer 18) and causing a high risk of leakage, thereby ensuring that the back contact battery has a high conversion efficiency.

[0059] In actual application, the embodiment of the present invention does not specifically limit the material and conductivity type of the semiconductor substrate. For example, the semiconductor substrate may be a silicon substrate; or, the semiconductor substrate may be a substrate made of any semiconductor material such as a germanium silicon substrate, a germanium substrate, or a gallium arsenide substrate. In addition, the semiconductor substrate may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0060] Secondly, the semiconductor substrate includes a first surface and a second surface relative to each other, the first surface of the semiconductor substrate corresponds to the backlight surface of the back contact battery, and the second surface of the semiconductor substrate corresponds to the light-facing surface of the back contact battery. Among them, the distribution of the first region, the second region and the overlapping region on the first surface can be determined according to the distribution of the first doped silicon layer and the second doped silicon layer formed on the first surface. Specifically, since the first doped silicon layer included in the back contact battery is arranged on the first region and the overlapping region, the distribution range of the first region and the overlapping region on the first surface can be determined according to the distribution requirements of the first doped silicon layer in the actual application scenario. Since part of the second doped silicon layer included in the back contact battery is arranged on the second region of the first surface, the distribution range of the second region on the first surface can be determined according to the distribution requirements of the second doped silicon layer on the semiconductor substrate in the actual application scenario. It can be understood that for the first surface, except for the first region and the overlapping region, the other regions are the second regions.

[0061] It can be understood that the first region corresponds to the first emitter region, the second region corresponds to the second emitter region, one of the first region and the second region corresponds to the P region, the other corresponds to the N region, and the overlapping region corresponds to the PN overlapping region.

[0062] The specific shapes of the first area and the second area can be set according to actual needs. For example, the first area and the second area can be arranged alternately in strips or in interdigitated shapes (i.e., a "F"-shaped) with alternating spacing.

[0063] In terms of surface morphology, Figure 1 As shown, the first surface and the second surface of the semiconductor substrate 11 may be planes. Figure 2 As shown, the second surface of the semiconductor substrate 11 can also be a velvet surface to improve the light trapping effect of the second surface and improve the light utilization rate of the semiconductor substrate 11. Of course, in the first surface, the surface of some areas (such as the second area) can also be a velvet surface, and the surface of some areas (such as the first area) can be a plane.

[0064] Secondly, if Figure 1 and Figure 2 As shown, the surfaces of the first area 12 and the second area 13 of the first surface may be flush; or Figure 3As shown, the second region 13 may also include a groove 20. At this time, along the direction from the second surface to the first surface, the surface height of the second region 13 corresponding to the groove 20 is lower than the surface height of the first region 12. In this case, the presence of the groove 20 not only indicates that after the tunneling passivation layer 15 and the first doped silicon layer 16 are patterned, the portions of the two located in the second region 13 have been completely removed, thereby improving the yield of the back contact battery. In addition, the presence of the groove 20 can also at least partially offset the first doped silicon layer 16 and the second doped silicon layer 18 of the opposite conductivity type along the thickness direction of the semiconductor substrate 11, thereby reducing the risk of leakage between the first doped silicon layer 16 and the second doped silicon layer 18, and further improving the conversion efficiency of the back contact battery.

[0065] As for the depth of the groove, it can be set according to actual needs and is not specifically limited here. Figure 3 As shown, the surface of the groove 20 can be a plane; or Figure 4 As shown, the bottom surface of the groove 20 may also be velvet to increase the contact area between the second doped silicon layer 18 formed on the second region 13 and the corresponding conductive material (transparent conductive layer 23 or metal electrode, etc.), which is beneficial to reduce transmission loss.

[0066] Specifically, Figure 3 As shown, the side surface of the groove 20 can be perpendicular to the groove bottom surface of the groove 20. Alternatively, as shown in FIG. Figure 4 and Figure 5 As shown, at least part of the side surface of the groove 20 can also be inclined relative to the bottom surface of the groove, and the groove bottom cross-sectional area of ​​the groove 20 is smaller than the groove opening cross-sectional area; in this case, the entire area of ​​the side surface of the groove 20 can be inclined relative to the bottom surface of the groove; or, along the width direction of the overlapping area 14, the side surface of the groove 20 has a first sub-area 21 and a second sub-area 22 that are continuously distributed, and the second sub-area 22 is close to the first area 12. The surface of the first sub-area 21 is inclined relative to the surface of the first area 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-area 21 gradually increases from the second surface to the first surface. The surface of the second sub-area 22 is a plane, which can be parallel to the second surface or inclined relative to the second surface. Moreover, in this case, when the depth of the groove 20 is fixed, the surface of the first sub-region 21 on the side of the groove 20 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface, which is beneficial to increase the lateral spacing between the doped layer 19 and the second doped silicon layer 18 located at the bottom of the groove, and reduce the risk of leakage between the two; in addition, since the second doped silicon layer 18 is formed relatively smoothly on the inclined surface corresponding to the first sub-region 21, it is beneficial to improve the film formation quality of the second doped silicon layer 18.

[0067] In addition, if Figure 4 As shown, along the direction from the first surface to the second surface, the doping concentration of the second doping element of the same conductivity type as the second doped silicon layer 18 in each part of the second region 13 of the semiconductor substrate 11 is the same. Specifically, the doping concentration of the second doping element in each part of the second region 13 of the semiconductor substrate 11 can be 0, that is, at this time, there is no second doping element in each part of the second region 13 of the semiconductor substrate 11; or, the second doping element can also be doped in each part of the second region 13 of the semiconductor substrate 11, but the distribution concentration of the second doping element in each position of the semiconductor substrate 11 corresponding to the second region 13 is the same, and the doping concentration of the doping element in the second region 13 can be determined according to the actual application scenario, and is not specifically limited here. It should be noted that, if in the actual application manufacturing process, the doping elements in the second doped silicon layer 18 diffuse through the intrinsic silicon layer 17 into the second region 13 of the semiconductor substrate 11, it can be known from the diffusion principle that the doping concentration of the doping elements diffused from the second doped silicon layer 18 into the second region 13 of the semiconductor substrate 11 will gradually decrease along the direction from the first surface to the second surface. In the embodiment of the present invention, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer 18 in each part of the second region 13 of the semiconductor substrate 11 is the same. Therefore, even if there is a second doping element in the second region 13 of the semiconductor substrate 11, the second doping element is not formed by the diffusion of the second doped silicon layer 18, but is the second doping element doped in the semiconductor substrate 11 itself.

[0068] As for the tunneling passivation layer and the first doped silicon layer, in terms of materials, the material of the tunneling passivation layer may include any passivation material having a tunneling effect, such as silicon oxide, aluminum oxide, titanium oxide, and zinc oxide. Secondly, the first doped silicon layer may be a doped crystalline silicon layer, and the material of the doped crystalline silicon layer may include polycrystalline silicon and / or single crystal silicon.

[0069] In terms of conductivity type, the conductivity type of the first doped silicon layer can be N-type, and the conductivity type of the second doped silicon layer is P-type; or, the conductivity type of the first doped silicon layer can also be P-type, and the conductivity type of the second doped silicon layer is N-type. Optionally, when the material of the first doped silicon layer includes polycrystalline silicon, the conductivity type of the first doped silicon layer is N-type; in this case, compared with P-type doped amorphous, microcrystalline silicon and nanocrystalline materials (i.e., P-type second doped silicon layer), when the material of the first doped silicon layer is P-type polycrystalline silicon, the contact resistance between the P-type doped polycrystalline silicon material and the conductive material is higher and the field passivation effect is poor. Therefore, when the conductivity type of the first doped silicon layer is set to N-type and the conductivity type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, and at the same time, the contact resistance between the first doped silicon layer and the conductive material can be reduced, which is beneficial to improving the electrical performance of the back contact battery.

[0070] As for the thickness of the tunnel passivation layer and the first doped silicon layer, they can be set according to actual needs and are not specifically limited here.

[0071] Exemplarily, the thickness of the tunneling passivation layer may be greater than or equal to 0.5 nm and less than or equal to 2.5 nm. For example, the thickness of the tunneling passivation layer may be 0.5 nm, 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 2 nm, 2.2 nm or 2.5 nm, etc. In this case, it is possible to prevent the tunneling resistance of the tunneling passivation layer from being too high due to the large thickness of the tunneling passivation layer, thereby affecting the collection efficiency of the first doped silicon layer for carriers. In addition, it is understandable that within a certain thickness range, the thickness of the tunneling passivation layer is proportional to its diffusion barrier effect. Therefore, if at least part of the first doping element in the doping layer is formed by the first doping element in the first doped silicon layer diffusing through the tunneling passivation layer to the first region and the overlapping region of the semiconductor substrate during the actual manufacturing process, then the thickness of the tunneling passivation layer is within the above range, and it is also possible to prevent the field passivation effect of the doping layer from being affected by the doping concentration of the first doping element in the doping layer being too low or too high due to the thickness of the tunneling passivation layer being too large or too small, thereby avoiding a high carrier recombination rate in the first region and the overlapping region.

[0072] Exemplarily, the thickness of the first doped silicon layer may be greater than or equal to 20nm and less than or equal to 300nm. For example, the thickness of the first doped silicon layer may be 20nm, 50nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 260nm, 280nm or 300nm. In this case, the thickness of the first doped silicon layer is within the above range, which can prevent the field passivation effect of the first doped silicon layer from being low due to the small thickness of the first doped silicon layer, and ensure that the first doped silicon layer has a higher carrier collection efficiency. At the same time, if in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer to the doping layer, then the thickness of the first doped silicon layer is within the above range, which can also prevent the doping concentration of the first doping element diffused from the first doped silicon layer to the doping layer from being low due to the small thickness of the first doped silicon layer, so setting the thickness of the first doped silicon layer within the above range can ensure that the doping layer has a higher field passivation effect. In addition, it can also prevent the large amount of consumables used in the first doped silicon layer due to the large thickness of the first doped silicon layer, and the problem of excessive doping concentration of the first doping element in the doping layer, thereby ensuring that the back contact battery has a higher conversion efficiency.

[0073] It should be noted that the type of the first doping element may be one, such as the first doping element may be phosphorus; or the type of the first doping element may be multiple types of the same conductivity type, such as the first doping element may include phosphorus and arsenic. The type of the first doping element in the first doped silicon layer may be the same as or different from the type of the first doping element in the doping layer. For example: when the conductivity type of the first doped silicon layer and the doping layer is N-type, the first doping elements in the first doped silicon layer and the doping layer may both be phosphorus. For another example: when the conductivity type of the first doped silicon layer and the doping layer is P-type, the first doping elements in the first doped silicon layer and the doping layer may both be boron. For another example: when the conductivity type of the first doped silicon layer and the doping layer is N-type, the first doping element in the first doped silicon layer may be phosphorus, and the first doping elements in the doping layer may both be arsenic. It can be understood that if in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer to the doping layer, the type of the first doping element in the first doped silicon layer is the same as the type of the first doping element in the doping layer. In the above case, the doping concentration of the first doping element in the first doped silicon layer will affect its own field passivation performance; secondly, in the actual manufacturing process, when at least part of the first doping element in the doping layer is diffused from the first doped silicon layer into the doping layer, the doping concentration of the first doping element in the first doped silicon layer will also affect the doping concentration of the first doping element in the doping layer. Therefore, it can be determined based on the field passivation effect of the first doped silicon layer and the doping concentration of the first doping element in the doping layer in the actual application scenario, and no specific limitation is made here.

[0074] For example, the doping concentration of the first doping element in the first doped silicon layer may be greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3 For example, the doping concentration of the first doping element in the first doped silicon layer may be 1×10 18 / cm 3 , 1×10 19 / cm 3 , 2×10 19 / cm 3 , 4×10 19 / cm 3 , 6×10 19 / cm 3 , 8×10 19 / cm 3 , 1×10 20 / cm 3 , 2×10 20 / cm 3 , 4×10 20 / cm 3 , 6×10 20 / cm 3 , 8×10 20 / cm 3 ,9×10 20 / cm 3 or 1×10 21 / cm 3 The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the thickness of the first doped silicon layer being greater than or equal to 20 nm and less than or equal to 300 nm described above, and will not be repeated here.

[0075] As for the intrinsic silicon layer and the second doped silicon layer, in terms of materials, the material of the intrinsic silicon layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon.

[0076] In terms of the formation position, Figure 4 As shown, the stacked intrinsic silicon layer 17 and the second doped silicon layer 18 extend to cover the portion above the overlapping region 14, and may be directly located on the tunnel passivation layer 15 and the first doped silicon layer 16, and contact the first doped silicon layer 16. Alternatively, as Figure 6As shown, the back contact cell may also include an insulating layer 27, which is located between the intrinsic silicon layer 17 and the first doped silicon layer 16 in the overlapping region 14. At this time, the insulating layer 27 will isolate the second doped silicon layer 18 on the overlapping region 14 from the first doped silicon layer 16, thereby reducing forward leakage loss and further improving the conversion efficiency of the back contact cell. The material and thickness of the above insulating layer can be determined according to the actual application scenario and are not specifically limited here. For example, the insulating layer may include a silicon oxide layer and / or an aluminum oxide layer.

[0077] In addition, as mentioned above, there is no internal diffusion doping layer corresponding to the second doped silicon layer in the second region of the semiconductor substrate. On the second region of the semiconductor substrate, the intrinsic silicon layer is located between the semiconductor substrate and the second doped silicon layer, which can play a diffusion barrier role for the doped elements in the second doped silicon layer. Therefore, the thickness of the intrinsic silicon layer will not only affect its own transmission resistance, but also affect the doping concentration of the second doped element in the semiconductor substrate (the type of the second doped element can be one, such as the second doped element can be boron; or, the type of the second doped element can be multiple with the same conductivity type, such as the second doped element can include boron and aluminum). In addition, the thickness of the second doped silicon layer and the doping concentration of the second doped element in itself will not only affect the field passivation effect of the second doped silicon layer, but also may affect whether the second doped element in the second doped silicon layer will diffuse into the second region of the semiconductor substrate. Therefore, the thickness of the intrinsic silicon layer can be determined according to the requirements for transmission resistance and diffusion barrier in the actual application scenario, and the thickness and doping concentration of the second doped silicon layer can be determined according to the requirements for field passivation effect and diffusion of the second doped element in the second doped silicon layer in the actual application scenario, which are not specifically limited here.

[0078] Exemplarily, the thickness of the intrinsic silicon layer may be greater than or equal to 5 nm and less than or equal to 20 nm. For example, the thickness of the intrinsic silicon layer may be 5 nm, 7 nm, 9 nm, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm or 20 nm. In this case, the thickness of the intrinsic silicon layer is within the above range, which can prevent the intrinsic silicon layer from having a weak diffusion barrier effect on the doped elements in the second doped silicon layer due to its small thickness, thereby ensuring that no inner diffusion doped layer with the same conductivity type as the second doped silicon layer is formed in the second region. In addition, it can also prevent the intrinsic silicon layer from having a large transmission resistance due to its large thickness, thereby ensuring that the second doped silicon layer has a high carrier collection efficiency.

[0079] For example, the doping concentration of the second doping element in the second doped silicon layer may be greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3For example, the doping concentration of the second doping element in the second doped silicon layer may be 1×10 18 / cm 3 , 1×10 19 / cm 3 , 2×10 19 / cm 3 , 4×10 19 / cm 3 , 6×10 19 / cm 3 , 8×10 19 / cm 3 , 1×10 20 / cm 3 , 2×10 20 / cm 3 , 4×10 20 / cm 3 , 6×10 20 / cm 3 , 8×10 20 / cm 3 ,9×10 20 / cm 3 or 1×10 21 / cm 3 In this case, while ensuring that the second doped silicon layer has a high field passivation effect, the second doping element in the second doped silicon layer is prevented from being too high, so that the difference in doping concentration of the second doping element between the second doped silicon layer and the second region of the semiconductor substrate is too large, and it is easy to diffuse into the second region of the semiconductor substrate to form an inner diffusion doping layer, ensuring that the doping layer will not be in electrical contact with the inner diffusion doping layer of the opposite conductivity type to itself, resulting in a high risk of leakage, thereby ensuring that the back contact battery has a high conversion efficiency.

[0080] Exemplarily, the thickness of the second doped silicon layer may be greater than or equal to 10 nm and less than or equal to 100 nm. For example, the thickness of the second doped silicon layer may be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm or 100 nm. The application principle of the beneficial effect in this case can refer to the above-mentioned doping concentration of the second doping element in the second doped silicon layer being greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3 The application principle of the beneficial effect is not repeated here. The conductivity type of the second doped silicon layer is opposite to the conductivity type of the first doped silicon layer.

[0081] Exemplarily, the sum of the thickness of the second doped silicon layer and the intrinsic silicon layer may be greater than or equal to 15 nm and less than or equal to 120 nm. For example, the sum of the thickness of the second doped silicon layer and the intrinsic silicon layer may be 15 nm, 20 nm, 30 nm, 50 nm, 70 nm, 90 nm, 100 nm or 120 nm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the thickness of the intrinsic silicon layer being greater than or equal to 5 nm and less than or equal to 20 nm, and the thickness of the second doped silicon layer being greater than or equal to 10 nm and less than or equal to 100 nm described above, which will not be repeated here.

[0082] In addition, if Figure 6 As shown, in the case where the second region 13 includes a groove 20, the depth of the groove 20 will affect the positive ratio between the portion of the second doped silicon layer 18 located at the bottom of the groove 20 and the doped layer 19 located in the first region 12 and the overlapping region 14 along the direction from the second surface to the first surface. In addition, because the conductivity type of the first doping element in the doped layer 19 is opposite to the conductivity type of the second doped silicon layer 18, the positive ratio between the portion of the second doped silicon layer 18 located at the bottom of the groove 20 and the doped layer 19 located in the first region 12 and the overlapping region 14 will affect the leakage risk between the two. Based on this, the depth of the groove 20 and the position between the surface height of the portion of the second doped silicon layer 18 located at the bottom of the groove 20 away from the semiconductor substrate 11 and the surface height of the doped layer 19 away from the tunnel passivation layer 15 can be determined according to the actual manufacturing process and the requirements for the leakage risk between the doped layer 19 and the second doped silicon layer 18 in the actual application scenario, and no specific limitation is made here.

[0083] For example, Figure 7As shown, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the groove 20 away from the semiconductor substrate 11 may be less than the surface height of the doped layer 19 away from the tunnel passivation layer 15. In this case, there is no structurally opposite portion between the doped layer 19 and the second doped silicon layer 18 located at the bottom of the groove 20 along the thickness direction of the semiconductor substrate 11. In other words, the presence of the groove 20 can also stagger the doped layer 19 and the first doped silicon layer 16 respectively with the second doped silicon layer 18 of the opposite conductivity type along the thickness direction of the semiconductor substrate 11, thereby reducing the risk of leakage between the doped layer 19 and the second doped silicon layer 18, and further improving the conversion efficiency of the back contact battery. In addition, it can be understood that the portion of the second doped silicon layer 18 located at the bottom of the groove 20 is mainly used to collect and conduct carriers. Therefore, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the groove 20 away from the semiconductor substrate 11 is set to be smaller than the surface height of the doping layer 19 away from the tunneling passivation layer 15. It is also beneficial to prevent the first doping element with a conductivity type opposite to that of the second doped silicon layer 18 in the doping layer 19 from diffusing into the second doped silicon layer 18, ensuring that the portion of the second doped silicon layer 18 corresponding to the bottom of the groove has a higher carrier collection ability, and preventing leakage between the second doped silicon layer 18 and the doping layer 19 located at the bottom of the groove, thereby affecting the power generation efficiency of the back contact battery.

[0084] Or, if Figure 6 As shown, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the groove 20 away from the semiconductor substrate 11 may also be lower than the surface height of the doped layer 19 close to the tunnel passivation layer 15, and higher than the surface height of the doped layer 19 away from the tunnel passivation layer 15. At this time, while preventing all portions of the doped layer 19 along the thickness direction from being aligned with the portion of the second doped silicon layer 18 located at the bottom of the groove, the depth of the groove 20 can be reduced, so that the portion of the semiconductor substrate 11 corresponding to the groove 20 has a higher light absorption depth, which improves the photoelectric conversion efficiency of the semiconductor substrate 11, and is also conducive to shortening the transmission path of carriers bypassing the side wall of the groove 20 with a higher depth and being collected by the portion of the second doped silicon layer 18 located at the bottom of the groove, thereby reducing transmission losses.

[0085] Exemplarily, the depth of the groove may be greater than or equal to 300nm and less than or equal to 15μm. For example, the depth of the groove may be 300nm, 1μm, 2μm, 3μm, 5μm, 7μm, 9μm, 10μm, 12μm or 15μm, etc. In this case, the depth of the groove is within the above range, which is conducive to preventing the high risk of leakage caused by the small offset spacing between the doped layer and the second doped silicon layer located at the bottom of the groove along the thickness direction of the semiconductor substrate due to the small depth of the groove. In addition, it can also prevent the light absorption depth of the part of the semiconductor substrate corresponding to the groove from being small due to the large depth of the groove, ensuring that the semiconductor substrate has a high photoelectric conversion efficiency, and then ensuring that the back contact battery has a high working performance. Furthermore, when the first doping element in the doping layer is at least formed by diffusing the first doped silicon layer to the semiconductor substrate, the depth of the groove is within the above range, and it can also ensure that after the first doped silicon layer on the second region is removed, the setting of the groove can also completely remove the doped layer formed by the first doped silicon layer in the second region, preventing the electric field of the doped layer remaining in the second region from affecting the carrier collection energy of the second doped silicon layer. It should be noted that when the bottom surface of the groove is a velvet surface, the depth of the groove is the distance between the surface of the first region and the bottom of the velvet structure (the side close to the semiconductor substrate).

[0086] Exemplarily, along the direction from the second surface to the first surface, the difference between the surface height of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate and the surface height of the doped layer away from the tunnel passivation layer can be greater than or equal to 180nm and less than or equal to 14.7μm. For example: the difference between the surface height of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate and the surface height of the doped layer away from the tunnel passivation layer can be 180nm, 200nm, 500nm, 1μm, 2μm, 4μm, 6μm, 8μm, 10μm or 14.7μm, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the depth of the groove being greater than or equal to 300nm and less than or equal to 15μm described above, which will not be repeated here.

[0087] In addition, in the actual application process, such as Figure 7As shown, in the case where the bottom surface of the groove 20 is a velvet surface, the thickness of the second doped silicon layer 18 located on the bottom of the groove 20 can be less than the thickness of the second doped silicon layer 18 located on the overlapping region 14. In this case, the thickness of the second doped silicon layer 18 located on the bottom of the groove 20 is relatively small, which can prevent the second doped elements in the second doped silicon layer 18 located on the bottom of the groove from diffusing into the second region 13 of the semiconductor substrate 11 due to the large thickness of the second doped silicon layer 18 located on the bottom of the groove, while ensuring that it has a good field passivation effect, and ensure that the doped layer 19 will not be in electrical contact with the inner diffusion doped layer 19 of the opposite conductivity type to itself, resulting in a high risk of leakage, thereby ensuring that the back contact battery has a high conversion efficiency. In addition, the thickness of the second doped silicon layer 18 located at the bottom of the groove is relatively small, and the distance between itself and the doped layer 19 along the thickness direction of the semiconductor substrate 11 can also be increased to prevent the first doped elements in the doped layer 19 from diffusing into the second doped silicon layer 18, and ensure that the second doped silicon layer 18 has a high field passivation effect and carrier collection efficiency. Specifically, the difference between the thickness of the second doped silicon layer 18 on the bottom of the groove 20 and the thickness of the second doped silicon layer 18 on the overlapping area 14 can be set according to the size of the suede structure and actual needs, and is not specifically limited here.

[0088] Of course, the thickness of the second doped silicon layer located on the bottom of the groove may also be equal to the thickness of the second doped silicon layer located in the overlapping region.

[0089] For the above-mentioned doping layer, in terms of the formation range, as mentioned above, the doping layer is arranged in the first region and the overlapping region of the semiconductor substrate. Specifically, in the width direction of the overlapping region, the doping layer can be arranged only in the first region and the local region of the overlapping region of the semiconductor substrate; or, the doping layer can also be in the entire first region and the overlapping region; in other words, along the width direction of the overlapping region, the width of the doping layer can be greater than or equal to the width of the first doped silicon layer. In this case, the doping layer has a larger formation range, which is conducive to improving the field passivation effect of the doping layer and further reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate.

[0090] As for the difference in width between the doped layer and the first doped silicon layer, it can be determined according to the scope of passivation treatment of the doped layer in the actual application scenario and the requirements for leakage risk, and is not specifically limited here.

[0091] Exemplarily, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer can be greater than 0 and less than or equal to 50 μm. For example: along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer can be 5nm, 10nm, 50nm, 100nm, 150nm, 200nm, 300nm, 400nm, 500nm, 1μm, 1.5μm, 2μm, 10μm, 20μm, 30μm, 40μm or 50μm, etc. In this case, the width of the doped layer is substantially the same as the width of the first doped silicon layer, ensuring that under the passivation effect of the doped layer, the first region and the overlapping region of the semiconductor substrate have a higher carrier recombination rate. In addition, it can be understood that the overlapping region is adjacent to the second region, and the second doped silicon layer located in the second region is mainly used to collect and conduct carriers, and the conductivity type of the first doping element doped in the doped layer is opposite to the conductivity type of the second doped silicon layer. Based on this, when the difference between the width of the doped layer and the width of the first doped silicon layer is within the above range, it can prevent the width of the doped layer from being larger, resulting in a smaller distance between the edge of the doped layer and the edge of the second doped silicon layer, thereby reducing the risk of leakage between the doped silicon and the second doped silicon layer.

[0092] In addition, as mentioned above, in the case where the second region includes a groove, and the side of the groove has a first sub-region and a second sub-region that are continuously distributed, Figure 8 and Fig. 9 As shown, the doping layer 19 may also extend to the second sub-region 22 of the semiconductor substrate 11; or, the doping layer 19 may also extend to the second sub-region 22 of the semiconductor substrate 11 and a part of the first sub-region 21 close to the second sub-region 22. In this case, when the depth of the groove 20 is fixed, the surface of the first sub-region 21 on the side of the groove 20 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the part of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface, which is conducive to increasing the lateral spacing between the doping layer 19 and the second doped silicon layer 18 located on the bottom of the groove, so that the edge of the doping layer 19 only extends from the overlapping area 14 to the second sub-region 22 of the semiconductor substrate 11 and a part of the first sub-region 21 close to the second sub-region 22, but does not extend to the bottom surface of the groove 20, further reducing the leakage risk between the two. At the same time, the formation range of the doping layer 19 in the semiconductor substrate 11 can also be increased, the range of the passivation treatment can be increased, and the carrier recombination rate on one side of the first surface can be further reduced.

[0093] In addition, along the thickness direction of the semiconductor substrate, the doping depth of the doping layer can be determined according to the manufacturing process of the doping layer and the requirements for the passivation effect of the doping layer, which is not specifically limited here.

[0094] Exemplarily, along the thickness direction of the semiconductor substrate, the doping depth of the doping layer can be greater than or equal to 1nm and less than or equal to 300nm. For example, the doping depth of the doping layer can be 1nm, 5nm, 10nm, 20nm, 40nm, 60nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 260nm or 300nm. In this case, the doping depth of the doping layer is within the above range, which is conducive to preventing the poor field passivation ability of the doping layer due to the small doping depth of the doping layer. In addition, it can also prevent the high Auger recombination rate in the semiconductor substrate due to the large doping depth of the doping layer, which affects the passivation effect of the semiconductor substrate, and ensure that the first region and the overlapping region where the semiconductor substrate is formed with the doping layer have a low carrier recombination rate. If in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer to the doping layer, the doping depth of the doping layer is within the above range, and it can also prevent the doping concentration of the first doping element in the first doped silicon layer from being low due to the large doping depth of the doping layer, and ensure that the first doped silicon layer has a high carrier collection efficiency.

[0095] As for the doping concentration of the first doping element in the doping layer, it can be set according to actual needs, as long as the doping concentration of the first doping element in the doping layer is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate.

[0096] For example, the doping concentration of the first doping element in the doping layer may be less than or equal to 9×10 20 / cm 3 , and greater than or equal to 8×10 9 / cm 3 For example, the doping concentration of the first doping element in the doping layer may be 8×10 9 / cm 3 , 1×10 10 / cm 3 , 1×10 12 / cm 3 , 1×10 16 / cm 3 , 1×10 16 / cm 3 , 2×10 16 / cm 3 , 4×10 16 / cm 3 , 6×10 16 / cm 3 , 8×10 16 / cm 3 , 1×10 17 / cm 3 , 1×10 18 / cm3 , 1×10 19 / cm 3 , 1×10 20 / cm 3 or 9×10 20 / cm 3 Etc. In this case, it is possible to prevent the poor passivation effect of the doping layer due to the low doping concentration of the first doping element. In addition, it is also possible to prevent the low carrier collection efficiency of the first doped silicon layer due to the high doping concentration of the first doping element in the doping layer, which causes the energy band to be recessed, thereby ensuring that the back contact battery has a higher conversion efficiency. If in the actual manufacturing process, the first doping element in the doping layer is diffused from the first doped silicon layer to the doping layer, the doping concentration of the first doping element in the doping layer is within the above range, and it is also possible to prevent the low doping concentration of the first doping element in the first doped silicon layer due to the high doping concentration of the first doping element in the doping layer, thereby ensuring that the first doped silicon layer has a higher carrier collection efficiency.

[0097] Specifically, along the direction from the second surface to the first surface, the doping concentration of the first doping element in each region of the doping layer can be the same. Alternatively, along the direction from the second surface to the first surface, the doping concentration of the first doping element in the doping layer can also gradually increase. In this case, along the direction from the second surface to the first surface, a high-low junction can be formed between different regions of the doping layer, and the built-in electric field of the high-low junction is consistent with the induced direction of the first doped silicon layer, which can further improve the collection efficiency of the first doped silicon layer for carriers, further reduce the carrier recombination rate, and help improve the conversion efficiency of the back contact battery. It should be noted that in the process of detecting the doping concentration and doping depth of the doping layer, when the detection device detects that the doping concentration of the first doping element in the semiconductor substrate is 0 (or close to 0); or, when it is detected that the doping concentration of the first doping element in the semiconductor substrate tends to be consistent, it can be considered that the doping concentration of the first doping element in the semiconductor substrate is 0, or the region where its doping concentration tends to be consistent is the non-doped layer of the semiconductor substrate, and the doping concentration of the first doping element in the semiconductor substrate is greater than 0, or the region where the doping concentration of the first doping element gradually decreases along the direction from the first surface to the second surface is the doping layer.

[0098] In addition, the doping concentration of the first doping element in the first doped silicon layer can be greater than the doping concentration of the first doping element in the doping layer. In this case, it is ensured that the first doped silicon layer has a higher field passivation effect, and the carrier collection ability of the first doped silicon layer is improved. In addition, a high-low junction can be formed between the first doped silicon layer and the doped layer, and the built-in electric field direction of the high-low junction is consistent with the induced direction of the first doped silicon layer, further improving the carrier collection ability of the first doped silicon layer.

[0099] Alternatively, the doping concentration of the first doping element in the first doped silicon layer may also be at least equal to the doping concentration of the first doping element in the side of the doping layer close to the tunnel passivation layer.

[0100] As for the conductivity type of the doped layer, reference may be made to the conductivity type of the first doped silicon layer, which will not be described in detail here.

[0101] Optionally, the conductivity types of the above-mentioned first doped silicon layer and the doped layer can be the same as the conductivity type of the semiconductor substrate. In addition, the second region of the semiconductor substrate does not have a second doping element. In this case, a high-low junction can be formed between each adjacent two of the semiconductor substrate, the doped layer and the first doped silicon layer. Under the action of the built-in electric field of the high-low junction, the collection efficiency of the first doped silicon layer for carriers can be further improved, and the conversion efficiency of the back contact battery can be further improved. The second region of the semiconductor substrate does not have a second doping element with a conductivity type opposite to that of the doped layer, which can ensure that the doped layer will not be in electrical contact with the inner expansion doped layer with a conductivity type opposite to its own, resulting in a higher risk of leakage, and can also reduce the recombination rate of electrons and holes in the semiconductor substrate, thereby ensuring that the back contact battery has a higher conversion efficiency.

[0102] It should be noted that, in the actual manufacturing process, the doping layer can be formed separately in the first region and the overlapping region of the semiconductor substrate by diffusion or ion implantation before the tunneling passivation layer and the first doped silicon layer are formed; at this time, the formation depth range of the doping layer in the semiconductor substrate and the doping concentration of the first doping element in the doping layer itself can be controlled by controlling the concentration, time and temperature of the diffusion or ion implantation. Alternatively, the doping layer can be formed by the first doping element in the first doped silicon layer being diffused into the semiconductor substrate while the tunneling passivation layer and the first doped silicon layer are formed; at this time, the formation range of the doping layer in the semiconductor substrate and the doping concentration of the first doping element in the doping layer itself can be controlled by controlling the thickness of the tunneling passivation layer, the thickness and doping concentration of the first doped silicon layer, and the time and temperature of doping the first doped silicon layer.

[0103] In addition, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer in each part of the second region of the semiconductor substrate is the same. This can be achieved by controlling the thickness of the intrinsic silicon layer, the thickness and doping concentration of the second doped silicon layer, and the time and temperature when doping the second doped silicon layer, so as to avoid or prevent the second doping element in the second doped silicon layer from diffusing into the second region of the semiconductor substrate as much as possible.

[0104] In one example, if Fig.10 and Fig.11As shown, the back contact cell may further include a transparent conductive layer 23. The transparent conductive layer 23 covers the first doped silicon layer 16 and the second doped silicon layer 18 on the side away from the semiconductor substrate 11 to improve the carrier collection efficiency. In addition, a through insulating groove 24 is provided in the transparent conductive layer 23 to disconnect the portion of the transparent conductive layer 23 corresponding to the first doped silicon layer 16 from the portion of the transparent conductive layer 23 corresponding to the second doped silicon layer 18 to prevent short circuit. In which, along the width direction of the overlapping region 14, both side edges of the insulating groove 24 may be located above the overlapping region 14; or, one side edge of the insulating groove 24 may be located above the overlapping region 14, and the other side edge may also be located above the first region 12; or, one side edge of the insulating groove may be located above the overlapping region, and the other side edge may also be located above the second region; or, one side edge of the insulating groove is located above the first region, and the other side edge is located above the second region.

[0105] Specifically, the embodiment of the present invention does not specifically limit the material and thickness of the transparent conductive layer, as long as it can be applied to the back contact battery provided in the embodiment of the present invention. For example, the material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide. The thickness of the transparent conductive layer may be greater than or equal to 10 nm and less than or equal to 200 nm. Among them, the surface of the part of the transparent conductive layer covering the groove that is away from the semiconductor substrate may be flush with the side of the doped layer away from the tunnel passivation layer, or may be higher or lower than the side of the doped layer away from the tunnel passivation layer.

[0106] As for the width of the insulating groove, Fig.10 As shown, when both side edges of the insulating groove 24 are located above the overlapping region 14, the etching amount of the insulating groove 24 opened in the transparent conductive layer 23 is small, which is conducive to improving the etching capacity. In addition, in this case, if the second doped silicon layer 18 on the overlapping region 14 can be electrically contacted with the first doped silicon layer 16 through the intrinsic silicon layer 17, the second doped silicon layer 18 on the overlapping region 14 is covered with the transparent conductive layer 23 extending from the second region 13, and a reverse leakage structure can be formed to reduce the risk of hot spots in the back contact battery. Fig.11As shown, when one side edge of the insulating groove 24 can be located above the overlapping area 14, and the other side edge can also be located above the first area 12, although the etching amount of opening the insulating groove 24 is large, the insulating groove 24 can completely isolate the transparent conductive layer 23 corresponding to the second area 13 and the corresponding first area 12, thereby greatly reducing the risk of leakage and improving the conversion efficiency of the back contact battery. From the above content, it can be seen that different widths of the insulating groove 24 have different effects, and the width of the insulating groove 24 can be set according to different application scenario requirements to improve the applicability of the back contact battery provided by the embodiment of the present invention in different application scenarios.

[0107] In addition, if Fig.11 and Fig.12 As shown, in the case where the back contact battery also includes a transparent conductive layer 23, the portion of the transparent conductive layer 23 that is the same conductivity type as the carriers transported by the second doped silicon layer 18 does not overlap with the doped layer 19 along the thickness direction of the semiconductor substrate 11. In this case, the transparent conductive layer 23 has good conductivity and can improve the carrier collection efficiency. In addition, the portion of the transparent conductive layer 23 that is the same conductivity type as the carriers transported by the second doped silicon layer 18 does not overlap with the doped layer 19 along the thickness direction of the semiconductor substrate 11, preventing the portion of the transparent conductive layer 23 that is the same conductivity type as the carriers transported by the second doped silicon layer 18 from overlapping with the doped layer 19 doped with the first doping element that is opposite to the conductivity type of the second doped silicon layer 18, thereby increasing the risk of leakage, thereby ensuring that the back contact battery has high electrical reliability.

[0108] In some cases, such as Fig.12 As shown, the back contact cell provided by the embodiment of the present invention may also include a surface passivation layer 25 and an anti-reflection layer 26 stacked in sequence on the second surface along the thickness direction of the semiconductor substrate 11, so as to reduce the carrier recombination rate on one side of the second surface, and facilitate more light to be incident from the second side into the semiconductor substrate 11, further improving the conversion efficiency of the back contact cell provided by the embodiment of the present invention. Among them, the embodiment of the present invention does not specifically limit the material and thickness of the surface passivation layer 25 and the anti-reflection layer 26.

[0109] Exemplarily, the surface passivation layer may include at least one of a silicon oxide layer, an aluminum oxide layer, and an intrinsic silicon layer.

[0110] Exemplarily, the anti-reflection layer may include a silicon nitride layer and / or a silicon oxynitride layer.

[0111] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0112] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0113] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0114] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface opposite to each other; the first surface comprises first regions and second regions alternately spaced and an overlapping region between the first regions and the second regions; A tunnel passivation layer and a first doped silicon layer are sequentially stacked on the first region and the overlapping region along a thickness direction of the semiconductor substrate; An intrinsic silicon layer and a second doped silicon layer are sequentially stacked on the second region along the thickness direction of the semiconductor substrate; the stacked intrinsic silicon layer and the second doped silicon layer also extend from the second region to cover the tunnel passivation layer and the first doped silicon layer located in the overlapping region; the conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer; A doping layer is arranged in the first region and the overlapping region of the semiconductor substrate; the doping concentration of a first doping element of the same conductivity type as the first doped silicon layer in the doping layer is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate; along the direction from the first surface to the second surface, the doping concentration of a second doping element of the same conductivity type as the second doped silicon layer in each part of the second region of the semiconductor substrate is the same.

2. The back contact cell according to claim 1, characterized in that: The second region includes a groove; along the direction from the second surface to the first surface, the surface height of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate is less than the surface height of the doped layer away from the tunnel passivation layer.

3. The back contact battery according to claim 2, characterized in that: Along the direction from the second surface to the first surface, the difference between the surface height of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate and the surface height of the doped layer away from the tunnel passivation layer is greater than or equal to 180nm and less than or equal to 14.7μm.

4. The back contact cell according to claim 2, characterized in that: The depth of the groove is greater than or equal to 300 nm and less than or equal to 15 μm.

5. The back contact cell according to claim 1, characterized in that: Along the width direction of the overlapping region, the width of the doped layer is greater than or equal to the width of the first doped silicon layer; And / or, along the width direction of the overlapping region, a difference between a width of the doped layer and a width of the first doped silicon layer is greater than 0 and less than or equal to 50 μm.

6. The back contact cell according to claim 1, characterized in that: The second region includes a groove; along the width direction of the overlapping region, the side surface of the groove has a first sub-region and a second sub-region that are continuously distributed, and the second sub-region is close to the first region; the surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface; the surface of the second sub-region is a plane; The doped layer further extends to the second sub-region of the semiconductor substrate; or, the doped layer further extends to the second sub-region of the semiconductor substrate and a partial region of the first sub-region close to the second sub-region.

7. The back contact cell according to claim 1, characterized in that: Along the direction from the second surface to the first surface, the doping concentration of the first doping element in the doping layer gradually increases.

8. The back contact cell according to claim 1, characterized in that: A doping concentration of the first doping element in the first doped silicon layer is greater than a doping concentration of the first doping element in the doping layer.

9. The back contact cell according to claim 1, characterized in that: The back contact cell further comprises a transparent conductive layer; the transparent conductive layer covers the first doped silicon layer and the second doped silicon layer on a side away from the semiconductor substrate; An insulating groove is provided in the transparent conductive layer to disconnect the portions of the transparent conductive layer corresponding to the first area and the second area from each other; The portion of the transparent conductive layer having the same conductivity type as that of the carriers transported by the second doped silicon layer has no overlap with the doped layer along the thickness direction of the semiconductor substrate.

10. The back contact cell according to claim 1, characterized in that: Along the thickness direction of the semiconductor substrate, the doping depth of the doping layer is greater than or equal to 1 nm and less than or equal to 300 nm.

11. The back contact cell according to claim 1, characterized in that: The doping concentration of the first doping element in the doping layer is less than or equal to 9×10 20 / cm 3 , and greater than or equal to 8×10 9 / cm 3 .

12. The back contact cell according to claim 1, characterized in that: The thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm; and / or, the doping concentration of the first doping element in the first doped silicon layer is greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3 .

13. The back contact cell according to claim 1, characterized in that: The sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer is greater than or equal to 15 nm and less than or equal to 120 nm; And / or, the doping concentration of the second doping element in the second doped silicon layer is greater than or equal to 1×10 18 / cm 3 , and less than or equal to 1×10 21 / cm 3 .

14. The back contact cell according to claim 1, characterized in that The conductivity types of the first doped silicon layer and the doped layer are the same as the conductivity type of the semiconductor substrate; the second region of the semiconductor substrate does not contain the second doping element; And / or, the conductivity type of the doped layer and the first doped silicon layer is N-type, and the conductivity type of the second doped silicon layer is P-type.

15. The back contact cell according to claim 1, characterized in that The second region includes a groove; the bottom surface of the groove is a velvet surface, and the thickness of the second doped silicon layer located on the bottom of the groove is less than the thickness of the second doped silicon layer located in the overlapping region.

16. A photovoltaic module, characterized in that: Comprising a back contact battery as claimed in any one of claims 1 to 15.

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